1 /* 2 * Copyright (c) 2001-2008, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _IF_EM_H_ 33 #define _IF_EM_H_ 34 35 /* Tunables */ 36 37 /* 38 * EM_TXD: Maximum number of Transmit Descriptors 39 * Valid Range: 256 for 82542 and 82543-based adapters 40 * 256-4096 for others 41 * Default Value: 256 42 * This value is the number of transmit descriptors allocated by the driver. 43 * Increasing this value allows the driver to queue more transmits. Each 44 * descriptor is 16 bytes. 45 * Since TDLEN should be multiple of 128bytes, the number of transmit 46 * desscriptors should meet the following condition. 47 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 48 */ 49 #define EM_MIN_TXD 256 50 #define EM_MAX_TXD_82543 EM_MIN_TXD 51 #define EM_MAX_TXD 4096 52 #define EM_DEFAULT_TXD EM_MIN_TXD 53 54 /* 55 * EM_RXD - Maximum number of receive Descriptors 56 * Valid Range: 256 for 82542 and 82543-based adapters 57 * 256-4096 for others 58 * Default Value: 256 59 * This value is the number of receive descriptors allocated by the driver. 60 * Increasing this value allows the driver to buffer more incoming packets. 61 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 62 * descriptor. The maximum MTU size is 16110. 63 * Since TDLEN should be multiple of 128bytes, the number of transmit 64 * desscriptors should meet the following condition. 65 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 66 */ 67 #define EM_MIN_RXD 256 68 #define EM_MAX_RXD_82543 EM_MIN_RXD 69 #define EM_MAX_RXD 4096 70 #define EM_DEFAULT_RXD EM_MIN_RXD 71 72 /* 73 * EM_TIDV - Transmit Interrupt Delay Value 74 * Valid Range: 0-65535 (0=off) 75 * Default Value: 64 76 * This value delays the generation of transmit interrupts in units of 77 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 78 * efficiency if properly tuned for specific network traffic. If the 79 * system is reporting dropped transmits, this value may be set too high 80 * causing the driver to run out of available transmit descriptors. 81 * 82 * NOTE: 83 * It is not used. In DragonFly the TX interrupt moderation is done by 84 * conditionally setting RS bit in TX descriptors. See the description 85 * in struct adapter. 86 */ 87 #define EM_TIDV 64 88 89 /* 90 * EM_TADV - Transmit Absolute Interrupt Delay Value 91 * (Not valid for 82542/82543/82544) 92 * Valid Range: 0-65535 (0=off) 93 * Default Value: 64 94 * This value, in units of 1.024 microseconds, limits the delay in which a 95 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 96 * this value ensures that an interrupt is generated after the initial 97 * packet is sent on the wire within the set amount of time. Proper tuning, 98 * along with EM_TIDV, may improve traffic throughput in specific 99 * network conditions. 100 * 101 * NOTE: 102 * It is not used. In DragonFly the TX interrupt moderation is done by 103 * conditionally setting RS bit in TX descriptors. See the description 104 * in struct adapter. 105 */ 106 #define EM_TADV 64 107 108 /* 109 * Receive Interrupt Delay Timer (Packet Timer) 110 * 111 * NOTE: 112 * RDTR and RADV are deprecated; use ITR instead. They are only used to 113 * workaround hardware bug on certain 82573 based NICs. 114 */ 115 #define EM_RDTR_82573 32 116 117 /* 118 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 119 * 120 * NOTE: 121 * RDTR and RADV are deprecated; use ITR instead. They are only used to 122 * workaround hardware bug on certain 82573 based NICs. 123 */ 124 #define EM_RADV_82573 64 125 126 /* 127 * This parameter controls the duration of transmit watchdog timer. 128 */ 129 #define EM_TX_TIMEOUT 5 130 131 /* One for TX csum offloading desc, the other is reserved */ 132 #define EM_TX_RESERVED 2 133 134 /* Large enough for 16K jumbo frame */ 135 #define EM_TX_SPARE 8 136 137 #define EM_TX_OACTIVE_MAX 64 138 139 /* Interrupt throttle rate */ 140 #define EM_DEFAULT_ITR 10000 141 142 /* 143 * This parameter controls whether or not autonegotation is enabled. 144 * 0 - Disable autonegotiation 145 * 1 - Enable autonegotiation 146 */ 147 #define DO_AUTO_NEG 1 148 149 /* 150 * This parameter control whether or not the driver will wait for 151 * autonegotiation to complete. 152 * 1 - Wait for autonegotiation to complete 153 * 0 - Don't wait for autonegotiation to complete 154 */ 155 #define WAIT_FOR_AUTO_NEG_DEFAULT 0 156 157 /* Tunables -- End */ 158 159 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | \ 160 ADVERTISE_10_FULL | \ 161 ADVERTISE_100_HALF | \ 162 ADVERTISE_100_FULL | \ 163 ADVERTISE_1000_FULL) 164 165 #define AUTO_ALL_MODES 0 166 167 /* PHY master/slave setting */ 168 #define EM_MASTER_SLAVE e1000_ms_hw_default 169 170 /* 171 * Micellaneous constants 172 */ 173 #define EM_VENDOR_ID 0x8086 174 175 #define EM_BAR_MEM PCIR_BAR(0) 176 #define EM_BAR_FLASH PCIR_BAR(1) 177 178 #define EM_JUMBO_PBA 0x00000028 179 #define EM_DEFAULT_PBA 0x00000030 180 #define EM_SMARTSPEED_DOWNSHIFT 3 181 #define EM_SMARTSPEED_MAX 15 182 #define EM_MAX_INTR 10 183 184 #define MAX_NUM_MULTICAST_ADDRESSES 128 185 #define PCI_ANY_ID (~0U) 186 #define EM_FC_PAUSE_TIME 1000 187 #define EM_EEPROM_APME 0x400; 188 189 /* 190 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 191 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 192 * also optimize cache line size effect. H/W supports up to cache line size 128. 193 */ 194 #define EM_DBA_ALIGN 128 195 196 #define SPEED_MODE_BIT (1 << 21) /* On PCI-E MACs only */ 197 198 /* PCI Config defines */ 199 #define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK) 200 #define EM_BAR_TYPE_MASK 0x00000001 201 #define EM_BAR_TYPE_MMEM 0x00000000 202 #define EM_BAR_TYPE_IO 0x00000001 203 #define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK) 204 #define EM_BAR_MEM_TYPE_MASK 0x00000006 205 #define EM_BAR_MEM_TYPE_32BIT 0x00000000 206 #define EM_BAR_MEM_TYPE_64BIT 0x00000004 207 208 #define EM_MAX_SCATTER 64 209 #define EM_TSO_SIZE (65535 + \ 210 sizeof(struct ether_vlan_header)) 211 #define EM_MAX_SEGSIZE 4096 212 #define EM_MSIX_MASK 0x01F00000 /* For 82574 use */ 213 #define ETH_ZLEN 60 214 215 #define EM_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 216 #define EM_IPVHL_SIZE 1 /* sizeof(ip.ip_vhl) */ 217 #define EM_TXCSUM_MINHL (ETHER_HDR_LEN + EVL_ENCAPLEN + \ 218 EM_IPVHL_SIZE) 219 220 /* 221 * 82574 has a nonstandard address for EIAC 222 * and since its only used in MSIX, and in 223 * the em driver only 82574 uses MSIX we can 224 * solve it just using this define. 225 */ 226 #define EM_EIAC 0x000DC 227 228 /* Used in for 82547 10Mb Half workaround */ 229 #define EM_PBA_BYTES_SHIFT 0xA 230 #define EM_TX_HEAD_ADDR_SHIFT 7 231 #define EM_PBA_TX_MASK 0xFFFF0000 232 #define EM_FIFO_HDR 0x10 233 #define EM_82547_PKT_THRESH 0x3e0 234 235 /* 236 * Bus dma allocation structure used by 237 * em_dma_malloc and em_dma_free. 238 */ 239 struct em_dma_alloc { 240 bus_addr_t dma_paddr; 241 void *dma_vaddr; 242 bus_dma_tag_t dma_tag; 243 bus_dmamap_t dma_map; 244 }; 245 246 /* Our adapter structure */ 247 struct adapter { 248 struct arpcom arpcom; 249 struct e1000_hw hw; 250 251 /* DragonFly operating-system-specific structures. */ 252 struct e1000_osdep osdep; 253 device_t dev; 254 255 bus_dma_tag_t parent_dtag; 256 257 struct resource *memory; 258 int memory_rid; 259 struct resource *flash; 260 int flash_rid; 261 262 struct resource *ioport; 263 int io_rid; 264 265 struct resource *intr_res; 266 void *intr_tag; 267 int intr_rid; 268 269 struct ifmedia media; 270 struct callout timer; 271 struct callout tx_fifo_timer; 272 int if_flags; 273 int max_frame_size; 274 int min_frame_size; 275 276 /* Management and WOL features */ 277 int wol; 278 int has_manage; 279 280 /* Info about the board itself */ 281 uint8_t link_active; 282 uint16_t link_speed; 283 uint16_t link_duplex; 284 uint32_t smartspeed; 285 int int_throttle_ceil; 286 287 /* 288 * Transmit definitions 289 * 290 * We have an array of num_tx_desc descriptors (handled 291 * by the controller) paired with an array of tx_buffers 292 * (at tx_buffer_area). 293 * The index of the next available descriptor is next_avail_tx_desc. 294 * The number of remaining tx_desc is num_tx_desc_avail. 295 */ 296 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */ 297 struct e1000_tx_desc *tx_desc_base; 298 struct em_buffer *tx_buffer_area; 299 uint32_t next_avail_tx_desc; 300 uint32_t next_tx_to_clean; 301 int num_tx_desc_avail; 302 int num_tx_desc; 303 bus_dma_tag_t txtag; /* dma tag for tx */ 304 int spare_tx_desc; 305 int oact_tx_desc; 306 307 /* Saved csum offloading context information */ 308 int csum_flags; 309 int csum_ehlen; 310 int csum_iphlen; 311 uint32_t csum_txd_upper; 312 uint32_t csum_txd_lower; 313 314 /* 315 * Variables used to reduce TX interrupt rate and 316 * number of device's TX ring write requests. 317 * 318 * tx_nsegs: 319 * Number of TX descriptors setup so far. 320 * 321 * tx_int_nsegs: 322 * Once tx_nsegs > tx_int_nsegs, RS bit will be set 323 * in the last TX descriptor of the packet, and 324 * tx_nsegs will be reset to 0. So TX interrupt and 325 * TX ring write request should be generated roughly 326 * every tx_int_nsegs TX descriptors. 327 * 328 * tx_dd[]: 329 * Index of the TX descriptors which have RS bit set, 330 * i.e. DD bit will be set on this TX descriptor after 331 * the data of the TX descriptor are transfered to 332 * hardware's internal packet buffer. Only the TX 333 * descriptors listed in tx_dd[] will be checked upon 334 * TX interrupt. This array is used as circular ring. 335 * 336 * tx_dd_tail, tx_dd_head: 337 * Tail and head index of valid elements in tx_dd[]. 338 * tx_dd_tail == tx_dd_head means there is no valid 339 * elements in tx_dd[]. tx_dd_tail points to the position 340 * which is one beyond the last valid element in tx_dd[]. 341 * tx_dd_head points to the first valid element in 342 * tx_dd[]. 343 */ 344 int tx_int_nsegs; 345 int tx_nsegs; 346 int tx_dd_tail; 347 int tx_dd_head; 348 #define EM_TXDD_MAX 64 349 #define EM_TXDD_SAFE 48 /* must be less than EM_TXDD_MAX */ 350 int tx_dd[EM_TXDD_MAX]; 351 352 /* 353 * Receive definitions 354 * 355 * we have an array of num_rx_desc rx_desc (handled by the 356 * controller), and paired with an array of rx_buffers 357 * (at rx_buffer_area). 358 * The next pair to check on receive is at offset next_rx_desc_to_check 359 */ 360 struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */ 361 struct e1000_rx_desc *rx_desc_base; 362 uint32_t next_rx_desc_to_check; 363 uint32_t rx_buffer_len; 364 int num_rx_desc; 365 struct em_buffer *rx_buffer_area; 366 bus_dma_tag_t rxtag; 367 bus_dmamap_t rx_sparemap; 368 369 /* 370 * First/last mbuf pointers, for 371 * collecting multisegment RX packets. 372 */ 373 struct mbuf *fmp; 374 struct mbuf *lmp; 375 376 /* Misc stats maintained by the driver */ 377 unsigned long dropped_pkts; 378 unsigned long mbuf_alloc_failed; 379 unsigned long mbuf_cluster_failed; 380 unsigned long no_tx_desc_avail1; 381 unsigned long no_tx_desc_avail2; 382 unsigned long no_tx_map_avail; 383 unsigned long no_tx_dma_setup; 384 unsigned long watchdog_events; 385 unsigned long rx_overruns; 386 unsigned long rx_irq; 387 unsigned long tx_irq; 388 unsigned long link_irq; 389 unsigned long tx_csum_try_pullup; 390 unsigned long tx_csum_pullup1; 391 unsigned long tx_csum_pullup1_failed; 392 unsigned long tx_csum_pullup2; 393 unsigned long tx_csum_pullup2_failed; 394 unsigned long tx_csum_drop1; 395 unsigned long tx_csum_drop2; 396 397 /* sysctl tree glue */ 398 struct sysctl_ctx_list sysctl_ctx; 399 struct sysctl_oid *sysctl_tree; 400 401 /* 82547 workaround */ 402 uint32_t tx_fifo_size; 403 uint32_t tx_fifo_head; 404 uint32_t tx_fifo_head_addr; 405 uint64_t tx_fifo_reset_cnt; 406 uint64_t tx_fifo_wrk_cnt; 407 uint32_t tx_head_addr; 408 409 /* For 82544 PCIX Workaround */ 410 boolean_t pcix_82544; 411 412 struct e1000_hw_stats stats; 413 }; 414 415 struct em_vendor_info { 416 uint16_t vendor_id; 417 uint16_t device_id; 418 int ret; 419 const char *desc; 420 }; 421 422 struct em_buffer { 423 struct mbuf *m_head; 424 bus_dmamap_t map; /* bus_dma map for packet */ 425 }; 426 427 /* For 82544 PCIX Workaround */ 428 typedef struct _ADDRESS_LENGTH_PAIR { 429 uint64_t address; 430 uint32_t length; 431 } ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR; 432 433 typedef struct _DESCRIPTOR_PAIR { 434 ADDRESS_LENGTH_PAIR descriptor[4]; 435 uint32_t elements; 436 } DESC_ARRAY, *PDESC_ARRAY; 437 438 #define EM_IS_OACTIVE(adapter) \ 439 ((adapter)->num_tx_desc_avail <= (adapter)->oact_tx_desc) 440 441 #define EM_INC_TXDD_IDX(idx) \ 442 do { \ 443 if (++(idx) == EM_TXDD_MAX) \ 444 (idx) = 0; \ 445 } while (0) 446 447 #endif /* _IF_EM_H_ */ 448