1 /************************************************************************** 2 3 Copyright (c) 2001-2005, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ***************************************************************************/ 33 34 /*$FreeBSD: src/sys/dev/em/if_em.h,v 1.1.2.13 2003/06/09 21:43:41 pdeuskar Exp $*/ 35 /*$DragonFly: src/sys/dev/netif/em/if_em.h,v 1.15 2006/06/25 11:02:38 corecode Exp $*/ 36 37 #ifndef _EM_H_DEFINED_ 38 #define _EM_H_DEFINED_ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/mbuf.h> 43 #include <sys/protosw.h> 44 #include <sys/socket.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/sockio.h> 48 #include <sys/sysctl.h> 49 #include <sys/ktr.h> 50 #include <sys/endian.h> 51 52 #include <net/if.h> 53 #include <net/if_arp.h> 54 #include <net/ethernet.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 58 #include <net/bpf.h> 59 #include <net/if_types.h> 60 #include <net/vlan/if_vlan_var.h> 61 62 #include <netinet/in_systm.h> 63 #include <netinet/in.h> 64 #include <netinet/ip.h> 65 #include <netinet/tcp.h> 66 #include <netinet/udp.h> 67 68 #include <sys/bus.h> 69 #include <machine/bus.h> 70 #include <sys/rman.h> 71 #include <machine/resource.h> 72 #include <vm/vm.h> 73 #include <vm/pmap.h> 74 #include <machine/clock.h> 75 #include <bus/pci/pcivar.h> 76 #include <bus/pci/pcireg.h> 77 #include <sys/proc.h> 78 #include <sys/sysctl.h> 79 #include <sys/thread2.h> 80 #include <sys/serialize.h> 81 82 #include <dev/netif/em/if_em_hw.h> 83 84 /* Tunables */ 85 86 /* 87 * EM_MAX_TXD: Maximum number of Transmit Descriptors 88 * Valid Range: 80-256 for 82542 and 82543-based adapters 89 * 80-4096 for others 90 * Default Value: 256 91 * This value is the number of transmit descriptors allocated by the driver. 92 * Increasing this value allows the driver to queue more transmits. Each 93 * descriptor is 16 bytes. 94 */ 95 #define EM_MAX_TXD 256 96 97 /* 98 * EM_MAX_RXD - Maximum number of receive Descriptors 99 * Valid Range: 80-256 for 82542 and 82543-based adapters 100 * 80-4096 for others 101 * Default Value: 256 102 * This value is the number of receive descriptors allocated by the driver. 103 * Increasing this value allows the driver to buffer more incoming packets. 104 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 105 * descriptor. The maximum MTU size is 16110. 106 * 107 */ 108 #define EM_MAX_RXD 256 109 110 /* 111 * EM_TIDV - Transmit Interrupt Delay Value 112 * Valid Range: 0-65535 (0=off) 113 * Default Value: 64 114 * This value delays the generation of transmit interrupts in units of 115 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 116 * efficiency if properly tuned for specific network traffic. If the 117 * system is reporting dropped transmits, this value may be set too high 118 * causing the driver to run out of available transmit descriptors. 119 */ 120 #define EM_TIDV 64 121 122 /* 123 * EM_TADV - Transmit Absolute Interrupt Delay Value (Not valid for 82542/82543/82544) 124 * Valid Range: 0-65535 (0=off) 125 * Default Value: 64 126 * This value, in units of 1.024 microseconds, limits the delay in which a 127 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 128 * this value ensures that an interrupt is generated after the initial 129 * packet is sent on the wire within the set amount of time. Proper tuning, 130 * along with EM_TIDV, may improve traffic throughput in specific 131 * network conditions. 132 */ 133 #define EM_TADV 64 134 135 /* 136 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 137 * Valid Range: 0-65535 (0=off) 138 * Default Value: 0 139 * This value delays the generation of receive interrupts in units of 1.024 140 * microseconds. Receive interrupt reduction can improve CPU efficiency if 141 * properly tuned for specific network traffic. Increasing this value adds 142 * extra latency to frame reception and can end up decreasing the throughput 143 * of TCP traffic. If the system is reporting dropped receives, this value 144 * may be set too high, causing the driver to run out of available receive 145 * descriptors. 146 * 147 * CAUTION: When setting EM_RDTR to a value other than 0, adapters 148 * may hang (stop transmitting) under certain network conditions. 149 * If this occurs a WATCHDOG message is logged in the system event log. 150 * In addition, the controller is automatically reset, restoring the 151 * network connection. To eliminate the potential for the hang 152 * ensure that EM_RDTR is set to 0. 153 */ 154 #define EM_RDTR 0 155 156 /* 157 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 158 * Valid Range: 0-65535 (0=off) 159 * Default Value: 64 160 * This value, in units of 1.024 microseconds, limits the delay in which a 161 * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 162 * this value ensures that an interrupt is generated after the initial 163 * packet is received within the set amount of time. Proper tuning, 164 * along with EM_RDTR, may improve traffic throughput in specific network 165 * conditions. 166 */ 167 #define EM_RADV 64 168 169 170 /* 171 * This parameter controls the maximum no of times the driver will loop 172 * in the isr. 173 * Minimum Value = 1 174 */ 175 #define EM_MAX_INTR 3 176 177 /* 178 * Inform the stack about transmit checksum offload capabilities. 179 */ 180 #define EM_CHECKSUM_FEATURES (CSUM_TCP | CSUM_UDP) 181 182 /* 183 * This parameter controls the duration of transmit watchdog timer. 184 */ 185 #define EM_TX_TIMEOUT 5 /* set to 5 seconds */ 186 187 /* 188 * This parameter controls when the driver calls the routine to reclaim 189 * transmit descriptors. 190 */ 191 #define EM_TX_CLEANUP_THRESHOLD EM_MAX_TXD / 8 192 193 /* 194 * This parameter controls whether or not autonegotation is enabled. 195 * 0 - Disable autonegotiation 196 * 1 - Enable autonegotiation 197 */ 198 #define DO_AUTO_NEG 1 199 200 /* 201 * This parameter control whether or not the driver will wait for 202 * autonegotiation to complete. 203 * 1 - Wait for autonegotiation to complete 204 * 0 - Don't wait for autonegotiation to complete 205 */ 206 #define WAIT_FOR_AUTO_NEG_DEFAULT 0 207 208 /* 209 * EM_MASTER_SLAVE is only defined to enable a workaround for a known 210 * compatibility issue with 82541/82547 devices and some switches. 211 * See the "Known Limitations" section of the README file for a complete 212 * description and a list of affected switches. 213 * 214 * 0 = Hardware default 215 * 1 = Master mode 216 * 2 = Slave mode 217 * 3 = Auto master/slave 218 */ 219 /* #define EM_MASTER_SLAVE 2 */ 220 221 /* Tunables -- End */ 222 223 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 224 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 225 ADVERTISE_1000_FULL) 226 227 #define EM_VENDOR_ID 0x8086 228 #define EM_MMBA 0x0010 /* Mem base address */ 229 #define EM_ROUNDUP(size, unit) (((size) + (unit) - 1) & ~((unit) - 1)) 230 231 #define EM_JUMBO_PBA 0x00000028 232 #define EM_DEFAULT_PBA 0x00000030 233 #define EM_SMARTSPEED_DOWNSHIFT 3 234 #define EM_SMARTSPEED_MAX 15 235 236 237 #define MAX_NUM_MULTICAST_ADDRESSES 128 238 #define PCI_ANY_ID (~0U) 239 #define ETHER_ALIGN 2 240 241 /* Defines for printing debug information */ 242 #define DEBUG_INIT 0 243 #define DEBUG_IOCTL 0 244 #define DEBUG_HW 0 245 246 #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 247 #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 248 #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 249 #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 250 #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 251 #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 252 #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 253 #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 254 #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 255 256 257 /* Supported RX Buffer Sizes */ 258 #define EM_RXBUFFER_2048 2048 259 #define EM_RXBUFFER_4096 4096 260 #define EM_RXBUFFER_8192 8192 261 #define EM_RXBUFFER_16384 16384 262 263 #define EM_MAX_SCATTER 64 264 265 /* ****************************************************************************** 266 * vendor_info_array 267 * 268 * This array contains the list of Subvendor/Subdevice IDs on which the driver 269 * should load. 270 * 271 * ******************************************************************************/ 272 typedef struct _em_vendor_info_t { 273 unsigned int vendor_id; 274 unsigned int device_id; 275 unsigned int subvendor_id; 276 unsigned int subdevice_id; 277 unsigned int index; 278 } em_vendor_info_t; 279 280 281 struct em_buffer { 282 struct mbuf *m_head; 283 bus_dmamap_t map; /* bus_dma map for packet */ 284 }; 285 286 struct em_q { 287 bus_dmamap_t map; /* bus_dma map for packet */ 288 int nsegs; /* # of segments/descriptors */ 289 bus_dma_segment_t segs[EM_MAX_SCATTER]; 290 }; 291 292 /* 293 * Bus dma allocation structure used by 294 * em_dma_malloc and em_dma_free. 295 */ 296 struct em_dma_alloc { 297 bus_addr_t dma_paddr; 298 caddr_t dma_vaddr; 299 bus_dma_tag_t dma_tag; 300 bus_dmamap_t dma_map; 301 bus_dma_segment_t dma_seg; 302 bus_size_t dma_size; 303 int dma_nseg; 304 }; 305 306 typedef enum _XSUM_CONTEXT_T { 307 OFFLOAD_NONE, 308 OFFLOAD_TCP_IP, 309 OFFLOAD_UDP_IP 310 } XSUM_CONTEXT_T; 311 312 struct adapter; 313 struct em_int_delay_info { 314 struct adapter *adapter; /* Back-pointer to the adapter struct */ 315 int offset; /* Register offset to read/write */ 316 int value; /* Current value in usecs */ 317 }; 318 319 /* For 82544 PCIX Workaround */ 320 typedef struct _ADDRESS_LENGTH_PAIR 321 { 322 u_int64_t address; 323 u_int32_t length; 324 } ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR; 325 326 typedef struct _DESCRIPTOR_PAIR 327 { 328 ADDRESS_LENGTH_PAIR descriptor[4]; 329 u_int32_t elements; 330 } DESC_ARRAY, *PDESC_ARRAY; 331 332 /* Our adapter structure */ 333 struct adapter { 334 struct arpcom interface_data; 335 struct em_hw hw; 336 337 /* Operating-system-specific structures */ 338 struct em_osdep osdep; 339 struct device *dev; 340 struct resource *res_memory; 341 struct resource *res_ioport; 342 struct resource *res_interrupt; 343 void *int_handler_tag; 344 struct ifmedia media; 345 struct callout timer; 346 struct callout tx_fifo_timer; 347 int io_rid; 348 349 /* Info about the board itself */ 350 u_int32_t part_num; 351 u_int8_t link_active; 352 u_int16_t link_speed; 353 u_int16_t link_duplex; 354 u_int32_t smartspeed; 355 struct em_int_delay_info tx_int_delay; 356 struct em_int_delay_info tx_abs_int_delay; 357 struct em_int_delay_info rx_int_delay; 358 struct em_int_delay_info rx_abs_int_delay; 359 360 XSUM_CONTEXT_T active_checksum_context; 361 362 /* 363 * Transmit definitions 364 * 365 * We have an array of num_tx_desc descriptors (handled 366 * by the controller) paired with an array of tx_buffers 367 * (at tx_buffer_area). 368 * The index of the next available descriptor is next_avail_tx_desc. 369 * The number of remaining tx_desc is num_tx_desc_avail. 370 */ 371 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */ 372 struct em_tx_desc *tx_desc_base; 373 u_int32_t next_avail_tx_desc; 374 u_int32_t oldest_used_tx_desc; 375 volatile u_int16_t num_tx_desc_avail; 376 u_int16_t num_tx_desc; 377 u_int32_t txd_cmd; 378 struct em_buffer *tx_buffer_area; 379 bus_dma_tag_t txtag; /* dma tag for tx */ 380 381 /* 382 * Receive definitions 383 * 384 * we have an array of num_rx_desc rx_desc (handled by the 385 * controller), and paired with an array of rx_buffers 386 * (at rx_buffer_area). 387 * The next pair to check on receive is at offset next_rx_desc_to_check 388 */ 389 struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */ 390 struct em_rx_desc *rx_desc_base; 391 u_int32_t next_rx_desc_to_check; 392 u_int16_t num_rx_desc; 393 u_int32_t rx_buffer_len; 394 struct em_buffer *rx_buffer_area; 395 bus_dma_tag_t rxtag; 396 397 /* Jumbo frame */ 398 struct mbuf *fmp; 399 struct mbuf *lmp; 400 401 struct sysctl_ctx_list sysctl_ctx; 402 struct sysctl_oid *sysctl_tree; 403 404 /* Misc stats maintained by the driver */ 405 unsigned long dropped_pkts; 406 unsigned long mbuf_alloc_failed; 407 unsigned long mbuf_cluster_failed; 408 unsigned long no_tx_desc_avail1; 409 unsigned long no_tx_desc_avail2; 410 unsigned long no_tx_map_avail; 411 unsigned long no_tx_dma_setup; 412 413 /* Used in for 82547 10Mb Half workaround */ 414 u_int32_t tx_fifo_size; 415 u_int32_t tx_fifo_head; 416 u_int32_t tx_fifo_head_addr; 417 u_int64_t tx_fifo_reset_cnt; 418 u_int64_t tx_fifo_wrk_cnt; 419 u_int32_t tx_head_addr; 420 421 #define EM_PBA_BYTES_SHIFT 0xA 422 #define EM_TX_HEAD_ADDR_SHIFT 7 423 #define EM_PBA_TX_MASK 0xFFFF0000 424 #define EM_FIFO_HDR 0x10 425 #define EM_82547_PKT_THRESH 0x3e0 426 427 /* For 82544 PCIX Workaround */ 428 boolean_t pcix_82544; 429 boolean_t in_detach; 430 431 struct em_hw_stats stats; 432 }; 433 434 #endif /* !_EM_H_DEFINED_ */ 435