1 /* 2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 3 * 4 * Copyright (c) 2001-2008, Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * 34 * Copyright (c) 2005 The DragonFly Project. All rights reserved. 35 * 36 * This code is derived from software contributed to The DragonFly Project 37 * by Matthew Dillon <dillon@backplane.com> 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in 47 * the documentation and/or other materials provided with the 48 * distribution. 49 * 3. Neither the name of The DragonFly Project nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific, prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 */ 66 67 /* 68 * NOTE: 69 * 70 * MSI-X MUST NOT be enabled on 82574: 71 * <<82574 specification update>> errata #15 72 */ 73 74 #include "opt_ifpoll.h" 75 #include "opt_rss.h" 76 #include "opt_emx.h" 77 78 #include <sys/param.h> 79 #include <sys/bus.h> 80 #include <sys/endian.h> 81 #include <sys/interrupt.h> 82 #include <sys/kernel.h> 83 #include <sys/ktr.h> 84 #include <sys/malloc.h> 85 #include <sys/mbuf.h> 86 #include <sys/proc.h> 87 #include <sys/rman.h> 88 #include <sys/serialize.h> 89 #include <sys/serialize2.h> 90 #include <sys/socket.h> 91 #include <sys/sockio.h> 92 #include <sys/sysctl.h> 93 #include <sys/systm.h> 94 95 #include <net/bpf.h> 96 #include <net/ethernet.h> 97 #include <net/if.h> 98 #include <net/if_arp.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 #include <net/ifq_var.h> 102 #include <net/toeplitz.h> 103 #include <net/toeplitz2.h> 104 #include <net/vlan/if_vlan_var.h> 105 #include <net/vlan/if_vlan_ether.h> 106 #include <net/if_poll.h> 107 108 #include <netinet/in_systm.h> 109 #include <netinet/in.h> 110 #include <netinet/ip.h> 111 #include <netinet/tcp.h> 112 #include <netinet/udp.h> 113 114 #include <bus/pci/pcivar.h> 115 #include <bus/pci/pcireg.h> 116 117 #include <dev/netif/ig_hal/e1000_api.h> 118 #include <dev/netif/ig_hal/e1000_82571.h> 119 #include <dev/netif/emx/if_emx.h> 120 121 #ifdef EMX_RSS_DEBUG 122 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \ 123 do { \ 124 if (sc->rss_debug >= lvl) \ 125 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \ 126 } while (0) 127 #else /* !EMX_RSS_DEBUG */ 128 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0) 129 #endif /* EMX_RSS_DEBUG */ 130 131 #define EMX_TX_SERIALIZE 1 132 #define EMX_RX_SERIALIZE 2 133 134 #define EMX_NAME "Intel(R) PRO/1000 " 135 136 #define EMX_DEVICE(id) \ 137 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id } 138 #define EMX_DEVICE_NULL { 0, 0, NULL } 139 140 static const struct emx_device { 141 uint16_t vid; 142 uint16_t did; 143 const char *desc; 144 } emx_devices[] = { 145 EMX_DEVICE(82571EB_COPPER), 146 EMX_DEVICE(82571EB_FIBER), 147 EMX_DEVICE(82571EB_SERDES), 148 EMX_DEVICE(82571EB_SERDES_DUAL), 149 EMX_DEVICE(82571EB_SERDES_QUAD), 150 EMX_DEVICE(82571EB_QUAD_COPPER), 151 EMX_DEVICE(82571EB_QUAD_COPPER_BP), 152 EMX_DEVICE(82571EB_QUAD_COPPER_LP), 153 EMX_DEVICE(82571EB_QUAD_FIBER), 154 EMX_DEVICE(82571PT_QUAD_COPPER), 155 156 EMX_DEVICE(82572EI_COPPER), 157 EMX_DEVICE(82572EI_FIBER), 158 EMX_DEVICE(82572EI_SERDES), 159 EMX_DEVICE(82572EI), 160 161 EMX_DEVICE(82573E), 162 EMX_DEVICE(82573E_IAMT), 163 EMX_DEVICE(82573L), 164 165 EMX_DEVICE(80003ES2LAN_COPPER_SPT), 166 EMX_DEVICE(80003ES2LAN_SERDES_SPT), 167 EMX_DEVICE(80003ES2LAN_COPPER_DPT), 168 EMX_DEVICE(80003ES2LAN_SERDES_DPT), 169 170 EMX_DEVICE(82574L), 171 EMX_DEVICE(82574LA), 172 173 /* required last entry */ 174 EMX_DEVICE_NULL 175 }; 176 177 static int emx_probe(device_t); 178 static int emx_attach(device_t); 179 static int emx_detach(device_t); 180 static int emx_shutdown(device_t); 181 static int emx_suspend(device_t); 182 static int emx_resume(device_t); 183 184 static void emx_init(void *); 185 static void emx_stop(struct emx_softc *); 186 static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 187 static void emx_start(struct ifnet *); 188 #ifdef IFPOLL_ENABLE 189 static void emx_qpoll(struct ifnet *, struct ifpoll_info *); 190 #endif 191 static void emx_watchdog(struct ifnet *); 192 static void emx_media_status(struct ifnet *, struct ifmediareq *); 193 static int emx_media_change(struct ifnet *); 194 static void emx_timer(void *); 195 static void emx_serialize(struct ifnet *, enum ifnet_serialize); 196 static void emx_deserialize(struct ifnet *, enum ifnet_serialize); 197 static int emx_tryserialize(struct ifnet *, enum ifnet_serialize); 198 #ifdef INVARIANTS 199 static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize, 200 boolean_t); 201 #endif 202 203 static void emx_intr(void *); 204 static void emx_rxeof(struct emx_softc *, int, int); 205 static void emx_txeof(struct emx_softc *); 206 static void emx_tx_collect(struct emx_softc *); 207 static void emx_tx_purge(struct emx_softc *); 208 static void emx_enable_intr(struct emx_softc *); 209 static void emx_disable_intr(struct emx_softc *); 210 211 static int emx_dma_alloc(struct emx_softc *); 212 static void emx_dma_free(struct emx_softc *); 213 static void emx_init_tx_ring(struct emx_softc *); 214 static int emx_init_rx_ring(struct emx_softc *, struct emx_rxdata *); 215 static void emx_free_rx_ring(struct emx_softc *, struct emx_rxdata *); 216 static int emx_create_tx_ring(struct emx_softc *); 217 static int emx_create_rx_ring(struct emx_softc *, struct emx_rxdata *); 218 static void emx_destroy_tx_ring(struct emx_softc *, int); 219 static void emx_destroy_rx_ring(struct emx_softc *, 220 struct emx_rxdata *, int); 221 static int emx_newbuf(struct emx_softc *, struct emx_rxdata *, int, int); 222 static int emx_encap(struct emx_softc *, struct mbuf **); 223 static int emx_txcsum_pullup(struct emx_softc *, struct mbuf **); 224 static int emx_txcsum(struct emx_softc *, struct mbuf *, 225 uint32_t *, uint32_t *); 226 227 static int emx_is_valid_eaddr(const uint8_t *); 228 static int emx_reset(struct emx_softc *); 229 static void emx_setup_ifp(struct emx_softc *); 230 static void emx_init_tx_unit(struct emx_softc *); 231 static void emx_init_rx_unit(struct emx_softc *); 232 static void emx_update_stats(struct emx_softc *); 233 static void emx_set_promisc(struct emx_softc *); 234 static void emx_disable_promisc(struct emx_softc *); 235 static void emx_set_multi(struct emx_softc *); 236 static void emx_update_link_status(struct emx_softc *); 237 static void emx_smartspeed(struct emx_softc *); 238 static void emx_set_itr(struct emx_softc *, uint32_t); 239 static void emx_disable_aspm(struct emx_softc *); 240 241 static void emx_print_debug_info(struct emx_softc *); 242 static void emx_print_nvm_info(struct emx_softc *); 243 static void emx_print_hw_stats(struct emx_softc *); 244 245 static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS); 246 static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 247 static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS); 248 static int emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS); 249 static void emx_add_sysctl(struct emx_softc *); 250 251 static void emx_serialize_skipmain(struct emx_softc *); 252 static void emx_deserialize_skipmain(struct emx_softc *); 253 254 /* Management and WOL Support */ 255 static void emx_get_mgmt(struct emx_softc *); 256 static void emx_rel_mgmt(struct emx_softc *); 257 static void emx_get_hw_control(struct emx_softc *); 258 static void emx_rel_hw_control(struct emx_softc *); 259 static void emx_enable_wol(device_t); 260 261 static device_method_t emx_methods[] = { 262 /* Device interface */ 263 DEVMETHOD(device_probe, emx_probe), 264 DEVMETHOD(device_attach, emx_attach), 265 DEVMETHOD(device_detach, emx_detach), 266 DEVMETHOD(device_shutdown, emx_shutdown), 267 DEVMETHOD(device_suspend, emx_suspend), 268 DEVMETHOD(device_resume, emx_resume), 269 { 0, 0 } 270 }; 271 272 static driver_t emx_driver = { 273 "emx", 274 emx_methods, 275 sizeof(struct emx_softc), 276 }; 277 278 static devclass_t emx_devclass; 279 280 DECLARE_DUMMY_MODULE(if_emx); 281 MODULE_DEPEND(emx, ig_hal, 1, 1, 1); 282 DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, NULL, NULL); 283 284 /* 285 * Tunables 286 */ 287 static int emx_int_throttle_ceil = EMX_DEFAULT_ITR; 288 static int emx_rxd = EMX_DEFAULT_RXD; 289 static int emx_txd = EMX_DEFAULT_TXD; 290 static int emx_smart_pwr_down = 0; 291 static int emx_rxr = 0; 292 293 /* Controls whether promiscuous also shows bad packets */ 294 static int emx_debug_sbp = 0; 295 296 static int emx_82573_workaround = 1; 297 static int emx_msi_enable = 1; 298 299 TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil); 300 TUNABLE_INT("hw.emx.rxd", &emx_rxd); 301 TUNABLE_INT("hw.emx.rxr", &emx_rxr); 302 TUNABLE_INT("hw.emx.txd", &emx_txd); 303 TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down); 304 TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp); 305 TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround); 306 TUNABLE_INT("hw.emx.msi.enable", &emx_msi_enable); 307 308 /* Global used in WOL setup with multiport cards */ 309 static int emx_global_quad_port_a = 0; 310 311 /* Set this to one to display debug statistics */ 312 static int emx_display_debug_stats = 0; 313 314 #if !defined(KTR_IF_EMX) 315 #define KTR_IF_EMX KTR_ALL 316 #endif 317 KTR_INFO_MASTER(if_emx); 318 KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin"); 319 KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end"); 320 KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet"); 321 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet"); 322 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean"); 323 #define logif(name) KTR_LOG(if_emx_ ## name) 324 325 static __inline void 326 emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf) 327 { 328 rxd->rxd_bufaddr = htole64(rxbuf->paddr); 329 /* DD bit must be cleared */ 330 rxd->rxd_staterr = 0; 331 } 332 333 static __inline void 334 emx_rxcsum(uint32_t staterr, struct mbuf *mp) 335 { 336 /* Ignore Checksum bit is set */ 337 if (staterr & E1000_RXD_STAT_IXSM) 338 return; 339 340 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) == 341 E1000_RXD_STAT_IPCS) 342 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID; 343 344 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) == 345 E1000_RXD_STAT_TCPCS) { 346 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 347 CSUM_PSEUDO_HDR | 348 CSUM_FRAG_NOT_CHECKED; 349 mp->m_pkthdr.csum_data = htons(0xffff); 350 } 351 } 352 353 static __inline struct pktinfo * 354 emx_rssinfo(struct mbuf *m, struct pktinfo *pi, 355 uint32_t mrq, uint32_t hash, uint32_t staterr) 356 { 357 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) { 358 case EMX_RXDMRQ_IPV4_TCP: 359 pi->pi_netisr = NETISR_IP; 360 pi->pi_flags = 0; 361 pi->pi_l3proto = IPPROTO_TCP; 362 break; 363 364 case EMX_RXDMRQ_IPV6_TCP: 365 pi->pi_netisr = NETISR_IPV6; 366 pi->pi_flags = 0; 367 pi->pi_l3proto = IPPROTO_TCP; 368 break; 369 370 case EMX_RXDMRQ_IPV4: 371 if (staterr & E1000_RXD_STAT_IXSM) 372 return NULL; 373 374 if ((staterr & 375 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) == 376 E1000_RXD_STAT_TCPCS) { 377 pi->pi_netisr = NETISR_IP; 378 pi->pi_flags = 0; 379 pi->pi_l3proto = IPPROTO_UDP; 380 break; 381 } 382 /* FALL THROUGH */ 383 default: 384 return NULL; 385 } 386 387 m->m_flags |= M_HASH; 388 m->m_pkthdr.hash = toeplitz_hash(hash); 389 return pi; 390 } 391 392 static int 393 emx_probe(device_t dev) 394 { 395 const struct emx_device *d; 396 uint16_t vid, did; 397 398 vid = pci_get_vendor(dev); 399 did = pci_get_device(dev); 400 401 for (d = emx_devices; d->desc != NULL; ++d) { 402 if (vid == d->vid && did == d->did) { 403 device_set_desc(dev, d->desc); 404 device_set_async_attach(dev, TRUE); 405 return 0; 406 } 407 } 408 return ENXIO; 409 } 410 411 static int 412 emx_attach(device_t dev) 413 { 414 struct emx_softc *sc = device_get_softc(dev); 415 struct ifnet *ifp = &sc->arpcom.ac_if; 416 int error = 0, i, throttle; 417 u_int intr_flags; 418 uint16_t eeprom_data, device_id, apme_mask; 419 420 lwkt_serialize_init(&sc->main_serialize); 421 lwkt_serialize_init(&sc->tx_serialize); 422 for (i = 0; i < EMX_NRX_RING; ++i) 423 lwkt_serialize_init(&sc->rx_data[i].rx_serialize); 424 425 i = 0; 426 sc->serializes[i++] = &sc->main_serialize; 427 sc->serializes[i++] = &sc->tx_serialize; 428 sc->serializes[i++] = &sc->rx_data[0].rx_serialize; 429 sc->serializes[i++] = &sc->rx_data[1].rx_serialize; 430 KKASSERT(i == EMX_NSERIALIZE); 431 432 callout_init_mp(&sc->timer); 433 434 sc->dev = sc->osdep.dev = dev; 435 436 /* 437 * Determine hardware and mac type 438 */ 439 sc->hw.vendor_id = pci_get_vendor(dev); 440 sc->hw.device_id = pci_get_device(dev); 441 sc->hw.revision_id = pci_get_revid(dev); 442 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev); 443 sc->hw.subsystem_device_id = pci_get_subdevice(dev); 444 445 if (e1000_set_mac_type(&sc->hw)) 446 return ENXIO; 447 448 /* Enable bus mastering */ 449 pci_enable_busmaster(dev); 450 451 /* 452 * Allocate IO memory 453 */ 454 sc->memory_rid = EMX_BAR_MEM; 455 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 456 &sc->memory_rid, RF_ACTIVE); 457 if (sc->memory == NULL) { 458 device_printf(dev, "Unable to allocate bus resource: memory\n"); 459 error = ENXIO; 460 goto fail; 461 } 462 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); 463 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory); 464 465 /* XXX This is quite goofy, it is not actually used */ 466 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle; 467 468 /* 469 * Allocate interrupt 470 */ 471 sc->intr_type = pci_alloc_1intr(dev, emx_msi_enable, 472 &sc->intr_rid, &intr_flags); 473 474 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid, 475 intr_flags); 476 if (sc->intr_res == NULL) { 477 device_printf(dev, "Unable to allocate bus resource: " 478 "interrupt\n"); 479 error = ENXIO; 480 goto fail; 481 } 482 483 /* Save PCI command register for Shared Code */ 484 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 485 sc->hw.back = &sc->osdep; 486 487 /* Do Shared Code initialization */ 488 if (e1000_setup_init_funcs(&sc->hw, TRUE)) { 489 device_printf(dev, "Setup of Shared code failed\n"); 490 error = ENXIO; 491 goto fail; 492 } 493 e1000_get_bus_info(&sc->hw); 494 495 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG; 496 sc->hw.phy.autoneg_wait_to_complete = FALSE; 497 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT; 498 499 /* 500 * Interrupt throttle rate 501 */ 502 throttle = device_getenv_int(dev, "int_throttle_ceil", 503 emx_int_throttle_ceil); 504 if (throttle == 0) { 505 sc->int_throttle_ceil = 0; 506 } else { 507 if (throttle < 0) 508 throttle = EMX_DEFAULT_ITR; 509 510 /* Recalculate the tunable value to get the exact frequency. */ 511 throttle = 1000000000 / 256 / throttle; 512 513 /* Upper 16bits of ITR is reserved and should be zero */ 514 if (throttle & 0xffff0000) 515 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR; 516 517 sc->int_throttle_ceil = 1000000000 / 256 / throttle; 518 } 519 520 e1000_init_script_state_82541(&sc->hw, TRUE); 521 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE); 522 523 /* Copper options */ 524 if (sc->hw.phy.media_type == e1000_media_type_copper) { 525 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES; 526 sc->hw.phy.disable_polarity_correction = FALSE; 527 sc->hw.phy.ms_type = EMX_MASTER_SLAVE; 528 } 529 530 /* Set the frame limits assuming standard ethernet sized frames. */ 531 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN; 532 sc->min_frame_size = ETHER_MIN_LEN; 533 534 /* This controls when hardware reports transmit completion status. */ 535 sc->hw.mac.report_tx_early = 1; 536 537 /* Calculate # of RX rings */ 538 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", emx_rxr); 539 sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, EMX_NRX_RING); 540 541 /* Allocate RX/TX rings' busdma(9) stuffs */ 542 error = emx_dma_alloc(sc); 543 if (error) 544 goto fail; 545 546 /* Allocate multicast array memory. */ 547 sc->mta = kmalloc(ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX, 548 M_DEVBUF, M_WAITOK); 549 550 /* Indicate SOL/IDER usage */ 551 if (e1000_check_reset_block(&sc->hw)) { 552 device_printf(dev, 553 "PHY reset is blocked due to SOL/IDER session.\n"); 554 } 555 556 /* 557 * Start from a known state, this is important in reading the 558 * nvm and mac from that. 559 */ 560 e1000_reset_hw(&sc->hw); 561 562 /* Make sure we have a good EEPROM before we read from it */ 563 if (e1000_validate_nvm_checksum(&sc->hw) < 0) { 564 /* 565 * Some PCI-E parts fail the first check due to 566 * the link being in sleep state, call it again, 567 * if it fails a second time its a real issue. 568 */ 569 if (e1000_validate_nvm_checksum(&sc->hw) < 0) { 570 device_printf(dev, 571 "The EEPROM Checksum Is Not Valid\n"); 572 error = EIO; 573 goto fail; 574 } 575 } 576 577 /* Copy the permanent MAC address out of the EEPROM */ 578 if (e1000_read_mac_addr(&sc->hw) < 0) { 579 device_printf(dev, "EEPROM read error while reading MAC" 580 " address\n"); 581 error = EIO; 582 goto fail; 583 } 584 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) { 585 device_printf(dev, "Invalid MAC address\n"); 586 error = EIO; 587 goto fail; 588 } 589 590 /* Determine if we have to control management hardware */ 591 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw); 592 593 /* 594 * Setup Wake-on-Lan 595 */ 596 apme_mask = EMX_EEPROM_APME; 597 eeprom_data = 0; 598 switch (sc->hw.mac.type) { 599 case e1000_82573: 600 sc->has_amt = 1; 601 /* FALL THROUGH */ 602 603 case e1000_82571: 604 case e1000_82572: 605 case e1000_80003es2lan: 606 if (sc->hw.bus.func == 1) { 607 e1000_read_nvm(&sc->hw, 608 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 609 } else { 610 e1000_read_nvm(&sc->hw, 611 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 612 } 613 break; 614 615 default: 616 e1000_read_nvm(&sc->hw, 617 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 618 break; 619 } 620 if (eeprom_data & apme_mask) 621 sc->wol = E1000_WUFC_MAG | E1000_WUFC_MC; 622 623 /* 624 * We have the eeprom settings, now apply the special cases 625 * where the eeprom may be wrong or the board won't support 626 * wake on lan on a particular port 627 */ 628 device_id = pci_get_device(dev); 629 switch (device_id) { 630 case E1000_DEV_ID_82571EB_FIBER: 631 /* 632 * Wake events only supported on port A for dual fiber 633 * regardless of eeprom setting 634 */ 635 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 636 E1000_STATUS_FUNC_1) 637 sc->wol = 0; 638 break; 639 640 case E1000_DEV_ID_82571EB_QUAD_COPPER: 641 case E1000_DEV_ID_82571EB_QUAD_FIBER: 642 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 643 /* if quad port sc, disable WoL on all but port A */ 644 if (emx_global_quad_port_a != 0) 645 sc->wol = 0; 646 /* Reset for multiple quad port adapters */ 647 if (++emx_global_quad_port_a == 4) 648 emx_global_quad_port_a = 0; 649 break; 650 } 651 652 /* XXX disable wol */ 653 sc->wol = 0; 654 655 /* Setup OS specific network interface */ 656 emx_setup_ifp(sc); 657 658 /* Add sysctl tree, must after em_setup_ifp() */ 659 emx_add_sysctl(sc); 660 661 /* Reset the hardware */ 662 error = emx_reset(sc); 663 if (error) { 664 device_printf(dev, "Unable to reset the hardware\n"); 665 goto fail; 666 } 667 668 /* Initialize statistics */ 669 emx_update_stats(sc); 670 671 sc->hw.mac.get_link_status = 1; 672 emx_update_link_status(sc); 673 674 sc->spare_tx_desc = EMX_TX_SPARE; 675 676 /* 677 * Keep following relationship between spare_tx_desc, oact_tx_desc 678 * and tx_int_nsegs: 679 * (spare_tx_desc + EMX_TX_RESERVED) <= 680 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_int_nsegs 681 */ 682 sc->oact_tx_desc = sc->num_tx_desc / 8; 683 if (sc->oact_tx_desc > EMX_TX_OACTIVE_MAX) 684 sc->oact_tx_desc = EMX_TX_OACTIVE_MAX; 685 if (sc->oact_tx_desc < sc->spare_tx_desc + EMX_TX_RESERVED) 686 sc->oact_tx_desc = sc->spare_tx_desc + EMX_TX_RESERVED; 687 688 sc->tx_int_nsegs = sc->num_tx_desc / 16; 689 if (sc->tx_int_nsegs < sc->oact_tx_desc) 690 sc->tx_int_nsegs = sc->oact_tx_desc; 691 692 /* Non-AMT based hardware can now take control from firmware */ 693 if (sc->has_manage && !sc->has_amt) 694 emx_get_hw_control(sc); 695 696 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, emx_intr, sc, 697 &sc->intr_tag, &sc->main_serialize); 698 if (error) { 699 device_printf(dev, "Failed to register interrupt handler"); 700 ether_ifdetach(&sc->arpcom.ac_if); 701 goto fail; 702 } 703 704 ifp->if_cpuid = rman_get_cpuid(sc->intr_res); 705 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 706 return (0); 707 fail: 708 emx_detach(dev); 709 return (error); 710 } 711 712 static int 713 emx_detach(device_t dev) 714 { 715 struct emx_softc *sc = device_get_softc(dev); 716 717 if (device_is_attached(dev)) { 718 struct ifnet *ifp = &sc->arpcom.ac_if; 719 720 ifnet_serialize_all(ifp); 721 722 emx_stop(sc); 723 724 e1000_phy_hw_reset(&sc->hw); 725 726 emx_rel_mgmt(sc); 727 emx_rel_hw_control(sc); 728 729 if (sc->wol) { 730 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 731 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 732 emx_enable_wol(dev); 733 } 734 735 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag); 736 737 ifnet_deserialize_all(ifp); 738 739 ether_ifdetach(ifp); 740 } else { 741 emx_rel_hw_control(sc); 742 } 743 bus_generic_detach(dev); 744 745 if (sc->intr_res != NULL) { 746 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid, 747 sc->intr_res); 748 } 749 750 if (sc->intr_type == PCI_INTR_TYPE_MSI) 751 pci_release_msi(dev); 752 753 if (sc->memory != NULL) { 754 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid, 755 sc->memory); 756 } 757 758 emx_dma_free(sc); 759 760 /* Free sysctl tree */ 761 if (sc->sysctl_tree != NULL) 762 sysctl_ctx_free(&sc->sysctl_ctx); 763 764 return (0); 765 } 766 767 static int 768 emx_shutdown(device_t dev) 769 { 770 return emx_suspend(dev); 771 } 772 773 static int 774 emx_suspend(device_t dev) 775 { 776 struct emx_softc *sc = device_get_softc(dev); 777 struct ifnet *ifp = &sc->arpcom.ac_if; 778 779 ifnet_serialize_all(ifp); 780 781 emx_stop(sc); 782 783 emx_rel_mgmt(sc); 784 emx_rel_hw_control(sc); 785 786 if (sc->wol) { 787 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 788 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 789 emx_enable_wol(dev); 790 } 791 792 ifnet_deserialize_all(ifp); 793 794 return bus_generic_suspend(dev); 795 } 796 797 static int 798 emx_resume(device_t dev) 799 { 800 struct emx_softc *sc = device_get_softc(dev); 801 struct ifnet *ifp = &sc->arpcom.ac_if; 802 803 ifnet_serialize_all(ifp); 804 805 emx_init(sc); 806 emx_get_mgmt(sc); 807 if_devstart(ifp); 808 809 ifnet_deserialize_all(ifp); 810 811 return bus_generic_resume(dev); 812 } 813 814 static void 815 emx_start(struct ifnet *ifp) 816 { 817 struct emx_softc *sc = ifp->if_softc; 818 struct mbuf *m_head; 819 820 ASSERT_SERIALIZED(&sc->tx_serialize); 821 822 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 823 return; 824 825 if (!sc->link_active) { 826 ifq_purge(&ifp->if_snd); 827 return; 828 } 829 830 while (!ifq_is_empty(&ifp->if_snd)) { 831 /* Now do we at least have a minimal? */ 832 if (EMX_IS_OACTIVE(sc)) { 833 emx_tx_collect(sc); 834 if (EMX_IS_OACTIVE(sc)) { 835 ifp->if_flags |= IFF_OACTIVE; 836 sc->no_tx_desc_avail1++; 837 break; 838 } 839 } 840 841 logif(pkt_txqueue); 842 m_head = ifq_dequeue(&ifp->if_snd, NULL); 843 if (m_head == NULL) 844 break; 845 846 if (emx_encap(sc, &m_head)) { 847 ifp->if_oerrors++; 848 emx_tx_collect(sc); 849 continue; 850 } 851 852 /* Send a copy of the frame to the BPF listener */ 853 ETHER_BPF_MTAP(ifp, m_head); 854 855 /* Set timeout in case hardware has problems transmitting. */ 856 ifp->if_timer = EMX_TX_TIMEOUT; 857 } 858 } 859 860 static int 861 emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 862 { 863 struct emx_softc *sc = ifp->if_softc; 864 struct ifreq *ifr = (struct ifreq *)data; 865 uint16_t eeprom_data = 0; 866 int max_frame_size, mask, reinit; 867 int error = 0; 868 869 ASSERT_IFNET_SERIALIZED_ALL(ifp); 870 871 switch (command) { 872 case SIOCSIFMTU: 873 switch (sc->hw.mac.type) { 874 case e1000_82573: 875 /* 876 * 82573 only supports jumbo frames 877 * if ASPM is disabled. 878 */ 879 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1, 880 &eeprom_data); 881 if (eeprom_data & NVM_WORD1A_ASPM_MASK) { 882 max_frame_size = ETHER_MAX_LEN; 883 break; 884 } 885 /* FALL THROUGH */ 886 887 /* Limit Jumbo Frame size */ 888 case e1000_82571: 889 case e1000_82572: 890 case e1000_82574: 891 case e1000_80003es2lan: 892 max_frame_size = 9234; 893 break; 894 895 default: 896 max_frame_size = MAX_JUMBO_FRAME_SIZE; 897 break; 898 } 899 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN - 900 ETHER_CRC_LEN) { 901 error = EINVAL; 902 break; 903 } 904 905 ifp->if_mtu = ifr->ifr_mtu; 906 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN + 907 ETHER_CRC_LEN; 908 909 if (ifp->if_flags & IFF_RUNNING) 910 emx_init(sc); 911 break; 912 913 case SIOCSIFFLAGS: 914 if (ifp->if_flags & IFF_UP) { 915 if ((ifp->if_flags & IFF_RUNNING)) { 916 if ((ifp->if_flags ^ sc->if_flags) & 917 (IFF_PROMISC | IFF_ALLMULTI)) { 918 emx_disable_promisc(sc); 919 emx_set_promisc(sc); 920 } 921 } else { 922 emx_init(sc); 923 } 924 } else if (ifp->if_flags & IFF_RUNNING) { 925 emx_stop(sc); 926 } 927 sc->if_flags = ifp->if_flags; 928 break; 929 930 case SIOCADDMULTI: 931 case SIOCDELMULTI: 932 if (ifp->if_flags & IFF_RUNNING) { 933 emx_disable_intr(sc); 934 emx_set_multi(sc); 935 #ifdef IFPOLL_ENABLE 936 if (!(ifp->if_flags & IFF_NPOLLING)) 937 #endif 938 emx_enable_intr(sc); 939 } 940 break; 941 942 case SIOCSIFMEDIA: 943 /* Check SOL/IDER usage */ 944 if (e1000_check_reset_block(&sc->hw)) { 945 device_printf(sc->dev, "Media change is" 946 " blocked due to SOL/IDER session.\n"); 947 break; 948 } 949 /* FALL THROUGH */ 950 951 case SIOCGIFMEDIA: 952 error = ifmedia_ioctl(ifp, ifr, &sc->media, command); 953 break; 954 955 case SIOCSIFCAP: 956 reinit = 0; 957 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 958 if (mask & IFCAP_HWCSUM) { 959 ifp->if_capenable ^= (mask & IFCAP_HWCSUM); 960 reinit = 1; 961 } 962 if (mask & IFCAP_VLAN_HWTAGGING) { 963 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 964 reinit = 1; 965 } 966 if (mask & IFCAP_RSS) 967 ifp->if_capenable ^= IFCAP_RSS; 968 if (reinit && (ifp->if_flags & IFF_RUNNING)) 969 emx_init(sc); 970 break; 971 972 default: 973 error = ether_ioctl(ifp, command, data); 974 break; 975 } 976 return (error); 977 } 978 979 static void 980 emx_watchdog(struct ifnet *ifp) 981 { 982 struct emx_softc *sc = ifp->if_softc; 983 984 ASSERT_IFNET_SERIALIZED_ALL(ifp); 985 986 /* 987 * The timer is set to 5 every time start queues a packet. 988 * Then txeof keeps resetting it as long as it cleans at 989 * least one descriptor. 990 * Finally, anytime all descriptors are clean the timer is 991 * set to 0. 992 */ 993 994 if (E1000_READ_REG(&sc->hw, E1000_TDT(0)) == 995 E1000_READ_REG(&sc->hw, E1000_TDH(0))) { 996 /* 997 * If we reach here, all TX jobs are completed and 998 * the TX engine should have been idled for some time. 999 * We don't need to call if_devstart() here. 1000 */ 1001 ifp->if_flags &= ~IFF_OACTIVE; 1002 ifp->if_timer = 0; 1003 return; 1004 } 1005 1006 /* 1007 * If we are in this routine because of pause frames, then 1008 * don't reset the hardware. 1009 */ 1010 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) { 1011 ifp->if_timer = EMX_TX_TIMEOUT; 1012 return; 1013 } 1014 1015 if (e1000_check_for_link(&sc->hw) == 0) 1016 if_printf(ifp, "watchdog timeout -- resetting\n"); 1017 1018 ifp->if_oerrors++; 1019 sc->watchdog_events++; 1020 1021 emx_init(sc); 1022 1023 if (!ifq_is_empty(&ifp->if_snd)) 1024 if_devstart(ifp); 1025 } 1026 1027 static void 1028 emx_init(void *xsc) 1029 { 1030 struct emx_softc *sc = xsc; 1031 struct ifnet *ifp = &sc->arpcom.ac_if; 1032 device_t dev = sc->dev; 1033 uint32_t pba; 1034 int i; 1035 1036 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1037 1038 emx_stop(sc); 1039 1040 /* 1041 * Packet Buffer Allocation (PBA) 1042 * Writing PBA sets the receive portion of the buffer 1043 * the remainder is used for the transmit buffer. 1044 */ 1045 switch (sc->hw.mac.type) { 1046 /* Total Packet Buffer on these is 48K */ 1047 case e1000_82571: 1048 case e1000_82572: 1049 case e1000_80003es2lan: 1050 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 1051 break; 1052 1053 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 1054 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 1055 break; 1056 1057 case e1000_82574: 1058 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 1059 break; 1060 1061 default: 1062 /* Devices before 82547 had a Packet Buffer of 64K. */ 1063 if (sc->max_frame_size > 8192) 1064 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1065 else 1066 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1067 } 1068 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba); 1069 1070 /* Get the latest mac address, User can use a LAA */ 1071 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN); 1072 1073 /* Put the address into the Receive Address Array */ 1074 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1075 1076 /* 1077 * With the 82571 sc, RAR[0] may be overwritten 1078 * when the other port is reset, we make a duplicate 1079 * in RAR[14] for that eventuality, this assures 1080 * the interface continues to function. 1081 */ 1082 if (sc->hw.mac.type == e1000_82571) { 1083 e1000_set_laa_state_82571(&sc->hw, TRUE); 1084 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 1085 E1000_RAR_ENTRIES - 1); 1086 } 1087 1088 /* Initialize the hardware */ 1089 if (emx_reset(sc)) { 1090 device_printf(dev, "Unable to reset the hardware\n"); 1091 /* XXX emx_stop()? */ 1092 return; 1093 } 1094 emx_update_link_status(sc); 1095 1096 /* Setup VLAN support, basic and offload if available */ 1097 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1098 1099 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 1100 uint32_t ctrl; 1101 1102 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL); 1103 ctrl |= E1000_CTRL_VME; 1104 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl); 1105 } 1106 1107 /* Set hardware offload abilities */ 1108 if (ifp->if_capenable & IFCAP_TXCSUM) 1109 ifp->if_hwassist = EMX_CSUM_FEATURES; 1110 else 1111 ifp->if_hwassist = 0; 1112 1113 /* Configure for OS presence */ 1114 emx_get_mgmt(sc); 1115 1116 /* Prepare transmit descriptors and buffers */ 1117 emx_init_tx_ring(sc); 1118 emx_init_tx_unit(sc); 1119 1120 /* Setup Multicast table */ 1121 emx_set_multi(sc); 1122 1123 /* Prepare receive descriptors and buffers */ 1124 for (i = 0; i < sc->rx_ring_cnt; ++i) { 1125 if (emx_init_rx_ring(sc, &sc->rx_data[i])) { 1126 device_printf(dev, 1127 "Could not setup receive structures\n"); 1128 emx_stop(sc); 1129 return; 1130 } 1131 } 1132 emx_init_rx_unit(sc); 1133 1134 /* Don't lose promiscuous settings */ 1135 emx_set_promisc(sc); 1136 1137 ifp->if_flags |= IFF_RUNNING; 1138 ifp->if_flags &= ~IFF_OACTIVE; 1139 1140 callout_reset(&sc->timer, hz, emx_timer, sc); 1141 e1000_clear_hw_cntrs_base_generic(&sc->hw); 1142 1143 /* MSI/X configuration for 82574 */ 1144 if (sc->hw.mac.type == e1000_82574) { 1145 int tmp; 1146 1147 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 1148 tmp |= E1000_CTRL_EXT_PBA_CLR; 1149 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp); 1150 /* 1151 * XXX MSIX 1152 * Set the IVAR - interrupt vector routing. 1153 * Each nibble represents a vector, high bit 1154 * is enable, other 3 bits are the MSIX table 1155 * entry, we map RXQ0 to 0, TXQ0 to 1, and 1156 * Link (other) to 2, hence the magic number. 1157 */ 1158 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908); 1159 } 1160 1161 #ifdef IFPOLL_ENABLE 1162 /* 1163 * Only enable interrupts if we are not polling, make sure 1164 * they are off otherwise. 1165 */ 1166 if (ifp->if_flags & IFF_NPOLLING) 1167 emx_disable_intr(sc); 1168 else 1169 #endif /* IFPOLL_ENABLE */ 1170 emx_enable_intr(sc); 1171 1172 /* AMT based hardware can now take control from firmware */ 1173 if (sc->has_manage && sc->has_amt) 1174 emx_get_hw_control(sc); 1175 1176 /* Don't reset the phy next time init gets called */ 1177 sc->hw.phy.reset_disable = TRUE; 1178 } 1179 1180 static void 1181 emx_intr(void *xsc) 1182 { 1183 struct emx_softc *sc = xsc; 1184 struct ifnet *ifp = &sc->arpcom.ac_if; 1185 uint32_t reg_icr; 1186 1187 logif(intr_beg); 1188 ASSERT_SERIALIZED(&sc->main_serialize); 1189 1190 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1191 1192 if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0) { 1193 logif(intr_end); 1194 return; 1195 } 1196 1197 /* 1198 * XXX: some laptops trigger several spurious interrupts 1199 * on emx(4) when in the resume cycle. The ICR register 1200 * reports all-ones value in this case. Processing such 1201 * interrupts would lead to a freeze. I don't know why. 1202 */ 1203 if (reg_icr == 0xffffffff) { 1204 logif(intr_end); 1205 return; 1206 } 1207 1208 if (ifp->if_flags & IFF_RUNNING) { 1209 if (reg_icr & 1210 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) { 1211 int i; 1212 1213 for (i = 0; i < sc->rx_ring_cnt; ++i) { 1214 lwkt_serialize_enter( 1215 &sc->rx_data[i].rx_serialize); 1216 emx_rxeof(sc, i, -1); 1217 lwkt_serialize_exit( 1218 &sc->rx_data[i].rx_serialize); 1219 } 1220 } 1221 if (reg_icr & E1000_ICR_TXDW) { 1222 lwkt_serialize_enter(&sc->tx_serialize); 1223 emx_txeof(sc); 1224 if (!ifq_is_empty(&ifp->if_snd)) 1225 if_devstart(ifp); 1226 lwkt_serialize_exit(&sc->tx_serialize); 1227 } 1228 } 1229 1230 /* Link status change */ 1231 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1232 emx_serialize_skipmain(sc); 1233 1234 callout_stop(&sc->timer); 1235 sc->hw.mac.get_link_status = 1; 1236 emx_update_link_status(sc); 1237 1238 /* Deal with TX cruft when link lost */ 1239 emx_tx_purge(sc); 1240 1241 callout_reset(&sc->timer, hz, emx_timer, sc); 1242 1243 emx_deserialize_skipmain(sc); 1244 } 1245 1246 if (reg_icr & E1000_ICR_RXO) 1247 sc->rx_overruns++; 1248 1249 logif(intr_end); 1250 } 1251 1252 static void 1253 emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1254 { 1255 struct emx_softc *sc = ifp->if_softc; 1256 1257 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1258 1259 emx_update_link_status(sc); 1260 1261 ifmr->ifm_status = IFM_AVALID; 1262 ifmr->ifm_active = IFM_ETHER; 1263 1264 if (!sc->link_active) 1265 return; 1266 1267 ifmr->ifm_status |= IFM_ACTIVE; 1268 1269 if (sc->hw.phy.media_type == e1000_media_type_fiber || 1270 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 1271 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX; 1272 } else { 1273 switch (sc->link_speed) { 1274 case 10: 1275 ifmr->ifm_active |= IFM_10_T; 1276 break; 1277 case 100: 1278 ifmr->ifm_active |= IFM_100_TX; 1279 break; 1280 1281 case 1000: 1282 ifmr->ifm_active |= IFM_1000_T; 1283 break; 1284 } 1285 if (sc->link_duplex == FULL_DUPLEX) 1286 ifmr->ifm_active |= IFM_FDX; 1287 else 1288 ifmr->ifm_active |= IFM_HDX; 1289 } 1290 } 1291 1292 static int 1293 emx_media_change(struct ifnet *ifp) 1294 { 1295 struct emx_softc *sc = ifp->if_softc; 1296 struct ifmedia *ifm = &sc->media; 1297 1298 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1299 1300 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1301 return (EINVAL); 1302 1303 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1304 case IFM_AUTO: 1305 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG; 1306 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT; 1307 break; 1308 1309 case IFM_1000_LX: 1310 case IFM_1000_SX: 1311 case IFM_1000_T: 1312 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG; 1313 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1314 break; 1315 1316 case IFM_100_TX: 1317 sc->hw.mac.autoneg = FALSE; 1318 sc->hw.phy.autoneg_advertised = 0; 1319 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1320 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1321 else 1322 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1323 break; 1324 1325 case IFM_10_T: 1326 sc->hw.mac.autoneg = FALSE; 1327 sc->hw.phy.autoneg_advertised = 0; 1328 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1329 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1330 else 1331 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1332 break; 1333 1334 default: 1335 if_printf(ifp, "Unsupported media type\n"); 1336 break; 1337 } 1338 1339 /* 1340 * As the speed/duplex settings my have changed we need to 1341 * reset the PHY. 1342 */ 1343 sc->hw.phy.reset_disable = FALSE; 1344 1345 emx_init(sc); 1346 1347 return (0); 1348 } 1349 1350 static int 1351 emx_encap(struct emx_softc *sc, struct mbuf **m_headp) 1352 { 1353 bus_dma_segment_t segs[EMX_MAX_SCATTER]; 1354 bus_dmamap_t map; 1355 struct emx_txbuf *tx_buffer, *tx_buffer_mapped; 1356 struct e1000_tx_desc *ctxd = NULL; 1357 struct mbuf *m_head = *m_headp; 1358 uint32_t txd_upper, txd_lower, cmd = 0; 1359 int maxsegs, nsegs, i, j, first, last = 0, error; 1360 1361 if (m_head->m_len < EMX_TXCSUM_MINHL && 1362 (m_head->m_flags & EMX_CSUM_FEATURES)) { 1363 /* 1364 * Make sure that ethernet header and ip.ip_hl are in 1365 * contiguous memory, since if TXCSUM is enabled, later 1366 * TX context descriptor's setup need to access ip.ip_hl. 1367 */ 1368 error = emx_txcsum_pullup(sc, m_headp); 1369 if (error) { 1370 KKASSERT(*m_headp == NULL); 1371 return error; 1372 } 1373 m_head = *m_headp; 1374 } 1375 1376 txd_upper = txd_lower = 0; 1377 1378 /* 1379 * Capture the first descriptor index, this descriptor 1380 * will have the index of the EOP which is the only one 1381 * that now gets a DONE bit writeback. 1382 */ 1383 first = sc->next_avail_tx_desc; 1384 tx_buffer = &sc->tx_buf[first]; 1385 tx_buffer_mapped = tx_buffer; 1386 map = tx_buffer->map; 1387 1388 maxsegs = sc->num_tx_desc_avail - EMX_TX_RESERVED; 1389 KASSERT(maxsegs >= sc->spare_tx_desc, ("not enough spare TX desc")); 1390 if (maxsegs > EMX_MAX_SCATTER) 1391 maxsegs = EMX_MAX_SCATTER; 1392 1393 error = bus_dmamap_load_mbuf_defrag(sc->txtag, map, m_headp, 1394 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 1395 if (error) { 1396 if (error == ENOBUFS) 1397 sc->mbuf_alloc_failed++; 1398 else 1399 sc->no_tx_dma_setup++; 1400 1401 m_freem(*m_headp); 1402 *m_headp = NULL; 1403 return error; 1404 } 1405 bus_dmamap_sync(sc->txtag, map, BUS_DMASYNC_PREWRITE); 1406 1407 m_head = *m_headp; 1408 sc->tx_nsegs += nsegs; 1409 1410 if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) { 1411 /* TX csum offloading will consume one TX desc */ 1412 sc->tx_nsegs += emx_txcsum(sc, m_head, &txd_upper, &txd_lower); 1413 } 1414 i = sc->next_avail_tx_desc; 1415 1416 /* Set up our transmit descriptors */ 1417 for (j = 0; j < nsegs; j++) { 1418 tx_buffer = &sc->tx_buf[i]; 1419 ctxd = &sc->tx_desc_base[i]; 1420 1421 ctxd->buffer_addr = htole64(segs[j].ds_addr); 1422 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS | 1423 txd_lower | segs[j].ds_len); 1424 ctxd->upper.data = htole32(txd_upper); 1425 1426 last = i; 1427 if (++i == sc->num_tx_desc) 1428 i = 0; 1429 } 1430 1431 sc->next_avail_tx_desc = i; 1432 1433 KKASSERT(sc->num_tx_desc_avail > nsegs); 1434 sc->num_tx_desc_avail -= nsegs; 1435 1436 /* Handle VLAN tag */ 1437 if (m_head->m_flags & M_VLANTAG) { 1438 /* Set the vlan id. */ 1439 ctxd->upper.fields.special = 1440 htole16(m_head->m_pkthdr.ether_vlantag); 1441 1442 /* Tell hardware to add tag */ 1443 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE); 1444 } 1445 1446 tx_buffer->m_head = m_head; 1447 tx_buffer_mapped->map = tx_buffer->map; 1448 tx_buffer->map = map; 1449 1450 if (sc->tx_nsegs >= sc->tx_int_nsegs) { 1451 sc->tx_nsegs = 0; 1452 1453 /* 1454 * Report Status (RS) is turned on 1455 * every tx_int_nsegs descriptors. 1456 */ 1457 cmd = E1000_TXD_CMD_RS; 1458 1459 /* 1460 * Keep track of the descriptor, which will 1461 * be written back by hardware. 1462 */ 1463 sc->tx_dd[sc->tx_dd_tail] = last; 1464 EMX_INC_TXDD_IDX(sc->tx_dd_tail); 1465 KKASSERT(sc->tx_dd_tail != sc->tx_dd_head); 1466 } 1467 1468 /* 1469 * Last Descriptor of Packet needs End Of Packet (EOP) 1470 */ 1471 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd); 1472 1473 /* 1474 * Advance the Transmit Descriptor Tail (TDT), this tells 1475 * the E1000 that this frame is available to transmit. 1476 */ 1477 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), i); 1478 1479 return (0); 1480 } 1481 1482 static void 1483 emx_set_promisc(struct emx_softc *sc) 1484 { 1485 struct ifnet *ifp = &sc->arpcom.ac_if; 1486 uint32_t reg_rctl; 1487 1488 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1489 1490 if (ifp->if_flags & IFF_PROMISC) { 1491 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1492 /* Turn this on if you want to see bad packets */ 1493 if (emx_debug_sbp) 1494 reg_rctl |= E1000_RCTL_SBP; 1495 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1496 } else if (ifp->if_flags & IFF_ALLMULTI) { 1497 reg_rctl |= E1000_RCTL_MPE; 1498 reg_rctl &= ~E1000_RCTL_UPE; 1499 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1500 } 1501 } 1502 1503 static void 1504 emx_disable_promisc(struct emx_softc *sc) 1505 { 1506 uint32_t reg_rctl; 1507 1508 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1509 1510 reg_rctl &= ~E1000_RCTL_UPE; 1511 reg_rctl &= ~E1000_RCTL_MPE; 1512 reg_rctl &= ~E1000_RCTL_SBP; 1513 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1514 } 1515 1516 static void 1517 emx_set_multi(struct emx_softc *sc) 1518 { 1519 struct ifnet *ifp = &sc->arpcom.ac_if; 1520 struct ifmultiaddr *ifma; 1521 uint32_t reg_rctl = 0; 1522 uint8_t *mta; 1523 int mcnt = 0; 1524 1525 mta = sc->mta; 1526 bzero(mta, ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX); 1527 1528 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1529 if (ifma->ifma_addr->sa_family != AF_LINK) 1530 continue; 1531 1532 if (mcnt == EMX_MCAST_ADDR_MAX) 1533 break; 1534 1535 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1536 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1537 mcnt++; 1538 } 1539 1540 if (mcnt >= EMX_MCAST_ADDR_MAX) { 1541 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1542 reg_rctl |= E1000_RCTL_MPE; 1543 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1544 } else { 1545 e1000_update_mc_addr_list(&sc->hw, mta, mcnt); 1546 } 1547 } 1548 1549 /* 1550 * This routine checks for link status and updates statistics. 1551 */ 1552 static void 1553 emx_timer(void *xsc) 1554 { 1555 struct emx_softc *sc = xsc; 1556 struct ifnet *ifp = &sc->arpcom.ac_if; 1557 1558 ifnet_serialize_all(ifp); 1559 1560 emx_update_link_status(sc); 1561 emx_update_stats(sc); 1562 1563 /* Reset LAA into RAR[0] on 82571 */ 1564 if (e1000_get_laa_state_82571(&sc->hw) == TRUE) 1565 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1566 1567 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING)) 1568 emx_print_hw_stats(sc); 1569 1570 emx_smartspeed(sc); 1571 1572 callout_reset(&sc->timer, hz, emx_timer, sc); 1573 1574 ifnet_deserialize_all(ifp); 1575 } 1576 1577 static void 1578 emx_update_link_status(struct emx_softc *sc) 1579 { 1580 struct e1000_hw *hw = &sc->hw; 1581 struct ifnet *ifp = &sc->arpcom.ac_if; 1582 device_t dev = sc->dev; 1583 uint32_t link_check = 0; 1584 1585 /* Get the cached link value or read phy for real */ 1586 switch (hw->phy.media_type) { 1587 case e1000_media_type_copper: 1588 if (hw->mac.get_link_status) { 1589 /* Do the work to read phy */ 1590 e1000_check_for_link(hw); 1591 link_check = !hw->mac.get_link_status; 1592 if (link_check) /* ESB2 fix */ 1593 e1000_cfg_on_link_up(hw); 1594 } else { 1595 link_check = TRUE; 1596 } 1597 break; 1598 1599 case e1000_media_type_fiber: 1600 e1000_check_for_link(hw); 1601 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU; 1602 break; 1603 1604 case e1000_media_type_internal_serdes: 1605 e1000_check_for_link(hw); 1606 link_check = sc->hw.mac.serdes_has_link; 1607 break; 1608 1609 case e1000_media_type_unknown: 1610 default: 1611 break; 1612 } 1613 1614 /* Now check for a transition */ 1615 if (link_check && sc->link_active == 0) { 1616 e1000_get_speed_and_duplex(hw, &sc->link_speed, 1617 &sc->link_duplex); 1618 1619 /* 1620 * Check if we should enable/disable SPEED_MODE bit on 1621 * 82571EB/82572EI 1622 */ 1623 if (sc->link_speed != SPEED_1000 && 1624 (hw->mac.type == e1000_82571 || 1625 hw->mac.type == e1000_82572)) { 1626 int tarc0; 1627 1628 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1629 tarc0 &= ~EMX_TARC_SPEED_MODE; 1630 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1631 } 1632 if (bootverbose) { 1633 device_printf(dev, "Link is up %d Mbps %s\n", 1634 sc->link_speed, 1635 ((sc->link_duplex == FULL_DUPLEX) ? 1636 "Full Duplex" : "Half Duplex")); 1637 } 1638 sc->link_active = 1; 1639 sc->smartspeed = 0; 1640 ifp->if_baudrate = sc->link_speed * 1000000; 1641 ifp->if_link_state = LINK_STATE_UP; 1642 if_link_state_change(ifp); 1643 } else if (!link_check && sc->link_active == 1) { 1644 ifp->if_baudrate = sc->link_speed = 0; 1645 sc->link_duplex = 0; 1646 if (bootverbose) 1647 device_printf(dev, "Link is Down\n"); 1648 sc->link_active = 0; 1649 #if 0 1650 /* Link down, disable watchdog */ 1651 if->if_timer = 0; 1652 #endif 1653 ifp->if_link_state = LINK_STATE_DOWN; 1654 if_link_state_change(ifp); 1655 } 1656 } 1657 1658 static void 1659 emx_stop(struct emx_softc *sc) 1660 { 1661 struct ifnet *ifp = &sc->arpcom.ac_if; 1662 int i; 1663 1664 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1665 1666 emx_disable_intr(sc); 1667 1668 callout_stop(&sc->timer); 1669 1670 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1671 ifp->if_timer = 0; 1672 1673 /* 1674 * Disable multiple receive queues. 1675 * 1676 * NOTE: 1677 * We should disable multiple receive queues before 1678 * resetting the hardware. 1679 */ 1680 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0); 1681 1682 e1000_reset_hw(&sc->hw); 1683 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0); 1684 1685 for (i = 0; i < sc->num_tx_desc; i++) { 1686 struct emx_txbuf *tx_buffer = &sc->tx_buf[i]; 1687 1688 if (tx_buffer->m_head != NULL) { 1689 bus_dmamap_unload(sc->txtag, tx_buffer->map); 1690 m_freem(tx_buffer->m_head); 1691 tx_buffer->m_head = NULL; 1692 } 1693 } 1694 1695 for (i = 0; i < sc->rx_ring_cnt; ++i) 1696 emx_free_rx_ring(sc, &sc->rx_data[i]); 1697 1698 sc->csum_flags = 0; 1699 sc->csum_ehlen = 0; 1700 sc->csum_iphlen = 0; 1701 1702 sc->tx_dd_head = 0; 1703 sc->tx_dd_tail = 0; 1704 sc->tx_nsegs = 0; 1705 } 1706 1707 static int 1708 emx_reset(struct emx_softc *sc) 1709 { 1710 device_t dev = sc->dev; 1711 uint16_t rx_buffer_size; 1712 1713 /* Set up smart power down as default off on newer adapters. */ 1714 if (!emx_smart_pwr_down && 1715 (sc->hw.mac.type == e1000_82571 || 1716 sc->hw.mac.type == e1000_82572)) { 1717 uint16_t phy_tmp = 0; 1718 1719 /* Speed up time to link by disabling smart power down. */ 1720 e1000_read_phy_reg(&sc->hw, 1721 IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 1722 phy_tmp &= ~IGP02E1000_PM_SPD; 1723 e1000_write_phy_reg(&sc->hw, 1724 IGP02E1000_PHY_POWER_MGMT, phy_tmp); 1725 } 1726 1727 /* 1728 * These parameters control the automatic generation (Tx) and 1729 * response (Rx) to Ethernet PAUSE frames. 1730 * - High water mark should allow for at least two frames to be 1731 * received after sending an XOFF. 1732 * - Low water mark works best when it is very near the high water mark. 1733 * This allows the receiver to restart by sending XON when it has 1734 * drained a bit. Here we use an arbitary value of 1500 which will 1735 * restart after one full frame is pulled from the buffer. There 1736 * could be several smaller frames in the buffer and if so they will 1737 * not trigger the XON until their total number reduces the buffer 1738 * by 1500. 1739 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 1740 */ 1741 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10; 1742 1743 sc->hw.fc.high_water = rx_buffer_size - 1744 roundup2(sc->max_frame_size, 1024); 1745 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500; 1746 1747 if (sc->hw.mac.type == e1000_80003es2lan) 1748 sc->hw.fc.pause_time = 0xFFFF; 1749 else 1750 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME; 1751 sc->hw.fc.send_xon = TRUE; 1752 sc->hw.fc.requested_mode = e1000_fc_full; 1753 1754 /* Issue a global reset */ 1755 e1000_reset_hw(&sc->hw); 1756 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0); 1757 emx_disable_aspm(sc); 1758 1759 if (e1000_init_hw(&sc->hw) < 0) { 1760 device_printf(dev, "Hardware Initialization Failed\n"); 1761 return (EIO); 1762 } 1763 1764 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1765 e1000_get_phy_info(&sc->hw); 1766 e1000_check_for_link(&sc->hw); 1767 1768 return (0); 1769 } 1770 1771 static void 1772 emx_setup_ifp(struct emx_softc *sc) 1773 { 1774 struct ifnet *ifp = &sc->arpcom.ac_if; 1775 1776 if_initname(ifp, device_get_name(sc->dev), 1777 device_get_unit(sc->dev)); 1778 ifp->if_softc = sc; 1779 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1780 ifp->if_init = emx_init; 1781 ifp->if_ioctl = emx_ioctl; 1782 ifp->if_start = emx_start; 1783 #ifdef IFPOLL_ENABLE 1784 ifp->if_qpoll = emx_qpoll; 1785 #endif 1786 ifp->if_watchdog = emx_watchdog; 1787 ifp->if_serialize = emx_serialize; 1788 ifp->if_deserialize = emx_deserialize; 1789 ifp->if_tryserialize = emx_tryserialize; 1790 #ifdef INVARIANTS 1791 ifp->if_serialize_assert = emx_serialize_assert; 1792 #endif 1793 ifq_set_maxlen(&ifp->if_snd, sc->num_tx_desc - 1); 1794 ifq_set_ready(&ifp->if_snd); 1795 1796 ether_ifattach(ifp, sc->hw.mac.addr, NULL); 1797 1798 ifp->if_capabilities = IFCAP_HWCSUM | 1799 IFCAP_VLAN_HWTAGGING | 1800 IFCAP_VLAN_MTU; 1801 if (sc->rx_ring_cnt > 1) 1802 ifp->if_capabilities |= IFCAP_RSS; 1803 ifp->if_capenable = ifp->if_capabilities; 1804 ifp->if_hwassist = EMX_CSUM_FEATURES; 1805 1806 /* 1807 * Tell the upper layer(s) we support long frames. 1808 */ 1809 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1810 1811 /* 1812 * Specify the media types supported by this sc and register 1813 * callbacks to update media and link information 1814 */ 1815 ifmedia_init(&sc->media, IFM_IMASK, 1816 emx_media_change, emx_media_status); 1817 if (sc->hw.phy.media_type == e1000_media_type_fiber || 1818 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 1819 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX, 1820 0, NULL); 1821 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL); 1822 } else { 1823 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 1824 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 1825 0, NULL); 1826 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 1827 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 1828 0, NULL); 1829 if (sc->hw.phy.type != e1000_phy_ife) { 1830 ifmedia_add(&sc->media, 1831 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 1832 ifmedia_add(&sc->media, 1833 IFM_ETHER | IFM_1000_T, 0, NULL); 1834 } 1835 } 1836 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 1837 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO); 1838 } 1839 1840 /* 1841 * Workaround for SmartSpeed on 82541 and 82547 controllers 1842 */ 1843 static void 1844 emx_smartspeed(struct emx_softc *sc) 1845 { 1846 uint16_t phy_tmp; 1847 1848 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp || 1849 sc->hw.mac.autoneg == 0 || 1850 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 1851 return; 1852 1853 if (sc->smartspeed == 0) { 1854 /* 1855 * If Master/Slave config fault is asserted twice, 1856 * we assume back-to-back 1857 */ 1858 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 1859 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 1860 return; 1861 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 1862 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 1863 e1000_read_phy_reg(&sc->hw, 1864 PHY_1000T_CTRL, &phy_tmp); 1865 if (phy_tmp & CR_1000T_MS_ENABLE) { 1866 phy_tmp &= ~CR_1000T_MS_ENABLE; 1867 e1000_write_phy_reg(&sc->hw, 1868 PHY_1000T_CTRL, phy_tmp); 1869 sc->smartspeed++; 1870 if (sc->hw.mac.autoneg && 1871 !e1000_phy_setup_autoneg(&sc->hw) && 1872 !e1000_read_phy_reg(&sc->hw, 1873 PHY_CONTROL, &phy_tmp)) { 1874 phy_tmp |= MII_CR_AUTO_NEG_EN | 1875 MII_CR_RESTART_AUTO_NEG; 1876 e1000_write_phy_reg(&sc->hw, 1877 PHY_CONTROL, phy_tmp); 1878 } 1879 } 1880 } 1881 return; 1882 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) { 1883 /* If still no link, perhaps using 2/3 pair cable */ 1884 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 1885 phy_tmp |= CR_1000T_MS_ENABLE; 1886 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 1887 if (sc->hw.mac.autoneg && 1888 !e1000_phy_setup_autoneg(&sc->hw) && 1889 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) { 1890 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG; 1891 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp); 1892 } 1893 } 1894 1895 /* Restart process after EMX_SMARTSPEED_MAX iterations */ 1896 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX) 1897 sc->smartspeed = 0; 1898 } 1899 1900 static int 1901 emx_create_tx_ring(struct emx_softc *sc) 1902 { 1903 device_t dev = sc->dev; 1904 struct emx_txbuf *tx_buffer; 1905 int error, i, tsize, ntxd; 1906 1907 /* 1908 * Validate number of transmit descriptors. It must not exceed 1909 * hardware maximum, and must be multiple of E1000_DBA_ALIGN. 1910 */ 1911 ntxd = device_getenv_int(dev, "txd", emx_txd); 1912 if ((ntxd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 || 1913 ntxd > EMX_MAX_TXD || ntxd < EMX_MIN_TXD) { 1914 device_printf(dev, "Using %d TX descriptors instead of %d!\n", 1915 EMX_DEFAULT_TXD, ntxd); 1916 sc->num_tx_desc = EMX_DEFAULT_TXD; 1917 } else { 1918 sc->num_tx_desc = ntxd; 1919 } 1920 1921 /* 1922 * Allocate Transmit Descriptor ring 1923 */ 1924 tsize = roundup2(sc->num_tx_desc * sizeof(struct e1000_tx_desc), 1925 EMX_DBA_ALIGN); 1926 sc->tx_desc_base = bus_dmamem_coherent_any(sc->parent_dtag, 1927 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK, 1928 &sc->tx_desc_dtag, &sc->tx_desc_dmap, 1929 &sc->tx_desc_paddr); 1930 if (sc->tx_desc_base == NULL) { 1931 device_printf(dev, "Unable to allocate tx_desc memory\n"); 1932 return ENOMEM; 1933 } 1934 1935 sc->tx_buf = kmalloc(sizeof(struct emx_txbuf) * sc->num_tx_desc, 1936 M_DEVBUF, M_WAITOK | M_ZERO); 1937 1938 /* 1939 * Create DMA tags for tx buffers 1940 */ 1941 error = bus_dma_tag_create(sc->parent_dtag, /* parent */ 1942 1, 0, /* alignment, bounds */ 1943 BUS_SPACE_MAXADDR, /* lowaddr */ 1944 BUS_SPACE_MAXADDR, /* highaddr */ 1945 NULL, NULL, /* filter, filterarg */ 1946 EMX_TSO_SIZE, /* maxsize */ 1947 EMX_MAX_SCATTER, /* nsegments */ 1948 EMX_MAX_SEGSIZE, /* maxsegsize */ 1949 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | 1950 BUS_DMA_ONEBPAGE, /* flags */ 1951 &sc->txtag); 1952 if (error) { 1953 device_printf(dev, "Unable to allocate TX DMA tag\n"); 1954 kfree(sc->tx_buf, M_DEVBUF); 1955 sc->tx_buf = NULL; 1956 return error; 1957 } 1958 1959 /* 1960 * Create DMA maps for tx buffers 1961 */ 1962 for (i = 0; i < sc->num_tx_desc; i++) { 1963 tx_buffer = &sc->tx_buf[i]; 1964 1965 error = bus_dmamap_create(sc->txtag, 1966 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 1967 &tx_buffer->map); 1968 if (error) { 1969 device_printf(dev, "Unable to create TX DMA map\n"); 1970 emx_destroy_tx_ring(sc, i); 1971 return error; 1972 } 1973 } 1974 return (0); 1975 } 1976 1977 static void 1978 emx_init_tx_ring(struct emx_softc *sc) 1979 { 1980 /* Clear the old ring contents */ 1981 bzero(sc->tx_desc_base, 1982 sizeof(struct e1000_tx_desc) * sc->num_tx_desc); 1983 1984 /* Reset state */ 1985 sc->next_avail_tx_desc = 0; 1986 sc->next_tx_to_clean = 0; 1987 sc->num_tx_desc_avail = sc->num_tx_desc; 1988 } 1989 1990 static void 1991 emx_init_tx_unit(struct emx_softc *sc) 1992 { 1993 uint32_t tctl, tarc, tipg = 0; 1994 uint64_t bus_addr; 1995 1996 /* Setup the Base and Length of the Tx Descriptor Ring */ 1997 bus_addr = sc->tx_desc_paddr; 1998 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(0), 1999 sc->num_tx_desc * sizeof(struct e1000_tx_desc)); 2000 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(0), 2001 (uint32_t)(bus_addr >> 32)); 2002 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(0), 2003 (uint32_t)bus_addr); 2004 /* Setup the HW Tx Head and Tail descriptor pointers */ 2005 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), 0); 2006 E1000_WRITE_REG(&sc->hw, E1000_TDH(0), 0); 2007 2008 /* Set the default values for the Tx Inter Packet Gap timer */ 2009 switch (sc->hw.mac.type) { 2010 case e1000_80003es2lan: 2011 tipg = DEFAULT_82543_TIPG_IPGR1; 2012 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 2013 E1000_TIPG_IPGR2_SHIFT; 2014 break; 2015 2016 default: 2017 if (sc->hw.phy.media_type == e1000_media_type_fiber || 2018 sc->hw.phy.media_type == e1000_media_type_internal_serdes) 2019 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2020 else 2021 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2022 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2023 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2024 break; 2025 } 2026 2027 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg); 2028 2029 /* NOTE: 0 is not allowed for TIDV */ 2030 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1); 2031 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0); 2032 2033 if (sc->hw.mac.type == e1000_82571 || 2034 sc->hw.mac.type == e1000_82572) { 2035 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0)); 2036 tarc |= EMX_TARC_SPEED_MODE; 2037 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc); 2038 } else if (sc->hw.mac.type == e1000_80003es2lan) { 2039 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0)); 2040 tarc |= 1; 2041 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc); 2042 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1)); 2043 tarc |= 1; 2044 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc); 2045 } 2046 2047 /* Program the Transmit Control Register */ 2048 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL); 2049 tctl &= ~E1000_TCTL_CT; 2050 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 2051 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2052 tctl |= E1000_TCTL_MULR; 2053 2054 /* This write will effectively turn on the transmit unit. */ 2055 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl); 2056 } 2057 2058 static void 2059 emx_destroy_tx_ring(struct emx_softc *sc, int ndesc) 2060 { 2061 struct emx_txbuf *tx_buffer; 2062 int i; 2063 2064 /* Free Transmit Descriptor ring */ 2065 if (sc->tx_desc_base) { 2066 bus_dmamap_unload(sc->tx_desc_dtag, sc->tx_desc_dmap); 2067 bus_dmamem_free(sc->tx_desc_dtag, sc->tx_desc_base, 2068 sc->tx_desc_dmap); 2069 bus_dma_tag_destroy(sc->tx_desc_dtag); 2070 2071 sc->tx_desc_base = NULL; 2072 } 2073 2074 if (sc->tx_buf == NULL) 2075 return; 2076 2077 for (i = 0; i < ndesc; i++) { 2078 tx_buffer = &sc->tx_buf[i]; 2079 2080 KKASSERT(tx_buffer->m_head == NULL); 2081 bus_dmamap_destroy(sc->txtag, tx_buffer->map); 2082 } 2083 bus_dma_tag_destroy(sc->txtag); 2084 2085 kfree(sc->tx_buf, M_DEVBUF); 2086 sc->tx_buf = NULL; 2087 } 2088 2089 /* 2090 * The offload context needs to be set when we transfer the first 2091 * packet of a particular protocol (TCP/UDP). This routine has been 2092 * enhanced to deal with inserted VLAN headers. 2093 * 2094 * If the new packet's ether header length, ip header length and 2095 * csum offloading type are same as the previous packet, we should 2096 * avoid allocating a new csum context descriptor; mainly to take 2097 * advantage of the pipeline effect of the TX data read request. 2098 * 2099 * This function returns number of TX descrptors allocated for 2100 * csum context. 2101 */ 2102 static int 2103 emx_txcsum(struct emx_softc *sc, struct mbuf *mp, 2104 uint32_t *txd_upper, uint32_t *txd_lower) 2105 { 2106 struct e1000_context_desc *TXD; 2107 struct emx_txbuf *tx_buffer; 2108 struct ether_vlan_header *eh; 2109 struct ip *ip; 2110 int curr_txd, ehdrlen, csum_flags; 2111 uint32_t cmd, hdr_len, ip_hlen; 2112 uint16_t etype; 2113 2114 /* 2115 * Determine where frame payload starts. 2116 * Jump over vlan headers if already present, 2117 * helpful for QinQ too. 2118 */ 2119 KASSERT(mp->m_len >= ETHER_HDR_LEN, 2120 ("emx_txcsum_pullup is not called (eh)?")); 2121 eh = mtod(mp, struct ether_vlan_header *); 2122 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2123 KASSERT(mp->m_len >= ETHER_HDR_LEN + EVL_ENCAPLEN, 2124 ("emx_txcsum_pullup is not called (evh)?")); 2125 etype = ntohs(eh->evl_proto); 2126 ehdrlen = ETHER_HDR_LEN + EVL_ENCAPLEN; 2127 } else { 2128 etype = ntohs(eh->evl_encap_proto); 2129 ehdrlen = ETHER_HDR_LEN; 2130 } 2131 2132 /* 2133 * We only support TCP/UDP for IPv4 for the moment. 2134 * TODO: Support SCTP too when it hits the tree. 2135 */ 2136 if (etype != ETHERTYPE_IP) 2137 return 0; 2138 2139 KASSERT(mp->m_len >= ehdrlen + EMX_IPVHL_SIZE, 2140 ("emx_txcsum_pullup is not called (eh+ip_vhl)?")); 2141 2142 /* NOTE: We could only safely access ip.ip_vhl part */ 2143 ip = (struct ip *)(mp->m_data + ehdrlen); 2144 ip_hlen = ip->ip_hl << 2; 2145 2146 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES; 2147 2148 if (sc->csum_ehlen == ehdrlen && sc->csum_iphlen == ip_hlen && 2149 sc->csum_flags == csum_flags) { 2150 /* 2151 * Same csum offload context as the previous packets; 2152 * just return. 2153 */ 2154 *txd_upper = sc->csum_txd_upper; 2155 *txd_lower = sc->csum_txd_lower; 2156 return 0; 2157 } 2158 2159 /* 2160 * Setup a new csum offload context. 2161 */ 2162 2163 curr_txd = sc->next_avail_tx_desc; 2164 tx_buffer = &sc->tx_buf[curr_txd]; 2165 TXD = (struct e1000_context_desc *)&sc->tx_desc_base[curr_txd]; 2166 2167 cmd = 0; 2168 2169 /* Setup of IP header checksum. */ 2170 if (csum_flags & CSUM_IP) { 2171 /* 2172 * Start offset for header checksum calculation. 2173 * End offset for header checksum calculation. 2174 * Offset of place to put the checksum. 2175 */ 2176 TXD->lower_setup.ip_fields.ipcss = ehdrlen; 2177 TXD->lower_setup.ip_fields.ipcse = 2178 htole16(ehdrlen + ip_hlen - 1); 2179 TXD->lower_setup.ip_fields.ipcso = 2180 ehdrlen + offsetof(struct ip, ip_sum); 2181 cmd |= E1000_TXD_CMD_IP; 2182 *txd_upper |= E1000_TXD_POPTS_IXSM << 8; 2183 } 2184 hdr_len = ehdrlen + ip_hlen; 2185 2186 if (csum_flags & CSUM_TCP) { 2187 /* 2188 * Start offset for payload checksum calculation. 2189 * End offset for payload checksum calculation. 2190 * Offset of place to put the checksum. 2191 */ 2192 TXD->upper_setup.tcp_fields.tucss = hdr_len; 2193 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2194 TXD->upper_setup.tcp_fields.tucso = 2195 hdr_len + offsetof(struct tcphdr, th_sum); 2196 cmd |= E1000_TXD_CMD_TCP; 2197 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 2198 } else if (csum_flags & CSUM_UDP) { 2199 /* 2200 * Start offset for header checksum calculation. 2201 * End offset for header checksum calculation. 2202 * Offset of place to put the checksum. 2203 */ 2204 TXD->upper_setup.tcp_fields.tucss = hdr_len; 2205 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2206 TXD->upper_setup.tcp_fields.tucso = 2207 hdr_len + offsetof(struct udphdr, uh_sum); 2208 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 2209 } 2210 2211 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */ 2212 E1000_TXD_DTYP_D; /* Data descr */ 2213 2214 /* Save the information for this csum offloading context */ 2215 sc->csum_ehlen = ehdrlen; 2216 sc->csum_iphlen = ip_hlen; 2217 sc->csum_flags = csum_flags; 2218 sc->csum_txd_upper = *txd_upper; 2219 sc->csum_txd_lower = *txd_lower; 2220 2221 TXD->tcp_seg_setup.data = htole32(0); 2222 TXD->cmd_and_length = 2223 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd); 2224 2225 if (++curr_txd == sc->num_tx_desc) 2226 curr_txd = 0; 2227 2228 KKASSERT(sc->num_tx_desc_avail > 0); 2229 sc->num_tx_desc_avail--; 2230 2231 sc->next_avail_tx_desc = curr_txd; 2232 return 1; 2233 } 2234 2235 static int 2236 emx_txcsum_pullup(struct emx_softc *sc, struct mbuf **m0) 2237 { 2238 struct mbuf *m = *m0; 2239 struct ether_header *eh; 2240 int len; 2241 2242 sc->tx_csum_try_pullup++; 2243 2244 len = ETHER_HDR_LEN + EMX_IPVHL_SIZE; 2245 2246 if (__predict_false(!M_WRITABLE(m))) { 2247 if (__predict_false(m->m_len < ETHER_HDR_LEN)) { 2248 sc->tx_csum_drop1++; 2249 m_freem(m); 2250 *m0 = NULL; 2251 return ENOBUFS; 2252 } 2253 eh = mtod(m, struct ether_header *); 2254 2255 if (eh->ether_type == htons(ETHERTYPE_VLAN)) 2256 len += EVL_ENCAPLEN; 2257 2258 if (m->m_len < len) { 2259 sc->tx_csum_drop2++; 2260 m_freem(m); 2261 *m0 = NULL; 2262 return ENOBUFS; 2263 } 2264 return 0; 2265 } 2266 2267 if (__predict_false(m->m_len < ETHER_HDR_LEN)) { 2268 sc->tx_csum_pullup1++; 2269 m = m_pullup(m, ETHER_HDR_LEN); 2270 if (m == NULL) { 2271 sc->tx_csum_pullup1_failed++; 2272 *m0 = NULL; 2273 return ENOBUFS; 2274 } 2275 *m0 = m; 2276 } 2277 eh = mtod(m, struct ether_header *); 2278 2279 if (eh->ether_type == htons(ETHERTYPE_VLAN)) 2280 len += EVL_ENCAPLEN; 2281 2282 if (m->m_len < len) { 2283 sc->tx_csum_pullup2++; 2284 m = m_pullup(m, len); 2285 if (m == NULL) { 2286 sc->tx_csum_pullup2_failed++; 2287 *m0 = NULL; 2288 return ENOBUFS; 2289 } 2290 *m0 = m; 2291 } 2292 return 0; 2293 } 2294 2295 static void 2296 emx_txeof(struct emx_softc *sc) 2297 { 2298 struct ifnet *ifp = &sc->arpcom.ac_if; 2299 struct emx_txbuf *tx_buffer; 2300 int first, num_avail; 2301 2302 if (sc->tx_dd_head == sc->tx_dd_tail) 2303 return; 2304 2305 if (sc->num_tx_desc_avail == sc->num_tx_desc) 2306 return; 2307 2308 num_avail = sc->num_tx_desc_avail; 2309 first = sc->next_tx_to_clean; 2310 2311 while (sc->tx_dd_head != sc->tx_dd_tail) { 2312 int dd_idx = sc->tx_dd[sc->tx_dd_head]; 2313 struct e1000_tx_desc *tx_desc; 2314 2315 tx_desc = &sc->tx_desc_base[dd_idx]; 2316 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) { 2317 EMX_INC_TXDD_IDX(sc->tx_dd_head); 2318 2319 if (++dd_idx == sc->num_tx_desc) 2320 dd_idx = 0; 2321 2322 while (first != dd_idx) { 2323 logif(pkt_txclean); 2324 2325 num_avail++; 2326 2327 tx_buffer = &sc->tx_buf[first]; 2328 if (tx_buffer->m_head) { 2329 ifp->if_opackets++; 2330 bus_dmamap_unload(sc->txtag, 2331 tx_buffer->map); 2332 m_freem(tx_buffer->m_head); 2333 tx_buffer->m_head = NULL; 2334 } 2335 2336 if (++first == sc->num_tx_desc) 2337 first = 0; 2338 } 2339 } else { 2340 break; 2341 } 2342 } 2343 sc->next_tx_to_clean = first; 2344 sc->num_tx_desc_avail = num_avail; 2345 2346 if (sc->tx_dd_head == sc->tx_dd_tail) { 2347 sc->tx_dd_head = 0; 2348 sc->tx_dd_tail = 0; 2349 } 2350 2351 if (!EMX_IS_OACTIVE(sc)) { 2352 ifp->if_flags &= ~IFF_OACTIVE; 2353 2354 /* All clean, turn off the timer */ 2355 if (sc->num_tx_desc_avail == sc->num_tx_desc) 2356 ifp->if_timer = 0; 2357 } 2358 } 2359 2360 static void 2361 emx_tx_collect(struct emx_softc *sc) 2362 { 2363 struct ifnet *ifp = &sc->arpcom.ac_if; 2364 struct emx_txbuf *tx_buffer; 2365 int tdh, first, num_avail, dd_idx = -1; 2366 2367 if (sc->num_tx_desc_avail == sc->num_tx_desc) 2368 return; 2369 2370 tdh = E1000_READ_REG(&sc->hw, E1000_TDH(0)); 2371 if (tdh == sc->next_tx_to_clean) 2372 return; 2373 2374 if (sc->tx_dd_head != sc->tx_dd_tail) 2375 dd_idx = sc->tx_dd[sc->tx_dd_head]; 2376 2377 num_avail = sc->num_tx_desc_avail; 2378 first = sc->next_tx_to_clean; 2379 2380 while (first != tdh) { 2381 logif(pkt_txclean); 2382 2383 num_avail++; 2384 2385 tx_buffer = &sc->tx_buf[first]; 2386 if (tx_buffer->m_head) { 2387 ifp->if_opackets++; 2388 bus_dmamap_unload(sc->txtag, 2389 tx_buffer->map); 2390 m_freem(tx_buffer->m_head); 2391 tx_buffer->m_head = NULL; 2392 } 2393 2394 if (first == dd_idx) { 2395 EMX_INC_TXDD_IDX(sc->tx_dd_head); 2396 if (sc->tx_dd_head == sc->tx_dd_tail) { 2397 sc->tx_dd_head = 0; 2398 sc->tx_dd_tail = 0; 2399 dd_idx = -1; 2400 } else { 2401 dd_idx = sc->tx_dd[sc->tx_dd_head]; 2402 } 2403 } 2404 2405 if (++first == sc->num_tx_desc) 2406 first = 0; 2407 } 2408 sc->next_tx_to_clean = first; 2409 sc->num_tx_desc_avail = num_avail; 2410 2411 if (!EMX_IS_OACTIVE(sc)) { 2412 ifp->if_flags &= ~IFF_OACTIVE; 2413 2414 /* All clean, turn off the timer */ 2415 if (sc->num_tx_desc_avail == sc->num_tx_desc) 2416 ifp->if_timer = 0; 2417 } 2418 } 2419 2420 /* 2421 * When Link is lost sometimes there is work still in the TX ring 2422 * which will result in a watchdog, rather than allow that do an 2423 * attempted cleanup and then reinit here. Note that this has been 2424 * seens mostly with fiber adapters. 2425 */ 2426 static void 2427 emx_tx_purge(struct emx_softc *sc) 2428 { 2429 struct ifnet *ifp = &sc->arpcom.ac_if; 2430 2431 if (!sc->link_active && ifp->if_timer) { 2432 emx_tx_collect(sc); 2433 if (ifp->if_timer) { 2434 if_printf(ifp, "Link lost, TX pending, reinit\n"); 2435 ifp->if_timer = 0; 2436 emx_init(sc); 2437 } 2438 } 2439 } 2440 2441 static int 2442 emx_newbuf(struct emx_softc *sc, struct emx_rxdata *rdata, int i, int init) 2443 { 2444 struct mbuf *m; 2445 bus_dma_segment_t seg; 2446 bus_dmamap_t map; 2447 struct emx_rxbuf *rx_buffer; 2448 int error, nseg; 2449 2450 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 2451 if (m == NULL) { 2452 rdata->mbuf_cluster_failed++; 2453 if (init) { 2454 if_printf(&sc->arpcom.ac_if, 2455 "Unable to allocate RX mbuf\n"); 2456 } 2457 return (ENOBUFS); 2458 } 2459 m->m_len = m->m_pkthdr.len = MCLBYTES; 2460 2461 if (sc->max_frame_size <= MCLBYTES - ETHER_ALIGN) 2462 m_adj(m, ETHER_ALIGN); 2463 2464 error = bus_dmamap_load_mbuf_segment(rdata->rxtag, 2465 rdata->rx_sparemap, m, 2466 &seg, 1, &nseg, BUS_DMA_NOWAIT); 2467 if (error) { 2468 m_freem(m); 2469 if (init) { 2470 if_printf(&sc->arpcom.ac_if, 2471 "Unable to load RX mbuf\n"); 2472 } 2473 return (error); 2474 } 2475 2476 rx_buffer = &rdata->rx_buf[i]; 2477 if (rx_buffer->m_head != NULL) 2478 bus_dmamap_unload(rdata->rxtag, rx_buffer->map); 2479 2480 map = rx_buffer->map; 2481 rx_buffer->map = rdata->rx_sparemap; 2482 rdata->rx_sparemap = map; 2483 2484 rx_buffer->m_head = m; 2485 rx_buffer->paddr = seg.ds_addr; 2486 2487 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer); 2488 return (0); 2489 } 2490 2491 static int 2492 emx_create_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata) 2493 { 2494 device_t dev = sc->dev; 2495 struct emx_rxbuf *rx_buffer; 2496 int i, error, rsize, nrxd; 2497 2498 /* 2499 * Validate number of receive descriptors. It must not exceed 2500 * hardware maximum, and must be multiple of E1000_DBA_ALIGN. 2501 */ 2502 nrxd = device_getenv_int(dev, "rxd", emx_rxd); 2503 if ((nrxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 || 2504 nrxd > EMX_MAX_RXD || nrxd < EMX_MIN_RXD) { 2505 device_printf(dev, "Using %d RX descriptors instead of %d!\n", 2506 EMX_DEFAULT_RXD, nrxd); 2507 rdata->num_rx_desc = EMX_DEFAULT_RXD; 2508 } else { 2509 rdata->num_rx_desc = nrxd; 2510 } 2511 2512 /* 2513 * Allocate Receive Descriptor ring 2514 */ 2515 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t), 2516 EMX_DBA_ALIGN); 2517 rdata->rx_desc = bus_dmamem_coherent_any(sc->parent_dtag, 2518 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK, 2519 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap, 2520 &rdata->rx_desc_paddr); 2521 if (rdata->rx_desc == NULL) { 2522 device_printf(dev, "Unable to allocate rx_desc memory\n"); 2523 return ENOMEM; 2524 } 2525 2526 rdata->rx_buf = kmalloc(sizeof(struct emx_rxbuf) * rdata->num_rx_desc, 2527 M_DEVBUF, M_WAITOK | M_ZERO); 2528 2529 /* 2530 * Create DMA tag for rx buffers 2531 */ 2532 error = bus_dma_tag_create(sc->parent_dtag, /* parent */ 2533 1, 0, /* alignment, bounds */ 2534 BUS_SPACE_MAXADDR, /* lowaddr */ 2535 BUS_SPACE_MAXADDR, /* highaddr */ 2536 NULL, NULL, /* filter, filterarg */ 2537 MCLBYTES, /* maxsize */ 2538 1, /* nsegments */ 2539 MCLBYTES, /* maxsegsize */ 2540 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */ 2541 &rdata->rxtag); 2542 if (error) { 2543 device_printf(dev, "Unable to allocate RX DMA tag\n"); 2544 kfree(rdata->rx_buf, M_DEVBUF); 2545 rdata->rx_buf = NULL; 2546 return error; 2547 } 2548 2549 /* 2550 * Create spare DMA map for rx buffers 2551 */ 2552 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK, 2553 &rdata->rx_sparemap); 2554 if (error) { 2555 device_printf(dev, "Unable to create spare RX DMA map\n"); 2556 bus_dma_tag_destroy(rdata->rxtag); 2557 kfree(rdata->rx_buf, M_DEVBUF); 2558 rdata->rx_buf = NULL; 2559 return error; 2560 } 2561 2562 /* 2563 * Create DMA maps for rx buffers 2564 */ 2565 for (i = 0; i < rdata->num_rx_desc; i++) { 2566 rx_buffer = &rdata->rx_buf[i]; 2567 2568 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK, 2569 &rx_buffer->map); 2570 if (error) { 2571 device_printf(dev, "Unable to create RX DMA map\n"); 2572 emx_destroy_rx_ring(sc, rdata, i); 2573 return error; 2574 } 2575 } 2576 return (0); 2577 } 2578 2579 static void 2580 emx_free_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata) 2581 { 2582 int i; 2583 2584 for (i = 0; i < rdata->num_rx_desc; i++) { 2585 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i]; 2586 2587 if (rx_buffer->m_head != NULL) { 2588 bus_dmamap_unload(rdata->rxtag, rx_buffer->map); 2589 m_freem(rx_buffer->m_head); 2590 rx_buffer->m_head = NULL; 2591 } 2592 } 2593 2594 if (rdata->fmp != NULL) 2595 m_freem(rdata->fmp); 2596 rdata->fmp = NULL; 2597 rdata->lmp = NULL; 2598 } 2599 2600 static int 2601 emx_init_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata) 2602 { 2603 int i, error; 2604 2605 /* Reset descriptor ring */ 2606 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc); 2607 2608 /* Allocate new ones. */ 2609 for (i = 0; i < rdata->num_rx_desc; i++) { 2610 error = emx_newbuf(sc, rdata, i, 1); 2611 if (error) 2612 return (error); 2613 } 2614 2615 /* Setup our descriptor pointers */ 2616 rdata->next_rx_desc_to_check = 0; 2617 2618 return (0); 2619 } 2620 2621 static void 2622 emx_init_rx_unit(struct emx_softc *sc) 2623 { 2624 struct ifnet *ifp = &sc->arpcom.ac_if; 2625 uint64_t bus_addr; 2626 uint32_t rctl, itr, rfctl; 2627 int i; 2628 2629 /* 2630 * Make sure receives are disabled while setting 2631 * up the descriptor ring 2632 */ 2633 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2634 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2635 2636 /* 2637 * Set the interrupt throttling rate. Value is calculated 2638 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns) 2639 */ 2640 if (sc->int_throttle_ceil) 2641 itr = 1000000000 / 256 / sc->int_throttle_ceil; 2642 else 2643 itr = 0; 2644 emx_set_itr(sc, itr); 2645 2646 /* Use extended RX descriptor */ 2647 rfctl = E1000_RFCTL_EXTEN; 2648 2649 /* Disable accelerated ackknowledge */ 2650 if (sc->hw.mac.type == e1000_82574) 2651 rfctl |= E1000_RFCTL_ACK_DIS; 2652 2653 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl); 2654 2655 /* 2656 * Receive Checksum Offload for TCP and UDP 2657 * 2658 * Checksum offloading is also enabled if multiple receive 2659 * queue is to be supported, since we need it to figure out 2660 * packet type. 2661 */ 2662 if ((ifp->if_capenable & IFCAP_RXCSUM) || 2663 sc->rx_ring_cnt > 1) { 2664 uint32_t rxcsum; 2665 2666 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM); 2667 2668 /* 2669 * NOTE: 2670 * PCSD must be enabled to enable multiple 2671 * receive queues. 2672 */ 2673 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL | 2674 E1000_RXCSUM_PCSD; 2675 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum); 2676 } 2677 2678 /* 2679 * Configure multiple receive queue (RSS) 2680 */ 2681 if (sc->rx_ring_cnt > 1) { 2682 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE]; 2683 uint32_t reta; 2684 2685 KASSERT(sc->rx_ring_cnt == EMX_NRX_RING, 2686 ("invalid number of RX ring (%d)", sc->rx_ring_cnt)); 2687 2688 /* 2689 * NOTE: 2690 * When we reach here, RSS has already been disabled 2691 * in emx_stop(), so we could safely configure RSS key 2692 * and redirect table. 2693 */ 2694 2695 /* 2696 * Configure RSS key 2697 */ 2698 toeplitz_get_key(key, sizeof(key)); 2699 for (i = 0; i < EMX_NRSSRK; ++i) { 2700 uint32_t rssrk; 2701 2702 rssrk = EMX_RSSRK_VAL(key, i); 2703 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk); 2704 2705 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk); 2706 } 2707 2708 /* 2709 * Configure RSS redirect table in following fashion: 2710 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2711 */ 2712 reta = 0; 2713 for (i = 0; i < EMX_RETA_SIZE; ++i) { 2714 uint32_t q; 2715 2716 q = (i % sc->rx_ring_cnt) << EMX_RETA_RINGIDX_SHIFT; 2717 reta |= q << (8 * i); 2718 } 2719 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta); 2720 2721 for (i = 0; i < EMX_NRETA; ++i) 2722 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta); 2723 2724 /* 2725 * Enable multiple receive queues. 2726 * Enable IPv4 RSS standard hash functions. 2727 * Disable RSS interrupt. 2728 */ 2729 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 2730 E1000_MRQC_ENABLE_RSS_2Q | 2731 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2732 E1000_MRQC_RSS_FIELD_IPV4); 2733 } 2734 2735 /* 2736 * XXX TEMPORARY WORKAROUND: on some systems with 82573 2737 * long latencies are observed, like Lenovo X60. This 2738 * change eliminates the problem, but since having positive 2739 * values in RDTR is a known source of problems on other 2740 * platforms another solution is being sought. 2741 */ 2742 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) { 2743 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573); 2744 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573); 2745 } 2746 2747 for (i = 0; i < sc->rx_ring_cnt; ++i) { 2748 struct emx_rxdata *rdata = &sc->rx_data[i]; 2749 2750 /* 2751 * Setup the Base and Length of the Rx Descriptor Ring 2752 */ 2753 bus_addr = rdata->rx_desc_paddr; 2754 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i), 2755 rdata->num_rx_desc * sizeof(emx_rxdesc_t)); 2756 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i), 2757 (uint32_t)(bus_addr >> 32)); 2758 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i), 2759 (uint32_t)bus_addr); 2760 2761 /* 2762 * Setup the HW Rx Head and Tail Descriptor Pointers 2763 */ 2764 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0); 2765 E1000_WRITE_REG(&sc->hw, E1000_RDT(i), 2766 sc->rx_data[i].num_rx_desc - 1); 2767 } 2768 2769 /* Setup the Receive Control Register */ 2770 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 2771 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 2772 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC | 2773 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 2774 2775 /* Make sure VLAN Filters are off */ 2776 rctl &= ~E1000_RCTL_VFE; 2777 2778 /* Don't store bad paket */ 2779 rctl &= ~E1000_RCTL_SBP; 2780 2781 /* MCLBYTES */ 2782 rctl |= E1000_RCTL_SZ_2048; 2783 2784 if (ifp->if_mtu > ETHERMTU) 2785 rctl |= E1000_RCTL_LPE; 2786 else 2787 rctl &= ~E1000_RCTL_LPE; 2788 2789 /* Enable Receives */ 2790 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl); 2791 } 2792 2793 static void 2794 emx_destroy_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata, int ndesc) 2795 { 2796 struct emx_rxbuf *rx_buffer; 2797 int i; 2798 2799 /* Free Receive Descriptor ring */ 2800 if (rdata->rx_desc) { 2801 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap); 2802 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc, 2803 rdata->rx_desc_dmap); 2804 bus_dma_tag_destroy(rdata->rx_desc_dtag); 2805 2806 rdata->rx_desc = NULL; 2807 } 2808 2809 if (rdata->rx_buf == NULL) 2810 return; 2811 2812 for (i = 0; i < ndesc; i++) { 2813 rx_buffer = &rdata->rx_buf[i]; 2814 2815 KKASSERT(rx_buffer->m_head == NULL); 2816 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map); 2817 } 2818 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap); 2819 bus_dma_tag_destroy(rdata->rxtag); 2820 2821 kfree(rdata->rx_buf, M_DEVBUF); 2822 rdata->rx_buf = NULL; 2823 } 2824 2825 static void 2826 emx_rxeof(struct emx_softc *sc, int ring_idx, int count) 2827 { 2828 struct emx_rxdata *rdata = &sc->rx_data[ring_idx]; 2829 struct ifnet *ifp = &sc->arpcom.ac_if; 2830 uint32_t staterr; 2831 emx_rxdesc_t *current_desc; 2832 struct mbuf *mp; 2833 int i; 2834 2835 i = rdata->next_rx_desc_to_check; 2836 current_desc = &rdata->rx_desc[i]; 2837 staterr = le32toh(current_desc->rxd_staterr); 2838 2839 if (!(staterr & E1000_RXD_STAT_DD)) 2840 return; 2841 2842 while ((staterr & E1000_RXD_STAT_DD) && count != 0) { 2843 struct pktinfo *pi = NULL, pi0; 2844 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i]; 2845 struct mbuf *m = NULL; 2846 int eop, len; 2847 2848 logif(pkt_receive); 2849 2850 mp = rx_buf->m_head; 2851 2852 /* 2853 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT 2854 * needs to access the last received byte in the mbuf. 2855 */ 2856 bus_dmamap_sync(rdata->rxtag, rx_buf->map, 2857 BUS_DMASYNC_POSTREAD); 2858 2859 len = le16toh(current_desc->rxd_length); 2860 if (staterr & E1000_RXD_STAT_EOP) { 2861 count--; 2862 eop = 1; 2863 } else { 2864 eop = 0; 2865 } 2866 2867 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) { 2868 uint16_t vlan = 0; 2869 uint32_t mrq, rss_hash; 2870 2871 /* 2872 * Save several necessary information, 2873 * before emx_newbuf() destroy it. 2874 */ 2875 if ((staterr & E1000_RXD_STAT_VP) && eop) 2876 vlan = le16toh(current_desc->rxd_vlan); 2877 2878 mrq = le32toh(current_desc->rxd_mrq); 2879 rss_hash = le32toh(current_desc->rxd_rss); 2880 2881 EMX_RSS_DPRINTF(sc, 10, 2882 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n", 2883 ring_idx, mrq, rss_hash); 2884 2885 if (emx_newbuf(sc, rdata, i, 0) != 0) { 2886 ifp->if_iqdrops++; 2887 goto discard; 2888 } 2889 2890 /* Assign correct length to the current fragment */ 2891 mp->m_len = len; 2892 2893 if (rdata->fmp == NULL) { 2894 mp->m_pkthdr.len = len; 2895 rdata->fmp = mp; /* Store the first mbuf */ 2896 rdata->lmp = mp; 2897 } else { 2898 /* 2899 * Chain mbuf's together 2900 */ 2901 rdata->lmp->m_next = mp; 2902 rdata->lmp = rdata->lmp->m_next; 2903 rdata->fmp->m_pkthdr.len += len; 2904 } 2905 2906 if (eop) { 2907 rdata->fmp->m_pkthdr.rcvif = ifp; 2908 ifp->if_ipackets++; 2909 2910 if (ifp->if_capenable & IFCAP_RXCSUM) 2911 emx_rxcsum(staterr, rdata->fmp); 2912 2913 if (staterr & E1000_RXD_STAT_VP) { 2914 rdata->fmp->m_pkthdr.ether_vlantag = 2915 vlan; 2916 rdata->fmp->m_flags |= M_VLANTAG; 2917 } 2918 m = rdata->fmp; 2919 rdata->fmp = NULL; 2920 rdata->lmp = NULL; 2921 2922 if (ifp->if_capenable & IFCAP_RSS) { 2923 pi = emx_rssinfo(m, &pi0, mrq, 2924 rss_hash, staterr); 2925 } 2926 #ifdef EMX_RSS_DEBUG 2927 rdata->rx_pkts++; 2928 #endif 2929 } 2930 } else { 2931 ifp->if_ierrors++; 2932 discard: 2933 emx_setup_rxdesc(current_desc, rx_buf); 2934 if (rdata->fmp != NULL) { 2935 m_freem(rdata->fmp); 2936 rdata->fmp = NULL; 2937 rdata->lmp = NULL; 2938 } 2939 m = NULL; 2940 } 2941 2942 if (m != NULL) 2943 ether_input_pkt(ifp, m, pi); 2944 2945 /* Advance our pointers to the next descriptor. */ 2946 if (++i == rdata->num_rx_desc) 2947 i = 0; 2948 2949 current_desc = &rdata->rx_desc[i]; 2950 staterr = le32toh(current_desc->rxd_staterr); 2951 } 2952 rdata->next_rx_desc_to_check = i; 2953 2954 /* Advance the E1000's Receive Queue "Tail Pointer". */ 2955 if (--i < 0) 2956 i = rdata->num_rx_desc - 1; 2957 E1000_WRITE_REG(&sc->hw, E1000_RDT(ring_idx), i); 2958 } 2959 2960 static void 2961 emx_enable_intr(struct emx_softc *sc) 2962 { 2963 uint32_t ims_mask = IMS_ENABLE_MASK; 2964 2965 lwkt_serialize_handler_enable(&sc->main_serialize); 2966 2967 #if 0 2968 if (sc->hw.mac.type == e1000_82574) { 2969 E1000_WRITE_REG(hw, EMX_EIAC, EM_MSIX_MASK); 2970 ims_mask |= EM_MSIX_MASK; 2971 } 2972 #endif 2973 E1000_WRITE_REG(&sc->hw, E1000_IMS, ims_mask); 2974 } 2975 2976 static void 2977 emx_disable_intr(struct emx_softc *sc) 2978 { 2979 if (sc->hw.mac.type == e1000_82574) 2980 E1000_WRITE_REG(&sc->hw, EMX_EIAC, 0); 2981 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff); 2982 2983 lwkt_serialize_handler_disable(&sc->main_serialize); 2984 } 2985 2986 /* 2987 * Bit of a misnomer, what this really means is 2988 * to enable OS management of the system... aka 2989 * to disable special hardware management features 2990 */ 2991 static void 2992 emx_get_mgmt(struct emx_softc *sc) 2993 { 2994 /* A shared code workaround */ 2995 if (sc->has_manage) { 2996 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H); 2997 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 2998 2999 /* disable hardware interception of ARP */ 3000 manc &= ~(E1000_MANC_ARP_EN); 3001 3002 /* enable receiving management packets to the host */ 3003 manc |= E1000_MANC_EN_MNG2HOST; 3004 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3005 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3006 manc2h |= E1000_MNG2HOST_PORT_623; 3007 manc2h |= E1000_MNG2HOST_PORT_664; 3008 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h); 3009 3010 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3011 } 3012 } 3013 3014 /* 3015 * Give control back to hardware management 3016 * controller if there is one. 3017 */ 3018 static void 3019 emx_rel_mgmt(struct emx_softc *sc) 3020 { 3021 if (sc->has_manage) { 3022 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3023 3024 /* re-enable hardware interception of ARP */ 3025 manc |= E1000_MANC_ARP_EN; 3026 manc &= ~E1000_MANC_EN_MNG2HOST; 3027 3028 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3029 } 3030 } 3031 3032 /* 3033 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3034 * For ASF and Pass Through versions of f/w this means that 3035 * the driver is loaded. For AMT version (only with 82573) 3036 * of the f/w this means that the network i/f is open. 3037 */ 3038 static void 3039 emx_get_hw_control(struct emx_softc *sc) 3040 { 3041 /* Let firmware know the driver has taken over */ 3042 if (sc->hw.mac.type == e1000_82573) { 3043 uint32_t swsm; 3044 3045 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3046 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3047 swsm | E1000_SWSM_DRV_LOAD); 3048 } else { 3049 uint32_t ctrl_ext; 3050 3051 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3052 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3053 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3054 } 3055 sc->control_hw = 1; 3056 } 3057 3058 /* 3059 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3060 * For ASF and Pass Through versions of f/w this means that the 3061 * driver is no longer loaded. For AMT version (only with 82573) 3062 * of the f/w this means that the network i/f is closed. 3063 */ 3064 static void 3065 emx_rel_hw_control(struct emx_softc *sc) 3066 { 3067 if (!sc->control_hw) 3068 return; 3069 sc->control_hw = 0; 3070 3071 /* Let firmware taken over control of h/w */ 3072 if (sc->hw.mac.type == e1000_82573) { 3073 uint32_t swsm; 3074 3075 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3076 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3077 swsm & ~E1000_SWSM_DRV_LOAD); 3078 } else { 3079 uint32_t ctrl_ext; 3080 3081 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3082 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3083 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3084 } 3085 } 3086 3087 static int 3088 emx_is_valid_eaddr(const uint8_t *addr) 3089 { 3090 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 }; 3091 3092 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN)) 3093 return (FALSE); 3094 3095 return (TRUE); 3096 } 3097 3098 /* 3099 * Enable PCI Wake On Lan capability 3100 */ 3101 void 3102 emx_enable_wol(device_t dev) 3103 { 3104 uint16_t cap, status; 3105 uint8_t id; 3106 3107 /* First find the capabilities pointer*/ 3108 cap = pci_read_config(dev, PCIR_CAP_PTR, 2); 3109 3110 /* Read the PM Capabilities */ 3111 id = pci_read_config(dev, cap, 1); 3112 if (id != PCIY_PMG) /* Something wrong */ 3113 return; 3114 3115 /* 3116 * OK, we have the power capabilities, 3117 * so now get the status register 3118 */ 3119 cap += PCIR_POWER_STATUS; 3120 status = pci_read_config(dev, cap, 2); 3121 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3122 pci_write_config(dev, cap, status, 2); 3123 } 3124 3125 static void 3126 emx_update_stats(struct emx_softc *sc) 3127 { 3128 struct ifnet *ifp = &sc->arpcom.ac_if; 3129 3130 if (sc->hw.phy.media_type == e1000_media_type_copper || 3131 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3132 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS); 3133 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC); 3134 } 3135 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS); 3136 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC); 3137 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC); 3138 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL); 3139 3140 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC); 3141 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL); 3142 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC); 3143 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC); 3144 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC); 3145 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC); 3146 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC); 3147 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC); 3148 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC); 3149 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC); 3150 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64); 3151 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127); 3152 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255); 3153 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511); 3154 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023); 3155 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522); 3156 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC); 3157 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC); 3158 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC); 3159 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC); 3160 3161 /* For the 64-bit byte counters the low dword must be read first. */ 3162 /* Both registers clear on the read of the high dword */ 3163 3164 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH); 3165 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH); 3166 3167 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC); 3168 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC); 3169 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC); 3170 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC); 3171 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC); 3172 3173 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH); 3174 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH); 3175 3176 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR); 3177 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT); 3178 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64); 3179 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127); 3180 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255); 3181 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511); 3182 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023); 3183 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522); 3184 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC); 3185 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC); 3186 3187 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC); 3188 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC); 3189 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS); 3190 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR); 3191 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC); 3192 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC); 3193 3194 ifp->if_collisions = sc->stats.colc; 3195 3196 /* Rx Errors */ 3197 ifp->if_ierrors = sc->dropped_pkts + sc->stats.rxerrc + 3198 sc->stats.crcerrs + sc->stats.algnerrc + 3199 sc->stats.ruc + sc->stats.roc + 3200 sc->stats.mpc + sc->stats.cexterr; 3201 3202 /* Tx Errors */ 3203 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol + 3204 sc->watchdog_events; 3205 } 3206 3207 static void 3208 emx_print_debug_info(struct emx_softc *sc) 3209 { 3210 device_t dev = sc->dev; 3211 uint8_t *hw_addr = sc->hw.hw_addr; 3212 3213 device_printf(dev, "Adapter hardware address = %p \n", hw_addr); 3214 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n", 3215 E1000_READ_REG(&sc->hw, E1000_CTRL), 3216 E1000_READ_REG(&sc->hw, E1000_RCTL)); 3217 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n", 3218 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\ 3219 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) ); 3220 device_printf(dev, "Flow control watermarks high = %d low = %d\n", 3221 sc->hw.fc.high_water, sc->hw.fc.low_water); 3222 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n", 3223 E1000_READ_REG(&sc->hw, E1000_TIDV), 3224 E1000_READ_REG(&sc->hw, E1000_TADV)); 3225 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n", 3226 E1000_READ_REG(&sc->hw, E1000_RDTR), 3227 E1000_READ_REG(&sc->hw, E1000_RADV)); 3228 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 3229 E1000_READ_REG(&sc->hw, E1000_TDH(0)), 3230 E1000_READ_REG(&sc->hw, E1000_TDT(0))); 3231 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 3232 E1000_READ_REG(&sc->hw, E1000_RDH(0)), 3233 E1000_READ_REG(&sc->hw, E1000_RDT(0))); 3234 device_printf(dev, "Num Tx descriptors avail = %d\n", 3235 sc->num_tx_desc_avail); 3236 device_printf(dev, "Tx Descriptors not avail1 = %ld\n", 3237 sc->no_tx_desc_avail1); 3238 device_printf(dev, "Tx Descriptors not avail2 = %ld\n", 3239 sc->no_tx_desc_avail2); 3240 device_printf(dev, "Std mbuf failed = %ld\n", 3241 sc->mbuf_alloc_failed); 3242 device_printf(dev, "Std mbuf cluster failed = %ld\n", 3243 sc->rx_data[0].mbuf_cluster_failed); 3244 device_printf(dev, "Driver dropped packets = %ld\n", 3245 sc->dropped_pkts); 3246 device_printf(dev, "Driver tx dma failure in encap = %ld\n", 3247 sc->no_tx_dma_setup); 3248 3249 device_printf(dev, "TXCSUM try pullup = %lu\n", 3250 sc->tx_csum_try_pullup); 3251 device_printf(dev, "TXCSUM m_pullup(eh) called = %lu\n", 3252 sc->tx_csum_pullup1); 3253 device_printf(dev, "TXCSUM m_pullup(eh) failed = %lu\n", 3254 sc->tx_csum_pullup1_failed); 3255 device_printf(dev, "TXCSUM m_pullup(eh+ip) called = %lu\n", 3256 sc->tx_csum_pullup2); 3257 device_printf(dev, "TXCSUM m_pullup(eh+ip) failed = %lu\n", 3258 sc->tx_csum_pullup2_failed); 3259 device_printf(dev, "TXCSUM non-writable(eh) droped = %lu\n", 3260 sc->tx_csum_drop1); 3261 device_printf(dev, "TXCSUM non-writable(eh+ip) droped = %lu\n", 3262 sc->tx_csum_drop2); 3263 } 3264 3265 static void 3266 emx_print_hw_stats(struct emx_softc *sc) 3267 { 3268 device_t dev = sc->dev; 3269 3270 device_printf(dev, "Excessive collisions = %lld\n", 3271 (long long)sc->stats.ecol); 3272 #if (DEBUG_HW > 0) /* Dont output these errors normally */ 3273 device_printf(dev, "Symbol errors = %lld\n", 3274 (long long)sc->stats.symerrs); 3275 #endif 3276 device_printf(dev, "Sequence errors = %lld\n", 3277 (long long)sc->stats.sec); 3278 device_printf(dev, "Defer count = %lld\n", 3279 (long long)sc->stats.dc); 3280 device_printf(dev, "Missed Packets = %lld\n", 3281 (long long)sc->stats.mpc); 3282 device_printf(dev, "Receive No Buffers = %lld\n", 3283 (long long)sc->stats.rnbc); 3284 /* RLEC is inaccurate on some hardware, calculate our own. */ 3285 device_printf(dev, "Receive Length Errors = %lld\n", 3286 ((long long)sc->stats.roc + (long long)sc->stats.ruc)); 3287 device_printf(dev, "Receive errors = %lld\n", 3288 (long long)sc->stats.rxerrc); 3289 device_printf(dev, "Crc errors = %lld\n", 3290 (long long)sc->stats.crcerrs); 3291 device_printf(dev, "Alignment errors = %lld\n", 3292 (long long)sc->stats.algnerrc); 3293 device_printf(dev, "Collision/Carrier extension errors = %lld\n", 3294 (long long)sc->stats.cexterr); 3295 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns); 3296 device_printf(dev, "watchdog timeouts = %ld\n", 3297 sc->watchdog_events); 3298 device_printf(dev, "XON Rcvd = %lld\n", 3299 (long long)sc->stats.xonrxc); 3300 device_printf(dev, "XON Xmtd = %lld\n", 3301 (long long)sc->stats.xontxc); 3302 device_printf(dev, "XOFF Rcvd = %lld\n", 3303 (long long)sc->stats.xoffrxc); 3304 device_printf(dev, "XOFF Xmtd = %lld\n", 3305 (long long)sc->stats.xofftxc); 3306 device_printf(dev, "Good Packets Rcvd = %lld\n", 3307 (long long)sc->stats.gprc); 3308 device_printf(dev, "Good Packets Xmtd = %lld\n", 3309 (long long)sc->stats.gptc); 3310 } 3311 3312 static void 3313 emx_print_nvm_info(struct emx_softc *sc) 3314 { 3315 uint16_t eeprom_data; 3316 int i, j, row = 0; 3317 3318 /* Its a bit crude, but it gets the job done */ 3319 kprintf("\nInterface EEPROM Dump:\n"); 3320 kprintf("Offset\n0x0000 "); 3321 for (i = 0, j = 0; i < 32; i++, j++) { 3322 if (j == 8) { /* Make the offset block */ 3323 j = 0; ++row; 3324 kprintf("\n0x00%x0 ",row); 3325 } 3326 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data); 3327 kprintf("%04x ", eeprom_data); 3328 } 3329 kprintf("\n"); 3330 } 3331 3332 static int 3333 emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 3334 { 3335 struct emx_softc *sc; 3336 struct ifnet *ifp; 3337 int error, result; 3338 3339 result = -1; 3340 error = sysctl_handle_int(oidp, &result, 0, req); 3341 if (error || !req->newptr) 3342 return (error); 3343 3344 sc = (struct emx_softc *)arg1; 3345 ifp = &sc->arpcom.ac_if; 3346 3347 ifnet_serialize_all(ifp); 3348 3349 if (result == 1) 3350 emx_print_debug_info(sc); 3351 3352 /* 3353 * This value will cause a hex dump of the 3354 * first 32 16-bit words of the EEPROM to 3355 * the screen. 3356 */ 3357 if (result == 2) 3358 emx_print_nvm_info(sc); 3359 3360 ifnet_deserialize_all(ifp); 3361 3362 return (error); 3363 } 3364 3365 static int 3366 emx_sysctl_stats(SYSCTL_HANDLER_ARGS) 3367 { 3368 int error, result; 3369 3370 result = -1; 3371 error = sysctl_handle_int(oidp, &result, 0, req); 3372 if (error || !req->newptr) 3373 return (error); 3374 3375 if (result == 1) { 3376 struct emx_softc *sc = (struct emx_softc *)arg1; 3377 struct ifnet *ifp = &sc->arpcom.ac_if; 3378 3379 ifnet_serialize_all(ifp); 3380 emx_print_hw_stats(sc); 3381 ifnet_deserialize_all(ifp); 3382 } 3383 return (error); 3384 } 3385 3386 static void 3387 emx_add_sysctl(struct emx_softc *sc) 3388 { 3389 #ifdef EMX_RSS_DEBUG 3390 char rx_pkt[32]; 3391 int i; 3392 #endif 3393 3394 sysctl_ctx_init(&sc->sysctl_ctx); 3395 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 3396 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 3397 device_get_nameunit(sc->dev), 3398 CTLFLAG_RD, 0, ""); 3399 if (sc->sysctl_tree == NULL) { 3400 device_printf(sc->dev, "can't add sysctl node\n"); 3401 return; 3402 } 3403 3404 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3405 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 3406 emx_sysctl_debug_info, "I", "Debug Information"); 3407 3408 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3409 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 3410 emx_sysctl_stats, "I", "Statistics"); 3411 3412 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3413 OID_AUTO, "rxd", CTLFLAG_RD, 3414 &sc->rx_data[0].num_rx_desc, 0, NULL); 3415 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3416 OID_AUTO, "txd", CTLFLAG_RD, &sc->num_tx_desc, 0, NULL); 3417 3418 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3419 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW, 3420 sc, 0, emx_sysctl_int_throttle, "I", 3421 "interrupt throttling rate"); 3422 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3423 OID_AUTO, "int_tx_nsegs", CTLTYPE_INT|CTLFLAG_RW, 3424 sc, 0, emx_sysctl_int_tx_nsegs, "I", 3425 "# segments per TX interrupt"); 3426 3427 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3428 OID_AUTO, "rx_ring_cnt", CTLFLAG_RD, 3429 &sc->rx_ring_cnt, 0, "RX ring count"); 3430 3431 #ifdef EMX_RSS_DEBUG 3432 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3433 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 3434 0, "RSS debug level"); 3435 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3436 ksnprintf(rx_pkt, sizeof(rx_pkt), "rx%d_pkt", i); 3437 SYSCTL_ADD_UINT(&sc->sysctl_ctx, 3438 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, 3439 rx_pkt, CTLFLAG_RW, 3440 &sc->rx_data[i].rx_pkts, 0, "RXed packets"); 3441 } 3442 #endif 3443 } 3444 3445 static int 3446 emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS) 3447 { 3448 struct emx_softc *sc = (void *)arg1; 3449 struct ifnet *ifp = &sc->arpcom.ac_if; 3450 int error, throttle; 3451 3452 throttle = sc->int_throttle_ceil; 3453 error = sysctl_handle_int(oidp, &throttle, 0, req); 3454 if (error || req->newptr == NULL) 3455 return error; 3456 if (throttle < 0 || throttle > 1000000000 / 256) 3457 return EINVAL; 3458 3459 if (throttle) { 3460 /* 3461 * Set the interrupt throttling rate in 256ns increments, 3462 * recalculate sysctl value assignment to get exact frequency. 3463 */ 3464 throttle = 1000000000 / 256 / throttle; 3465 3466 /* Upper 16bits of ITR is reserved and should be zero */ 3467 if (throttle & 0xffff0000) 3468 return EINVAL; 3469 } 3470 3471 ifnet_serialize_all(ifp); 3472 3473 if (throttle) 3474 sc->int_throttle_ceil = 1000000000 / 256 / throttle; 3475 else 3476 sc->int_throttle_ceil = 0; 3477 3478 if (ifp->if_flags & IFF_RUNNING) 3479 emx_set_itr(sc, throttle); 3480 3481 ifnet_deserialize_all(ifp); 3482 3483 if (bootverbose) { 3484 if_printf(ifp, "Interrupt moderation set to %d/sec\n", 3485 sc->int_throttle_ceil); 3486 } 3487 return 0; 3488 } 3489 3490 static int 3491 emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS) 3492 { 3493 struct emx_softc *sc = (void *)arg1; 3494 struct ifnet *ifp = &sc->arpcom.ac_if; 3495 int error, segs; 3496 3497 segs = sc->tx_int_nsegs; 3498 error = sysctl_handle_int(oidp, &segs, 0, req); 3499 if (error || req->newptr == NULL) 3500 return error; 3501 if (segs <= 0) 3502 return EINVAL; 3503 3504 ifnet_serialize_all(ifp); 3505 3506 /* 3507 * Don't allow int_tx_nsegs to become: 3508 * o Less the oact_tx_desc 3509 * o Too large that no TX desc will cause TX interrupt to 3510 * be generated (OACTIVE will never recover) 3511 * o Too small that will cause tx_dd[] overflow 3512 */ 3513 if (segs < sc->oact_tx_desc || 3514 segs >= sc->num_tx_desc - sc->oact_tx_desc || 3515 segs < sc->num_tx_desc / EMX_TXDD_SAFE) { 3516 error = EINVAL; 3517 } else { 3518 error = 0; 3519 sc->tx_int_nsegs = segs; 3520 } 3521 3522 ifnet_deserialize_all(ifp); 3523 3524 return error; 3525 } 3526 3527 static int 3528 emx_dma_alloc(struct emx_softc *sc) 3529 { 3530 int error, i; 3531 3532 /* 3533 * Create top level busdma tag 3534 */ 3535 error = bus_dma_tag_create(NULL, 1, 0, 3536 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 3537 NULL, NULL, 3538 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 3539 0, &sc->parent_dtag); 3540 if (error) { 3541 device_printf(sc->dev, "could not create top level DMA tag\n"); 3542 return error; 3543 } 3544 3545 /* 3546 * Allocate transmit descriptors ring and buffers 3547 */ 3548 error = emx_create_tx_ring(sc); 3549 if (error) { 3550 device_printf(sc->dev, "Could not setup transmit structures\n"); 3551 return error; 3552 } 3553 3554 /* 3555 * Allocate receive descriptors ring and buffers 3556 */ 3557 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3558 error = emx_create_rx_ring(sc, &sc->rx_data[i]); 3559 if (error) { 3560 device_printf(sc->dev, 3561 "Could not setup receive structures\n"); 3562 return error; 3563 } 3564 } 3565 return 0; 3566 } 3567 3568 static void 3569 emx_dma_free(struct emx_softc *sc) 3570 { 3571 int i; 3572 3573 emx_destroy_tx_ring(sc, sc->num_tx_desc); 3574 3575 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3576 emx_destroy_rx_ring(sc, &sc->rx_data[i], 3577 sc->rx_data[i].num_rx_desc); 3578 } 3579 3580 /* Free top level busdma tag */ 3581 if (sc->parent_dtag != NULL) 3582 bus_dma_tag_destroy(sc->parent_dtag); 3583 } 3584 3585 static void 3586 emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz) 3587 { 3588 struct emx_softc *sc = ifp->if_softc; 3589 3590 ifnet_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 3591 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz); 3592 } 3593 3594 static void 3595 emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz) 3596 { 3597 struct emx_softc *sc = ifp->if_softc; 3598 3599 ifnet_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 3600 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz); 3601 } 3602 3603 static int 3604 emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz) 3605 { 3606 struct emx_softc *sc = ifp->if_softc; 3607 3608 return ifnet_serialize_array_try(sc->serializes, EMX_NSERIALIZE, 3609 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz); 3610 } 3611 3612 static void 3613 emx_serialize_skipmain(struct emx_softc *sc) 3614 { 3615 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1); 3616 } 3617 3618 static void 3619 emx_deserialize_skipmain(struct emx_softc *sc) 3620 { 3621 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1); 3622 } 3623 3624 #ifdef INVARIANTS 3625 3626 static void 3627 emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz, 3628 boolean_t serialized) 3629 { 3630 struct emx_softc *sc = ifp->if_softc; 3631 3632 ifnet_serialize_array_assert(sc->serializes, EMX_NSERIALIZE, 3633 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz, serialized); 3634 } 3635 3636 #endif /* INVARIANTS */ 3637 3638 #ifdef IFPOLL_ENABLE 3639 3640 static void 3641 emx_qpoll_status(struct ifnet *ifp, int pollhz __unused) 3642 { 3643 struct emx_softc *sc = ifp->if_softc; 3644 uint32_t reg_icr; 3645 3646 ASSERT_SERIALIZED(&sc->main_serialize); 3647 3648 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 3649 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 3650 emx_serialize_skipmain(sc); 3651 3652 callout_stop(&sc->timer); 3653 sc->hw.mac.get_link_status = 1; 3654 emx_update_link_status(sc); 3655 callout_reset(&sc->timer, hz, emx_timer, sc); 3656 3657 emx_deserialize_skipmain(sc); 3658 } 3659 } 3660 3661 static void 3662 emx_qpoll_tx(struct ifnet *ifp, void *arg __unused, int cycle __unused) 3663 { 3664 struct emx_softc *sc = ifp->if_softc; 3665 3666 ASSERT_SERIALIZED(&sc->tx_serialize); 3667 3668 emx_txeof(sc); 3669 if (!ifq_is_empty(&ifp->if_snd)) 3670 if_devstart(ifp); 3671 } 3672 3673 static void 3674 emx_qpoll_rx(struct ifnet *ifp, void *arg, int cycle) 3675 { 3676 struct emx_softc *sc = ifp->if_softc; 3677 struct emx_rxdata *rdata = arg; 3678 3679 ASSERT_SERIALIZED(&rdata->rx_serialize); 3680 3681 emx_rxeof(sc, rdata - sc->rx_data, cycle); 3682 } 3683 3684 static void 3685 emx_qpoll(struct ifnet *ifp, struct ifpoll_info *info) 3686 { 3687 struct emx_softc *sc = ifp->if_softc; 3688 3689 ASSERT_IFNET_SERIALIZED_ALL(ifp); 3690 3691 if (info) { 3692 int i; 3693 3694 info->ifpi_status.status_func = emx_qpoll_status; 3695 info->ifpi_status.serializer = &sc->main_serialize; 3696 3697 info->ifpi_tx[0].poll_func = emx_qpoll_tx; 3698 info->ifpi_tx[0].arg = NULL; 3699 info->ifpi_tx[0].serializer = &sc->tx_serialize; 3700 3701 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3702 info->ifpi_rx[i].poll_func = emx_qpoll_rx; 3703 info->ifpi_rx[i].arg = &sc->rx_data[i]; 3704 info->ifpi_rx[i].serializer = 3705 &sc->rx_data[i].rx_serialize; 3706 } 3707 3708 if (ifp->if_flags & IFF_RUNNING) 3709 emx_disable_intr(sc); 3710 } else if (ifp->if_flags & IFF_RUNNING) { 3711 emx_enable_intr(sc); 3712 } 3713 } 3714 3715 #endif /* IFPOLL_ENABLE */ 3716 3717 static void 3718 emx_set_itr(struct emx_softc *sc, uint32_t itr) 3719 { 3720 E1000_WRITE_REG(&sc->hw, E1000_ITR, itr); 3721 if (sc->hw.mac.type == e1000_82574) { 3722 int i; 3723 3724 /* 3725 * When using MSIX interrupts we need to 3726 * throttle using the EITR register 3727 */ 3728 for (i = 0; i < 4; ++i) 3729 E1000_WRITE_REG(&sc->hw, E1000_EITR_82574(i), itr); 3730 } 3731 } 3732 3733 /* 3734 * Disable the L0s, 82574L Errata #20 3735 */ 3736 static void 3737 emx_disable_aspm(struct emx_softc *sc) 3738 { 3739 uint16_t link_cap, link_ctrl; 3740 uint8_t pcie_ptr, reg; 3741 device_t dev = sc->dev; 3742 3743 switch (sc->hw.mac.type) { 3744 case e1000_82573: 3745 case e1000_82574: 3746 break; 3747 3748 default: 3749 return; 3750 } 3751 3752 pcie_ptr = pci_get_pciecap_ptr(dev); 3753 if (pcie_ptr == 0) 3754 return; 3755 3756 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2); 3757 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0) 3758 return; 3759 3760 if (bootverbose) 3761 if_printf(&sc->arpcom.ac_if, "disable L0s\n"); 3762 3763 reg = pcie_ptr + PCIER_LINKCTRL; 3764 link_ctrl = pci_read_config(dev, reg, 2); 3765 link_ctrl &= ~PCIEM_LNKCTL_ASPM_L0S; 3766 pci_write_config(dev, reg, link_ctrl, 2); 3767 } 3768