1 /* 2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 3 * 4 * Copyright (c) 2001-2008, Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * 34 * Copyright (c) 2005 The DragonFly Project. All rights reserved. 35 * 36 * This code is derived from software contributed to The DragonFly Project 37 * by Matthew Dillon <dillon@backplane.com> 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in 47 * the documentation and/or other materials provided with the 48 * distribution. 49 * 3. Neither the name of The DragonFly Project nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific, prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 */ 66 67 #include "opt_polling.h" 68 #include "opt_serializer.h" 69 #include "opt_rss.h" 70 #include "opt_emx.h" 71 72 #include <sys/param.h> 73 #include <sys/bus.h> 74 #include <sys/endian.h> 75 #include <sys/interrupt.h> 76 #include <sys/kernel.h> 77 #include <sys/ktr.h> 78 #include <sys/malloc.h> 79 #include <sys/mbuf.h> 80 #include <sys/proc.h> 81 #include <sys/rman.h> 82 #include <sys/serialize.h> 83 #include <sys/socket.h> 84 #include <sys/sockio.h> 85 #include <sys/sysctl.h> 86 #include <sys/systm.h> 87 88 #include <net/bpf.h> 89 #include <net/ethernet.h> 90 #include <net/if.h> 91 #include <net/if_arp.h> 92 #include <net/if_dl.h> 93 #include <net/if_media.h> 94 #include <net/ifq_var.h> 95 #include <net/toeplitz.h> 96 #include <net/toeplitz2.h> 97 #include <net/vlan/if_vlan_var.h> 98 #include <net/vlan/if_vlan_ether.h> 99 100 #include <netinet/in_systm.h> 101 #include <netinet/in.h> 102 #include <netinet/ip.h> 103 #include <netinet/tcp.h> 104 #include <netinet/udp.h> 105 106 #include <bus/pci/pcivar.h> 107 #include <bus/pci/pcireg.h> 108 109 #include <dev/netif/ig_hal/e1000_api.h> 110 #include <dev/netif/ig_hal/e1000_82571.h> 111 #include <dev/netif/emx/if_emx.h> 112 113 #ifdef EMX_RSS_DEBUG 114 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \ 115 do { \ 116 if (sc->rss_debug >= lvl) \ 117 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \ 118 } while (0) 119 #else /* !EMX_RSS_DEBUG */ 120 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0) 121 #endif /* EMX_RSS_DEBUG */ 122 123 #define EMX_NAME "Intel(R) PRO/1000 " 124 125 #define EMX_DEVICE(id) \ 126 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id } 127 #define EMX_DEVICE_NULL { 0, 0, NULL } 128 129 static const struct emx_device { 130 uint16_t vid; 131 uint16_t did; 132 const char *desc; 133 } emx_devices[] = { 134 EMX_DEVICE(82571EB_COPPER), 135 EMX_DEVICE(82571EB_FIBER), 136 EMX_DEVICE(82571EB_SERDES), 137 EMX_DEVICE(82571EB_SERDES_DUAL), 138 EMX_DEVICE(82571EB_SERDES_QUAD), 139 EMX_DEVICE(82571EB_QUAD_COPPER), 140 EMX_DEVICE(82571EB_QUAD_COPPER_BP), 141 EMX_DEVICE(82571EB_QUAD_COPPER_LP), 142 EMX_DEVICE(82571EB_QUAD_FIBER), 143 EMX_DEVICE(82571PT_QUAD_COPPER), 144 145 EMX_DEVICE(82572EI_COPPER), 146 EMX_DEVICE(82572EI_FIBER), 147 EMX_DEVICE(82572EI_SERDES), 148 EMX_DEVICE(82572EI), 149 150 EMX_DEVICE(82573E), 151 EMX_DEVICE(82573E_IAMT), 152 EMX_DEVICE(82573L), 153 154 EMX_DEVICE(80003ES2LAN_COPPER_SPT), 155 EMX_DEVICE(80003ES2LAN_SERDES_SPT), 156 EMX_DEVICE(80003ES2LAN_COPPER_DPT), 157 EMX_DEVICE(80003ES2LAN_SERDES_DPT), 158 159 EMX_DEVICE(82574L), 160 161 /* required last entry */ 162 EMX_DEVICE_NULL 163 }; 164 165 static int emx_probe(device_t); 166 static int emx_attach(device_t); 167 static int emx_detach(device_t); 168 static int emx_shutdown(device_t); 169 static int emx_suspend(device_t); 170 static int emx_resume(device_t); 171 172 static void emx_init(void *); 173 static void emx_stop(struct emx_softc *); 174 static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 175 static void emx_start(struct ifnet *); 176 #ifdef DEVICE_POLLING 177 static void emx_poll(struct ifnet *, enum poll_cmd, int); 178 #endif 179 static void emx_watchdog(struct ifnet *); 180 static void emx_media_status(struct ifnet *, struct ifmediareq *); 181 static int emx_media_change(struct ifnet *); 182 static void emx_timer(void *); 183 184 static void emx_intr(void *); 185 static void emx_rxeof(struct emx_softc *, int, int); 186 static void emx_txeof(struct emx_softc *); 187 static void emx_tx_collect(struct emx_softc *); 188 static void emx_tx_purge(struct emx_softc *); 189 static void emx_enable_intr(struct emx_softc *); 190 static void emx_disable_intr(struct emx_softc *); 191 192 static int emx_dma_alloc(struct emx_softc *); 193 static void emx_dma_free(struct emx_softc *); 194 static void emx_init_tx_ring(struct emx_softc *); 195 static int emx_init_rx_ring(struct emx_softc *, struct emx_rxdata *); 196 static void emx_free_rx_ring(struct emx_softc *, struct emx_rxdata *); 197 static int emx_create_tx_ring(struct emx_softc *); 198 static int emx_create_rx_ring(struct emx_softc *, struct emx_rxdata *); 199 static void emx_destroy_tx_ring(struct emx_softc *, int); 200 static void emx_destroy_rx_ring(struct emx_softc *, 201 struct emx_rxdata *, int); 202 static int emx_newbuf(struct emx_softc *, struct emx_rxdata *, int, int); 203 static int emx_encap(struct emx_softc *, struct mbuf **); 204 static int emx_txcsum_pullup(struct emx_softc *, struct mbuf **); 205 static int emx_txcsum(struct emx_softc *, struct mbuf *, 206 uint32_t *, uint32_t *); 207 208 static int emx_is_valid_eaddr(const uint8_t *); 209 static int emx_hw_init(struct emx_softc *); 210 static void emx_setup_ifp(struct emx_softc *); 211 static void emx_init_tx_unit(struct emx_softc *); 212 static void emx_init_rx_unit(struct emx_softc *); 213 static void emx_update_stats(struct emx_softc *); 214 static void emx_set_promisc(struct emx_softc *); 215 static void emx_disable_promisc(struct emx_softc *); 216 static void emx_set_multi(struct emx_softc *); 217 static void emx_update_link_status(struct emx_softc *); 218 static void emx_smartspeed(struct emx_softc *); 219 220 static void emx_print_debug_info(struct emx_softc *); 221 static void emx_print_nvm_info(struct emx_softc *); 222 static void emx_print_hw_stats(struct emx_softc *); 223 224 static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS); 225 static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 226 static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS); 227 static int emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS); 228 static void emx_add_sysctl(struct emx_softc *); 229 230 /* Management and WOL Support */ 231 static void emx_get_mgmt(struct emx_softc *); 232 static void emx_rel_mgmt(struct emx_softc *); 233 static void emx_get_hw_control(struct emx_softc *); 234 static void emx_rel_hw_control(struct emx_softc *); 235 static void emx_enable_wol(device_t); 236 237 static device_method_t emx_methods[] = { 238 /* Device interface */ 239 DEVMETHOD(device_probe, emx_probe), 240 DEVMETHOD(device_attach, emx_attach), 241 DEVMETHOD(device_detach, emx_detach), 242 DEVMETHOD(device_shutdown, emx_shutdown), 243 DEVMETHOD(device_suspend, emx_suspend), 244 DEVMETHOD(device_resume, emx_resume), 245 { 0, 0 } 246 }; 247 248 static driver_t emx_driver = { 249 "emx", 250 emx_methods, 251 sizeof(struct emx_softc), 252 }; 253 254 static devclass_t emx_devclass; 255 256 DECLARE_DUMMY_MODULE(if_emx); 257 MODULE_DEPEND(emx, ig_hal, 1, 1, 1); 258 DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, 0, 0); 259 260 /* 261 * Tunables 262 */ 263 static int emx_int_throttle_ceil = EMX_DEFAULT_ITR; 264 static int emx_rxd = EMX_DEFAULT_RXD; 265 static int emx_txd = EMX_DEFAULT_TXD; 266 static int emx_smart_pwr_down = FALSE; 267 268 /* Controls whether promiscuous also shows bad packets */ 269 static int emx_debug_sbp = FALSE; 270 271 static int emx_82573_workaround = TRUE; 272 273 TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil); 274 TUNABLE_INT("hw.emx.rxd", &emx_rxd); 275 TUNABLE_INT("hw.emx.txd", &emx_txd); 276 TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down); 277 TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp); 278 TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround); 279 280 /* Global used in WOL setup with multiport cards */ 281 static int emx_global_quad_port_a = 0; 282 283 /* Set this to one to display debug statistics */ 284 static int emx_display_debug_stats = 0; 285 286 #if !defined(KTR_IF_EMX) 287 #define KTR_IF_EMX KTR_ALL 288 #endif 289 KTR_INFO_MASTER(if_emx); 290 KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin", 0); 291 KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end", 0); 292 KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet", 0); 293 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet", 0); 294 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean", 0); 295 #define logif(name) KTR_LOG(if_emx_ ## name) 296 297 static __inline void 298 emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf) 299 { 300 rxd->rxd_bufaddr = htole64(rxbuf->paddr); 301 /* DD bit must be cleared */ 302 rxd->rxd_staterr = 0; 303 } 304 305 static __inline void 306 emx_rxcsum(uint32_t staterr, struct mbuf *mp) 307 { 308 /* Ignore Checksum bit is set */ 309 if (staterr & E1000_RXD_STAT_IXSM) 310 return; 311 312 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) == 313 E1000_RXD_STAT_IPCS) 314 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID; 315 316 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) == 317 E1000_RXD_STAT_TCPCS) { 318 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 319 CSUM_PSEUDO_HDR | 320 CSUM_FRAG_NOT_CHECKED; 321 mp->m_pkthdr.csum_data = htons(0xffff); 322 } 323 } 324 325 static __inline struct pktinfo * 326 emx_rssinfo(struct mbuf *m, struct pktinfo *pi, 327 uint32_t mrq, uint32_t hash, uint32_t staterr) 328 { 329 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) { 330 case EMX_RXDMRQ_IPV4_TCP: 331 pi->pi_netisr = NETISR_IP; 332 pi->pi_flags = 0; 333 pi->pi_l3proto = IPPROTO_TCP; 334 break; 335 336 case EMX_RXDMRQ_IPV6_TCP: 337 pi->pi_netisr = NETISR_IPV6; 338 pi->pi_flags = 0; 339 pi->pi_l3proto = IPPROTO_TCP; 340 break; 341 342 case EMX_RXDMRQ_IPV4: 343 if (staterr & E1000_RXD_STAT_IXSM) 344 return NULL; 345 346 if ((staterr & 347 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) == 348 E1000_RXD_STAT_TCPCS) { 349 pi->pi_netisr = NETISR_IP; 350 pi->pi_flags = 0; 351 pi->pi_l3proto = IPPROTO_UDP; 352 break; 353 } 354 /* FALL THROUGH */ 355 default: 356 return NULL; 357 } 358 359 m->m_flags |= M_HASH; 360 m->m_pkthdr.hash = toeplitz_hash(hash); 361 return pi; 362 } 363 364 static int 365 emx_probe(device_t dev) 366 { 367 const struct emx_device *d; 368 uint16_t vid, did; 369 370 vid = pci_get_vendor(dev); 371 did = pci_get_device(dev); 372 373 for (d = emx_devices; d->desc != NULL; ++d) { 374 if (vid == d->vid && did == d->did) { 375 device_set_desc(dev, d->desc); 376 device_set_async_attach(dev, TRUE); 377 return 0; 378 } 379 } 380 return ENXIO; 381 } 382 383 static int 384 emx_attach(device_t dev) 385 { 386 struct emx_softc *sc = device_get_softc(dev); 387 struct ifnet *ifp = &sc->arpcom.ac_if; 388 int error = 0; 389 uint16_t eeprom_data, device_id; 390 391 callout_init(&sc->timer); 392 393 sc->dev = sc->osdep.dev = dev; 394 395 /* 396 * Determine hardware and mac type 397 */ 398 sc->hw.vendor_id = pci_get_vendor(dev); 399 sc->hw.device_id = pci_get_device(dev); 400 sc->hw.revision_id = pci_get_revid(dev); 401 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev); 402 sc->hw.subsystem_device_id = pci_get_subdevice(dev); 403 404 if (e1000_set_mac_type(&sc->hw)) 405 return ENXIO; 406 407 /* Enable bus mastering */ 408 pci_enable_busmaster(dev); 409 410 /* 411 * Allocate IO memory 412 */ 413 sc->memory_rid = EMX_BAR_MEM; 414 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 415 &sc->memory_rid, RF_ACTIVE); 416 if (sc->memory == NULL) { 417 device_printf(dev, "Unable to allocate bus resource: memory\n"); 418 error = ENXIO; 419 goto fail; 420 } 421 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); 422 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory); 423 424 /* XXX This is quite goofy, it is not actually used */ 425 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle; 426 427 /* 428 * Allocate interrupt 429 */ 430 sc->intr_rid = 0; 431 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid, 432 RF_SHAREABLE | RF_ACTIVE); 433 if (sc->intr_res == NULL) { 434 device_printf(dev, "Unable to allocate bus resource: " 435 "interrupt\n"); 436 error = ENXIO; 437 goto fail; 438 } 439 440 /* Save PCI command register for Shared Code */ 441 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 442 sc->hw.back = &sc->osdep; 443 444 /* Do Shared Code initialization */ 445 if (e1000_setup_init_funcs(&sc->hw, TRUE)) { 446 device_printf(dev, "Setup of Shared code failed\n"); 447 error = ENXIO; 448 goto fail; 449 } 450 e1000_get_bus_info(&sc->hw); 451 452 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG; 453 sc->hw.phy.autoneg_wait_to_complete = FALSE; 454 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT; 455 456 /* 457 * Interrupt throttle rate 458 */ 459 if (emx_int_throttle_ceil == 0) { 460 sc->int_throttle_ceil = 0; 461 } else { 462 int throttle = emx_int_throttle_ceil; 463 464 if (throttle < 0) 465 throttle = EMX_DEFAULT_ITR; 466 467 /* Recalculate the tunable value to get the exact frequency. */ 468 throttle = 1000000000 / 256 / throttle; 469 470 /* Upper 16bits of ITR is reserved and should be zero */ 471 if (throttle & 0xffff0000) 472 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR; 473 474 sc->int_throttle_ceil = 1000000000 / 256 / throttle; 475 } 476 477 e1000_init_script_state_82541(&sc->hw, TRUE); 478 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE); 479 480 /* Copper options */ 481 if (sc->hw.phy.media_type == e1000_media_type_copper) { 482 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES; 483 sc->hw.phy.disable_polarity_correction = FALSE; 484 sc->hw.phy.ms_type = EMX_MASTER_SLAVE; 485 } 486 487 /* Set the frame limits assuming standard ethernet sized frames. */ 488 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN; 489 sc->min_frame_size = ETHER_MIN_LEN; 490 491 /* This controls when hardware reports transmit completion status. */ 492 sc->hw.mac.report_tx_early = 1; 493 494 #ifdef RSS 495 /* Calculate # of RX rings */ 496 if (ncpus > 1) 497 sc->rx_ring_cnt = EMX_NRX_RING; 498 else 499 #endif 500 sc->rx_ring_cnt = 1; 501 sc->rx_ring_inuse = sc->rx_ring_cnt; 502 503 /* Allocate RX/TX rings' busdma(9) stuffs */ 504 error = emx_dma_alloc(sc); 505 if (error) 506 goto fail; 507 508 /* Make sure we have a good EEPROM before we read from it */ 509 if (e1000_validate_nvm_checksum(&sc->hw) < 0) { 510 /* 511 * Some PCI-E parts fail the first check due to 512 * the link being in sleep state, call it again, 513 * if it fails a second time its a real issue. 514 */ 515 if (e1000_validate_nvm_checksum(&sc->hw) < 0) { 516 device_printf(dev, 517 "The EEPROM Checksum Is Not Valid\n"); 518 error = EIO; 519 goto fail; 520 } 521 } 522 523 /* Initialize the hardware */ 524 error = emx_hw_init(sc); 525 if (error) { 526 device_printf(dev, "Unable to initialize the hardware\n"); 527 goto fail; 528 } 529 530 /* Copy the permanent MAC address out of the EEPROM */ 531 if (e1000_read_mac_addr(&sc->hw) < 0) { 532 device_printf(dev, "EEPROM read error while reading MAC" 533 " address\n"); 534 error = EIO; 535 goto fail; 536 } 537 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) { 538 device_printf(dev, "Invalid MAC address\n"); 539 error = EIO; 540 goto fail; 541 } 542 543 /* Manually turn off all interrupts */ 544 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff); 545 546 /* Setup OS specific network interface */ 547 emx_setup_ifp(sc); 548 549 /* Add sysctl tree, must after emx_setup_ifp() */ 550 emx_add_sysctl(sc); 551 552 /* Initialize statistics */ 553 emx_update_stats(sc); 554 555 sc->hw.mac.get_link_status = 1; 556 emx_update_link_status(sc); 557 558 /* Indicate SOL/IDER usage */ 559 if (e1000_check_reset_block(&sc->hw)) { 560 device_printf(dev, 561 "PHY reset is blocked due to SOL/IDER session.\n"); 562 } 563 564 /* Determine if we have to control management hardware */ 565 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw); 566 567 /* 568 * Setup Wake-on-Lan 569 */ 570 switch (sc->hw.mac.type) { 571 case e1000_82571: 572 case e1000_80003es2lan: 573 if (sc->hw.bus.func == 1) { 574 e1000_read_nvm(&sc->hw, 575 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 576 } else { 577 e1000_read_nvm(&sc->hw, 578 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 579 } 580 eeprom_data &= EMX_EEPROM_APME; 581 break; 582 583 default: 584 /* APME bit in EEPROM is mapped to WUC.APME */ 585 eeprom_data = 586 E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME; 587 break; 588 } 589 if (eeprom_data) 590 sc->wol = E1000_WUFC_MAG; 591 /* 592 * We have the eeprom settings, now apply the special cases 593 * where the eeprom may be wrong or the board won't support 594 * wake on lan on a particular port 595 */ 596 device_id = pci_get_device(dev); 597 switch (device_id) { 598 case E1000_DEV_ID_82571EB_FIBER: 599 /* 600 * Wake events only supported on port A for dual fiber 601 * regardless of eeprom setting 602 */ 603 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 604 E1000_STATUS_FUNC_1) 605 sc->wol = 0; 606 break; 607 608 case E1000_DEV_ID_82571EB_QUAD_COPPER: 609 case E1000_DEV_ID_82571EB_QUAD_FIBER: 610 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 611 /* if quad port sc, disable WoL on all but port A */ 612 if (emx_global_quad_port_a != 0) 613 sc->wol = 0; 614 /* Reset for multiple quad port adapters */ 615 if (++emx_global_quad_port_a == 4) 616 emx_global_quad_port_a = 0; 617 break; 618 } 619 620 /* XXX disable wol */ 621 sc->wol = 0; 622 623 sc->spare_tx_desc = EMX_TX_SPARE; 624 625 /* 626 * Keep following relationship between spare_tx_desc, oact_tx_desc 627 * and tx_int_nsegs: 628 * (spare_tx_desc + EMX_TX_RESERVED) <= 629 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_int_nsegs 630 */ 631 sc->oact_tx_desc = sc->num_tx_desc / 8; 632 if (sc->oact_tx_desc > EMX_TX_OACTIVE_MAX) 633 sc->oact_tx_desc = EMX_TX_OACTIVE_MAX; 634 if (sc->oact_tx_desc < sc->spare_tx_desc + EMX_TX_RESERVED) 635 sc->oact_tx_desc = sc->spare_tx_desc + EMX_TX_RESERVED; 636 637 sc->tx_int_nsegs = sc->num_tx_desc / 16; 638 if (sc->tx_int_nsegs < sc->oact_tx_desc) 639 sc->tx_int_nsegs = sc->oact_tx_desc; 640 641 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, emx_intr, sc, 642 &sc->intr_tag, ifp->if_serializer); 643 if (error) { 644 device_printf(dev, "Failed to register interrupt handler"); 645 ether_ifdetach(&sc->arpcom.ac_if); 646 goto fail; 647 } 648 649 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->intr_res)); 650 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 651 return (0); 652 fail: 653 emx_detach(dev); 654 return (error); 655 } 656 657 static int 658 emx_detach(device_t dev) 659 { 660 struct emx_softc *sc = device_get_softc(dev); 661 662 if (device_is_attached(dev)) { 663 struct ifnet *ifp = &sc->arpcom.ac_if; 664 665 lwkt_serialize_enter(ifp->if_serializer); 666 667 emx_stop(sc); 668 669 e1000_phy_hw_reset(&sc->hw); 670 671 emx_rel_mgmt(sc); 672 673 if (sc->hw.mac.type == e1000_82573 && 674 e1000_check_mng_mode(&sc->hw)) 675 emx_rel_hw_control(sc); 676 677 if (sc->wol) { 678 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 679 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 680 emx_enable_wol(dev); 681 } 682 683 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag); 684 685 lwkt_serialize_exit(ifp->if_serializer); 686 687 ether_ifdetach(ifp); 688 } 689 bus_generic_detach(dev); 690 691 if (sc->intr_res != NULL) { 692 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid, 693 sc->intr_res); 694 } 695 696 if (sc->memory != NULL) { 697 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid, 698 sc->memory); 699 } 700 701 emx_dma_free(sc); 702 703 /* Free sysctl tree */ 704 if (sc->sysctl_tree != NULL) 705 sysctl_ctx_free(&sc->sysctl_ctx); 706 707 return (0); 708 } 709 710 static int 711 emx_shutdown(device_t dev) 712 { 713 return emx_suspend(dev); 714 } 715 716 static int 717 emx_suspend(device_t dev) 718 { 719 struct emx_softc *sc = device_get_softc(dev); 720 struct ifnet *ifp = &sc->arpcom.ac_if; 721 722 lwkt_serialize_enter(ifp->if_serializer); 723 724 emx_stop(sc); 725 726 emx_rel_mgmt(sc); 727 728 if (sc->hw.mac.type == e1000_82573 && 729 e1000_check_mng_mode(&sc->hw)) 730 emx_rel_hw_control(sc); 731 732 if (sc->wol) { 733 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 734 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 735 emx_enable_wol(dev); 736 } 737 738 lwkt_serialize_exit(ifp->if_serializer); 739 740 return bus_generic_suspend(dev); 741 } 742 743 static int 744 emx_resume(device_t dev) 745 { 746 struct emx_softc *sc = device_get_softc(dev); 747 struct ifnet *ifp = &sc->arpcom.ac_if; 748 749 lwkt_serialize_enter(ifp->if_serializer); 750 751 emx_init(sc); 752 emx_get_mgmt(sc); 753 if_devstart(ifp); 754 755 lwkt_serialize_exit(ifp->if_serializer); 756 757 return bus_generic_resume(dev); 758 } 759 760 static void 761 emx_start(struct ifnet *ifp) 762 { 763 struct emx_softc *sc = ifp->if_softc; 764 struct mbuf *m_head; 765 766 ASSERT_SERIALIZED(ifp->if_serializer); 767 768 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 769 return; 770 771 if (!sc->link_active) { 772 ifq_purge(&ifp->if_snd); 773 return; 774 } 775 776 while (!ifq_is_empty(&ifp->if_snd)) { 777 /* Now do we at least have a minimal? */ 778 if (EMX_IS_OACTIVE(sc)) { 779 emx_tx_collect(sc); 780 if (EMX_IS_OACTIVE(sc)) { 781 ifp->if_flags |= IFF_OACTIVE; 782 sc->no_tx_desc_avail1++; 783 break; 784 } 785 } 786 787 logif(pkt_txqueue); 788 m_head = ifq_dequeue(&ifp->if_snd, NULL); 789 if (m_head == NULL) 790 break; 791 792 if (emx_encap(sc, &m_head)) { 793 ifp->if_oerrors++; 794 emx_tx_collect(sc); 795 continue; 796 } 797 798 /* Send a copy of the frame to the BPF listener */ 799 ETHER_BPF_MTAP(ifp, m_head); 800 801 /* Set timeout in case hardware has problems transmitting. */ 802 ifp->if_timer = EMX_TX_TIMEOUT; 803 } 804 } 805 806 static int 807 emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 808 { 809 struct emx_softc *sc = ifp->if_softc; 810 struct ifreq *ifr = (struct ifreq *)data; 811 uint16_t eeprom_data = 0; 812 int max_frame_size, mask, reinit; 813 int error = 0; 814 815 ASSERT_SERIALIZED(ifp->if_serializer); 816 817 switch (command) { 818 case SIOCSIFMTU: 819 switch (sc->hw.mac.type) { 820 case e1000_82573: 821 /* 822 * 82573 only supports jumbo frames 823 * if ASPM is disabled. 824 */ 825 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1, 826 &eeprom_data); 827 if (eeprom_data & NVM_WORD1A_ASPM_MASK) { 828 max_frame_size = ETHER_MAX_LEN; 829 break; 830 } 831 /* FALL THROUGH */ 832 833 /* Limit Jumbo Frame size */ 834 case e1000_82571: 835 case e1000_82572: 836 case e1000_82574: 837 case e1000_80003es2lan: 838 max_frame_size = 9234; 839 break; 840 841 default: 842 max_frame_size = MAX_JUMBO_FRAME_SIZE; 843 break; 844 } 845 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN - 846 ETHER_CRC_LEN) { 847 error = EINVAL; 848 break; 849 } 850 851 ifp->if_mtu = ifr->ifr_mtu; 852 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN + 853 ETHER_CRC_LEN; 854 855 if (ifp->if_flags & IFF_RUNNING) 856 emx_init(sc); 857 break; 858 859 case SIOCSIFFLAGS: 860 if (ifp->if_flags & IFF_UP) { 861 if ((ifp->if_flags & IFF_RUNNING)) { 862 if ((ifp->if_flags ^ sc->if_flags) & 863 (IFF_PROMISC | IFF_ALLMULTI)) { 864 emx_disable_promisc(sc); 865 emx_set_promisc(sc); 866 } 867 } else { 868 emx_init(sc); 869 } 870 } else if (ifp->if_flags & IFF_RUNNING) { 871 emx_stop(sc); 872 } 873 sc->if_flags = ifp->if_flags; 874 break; 875 876 case SIOCADDMULTI: 877 case SIOCDELMULTI: 878 if (ifp->if_flags & IFF_RUNNING) { 879 emx_disable_intr(sc); 880 emx_set_multi(sc); 881 #ifdef DEVICE_POLLING 882 if (!(ifp->if_flags & IFF_POLLING)) 883 #endif 884 emx_enable_intr(sc); 885 } 886 break; 887 888 case SIOCSIFMEDIA: 889 /* Check SOL/IDER usage */ 890 if (e1000_check_reset_block(&sc->hw)) { 891 device_printf(sc->dev, "Media change is" 892 " blocked due to SOL/IDER session.\n"); 893 break; 894 } 895 /* FALL THROUGH */ 896 897 case SIOCGIFMEDIA: 898 error = ifmedia_ioctl(ifp, ifr, &sc->media, command); 899 break; 900 901 case SIOCSIFCAP: 902 reinit = 0; 903 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 904 if (mask & IFCAP_HWCSUM) { 905 ifp->if_capenable ^= (mask & IFCAP_HWCSUM); 906 reinit = 1; 907 } 908 if (mask & IFCAP_VLAN_HWTAGGING) { 909 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 910 reinit = 1; 911 } 912 if (mask & IFCAP_RSS) { 913 ifp->if_capenable ^= IFCAP_RSS; 914 reinit = 1; 915 } 916 if (reinit && (ifp->if_flags & IFF_RUNNING)) 917 emx_init(sc); 918 break; 919 920 default: 921 error = ether_ioctl(ifp, command, data); 922 break; 923 } 924 return (error); 925 } 926 927 static void 928 emx_watchdog(struct ifnet *ifp) 929 { 930 struct emx_softc *sc = ifp->if_softc; 931 932 ASSERT_SERIALIZED(ifp->if_serializer); 933 934 /* 935 * The timer is set to 5 every time start queues a packet. 936 * Then txeof keeps resetting it as long as it cleans at 937 * least one descriptor. 938 * Finally, anytime all descriptors are clean the timer is 939 * set to 0. 940 */ 941 942 if (E1000_READ_REG(&sc->hw, E1000_TDT(0)) == 943 E1000_READ_REG(&sc->hw, E1000_TDH(0))) { 944 /* 945 * If we reach here, all TX jobs are completed and 946 * the TX engine should have been idled for some time. 947 * We don't need to call if_devstart() here. 948 */ 949 ifp->if_flags &= ~IFF_OACTIVE; 950 ifp->if_timer = 0; 951 return; 952 } 953 954 /* 955 * If we are in this routine because of pause frames, then 956 * don't reset the hardware. 957 */ 958 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) { 959 ifp->if_timer = EMX_TX_TIMEOUT; 960 return; 961 } 962 963 if (e1000_check_for_link(&sc->hw) == 0) 964 if_printf(ifp, "watchdog timeout -- resetting\n"); 965 966 ifp->if_oerrors++; 967 sc->watchdog_events++; 968 969 emx_init(sc); 970 971 if (!ifq_is_empty(&ifp->if_snd)) 972 if_devstart(ifp); 973 } 974 975 static void 976 emx_init(void *xsc) 977 { 978 struct emx_softc *sc = xsc; 979 struct ifnet *ifp = &sc->arpcom.ac_if; 980 device_t dev = sc->dev; 981 uint32_t pba; 982 int i; 983 984 ASSERT_SERIALIZED(ifp->if_serializer); 985 986 emx_stop(sc); 987 988 /* 989 * Packet Buffer Allocation (PBA) 990 * Writing PBA sets the receive portion of the buffer 991 * the remainder is used for the transmit buffer. 992 */ 993 switch (sc->hw.mac.type) { 994 /* Total Packet Buffer on these is 48K */ 995 case e1000_82571: 996 case e1000_82572: 997 case e1000_80003es2lan: 998 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 999 break; 1000 1001 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 1002 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 1003 break; 1004 1005 case e1000_82574: 1006 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 1007 break; 1008 1009 default: 1010 /* Devices before 82547 had a Packet Buffer of 64K. */ 1011 if (sc->max_frame_size > 8192) 1012 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1013 else 1014 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1015 } 1016 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba); 1017 1018 /* Get the latest mac address, User can use a LAA */ 1019 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN); 1020 1021 /* Put the address into the Receive Address Array */ 1022 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1023 1024 /* 1025 * With the 82571 sc, RAR[0] may be overwritten 1026 * when the other port is reset, we make a duplicate 1027 * in RAR[14] for that eventuality, this assures 1028 * the interface continues to function. 1029 */ 1030 if (sc->hw.mac.type == e1000_82571) { 1031 e1000_set_laa_state_82571(&sc->hw, TRUE); 1032 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 1033 E1000_RAR_ENTRIES - 1); 1034 } 1035 1036 /* Initialize the hardware */ 1037 if (emx_hw_init(sc)) { 1038 device_printf(dev, "Unable to initialize the hardware\n"); 1039 /* XXX emx_stop()? */ 1040 return; 1041 } 1042 emx_update_link_status(sc); 1043 1044 /* Setup VLAN support, basic and offload if available */ 1045 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1046 1047 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 1048 uint32_t ctrl; 1049 1050 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL); 1051 ctrl |= E1000_CTRL_VME; 1052 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl); 1053 } 1054 1055 /* Set hardware offload abilities */ 1056 if (ifp->if_capenable & IFCAP_TXCSUM) 1057 ifp->if_hwassist = EMX_CSUM_FEATURES; 1058 else 1059 ifp->if_hwassist = 0; 1060 1061 /* Configure for OS presence */ 1062 emx_get_mgmt(sc); 1063 1064 /* Prepare transmit descriptors and buffers */ 1065 emx_init_tx_ring(sc); 1066 emx_init_tx_unit(sc); 1067 1068 /* Setup Multicast table */ 1069 emx_set_multi(sc); 1070 1071 /* 1072 * Adjust # of RX ring to be used based on IFCAP_RSS 1073 */ 1074 if (ifp->if_capenable & IFCAP_RSS) 1075 sc->rx_ring_inuse = sc->rx_ring_cnt; 1076 else 1077 sc->rx_ring_inuse = 1; 1078 1079 /* Prepare receive descriptors and buffers */ 1080 for (i = 0; i < sc->rx_ring_inuse; ++i) { 1081 if (emx_init_rx_ring(sc, &sc->rx_data[i])) { 1082 device_printf(dev, 1083 "Could not setup receive structures\n"); 1084 emx_stop(sc); 1085 return; 1086 } 1087 } 1088 emx_init_rx_unit(sc); 1089 1090 /* Don't lose promiscuous settings */ 1091 emx_set_promisc(sc); 1092 1093 ifp->if_flags |= IFF_RUNNING; 1094 ifp->if_flags &= ~IFF_OACTIVE; 1095 1096 callout_reset(&sc->timer, hz, emx_timer, sc); 1097 e1000_clear_hw_cntrs_base_generic(&sc->hw); 1098 1099 /* MSI/X configuration for 82574 */ 1100 if (sc->hw.mac.type == e1000_82574) { 1101 int tmp; 1102 1103 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 1104 tmp |= E1000_CTRL_EXT_PBA_CLR; 1105 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp); 1106 /* 1107 * Set the IVAR - interrupt vector routing. 1108 * Each nibble represents a vector, high bit 1109 * is enable, other 3 bits are the MSIX table 1110 * entry, we map RXQ0 to 0, TXQ0 to 1, and 1111 * Link (other) to 2, hence the magic number. 1112 */ 1113 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908); 1114 } 1115 1116 #ifdef DEVICE_POLLING 1117 /* 1118 * Only enable interrupts if we are not polling, make sure 1119 * they are off otherwise. 1120 */ 1121 if (ifp->if_flags & IFF_POLLING) 1122 emx_disable_intr(sc); 1123 else 1124 #endif /* DEVICE_POLLING */ 1125 emx_enable_intr(sc); 1126 1127 /* Don't reset the phy next time init gets called */ 1128 sc->hw.phy.reset_disable = TRUE; 1129 } 1130 1131 #ifdef DEVICE_POLLING 1132 1133 static void 1134 emx_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1135 { 1136 struct emx_softc *sc = ifp->if_softc; 1137 uint32_t reg_icr; 1138 1139 ASSERT_SERIALIZED(ifp->if_serializer); 1140 1141 switch (cmd) { 1142 case POLL_REGISTER: 1143 emx_disable_intr(sc); 1144 break; 1145 1146 case POLL_DEREGISTER: 1147 emx_enable_intr(sc); 1148 break; 1149 1150 case POLL_AND_CHECK_STATUS: 1151 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1152 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1153 callout_stop(&sc->timer); 1154 sc->hw.mac.get_link_status = 1; 1155 emx_update_link_status(sc); 1156 callout_reset(&sc->timer, hz, emx_timer, sc); 1157 } 1158 /* FALL THROUGH */ 1159 case POLL_ONLY: 1160 if (ifp->if_flags & IFF_RUNNING) { 1161 int i; 1162 1163 for (i = 0; i < sc->rx_ring_inuse; ++i) 1164 emx_rxeof(sc, i, count); 1165 1166 emx_txeof(sc); 1167 if (!ifq_is_empty(&ifp->if_snd)) 1168 if_devstart(ifp); 1169 } 1170 break; 1171 } 1172 } 1173 1174 #endif /* DEVICE_POLLING */ 1175 1176 static void 1177 emx_intr(void *xsc) 1178 { 1179 struct emx_softc *sc = xsc; 1180 struct ifnet *ifp = &sc->arpcom.ac_if; 1181 uint32_t reg_icr; 1182 1183 logif(intr_beg); 1184 ASSERT_SERIALIZED(ifp->if_serializer); 1185 1186 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1187 1188 if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0) { 1189 logif(intr_end); 1190 return; 1191 } 1192 1193 /* 1194 * XXX: some laptops trigger several spurious interrupts 1195 * on emx(4) when in the resume cycle. The ICR register 1196 * reports all-ones value in this case. Processing such 1197 * interrupts would lead to a freeze. I don't know why. 1198 */ 1199 if (reg_icr == 0xffffffff) { 1200 logif(intr_end); 1201 return; 1202 } 1203 1204 if (ifp->if_flags & IFF_RUNNING) { 1205 if (reg_icr & 1206 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) { 1207 int i; 1208 1209 for (i = 0; i < sc->rx_ring_inuse; ++i) 1210 emx_rxeof(sc, i, -1); 1211 } 1212 if (reg_icr & E1000_ICR_TXDW) { 1213 emx_txeof(sc); 1214 if (!ifq_is_empty(&ifp->if_snd)) 1215 if_devstart(ifp); 1216 } 1217 } 1218 1219 /* Link status change */ 1220 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1221 callout_stop(&sc->timer); 1222 sc->hw.mac.get_link_status = 1; 1223 emx_update_link_status(sc); 1224 1225 /* Deal with TX cruft when link lost */ 1226 emx_tx_purge(sc); 1227 1228 callout_reset(&sc->timer, hz, emx_timer, sc); 1229 } 1230 1231 if (reg_icr & E1000_ICR_RXO) 1232 sc->rx_overruns++; 1233 1234 logif(intr_end); 1235 } 1236 1237 static void 1238 emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1239 { 1240 struct emx_softc *sc = ifp->if_softc; 1241 1242 ASSERT_SERIALIZED(ifp->if_serializer); 1243 1244 emx_update_link_status(sc); 1245 1246 ifmr->ifm_status = IFM_AVALID; 1247 ifmr->ifm_active = IFM_ETHER; 1248 1249 if (!sc->link_active) 1250 return; 1251 1252 ifmr->ifm_status |= IFM_ACTIVE; 1253 1254 if (sc->hw.phy.media_type == e1000_media_type_fiber || 1255 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 1256 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX; 1257 } else { 1258 switch (sc->link_speed) { 1259 case 10: 1260 ifmr->ifm_active |= IFM_10_T; 1261 break; 1262 case 100: 1263 ifmr->ifm_active |= IFM_100_TX; 1264 break; 1265 1266 case 1000: 1267 ifmr->ifm_active |= IFM_1000_T; 1268 break; 1269 } 1270 if (sc->link_duplex == FULL_DUPLEX) 1271 ifmr->ifm_active |= IFM_FDX; 1272 else 1273 ifmr->ifm_active |= IFM_HDX; 1274 } 1275 } 1276 1277 static int 1278 emx_media_change(struct ifnet *ifp) 1279 { 1280 struct emx_softc *sc = ifp->if_softc; 1281 struct ifmedia *ifm = &sc->media; 1282 1283 ASSERT_SERIALIZED(ifp->if_serializer); 1284 1285 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1286 return (EINVAL); 1287 1288 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1289 case IFM_AUTO: 1290 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG; 1291 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT; 1292 break; 1293 1294 case IFM_1000_LX: 1295 case IFM_1000_SX: 1296 case IFM_1000_T: 1297 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG; 1298 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1299 break; 1300 1301 case IFM_100_TX: 1302 sc->hw.mac.autoneg = FALSE; 1303 sc->hw.phy.autoneg_advertised = 0; 1304 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1305 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1306 else 1307 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1308 break; 1309 1310 case IFM_10_T: 1311 sc->hw.mac.autoneg = FALSE; 1312 sc->hw.phy.autoneg_advertised = 0; 1313 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1314 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1315 else 1316 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1317 break; 1318 1319 default: 1320 if_printf(ifp, "Unsupported media type\n"); 1321 break; 1322 } 1323 1324 /* 1325 * As the speed/duplex settings my have changed we need to 1326 * reset the PHY. 1327 */ 1328 sc->hw.phy.reset_disable = FALSE; 1329 1330 emx_init(sc); 1331 1332 return (0); 1333 } 1334 1335 static int 1336 emx_encap(struct emx_softc *sc, struct mbuf **m_headp) 1337 { 1338 bus_dma_segment_t segs[EMX_MAX_SCATTER]; 1339 bus_dmamap_t map; 1340 struct emx_txbuf *tx_buffer, *tx_buffer_mapped; 1341 struct e1000_tx_desc *ctxd = NULL; 1342 struct mbuf *m_head = *m_headp; 1343 uint32_t txd_upper, txd_lower, cmd = 0; 1344 int maxsegs, nsegs, i, j, first, last = 0, error; 1345 1346 if (m_head->m_len < EMX_TXCSUM_MINHL && 1347 (m_head->m_flags & EMX_CSUM_FEATURES)) { 1348 /* 1349 * Make sure that ethernet header and ip.ip_hl are in 1350 * contiguous memory, since if TXCSUM is enabled, later 1351 * TX context descriptor's setup need to access ip.ip_hl. 1352 */ 1353 error = emx_txcsum_pullup(sc, m_headp); 1354 if (error) { 1355 KKASSERT(*m_headp == NULL); 1356 return error; 1357 } 1358 m_head = *m_headp; 1359 } 1360 1361 txd_upper = txd_lower = 0; 1362 1363 /* 1364 * Capture the first descriptor index, this descriptor 1365 * will have the index of the EOP which is the only one 1366 * that now gets a DONE bit writeback. 1367 */ 1368 first = sc->next_avail_tx_desc; 1369 tx_buffer = &sc->tx_buf[first]; 1370 tx_buffer_mapped = tx_buffer; 1371 map = tx_buffer->map; 1372 1373 maxsegs = sc->num_tx_desc_avail - EMX_TX_RESERVED; 1374 KASSERT(maxsegs >= sc->spare_tx_desc, ("not enough spare TX desc\n")); 1375 if (maxsegs > EMX_MAX_SCATTER) 1376 maxsegs = EMX_MAX_SCATTER; 1377 1378 error = bus_dmamap_load_mbuf_defrag(sc->txtag, map, m_headp, 1379 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 1380 if (error) { 1381 if (error == ENOBUFS) 1382 sc->mbuf_alloc_failed++; 1383 else 1384 sc->no_tx_dma_setup++; 1385 1386 m_freem(*m_headp); 1387 *m_headp = NULL; 1388 return error; 1389 } 1390 bus_dmamap_sync(sc->txtag, map, BUS_DMASYNC_PREWRITE); 1391 1392 m_head = *m_headp; 1393 sc->tx_nsegs += nsegs; 1394 1395 if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) { 1396 /* TX csum offloading will consume one TX desc */ 1397 sc->tx_nsegs += emx_txcsum(sc, m_head, &txd_upper, &txd_lower); 1398 } 1399 i = sc->next_avail_tx_desc; 1400 1401 /* Set up our transmit descriptors */ 1402 for (j = 0; j < nsegs; j++) { 1403 tx_buffer = &sc->tx_buf[i]; 1404 ctxd = &sc->tx_desc_base[i]; 1405 1406 ctxd->buffer_addr = htole64(segs[j].ds_addr); 1407 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS | 1408 txd_lower | segs[j].ds_len); 1409 ctxd->upper.data = htole32(txd_upper); 1410 1411 last = i; 1412 if (++i == sc->num_tx_desc) 1413 i = 0; 1414 } 1415 1416 sc->next_avail_tx_desc = i; 1417 1418 KKASSERT(sc->num_tx_desc_avail > nsegs); 1419 sc->num_tx_desc_avail -= nsegs; 1420 1421 /* Handle VLAN tag */ 1422 if (m_head->m_flags & M_VLANTAG) { 1423 /* Set the vlan id. */ 1424 ctxd->upper.fields.special = 1425 htole16(m_head->m_pkthdr.ether_vlantag); 1426 1427 /* Tell hardware to add tag */ 1428 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE); 1429 } 1430 1431 tx_buffer->m_head = m_head; 1432 tx_buffer_mapped->map = tx_buffer->map; 1433 tx_buffer->map = map; 1434 1435 if (sc->tx_nsegs >= sc->tx_int_nsegs) { 1436 sc->tx_nsegs = 0; 1437 1438 /* 1439 * Report Status (RS) is turned on 1440 * every tx_int_nsegs descriptors. 1441 */ 1442 cmd = E1000_TXD_CMD_RS; 1443 1444 /* 1445 * Keep track of the descriptor, which will 1446 * be written back by hardware. 1447 */ 1448 sc->tx_dd[sc->tx_dd_tail] = last; 1449 EMX_INC_TXDD_IDX(sc->tx_dd_tail); 1450 KKASSERT(sc->tx_dd_tail != sc->tx_dd_head); 1451 } 1452 1453 /* 1454 * Last Descriptor of Packet needs End Of Packet (EOP) 1455 */ 1456 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd); 1457 1458 /* 1459 * Advance the Transmit Descriptor Tail (TDT), this tells 1460 * the E1000 that this frame is available to transmit. 1461 */ 1462 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), i); 1463 1464 return (0); 1465 } 1466 1467 static void 1468 emx_set_promisc(struct emx_softc *sc) 1469 { 1470 struct ifnet *ifp = &sc->arpcom.ac_if; 1471 uint32_t reg_rctl; 1472 1473 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1474 1475 if (ifp->if_flags & IFF_PROMISC) { 1476 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1477 /* Turn this on if you want to see bad packets */ 1478 if (emx_debug_sbp) 1479 reg_rctl |= E1000_RCTL_SBP; 1480 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1481 } else if (ifp->if_flags & IFF_ALLMULTI) { 1482 reg_rctl |= E1000_RCTL_MPE; 1483 reg_rctl &= ~E1000_RCTL_UPE; 1484 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1485 } 1486 } 1487 1488 static void 1489 emx_disable_promisc(struct emx_softc *sc) 1490 { 1491 uint32_t reg_rctl; 1492 1493 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1494 1495 reg_rctl &= ~E1000_RCTL_UPE; 1496 reg_rctl &= ~E1000_RCTL_MPE; 1497 reg_rctl &= ~E1000_RCTL_SBP; 1498 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1499 } 1500 1501 static void 1502 emx_set_multi(struct emx_softc *sc) 1503 { 1504 struct ifnet *ifp = &sc->arpcom.ac_if; 1505 struct ifmultiaddr *ifma; 1506 uint32_t reg_rctl = 0; 1507 uint8_t mta[512]; /* Largest MTS is 4096 bits */ 1508 int mcnt = 0; 1509 1510 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1511 if (ifma->ifma_addr->sa_family != AF_LINK) 1512 continue; 1513 1514 if (mcnt == EMX_MCAST_ADDR_MAX) 1515 break; 1516 1517 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1518 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1519 mcnt++; 1520 } 1521 1522 if (mcnt >= EMX_MCAST_ADDR_MAX) { 1523 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1524 reg_rctl |= E1000_RCTL_MPE; 1525 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1526 } else { 1527 e1000_update_mc_addr_list(&sc->hw, mta, 1528 mcnt, 1, sc->hw.mac.rar_entry_count); 1529 } 1530 } 1531 1532 /* 1533 * This routine checks for link status and updates statistics. 1534 */ 1535 static void 1536 emx_timer(void *xsc) 1537 { 1538 struct emx_softc *sc = xsc; 1539 struct ifnet *ifp = &sc->arpcom.ac_if; 1540 1541 lwkt_serialize_enter(ifp->if_serializer); 1542 1543 emx_update_link_status(sc); 1544 emx_update_stats(sc); 1545 1546 /* Reset LAA into RAR[0] on 82571 */ 1547 if (e1000_get_laa_state_82571(&sc->hw) == TRUE) 1548 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1549 1550 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING)) 1551 emx_print_hw_stats(sc); 1552 1553 emx_smartspeed(sc); 1554 1555 callout_reset(&sc->timer, hz, emx_timer, sc); 1556 1557 lwkt_serialize_exit(ifp->if_serializer); 1558 } 1559 1560 static void 1561 emx_update_link_status(struct emx_softc *sc) 1562 { 1563 struct e1000_hw *hw = &sc->hw; 1564 struct ifnet *ifp = &sc->arpcom.ac_if; 1565 device_t dev = sc->dev; 1566 uint32_t link_check = 0; 1567 1568 /* Get the cached link value or read phy for real */ 1569 switch (hw->phy.media_type) { 1570 case e1000_media_type_copper: 1571 if (hw->mac.get_link_status) { 1572 /* Do the work to read phy */ 1573 e1000_check_for_link(hw); 1574 link_check = !hw->mac.get_link_status; 1575 if (link_check) /* ESB2 fix */ 1576 e1000_cfg_on_link_up(hw); 1577 } else { 1578 link_check = TRUE; 1579 } 1580 break; 1581 1582 case e1000_media_type_fiber: 1583 e1000_check_for_link(hw); 1584 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU; 1585 break; 1586 1587 case e1000_media_type_internal_serdes: 1588 e1000_check_for_link(hw); 1589 link_check = sc->hw.mac.serdes_has_link; 1590 break; 1591 1592 case e1000_media_type_unknown: 1593 default: 1594 break; 1595 } 1596 1597 /* Now check for a transition */ 1598 if (link_check && sc->link_active == 0) { 1599 e1000_get_speed_and_duplex(hw, &sc->link_speed, 1600 &sc->link_duplex); 1601 1602 /* 1603 * Check if we should enable/disable SPEED_MODE bit on 1604 * 82571EB/82572EI 1605 */ 1606 if (hw->mac.type == e1000_82571 || 1607 hw->mac.type == e1000_82572) { 1608 int tarc0; 1609 1610 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1611 if (sc->link_speed != SPEED_1000) 1612 tarc0 &= ~EMX_TARC_SPEED_MODE; 1613 else 1614 tarc0 |= EMX_TARC_SPEED_MODE; 1615 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1616 } 1617 if (bootverbose) { 1618 device_printf(dev, "Link is up %d Mbps %s\n", 1619 sc->link_speed, 1620 ((sc->link_duplex == FULL_DUPLEX) ? 1621 "Full Duplex" : "Half Duplex")); 1622 } 1623 sc->link_active = 1; 1624 sc->smartspeed = 0; 1625 ifp->if_baudrate = sc->link_speed * 1000000; 1626 ifp->if_link_state = LINK_STATE_UP; 1627 if_link_state_change(ifp); 1628 } else if (!link_check && sc->link_active == 1) { 1629 ifp->if_baudrate = sc->link_speed = 0; 1630 sc->link_duplex = 0; 1631 if (bootverbose) 1632 device_printf(dev, "Link is Down\n"); 1633 sc->link_active = 0; 1634 #if 0 1635 /* Link down, disable watchdog */ 1636 if->if_timer = 0; 1637 #endif 1638 ifp->if_link_state = LINK_STATE_DOWN; 1639 if_link_state_change(ifp); 1640 } 1641 } 1642 1643 static void 1644 emx_stop(struct emx_softc *sc) 1645 { 1646 struct ifnet *ifp = &sc->arpcom.ac_if; 1647 int i; 1648 1649 ASSERT_SERIALIZED(ifp->if_serializer); 1650 1651 emx_disable_intr(sc); 1652 1653 callout_stop(&sc->timer); 1654 1655 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1656 ifp->if_timer = 0; 1657 1658 /* 1659 * Disable multiple receive queues. 1660 * 1661 * NOTE: 1662 * We should disable multiple receive queues before 1663 * resetting the hardware. 1664 */ 1665 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0); 1666 1667 e1000_reset_hw(&sc->hw); 1668 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0); 1669 1670 for (i = 0; i < sc->num_tx_desc; i++) { 1671 struct emx_txbuf *tx_buffer = &sc->tx_buf[i]; 1672 1673 if (tx_buffer->m_head != NULL) { 1674 bus_dmamap_unload(sc->txtag, tx_buffer->map); 1675 m_freem(tx_buffer->m_head); 1676 tx_buffer->m_head = NULL; 1677 } 1678 } 1679 1680 for (i = 0; i < sc->rx_ring_inuse; ++i) 1681 emx_free_rx_ring(sc, &sc->rx_data[i]); 1682 1683 sc->csum_flags = 0; 1684 sc->csum_ehlen = 0; 1685 sc->csum_iphlen = 0; 1686 1687 sc->tx_dd_head = 0; 1688 sc->tx_dd_tail = 0; 1689 sc->tx_nsegs = 0; 1690 } 1691 1692 static int 1693 emx_hw_init(struct emx_softc *sc) 1694 { 1695 device_t dev = sc->dev; 1696 uint16_t rx_buffer_size; 1697 1698 /* Issue a global reset */ 1699 e1000_reset_hw(&sc->hw); 1700 1701 /* Get control from any management/hw control */ 1702 if (sc->hw.mac.type == e1000_82573 && 1703 e1000_check_mng_mode(&sc->hw)) 1704 emx_get_hw_control(sc); 1705 1706 /* Set up smart power down as default off on newer adapters. */ 1707 if (!emx_smart_pwr_down && 1708 (sc->hw.mac.type == e1000_82571 || 1709 sc->hw.mac.type == e1000_82572)) { 1710 uint16_t phy_tmp = 0; 1711 1712 /* Speed up time to link by disabling smart power down. */ 1713 e1000_read_phy_reg(&sc->hw, 1714 IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 1715 phy_tmp &= ~IGP02E1000_PM_SPD; 1716 e1000_write_phy_reg(&sc->hw, 1717 IGP02E1000_PHY_POWER_MGMT, phy_tmp); 1718 } 1719 1720 /* 1721 * These parameters control the automatic generation (Tx) and 1722 * response (Rx) to Ethernet PAUSE frames. 1723 * - High water mark should allow for at least two frames to be 1724 * received after sending an XOFF. 1725 * - Low water mark works best when it is very near the high water mark. 1726 * This allows the receiver to restart by sending XON when it has 1727 * drained a bit. Here we use an arbitary value of 1500 which will 1728 * restart after one full frame is pulled from the buffer. There 1729 * could be several smaller frames in the buffer and if so they will 1730 * not trigger the XON until their total number reduces the buffer 1731 * by 1500. 1732 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 1733 */ 1734 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10; 1735 1736 sc->hw.fc.high_water = rx_buffer_size - 1737 roundup2(sc->max_frame_size, 1024); 1738 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500; 1739 1740 if (sc->hw.mac.type == e1000_80003es2lan) 1741 sc->hw.fc.pause_time = 0xFFFF; 1742 else 1743 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME; 1744 sc->hw.fc.send_xon = TRUE; 1745 sc->hw.fc.requested_mode = e1000_fc_full; 1746 1747 if (e1000_init_hw(&sc->hw) < 0) { 1748 device_printf(dev, "Hardware Initialization Failed\n"); 1749 return (EIO); 1750 } 1751 1752 e1000_check_for_link(&sc->hw); 1753 1754 return (0); 1755 } 1756 1757 static void 1758 emx_setup_ifp(struct emx_softc *sc) 1759 { 1760 struct ifnet *ifp = &sc->arpcom.ac_if; 1761 1762 if_initname(ifp, device_get_name(sc->dev), 1763 device_get_unit(sc->dev)); 1764 ifp->if_softc = sc; 1765 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1766 ifp->if_init = emx_init; 1767 ifp->if_ioctl = emx_ioctl; 1768 ifp->if_start = emx_start; 1769 #ifdef DEVICE_POLLING 1770 ifp->if_poll = emx_poll; 1771 #endif 1772 ifp->if_watchdog = emx_watchdog; 1773 ifq_set_maxlen(&ifp->if_snd, sc->num_tx_desc - 1); 1774 ifq_set_ready(&ifp->if_snd); 1775 1776 ether_ifattach(ifp, sc->hw.mac.addr, NULL); 1777 1778 ifp->if_capabilities = IFCAP_HWCSUM | 1779 IFCAP_VLAN_HWTAGGING | 1780 IFCAP_VLAN_MTU; 1781 if (sc->rx_ring_cnt > 1) 1782 ifp->if_capabilities |= IFCAP_RSS; 1783 ifp->if_capenable = ifp->if_capabilities; 1784 ifp->if_hwassist = EMX_CSUM_FEATURES; 1785 1786 /* 1787 * Tell the upper layer(s) we support long frames. 1788 */ 1789 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1790 1791 /* 1792 * Specify the media types supported by this sc and register 1793 * callbacks to update media and link information 1794 */ 1795 ifmedia_init(&sc->media, IFM_IMASK, 1796 emx_media_change, emx_media_status); 1797 if (sc->hw.phy.media_type == e1000_media_type_fiber || 1798 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 1799 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX, 1800 0, NULL); 1801 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL); 1802 } else { 1803 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 1804 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 1805 0, NULL); 1806 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 1807 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 1808 0, NULL); 1809 if (sc->hw.phy.type != e1000_phy_ife) { 1810 ifmedia_add(&sc->media, 1811 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 1812 ifmedia_add(&sc->media, 1813 IFM_ETHER | IFM_1000_T, 0, NULL); 1814 } 1815 } 1816 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 1817 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO); 1818 } 1819 1820 /* 1821 * Workaround for SmartSpeed on 82541 and 82547 controllers 1822 */ 1823 static void 1824 emx_smartspeed(struct emx_softc *sc) 1825 { 1826 uint16_t phy_tmp; 1827 1828 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp || 1829 sc->hw.mac.autoneg == 0 || 1830 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 1831 return; 1832 1833 if (sc->smartspeed == 0) { 1834 /* 1835 * If Master/Slave config fault is asserted twice, 1836 * we assume back-to-back 1837 */ 1838 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 1839 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 1840 return; 1841 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 1842 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 1843 e1000_read_phy_reg(&sc->hw, 1844 PHY_1000T_CTRL, &phy_tmp); 1845 if (phy_tmp & CR_1000T_MS_ENABLE) { 1846 phy_tmp &= ~CR_1000T_MS_ENABLE; 1847 e1000_write_phy_reg(&sc->hw, 1848 PHY_1000T_CTRL, phy_tmp); 1849 sc->smartspeed++; 1850 if (sc->hw.mac.autoneg && 1851 !e1000_phy_setup_autoneg(&sc->hw) && 1852 !e1000_read_phy_reg(&sc->hw, 1853 PHY_CONTROL, &phy_tmp)) { 1854 phy_tmp |= MII_CR_AUTO_NEG_EN | 1855 MII_CR_RESTART_AUTO_NEG; 1856 e1000_write_phy_reg(&sc->hw, 1857 PHY_CONTROL, phy_tmp); 1858 } 1859 } 1860 } 1861 return; 1862 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) { 1863 /* If still no link, perhaps using 2/3 pair cable */ 1864 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 1865 phy_tmp |= CR_1000T_MS_ENABLE; 1866 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 1867 if (sc->hw.mac.autoneg && 1868 !e1000_phy_setup_autoneg(&sc->hw) && 1869 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) { 1870 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG; 1871 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp); 1872 } 1873 } 1874 1875 /* Restart process after EMX_SMARTSPEED_MAX iterations */ 1876 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX) 1877 sc->smartspeed = 0; 1878 } 1879 1880 static int 1881 emx_create_tx_ring(struct emx_softc *sc) 1882 { 1883 device_t dev = sc->dev; 1884 struct emx_txbuf *tx_buffer; 1885 int error, i, tsize; 1886 1887 /* 1888 * Validate number of transmit descriptors. It must not exceed 1889 * hardware maximum, and must be multiple of E1000_DBA_ALIGN. 1890 */ 1891 if ((emx_txd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 || 1892 emx_txd > EMX_MAX_TXD || emx_txd < EMX_MIN_TXD) { 1893 device_printf(dev, "Using %d TX descriptors instead of %d!\n", 1894 EMX_DEFAULT_TXD, emx_txd); 1895 sc->num_tx_desc = EMX_DEFAULT_TXD; 1896 } else { 1897 sc->num_tx_desc = emx_txd; 1898 } 1899 1900 /* 1901 * Allocate Transmit Descriptor ring 1902 */ 1903 tsize = roundup2(sc->num_tx_desc * sizeof(struct e1000_tx_desc), 1904 EMX_DBA_ALIGN); 1905 sc->tx_desc_base = bus_dmamem_coherent_any(sc->parent_dtag, 1906 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK, 1907 &sc->tx_desc_dtag, &sc->tx_desc_dmap, 1908 &sc->tx_desc_paddr); 1909 if (sc->tx_desc_base == NULL) { 1910 device_printf(dev, "Unable to allocate tx_desc memory\n"); 1911 return ENOMEM; 1912 } 1913 1914 sc->tx_buf = kmalloc(sizeof(struct emx_txbuf) * sc->num_tx_desc, 1915 M_DEVBUF, M_WAITOK | M_ZERO); 1916 1917 /* 1918 * Create DMA tags for tx buffers 1919 */ 1920 error = bus_dma_tag_create(sc->parent_dtag, /* parent */ 1921 1, 0, /* alignment, bounds */ 1922 BUS_SPACE_MAXADDR, /* lowaddr */ 1923 BUS_SPACE_MAXADDR, /* highaddr */ 1924 NULL, NULL, /* filter, filterarg */ 1925 EMX_TSO_SIZE, /* maxsize */ 1926 EMX_MAX_SCATTER, /* nsegments */ 1927 EMX_MAX_SEGSIZE, /* maxsegsize */ 1928 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | 1929 BUS_DMA_ONEBPAGE, /* flags */ 1930 &sc->txtag); 1931 if (error) { 1932 device_printf(dev, "Unable to allocate TX DMA tag\n"); 1933 kfree(sc->tx_buf, M_DEVBUF); 1934 sc->tx_buf = NULL; 1935 return error; 1936 } 1937 1938 /* 1939 * Create DMA maps for tx buffers 1940 */ 1941 for (i = 0; i < sc->num_tx_desc; i++) { 1942 tx_buffer = &sc->tx_buf[i]; 1943 1944 error = bus_dmamap_create(sc->txtag, 1945 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 1946 &tx_buffer->map); 1947 if (error) { 1948 device_printf(dev, "Unable to create TX DMA map\n"); 1949 emx_destroy_tx_ring(sc, i); 1950 return error; 1951 } 1952 } 1953 return (0); 1954 } 1955 1956 static void 1957 emx_init_tx_ring(struct emx_softc *sc) 1958 { 1959 /* Clear the old ring contents */ 1960 bzero(sc->tx_desc_base, 1961 sizeof(struct e1000_tx_desc) * sc->num_tx_desc); 1962 1963 /* Reset state */ 1964 sc->next_avail_tx_desc = 0; 1965 sc->next_tx_to_clean = 0; 1966 sc->num_tx_desc_avail = sc->num_tx_desc; 1967 } 1968 1969 static void 1970 emx_init_tx_unit(struct emx_softc *sc) 1971 { 1972 uint32_t tctl, tarc, tipg = 0; 1973 uint64_t bus_addr; 1974 1975 /* Setup the Base and Length of the Tx Descriptor Ring */ 1976 bus_addr = sc->tx_desc_paddr; 1977 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(0), 1978 sc->num_tx_desc * sizeof(struct e1000_tx_desc)); 1979 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(0), 1980 (uint32_t)(bus_addr >> 32)); 1981 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(0), 1982 (uint32_t)bus_addr); 1983 /* Setup the HW Tx Head and Tail descriptor pointers */ 1984 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), 0); 1985 E1000_WRITE_REG(&sc->hw, E1000_TDH(0), 0); 1986 1987 /* Set the default values for the Tx Inter Packet Gap timer */ 1988 switch (sc->hw.mac.type) { 1989 case e1000_80003es2lan: 1990 tipg = DEFAULT_82543_TIPG_IPGR1; 1991 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 1992 E1000_TIPG_IPGR2_SHIFT; 1993 break; 1994 1995 default: 1996 if (sc->hw.phy.media_type == e1000_media_type_fiber || 1997 sc->hw.phy.media_type == e1000_media_type_internal_serdes) 1998 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 1999 else 2000 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2001 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2002 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2003 break; 2004 } 2005 2006 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg); 2007 2008 /* NOTE: 0 is not allowed for TIDV */ 2009 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1); 2010 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0); 2011 2012 if (sc->hw.mac.type == e1000_82571 || 2013 sc->hw.mac.type == e1000_82572) { 2014 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0)); 2015 tarc |= EMX_TARC_SPEED_MODE; 2016 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc); 2017 } else if (sc->hw.mac.type == e1000_80003es2lan) { 2018 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0)); 2019 tarc |= 1; 2020 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc); 2021 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1)); 2022 tarc |= 1; 2023 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc); 2024 } 2025 2026 /* Program the Transmit Control Register */ 2027 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL); 2028 tctl &= ~E1000_TCTL_CT; 2029 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 2030 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2031 tctl |= E1000_TCTL_MULR; 2032 2033 /* This write will effectively turn on the transmit unit. */ 2034 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl); 2035 } 2036 2037 static void 2038 emx_destroy_tx_ring(struct emx_softc *sc, int ndesc) 2039 { 2040 struct emx_txbuf *tx_buffer; 2041 int i; 2042 2043 /* Free Transmit Descriptor ring */ 2044 if (sc->tx_desc_base) { 2045 bus_dmamap_unload(sc->tx_desc_dtag, sc->tx_desc_dmap); 2046 bus_dmamem_free(sc->tx_desc_dtag, sc->tx_desc_base, 2047 sc->tx_desc_dmap); 2048 bus_dma_tag_destroy(sc->tx_desc_dtag); 2049 2050 sc->tx_desc_base = NULL; 2051 } 2052 2053 if (sc->tx_buf == NULL) 2054 return; 2055 2056 for (i = 0; i < ndesc; i++) { 2057 tx_buffer = &sc->tx_buf[i]; 2058 2059 KKASSERT(tx_buffer->m_head == NULL); 2060 bus_dmamap_destroy(sc->txtag, tx_buffer->map); 2061 } 2062 bus_dma_tag_destroy(sc->txtag); 2063 2064 kfree(sc->tx_buf, M_DEVBUF); 2065 sc->tx_buf = NULL; 2066 } 2067 2068 /* 2069 * The offload context needs to be set when we transfer the first 2070 * packet of a particular protocol (TCP/UDP). This routine has been 2071 * enhanced to deal with inserted VLAN headers. 2072 * 2073 * If the new packet's ether header length, ip header length and 2074 * csum offloading type are same as the previous packet, we should 2075 * avoid allocating a new csum context descriptor; mainly to take 2076 * advantage of the pipeline effect of the TX data read request. 2077 * 2078 * This function returns number of TX descrptors allocated for 2079 * csum context. 2080 */ 2081 static int 2082 emx_txcsum(struct emx_softc *sc, struct mbuf *mp, 2083 uint32_t *txd_upper, uint32_t *txd_lower) 2084 { 2085 struct e1000_context_desc *TXD; 2086 struct emx_txbuf *tx_buffer; 2087 struct ether_vlan_header *eh; 2088 struct ip *ip; 2089 int curr_txd, ehdrlen, csum_flags; 2090 uint32_t cmd, hdr_len, ip_hlen; 2091 uint16_t etype; 2092 2093 /* 2094 * Determine where frame payload starts. 2095 * Jump over vlan headers if already present, 2096 * helpful for QinQ too. 2097 */ 2098 KASSERT(mp->m_len >= ETHER_HDR_LEN, 2099 ("emx_txcsum_pullup is not called (eh)?\n")); 2100 eh = mtod(mp, struct ether_vlan_header *); 2101 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2102 KASSERT(mp->m_len >= ETHER_HDR_LEN + EVL_ENCAPLEN, 2103 ("emx_txcsum_pullup is not called (evh)?\n")); 2104 etype = ntohs(eh->evl_proto); 2105 ehdrlen = ETHER_HDR_LEN + EVL_ENCAPLEN; 2106 } else { 2107 etype = ntohs(eh->evl_encap_proto); 2108 ehdrlen = ETHER_HDR_LEN; 2109 } 2110 2111 /* 2112 * We only support TCP/UDP for IPv4 for the moment. 2113 * TODO: Support SCTP too when it hits the tree. 2114 */ 2115 if (etype != ETHERTYPE_IP) 2116 return 0; 2117 2118 KASSERT(mp->m_len >= ehdrlen + EMX_IPVHL_SIZE, 2119 ("emx_txcsum_pullup is not called (eh+ip_vhl)?\n")); 2120 2121 /* NOTE: We could only safely access ip.ip_vhl part */ 2122 ip = (struct ip *)(mp->m_data + ehdrlen); 2123 ip_hlen = ip->ip_hl << 2; 2124 2125 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES; 2126 2127 if (sc->csum_ehlen == ehdrlen && sc->csum_iphlen == ip_hlen && 2128 sc->csum_flags == csum_flags) { 2129 /* 2130 * Same csum offload context as the previous packets; 2131 * just return. 2132 */ 2133 *txd_upper = sc->csum_txd_upper; 2134 *txd_lower = sc->csum_txd_lower; 2135 return 0; 2136 } 2137 2138 /* 2139 * Setup a new csum offload context. 2140 */ 2141 2142 curr_txd = sc->next_avail_tx_desc; 2143 tx_buffer = &sc->tx_buf[curr_txd]; 2144 TXD = (struct e1000_context_desc *)&sc->tx_desc_base[curr_txd]; 2145 2146 cmd = 0; 2147 2148 /* Setup of IP header checksum. */ 2149 if (csum_flags & CSUM_IP) { 2150 /* 2151 * Start offset for header checksum calculation. 2152 * End offset for header checksum calculation. 2153 * Offset of place to put the checksum. 2154 */ 2155 TXD->lower_setup.ip_fields.ipcss = ehdrlen; 2156 TXD->lower_setup.ip_fields.ipcse = 2157 htole16(ehdrlen + ip_hlen - 1); 2158 TXD->lower_setup.ip_fields.ipcso = 2159 ehdrlen + offsetof(struct ip, ip_sum); 2160 cmd |= E1000_TXD_CMD_IP; 2161 *txd_upper |= E1000_TXD_POPTS_IXSM << 8; 2162 } 2163 hdr_len = ehdrlen + ip_hlen; 2164 2165 if (csum_flags & CSUM_TCP) { 2166 /* 2167 * Start offset for payload checksum calculation. 2168 * End offset for payload checksum calculation. 2169 * Offset of place to put the checksum. 2170 */ 2171 TXD->upper_setup.tcp_fields.tucss = hdr_len; 2172 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2173 TXD->upper_setup.tcp_fields.tucso = 2174 hdr_len + offsetof(struct tcphdr, th_sum); 2175 cmd |= E1000_TXD_CMD_TCP; 2176 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 2177 } else if (csum_flags & CSUM_UDP) { 2178 /* 2179 * Start offset for header checksum calculation. 2180 * End offset for header checksum calculation. 2181 * Offset of place to put the checksum. 2182 */ 2183 TXD->upper_setup.tcp_fields.tucss = hdr_len; 2184 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2185 TXD->upper_setup.tcp_fields.tucso = 2186 hdr_len + offsetof(struct udphdr, uh_sum); 2187 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 2188 } 2189 2190 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */ 2191 E1000_TXD_DTYP_D; /* Data descr */ 2192 2193 /* Save the information for this csum offloading context */ 2194 sc->csum_ehlen = ehdrlen; 2195 sc->csum_iphlen = ip_hlen; 2196 sc->csum_flags = csum_flags; 2197 sc->csum_txd_upper = *txd_upper; 2198 sc->csum_txd_lower = *txd_lower; 2199 2200 TXD->tcp_seg_setup.data = htole32(0); 2201 TXD->cmd_and_length = 2202 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd); 2203 2204 if (++curr_txd == sc->num_tx_desc) 2205 curr_txd = 0; 2206 2207 KKASSERT(sc->num_tx_desc_avail > 0); 2208 sc->num_tx_desc_avail--; 2209 2210 sc->next_avail_tx_desc = curr_txd; 2211 return 1; 2212 } 2213 2214 static int 2215 emx_txcsum_pullup(struct emx_softc *sc, struct mbuf **m0) 2216 { 2217 struct mbuf *m = *m0; 2218 struct ether_header *eh; 2219 int len; 2220 2221 sc->tx_csum_try_pullup++; 2222 2223 len = ETHER_HDR_LEN + EMX_IPVHL_SIZE; 2224 2225 if (__predict_false(!M_WRITABLE(m))) { 2226 if (__predict_false(m->m_len < ETHER_HDR_LEN)) { 2227 sc->tx_csum_drop1++; 2228 m_freem(m); 2229 *m0 = NULL; 2230 return ENOBUFS; 2231 } 2232 eh = mtod(m, struct ether_header *); 2233 2234 if (eh->ether_type == htons(ETHERTYPE_VLAN)) 2235 len += EVL_ENCAPLEN; 2236 2237 if (m->m_len < len) { 2238 sc->tx_csum_drop2++; 2239 m_freem(m); 2240 *m0 = NULL; 2241 return ENOBUFS; 2242 } 2243 return 0; 2244 } 2245 2246 if (__predict_false(m->m_len < ETHER_HDR_LEN)) { 2247 sc->tx_csum_pullup1++; 2248 m = m_pullup(m, ETHER_HDR_LEN); 2249 if (m == NULL) { 2250 sc->tx_csum_pullup1_failed++; 2251 *m0 = NULL; 2252 return ENOBUFS; 2253 } 2254 *m0 = m; 2255 } 2256 eh = mtod(m, struct ether_header *); 2257 2258 if (eh->ether_type == htons(ETHERTYPE_VLAN)) 2259 len += EVL_ENCAPLEN; 2260 2261 if (m->m_len < len) { 2262 sc->tx_csum_pullup2++; 2263 m = m_pullup(m, len); 2264 if (m == NULL) { 2265 sc->tx_csum_pullup2_failed++; 2266 *m0 = NULL; 2267 return ENOBUFS; 2268 } 2269 *m0 = m; 2270 } 2271 return 0; 2272 } 2273 2274 static void 2275 emx_txeof(struct emx_softc *sc) 2276 { 2277 struct ifnet *ifp = &sc->arpcom.ac_if; 2278 struct emx_txbuf *tx_buffer; 2279 int first, num_avail; 2280 2281 if (sc->tx_dd_head == sc->tx_dd_tail) 2282 return; 2283 2284 if (sc->num_tx_desc_avail == sc->num_tx_desc) 2285 return; 2286 2287 num_avail = sc->num_tx_desc_avail; 2288 first = sc->next_tx_to_clean; 2289 2290 while (sc->tx_dd_head != sc->tx_dd_tail) { 2291 int dd_idx = sc->tx_dd[sc->tx_dd_head]; 2292 struct e1000_tx_desc *tx_desc; 2293 2294 tx_desc = &sc->tx_desc_base[dd_idx]; 2295 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) { 2296 EMX_INC_TXDD_IDX(sc->tx_dd_head); 2297 2298 if (++dd_idx == sc->num_tx_desc) 2299 dd_idx = 0; 2300 2301 while (first != dd_idx) { 2302 logif(pkt_txclean); 2303 2304 num_avail++; 2305 2306 tx_buffer = &sc->tx_buf[first]; 2307 if (tx_buffer->m_head) { 2308 ifp->if_opackets++; 2309 bus_dmamap_unload(sc->txtag, 2310 tx_buffer->map); 2311 m_freem(tx_buffer->m_head); 2312 tx_buffer->m_head = NULL; 2313 } 2314 2315 if (++first == sc->num_tx_desc) 2316 first = 0; 2317 } 2318 } else { 2319 break; 2320 } 2321 } 2322 sc->next_tx_to_clean = first; 2323 sc->num_tx_desc_avail = num_avail; 2324 2325 if (sc->tx_dd_head == sc->tx_dd_tail) { 2326 sc->tx_dd_head = 0; 2327 sc->tx_dd_tail = 0; 2328 } 2329 2330 if (!EMX_IS_OACTIVE(sc)) { 2331 ifp->if_flags &= ~IFF_OACTIVE; 2332 2333 /* All clean, turn off the timer */ 2334 if (sc->num_tx_desc_avail == sc->num_tx_desc) 2335 ifp->if_timer = 0; 2336 } 2337 } 2338 2339 static void 2340 emx_tx_collect(struct emx_softc *sc) 2341 { 2342 struct ifnet *ifp = &sc->arpcom.ac_if; 2343 struct emx_txbuf *tx_buffer; 2344 int tdh, first, num_avail, dd_idx = -1; 2345 2346 if (sc->num_tx_desc_avail == sc->num_tx_desc) 2347 return; 2348 2349 tdh = E1000_READ_REG(&sc->hw, E1000_TDH(0)); 2350 if (tdh == sc->next_tx_to_clean) 2351 return; 2352 2353 if (sc->tx_dd_head != sc->tx_dd_tail) 2354 dd_idx = sc->tx_dd[sc->tx_dd_head]; 2355 2356 num_avail = sc->num_tx_desc_avail; 2357 first = sc->next_tx_to_clean; 2358 2359 while (first != tdh) { 2360 logif(pkt_txclean); 2361 2362 num_avail++; 2363 2364 tx_buffer = &sc->tx_buf[first]; 2365 if (tx_buffer->m_head) { 2366 ifp->if_opackets++; 2367 bus_dmamap_unload(sc->txtag, 2368 tx_buffer->map); 2369 m_freem(tx_buffer->m_head); 2370 tx_buffer->m_head = NULL; 2371 } 2372 2373 if (first == dd_idx) { 2374 EMX_INC_TXDD_IDX(sc->tx_dd_head); 2375 if (sc->tx_dd_head == sc->tx_dd_tail) { 2376 sc->tx_dd_head = 0; 2377 sc->tx_dd_tail = 0; 2378 dd_idx = -1; 2379 } else { 2380 dd_idx = sc->tx_dd[sc->tx_dd_head]; 2381 } 2382 } 2383 2384 if (++first == sc->num_tx_desc) 2385 first = 0; 2386 } 2387 sc->next_tx_to_clean = first; 2388 sc->num_tx_desc_avail = num_avail; 2389 2390 if (!EMX_IS_OACTIVE(sc)) { 2391 ifp->if_flags &= ~IFF_OACTIVE; 2392 2393 /* All clean, turn off the timer */ 2394 if (sc->num_tx_desc_avail == sc->num_tx_desc) 2395 ifp->if_timer = 0; 2396 } 2397 } 2398 2399 /* 2400 * When Link is lost sometimes there is work still in the TX ring 2401 * which will result in a watchdog, rather than allow that do an 2402 * attempted cleanup and then reinit here. Note that this has been 2403 * seens mostly with fiber adapters. 2404 */ 2405 static void 2406 emx_tx_purge(struct emx_softc *sc) 2407 { 2408 struct ifnet *ifp = &sc->arpcom.ac_if; 2409 2410 if (!sc->link_active && ifp->if_timer) { 2411 emx_tx_collect(sc); 2412 if (ifp->if_timer) { 2413 if_printf(ifp, "Link lost, TX pending, reinit\n"); 2414 ifp->if_timer = 0; 2415 emx_init(sc); 2416 } 2417 } 2418 } 2419 2420 static int 2421 emx_newbuf(struct emx_softc *sc, struct emx_rxdata *rdata, int i, int init) 2422 { 2423 struct mbuf *m; 2424 bus_dma_segment_t seg; 2425 bus_dmamap_t map; 2426 struct emx_rxbuf *rx_buffer; 2427 int error, nseg; 2428 2429 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 2430 if (m == NULL) { 2431 rdata->mbuf_cluster_failed++; 2432 if (init) { 2433 if_printf(&sc->arpcom.ac_if, 2434 "Unable to allocate RX mbuf\n"); 2435 } 2436 return (ENOBUFS); 2437 } 2438 m->m_len = m->m_pkthdr.len = MCLBYTES; 2439 2440 if (sc->max_frame_size <= MCLBYTES - ETHER_ALIGN) 2441 m_adj(m, ETHER_ALIGN); 2442 2443 error = bus_dmamap_load_mbuf_segment(rdata->rxtag, 2444 rdata->rx_sparemap, m, 2445 &seg, 1, &nseg, BUS_DMA_NOWAIT); 2446 if (error) { 2447 m_freem(m); 2448 if (init) { 2449 if_printf(&sc->arpcom.ac_if, 2450 "Unable to load RX mbuf\n"); 2451 } 2452 return (error); 2453 } 2454 2455 rx_buffer = &rdata->rx_buf[i]; 2456 if (rx_buffer->m_head != NULL) 2457 bus_dmamap_unload(rdata->rxtag, rx_buffer->map); 2458 2459 map = rx_buffer->map; 2460 rx_buffer->map = rdata->rx_sparemap; 2461 rdata->rx_sparemap = map; 2462 2463 rx_buffer->m_head = m; 2464 rx_buffer->paddr = seg.ds_addr; 2465 2466 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer); 2467 return (0); 2468 } 2469 2470 static int 2471 emx_create_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata) 2472 { 2473 device_t dev = sc->dev; 2474 struct emx_rxbuf *rx_buffer; 2475 int i, error, rsize; 2476 2477 /* 2478 * Validate number of receive descriptors. It must not exceed 2479 * hardware maximum, and must be multiple of E1000_DBA_ALIGN. 2480 */ 2481 if ((emx_rxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 || 2482 emx_rxd > EMX_MAX_RXD || emx_rxd < EMX_MIN_RXD) { 2483 device_printf(dev, "Using %d RX descriptors instead of %d!\n", 2484 EMX_DEFAULT_RXD, emx_rxd); 2485 rdata->num_rx_desc = EMX_DEFAULT_RXD; 2486 } else { 2487 rdata->num_rx_desc = emx_rxd; 2488 } 2489 2490 /* 2491 * Allocate Receive Descriptor ring 2492 */ 2493 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t), 2494 EMX_DBA_ALIGN); 2495 rdata->rx_desc = bus_dmamem_coherent_any(sc->parent_dtag, 2496 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK, 2497 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap, 2498 &rdata->rx_desc_paddr); 2499 if (rdata->rx_desc == NULL) { 2500 device_printf(dev, "Unable to allocate rx_desc memory\n"); 2501 return ENOMEM; 2502 } 2503 2504 rdata->rx_buf = kmalloc(sizeof(struct emx_rxbuf) * rdata->num_rx_desc, 2505 M_DEVBUF, M_WAITOK | M_ZERO); 2506 2507 /* 2508 * Create DMA tag for rx buffers 2509 */ 2510 error = bus_dma_tag_create(sc->parent_dtag, /* parent */ 2511 1, 0, /* alignment, bounds */ 2512 BUS_SPACE_MAXADDR, /* lowaddr */ 2513 BUS_SPACE_MAXADDR, /* highaddr */ 2514 NULL, NULL, /* filter, filterarg */ 2515 MCLBYTES, /* maxsize */ 2516 1, /* nsegments */ 2517 MCLBYTES, /* maxsegsize */ 2518 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */ 2519 &rdata->rxtag); 2520 if (error) { 2521 device_printf(dev, "Unable to allocate RX DMA tag\n"); 2522 kfree(rdata->rx_buf, M_DEVBUF); 2523 rdata->rx_buf = NULL; 2524 return error; 2525 } 2526 2527 /* 2528 * Create spare DMA map for rx buffers 2529 */ 2530 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK, 2531 &rdata->rx_sparemap); 2532 if (error) { 2533 device_printf(dev, "Unable to create spare RX DMA map\n"); 2534 bus_dma_tag_destroy(rdata->rxtag); 2535 kfree(rdata->rx_buf, M_DEVBUF); 2536 rdata->rx_buf = NULL; 2537 return error; 2538 } 2539 2540 /* 2541 * Create DMA maps for rx buffers 2542 */ 2543 for (i = 0; i < rdata->num_rx_desc; i++) { 2544 rx_buffer = &rdata->rx_buf[i]; 2545 2546 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK, 2547 &rx_buffer->map); 2548 if (error) { 2549 device_printf(dev, "Unable to create RX DMA map\n"); 2550 emx_destroy_rx_ring(sc, rdata, i); 2551 return error; 2552 } 2553 } 2554 return (0); 2555 } 2556 2557 static void 2558 emx_free_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata) 2559 { 2560 int i; 2561 2562 for (i = 0; i < rdata->num_rx_desc; i++) { 2563 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i]; 2564 2565 if (rx_buffer->m_head != NULL) { 2566 bus_dmamap_unload(rdata->rxtag, rx_buffer->map); 2567 m_freem(rx_buffer->m_head); 2568 rx_buffer->m_head = NULL; 2569 } 2570 } 2571 2572 if (rdata->fmp != NULL) 2573 m_freem(rdata->fmp); 2574 rdata->fmp = NULL; 2575 rdata->lmp = NULL; 2576 } 2577 2578 static int 2579 emx_init_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata) 2580 { 2581 int i, error; 2582 2583 /* Reset descriptor ring */ 2584 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc); 2585 2586 /* Allocate new ones. */ 2587 for (i = 0; i < rdata->num_rx_desc; i++) { 2588 error = emx_newbuf(sc, rdata, i, 1); 2589 if (error) 2590 return (error); 2591 } 2592 2593 /* Setup our descriptor pointers */ 2594 rdata->next_rx_desc_to_check = 0; 2595 2596 return (0); 2597 } 2598 2599 static void 2600 emx_init_rx_unit(struct emx_softc *sc) 2601 { 2602 struct ifnet *ifp = &sc->arpcom.ac_if; 2603 uint64_t bus_addr; 2604 uint32_t rctl, rxcsum, rfctl; 2605 int i; 2606 2607 /* 2608 * Make sure receives are disabled while setting 2609 * up the descriptor ring 2610 */ 2611 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2612 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2613 2614 /* 2615 * Set the interrupt throttling rate. Value is calculated 2616 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns) 2617 */ 2618 if (sc->int_throttle_ceil) { 2619 E1000_WRITE_REG(&sc->hw, E1000_ITR, 2620 1000000000 / 256 / sc->int_throttle_ceil); 2621 } else { 2622 E1000_WRITE_REG(&sc->hw, E1000_ITR, 0); 2623 } 2624 2625 /* Use extended RX descriptor */ 2626 rfctl = E1000_RFCTL_EXTEN; 2627 2628 /* Disable accelerated ackknowledge */ 2629 if (sc->hw.mac.type == e1000_82574) 2630 rfctl |= E1000_RFCTL_ACK_DIS; 2631 2632 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl); 2633 2634 /* Setup the Base and Length of the Rx Descriptor Ring */ 2635 for (i = 0; i < sc->rx_ring_inuse; ++i) { 2636 struct emx_rxdata *rdata = &sc->rx_data[i]; 2637 2638 bus_addr = rdata->rx_desc_paddr; 2639 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i), 2640 rdata->num_rx_desc * sizeof(emx_rxdesc_t)); 2641 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i), 2642 (uint32_t)(bus_addr >> 32)); 2643 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i), 2644 (uint32_t)bus_addr); 2645 } 2646 2647 /* Setup the Receive Control Register */ 2648 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 2649 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 2650 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC | 2651 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 2652 2653 /* Make sure VLAN Filters are off */ 2654 rctl &= ~E1000_RCTL_VFE; 2655 2656 /* Don't store bad paket */ 2657 rctl &= ~E1000_RCTL_SBP; 2658 2659 /* MCLBYTES */ 2660 rctl |= E1000_RCTL_SZ_2048; 2661 2662 if (ifp->if_mtu > ETHERMTU) 2663 rctl |= E1000_RCTL_LPE; 2664 else 2665 rctl &= ~E1000_RCTL_LPE; 2666 2667 /* 2668 * Receive Checksum Offload for TCP and UDP 2669 * 2670 * Checksum offloading is also enabled if multiple receive 2671 * queue is to be supported, since we need it to figure out 2672 * packet type. 2673 */ 2674 if (ifp->if_capenable & (IFCAP_RSS | IFCAP_RXCSUM)) { 2675 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM); 2676 2677 /* 2678 * NOTE: 2679 * PCSD must be enabled to enable multiple 2680 * receive queues. 2681 */ 2682 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL | 2683 E1000_RXCSUM_PCSD; 2684 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum); 2685 } 2686 2687 /* 2688 * Configure multiple receive queue (RSS) 2689 */ 2690 if (ifp->if_capenable & IFCAP_RSS) { 2691 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE]; 2692 uint32_t reta; 2693 2694 KASSERT(sc->rx_ring_inuse == EMX_NRX_RING, 2695 ("invalid number of RX ring (%d)", 2696 sc->rx_ring_inuse)); 2697 2698 /* 2699 * NOTE: 2700 * When we reach here, RSS has already been disabled 2701 * in emx_stop(), so we could safely configure RSS key 2702 * and redirect table. 2703 */ 2704 2705 /* 2706 * Configure RSS key 2707 */ 2708 toeplitz_get_key(key, sizeof(key)); 2709 for (i = 0; i < EMX_NRSSRK; ++i) { 2710 uint32_t rssrk; 2711 2712 rssrk = EMX_RSSRK_VAL(key, i); 2713 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk); 2714 2715 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk); 2716 } 2717 2718 /* 2719 * Configure RSS redirect table in following fashion: 2720 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2721 */ 2722 reta = 0; 2723 for (i = 0; i < EMX_RETA_SIZE; ++i) { 2724 uint32_t q; 2725 2726 q = (i % sc->rx_ring_inuse) << EMX_RETA_RINGIDX_SHIFT; 2727 reta |= q << (8 * i); 2728 } 2729 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta); 2730 2731 for (i = 0; i < EMX_NRETA; ++i) 2732 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta); 2733 2734 /* 2735 * Enable multiple receive queues. 2736 * Enable IPv4 RSS standard hash functions. 2737 * Disable RSS interrupt. 2738 */ 2739 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 2740 E1000_MRQC_ENABLE_RSS_2Q | 2741 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2742 E1000_MRQC_RSS_FIELD_IPV4); 2743 } 2744 2745 /* 2746 * XXX TEMPORARY WORKAROUND: on some systems with 82573 2747 * long latencies are observed, like Lenovo X60. This 2748 * change eliminates the problem, but since having positive 2749 * values in RDTR is a known source of problems on other 2750 * platforms another solution is being sought. 2751 */ 2752 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) { 2753 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573); 2754 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573); 2755 } 2756 2757 /* 2758 * Setup the HW Rx Head and Tail Descriptor Pointers 2759 */ 2760 for (i = 0; i < sc->rx_ring_inuse; ++i) { 2761 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0); 2762 E1000_WRITE_REG(&sc->hw, E1000_RDT(i), 2763 sc->rx_data[i].num_rx_desc - 1); 2764 } 2765 2766 /* Enable Receives */ 2767 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl); 2768 } 2769 2770 static void 2771 emx_destroy_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata, int ndesc) 2772 { 2773 struct emx_rxbuf *rx_buffer; 2774 int i; 2775 2776 /* Free Receive Descriptor ring */ 2777 if (rdata->rx_desc) { 2778 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap); 2779 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc, 2780 rdata->rx_desc_dmap); 2781 bus_dma_tag_destroy(rdata->rx_desc_dtag); 2782 2783 rdata->rx_desc = NULL; 2784 } 2785 2786 if (rdata->rx_buf == NULL) 2787 return; 2788 2789 for (i = 0; i < ndesc; i++) { 2790 rx_buffer = &rdata->rx_buf[i]; 2791 2792 KKASSERT(rx_buffer->m_head == NULL); 2793 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map); 2794 } 2795 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap); 2796 bus_dma_tag_destroy(rdata->rxtag); 2797 2798 kfree(rdata->rx_buf, M_DEVBUF); 2799 rdata->rx_buf = NULL; 2800 } 2801 2802 static void 2803 emx_rxeof(struct emx_softc *sc, int ring_idx, int count) 2804 { 2805 struct emx_rxdata *rdata = &sc->rx_data[ring_idx]; 2806 struct ifnet *ifp = &sc->arpcom.ac_if; 2807 uint32_t staterr; 2808 emx_rxdesc_t *current_desc; 2809 struct mbuf *mp; 2810 int i; 2811 struct mbuf_chain chain[MAXCPU]; 2812 2813 i = rdata->next_rx_desc_to_check; 2814 current_desc = &rdata->rx_desc[i]; 2815 staterr = le32toh(current_desc->rxd_staterr); 2816 2817 if (!(staterr & E1000_RXD_STAT_DD)) 2818 return; 2819 2820 ether_input_chain_init(chain); 2821 2822 while ((staterr & E1000_RXD_STAT_DD) && count != 0) { 2823 struct pktinfo *pi = NULL, pi0; 2824 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i]; 2825 struct mbuf *m = NULL; 2826 int eop, len; 2827 2828 logif(pkt_receive); 2829 2830 mp = rx_buf->m_head; 2831 2832 /* 2833 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT 2834 * needs to access the last received byte in the mbuf. 2835 */ 2836 bus_dmamap_sync(rdata->rxtag, rx_buf->map, 2837 BUS_DMASYNC_POSTREAD); 2838 2839 len = le16toh(current_desc->rxd_length); 2840 if (staterr & E1000_RXD_STAT_EOP) { 2841 count--; 2842 eop = 1; 2843 } else { 2844 eop = 0; 2845 } 2846 2847 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) { 2848 uint16_t vlan = 0; 2849 uint32_t mrq, rss_hash; 2850 2851 /* 2852 * Save several necessary information, 2853 * before emx_newbuf() destroy it. 2854 */ 2855 if ((staterr & E1000_RXD_STAT_VP) && eop) 2856 vlan = le16toh(current_desc->rxd_vlan); 2857 2858 mrq = le32toh(current_desc->rxd_mrq); 2859 rss_hash = le32toh(current_desc->rxd_rss); 2860 2861 EMX_RSS_DPRINTF(sc, 10, 2862 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n", 2863 ring_idx, mrq, rss_hash); 2864 2865 if (emx_newbuf(sc, rdata, i, 0) != 0) { 2866 ifp->if_iqdrops++; 2867 goto discard; 2868 } 2869 2870 /* Assign correct length to the current fragment */ 2871 mp->m_len = len; 2872 2873 if (rdata->fmp == NULL) { 2874 mp->m_pkthdr.len = len; 2875 rdata->fmp = mp; /* Store the first mbuf */ 2876 rdata->lmp = mp; 2877 } else { 2878 /* 2879 * Chain mbuf's together 2880 */ 2881 rdata->lmp->m_next = mp; 2882 rdata->lmp = rdata->lmp->m_next; 2883 rdata->fmp->m_pkthdr.len += len; 2884 } 2885 2886 if (eop) { 2887 rdata->fmp->m_pkthdr.rcvif = ifp; 2888 ifp->if_ipackets++; 2889 2890 if (ifp->if_capenable & IFCAP_RXCSUM) 2891 emx_rxcsum(staterr, rdata->fmp); 2892 2893 if (staterr & E1000_RXD_STAT_VP) { 2894 rdata->fmp->m_pkthdr.ether_vlantag = 2895 vlan; 2896 rdata->fmp->m_flags |= M_VLANTAG; 2897 } 2898 m = rdata->fmp; 2899 rdata->fmp = NULL; 2900 rdata->lmp = NULL; 2901 2902 if (ifp->if_capenable & IFCAP_RSS) { 2903 pi = emx_rssinfo(m, &pi0, mrq, 2904 rss_hash, staterr); 2905 } 2906 #ifdef EMX_RSS_DEBUG 2907 rdata->rx_pkts++; 2908 #endif 2909 } 2910 } else { 2911 ifp->if_ierrors++; 2912 discard: 2913 emx_setup_rxdesc(current_desc, rx_buf); 2914 if (rdata->fmp != NULL) { 2915 m_freem(rdata->fmp); 2916 rdata->fmp = NULL; 2917 rdata->lmp = NULL; 2918 } 2919 m = NULL; 2920 } 2921 2922 if (m != NULL) 2923 ether_input_chain(ifp, m, pi, chain); 2924 2925 /* Advance our pointers to the next descriptor. */ 2926 if (++i == rdata->num_rx_desc) 2927 i = 0; 2928 2929 current_desc = &rdata->rx_desc[i]; 2930 staterr = le32toh(current_desc->rxd_staterr); 2931 } 2932 rdata->next_rx_desc_to_check = i; 2933 2934 ether_input_dispatch(chain); 2935 2936 /* Advance the E1000's Receive Queue "Tail Pointer". */ 2937 if (--i < 0) 2938 i = rdata->num_rx_desc - 1; 2939 E1000_WRITE_REG(&sc->hw, E1000_RDT(ring_idx), i); 2940 } 2941 2942 static void 2943 emx_enable_intr(struct emx_softc *sc) 2944 { 2945 lwkt_serialize_handler_enable(sc->arpcom.ac_if.if_serializer); 2946 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK); 2947 } 2948 2949 static void 2950 emx_disable_intr(struct emx_softc *sc) 2951 { 2952 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff); 2953 lwkt_serialize_handler_disable(sc->arpcom.ac_if.if_serializer); 2954 } 2955 2956 /* 2957 * Bit of a misnomer, what this really means is 2958 * to enable OS management of the system... aka 2959 * to disable special hardware management features 2960 */ 2961 static void 2962 emx_get_mgmt(struct emx_softc *sc) 2963 { 2964 /* A shared code workaround */ 2965 if (sc->has_manage) { 2966 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H); 2967 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 2968 2969 /* disable hardware interception of ARP */ 2970 manc &= ~(E1000_MANC_ARP_EN); 2971 2972 /* enable receiving management packets to the host */ 2973 manc |= E1000_MANC_EN_MNG2HOST; 2974 #define E1000_MNG2HOST_PORT_623 (1 << 5) 2975 #define E1000_MNG2HOST_PORT_664 (1 << 6) 2976 manc2h |= E1000_MNG2HOST_PORT_623; 2977 manc2h |= E1000_MNG2HOST_PORT_664; 2978 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h); 2979 2980 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 2981 } 2982 } 2983 2984 /* 2985 * Give control back to hardware management 2986 * controller if there is one. 2987 */ 2988 static void 2989 emx_rel_mgmt(struct emx_softc *sc) 2990 { 2991 if (sc->has_manage) { 2992 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 2993 2994 /* re-enable hardware interception of ARP */ 2995 manc |= E1000_MANC_ARP_EN; 2996 manc &= ~E1000_MANC_EN_MNG2HOST; 2997 2998 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 2999 } 3000 } 3001 3002 /* 3003 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3004 * For ASF and Pass Through versions of f/w this means that 3005 * the driver is loaded. For AMT version (only with 82573) 3006 * of the f/w this means that the network i/f is open. 3007 */ 3008 static void 3009 emx_get_hw_control(struct emx_softc *sc) 3010 { 3011 uint32_t ctrl_ext, swsm; 3012 3013 /* Let firmware know the driver has taken over */ 3014 switch (sc->hw.mac.type) { 3015 case e1000_82573: 3016 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3017 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3018 swsm | E1000_SWSM_DRV_LOAD); 3019 break; 3020 3021 case e1000_82571: 3022 case e1000_82572: 3023 case e1000_80003es2lan: 3024 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3025 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3026 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3027 break; 3028 3029 default: 3030 break; 3031 } 3032 } 3033 3034 /* 3035 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3036 * For ASF and Pass Through versions of f/w this means that the 3037 * driver is no longer loaded. For AMT version (only with 82573) 3038 * of the f/w this means that the network i/f is closed. 3039 */ 3040 static void 3041 emx_rel_hw_control(struct emx_softc *sc) 3042 { 3043 uint32_t ctrl_ext, swsm; 3044 3045 /* Let firmware taken over control of h/w */ 3046 switch (sc->hw.mac.type) { 3047 case e1000_82573: 3048 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3049 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3050 swsm & ~E1000_SWSM_DRV_LOAD); 3051 break; 3052 3053 case e1000_82571: 3054 case e1000_82572: 3055 case e1000_80003es2lan: 3056 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3057 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3058 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3059 break; 3060 3061 default: 3062 break; 3063 } 3064 } 3065 3066 static int 3067 emx_is_valid_eaddr(const uint8_t *addr) 3068 { 3069 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 }; 3070 3071 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN)) 3072 return (FALSE); 3073 3074 return (TRUE); 3075 } 3076 3077 /* 3078 * Enable PCI Wake On Lan capability 3079 */ 3080 void 3081 emx_enable_wol(device_t dev) 3082 { 3083 uint16_t cap, status; 3084 uint8_t id; 3085 3086 /* First find the capabilities pointer*/ 3087 cap = pci_read_config(dev, PCIR_CAP_PTR, 2); 3088 3089 /* Read the PM Capabilities */ 3090 id = pci_read_config(dev, cap, 1); 3091 if (id != PCIY_PMG) /* Something wrong */ 3092 return; 3093 3094 /* 3095 * OK, we have the power capabilities, 3096 * so now get the status register 3097 */ 3098 cap += PCIR_POWER_STATUS; 3099 status = pci_read_config(dev, cap, 2); 3100 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3101 pci_write_config(dev, cap, status, 2); 3102 } 3103 3104 static void 3105 emx_update_stats(struct emx_softc *sc) 3106 { 3107 struct ifnet *ifp = &sc->arpcom.ac_if; 3108 3109 if (sc->hw.phy.media_type == e1000_media_type_copper || 3110 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3111 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS); 3112 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC); 3113 } 3114 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS); 3115 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC); 3116 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC); 3117 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL); 3118 3119 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC); 3120 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL); 3121 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC); 3122 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC); 3123 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC); 3124 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC); 3125 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC); 3126 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC); 3127 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC); 3128 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC); 3129 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64); 3130 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127); 3131 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255); 3132 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511); 3133 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023); 3134 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522); 3135 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC); 3136 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC); 3137 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC); 3138 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC); 3139 3140 /* For the 64-bit byte counters the low dword must be read first. */ 3141 /* Both registers clear on the read of the high dword */ 3142 3143 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH); 3144 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH); 3145 3146 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC); 3147 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC); 3148 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC); 3149 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC); 3150 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC); 3151 3152 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH); 3153 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH); 3154 3155 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR); 3156 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT); 3157 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64); 3158 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127); 3159 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255); 3160 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511); 3161 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023); 3162 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522); 3163 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC); 3164 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC); 3165 3166 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC); 3167 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC); 3168 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS); 3169 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR); 3170 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC); 3171 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC); 3172 3173 ifp->if_collisions = sc->stats.colc; 3174 3175 /* Rx Errors */ 3176 ifp->if_ierrors = sc->dropped_pkts + sc->stats.rxerrc + 3177 sc->stats.crcerrs + sc->stats.algnerrc + 3178 sc->stats.ruc + sc->stats.roc + 3179 sc->stats.mpc + sc->stats.cexterr; 3180 3181 /* Tx Errors */ 3182 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol + 3183 sc->watchdog_events; 3184 } 3185 3186 static void 3187 emx_print_debug_info(struct emx_softc *sc) 3188 { 3189 device_t dev = sc->dev; 3190 uint8_t *hw_addr = sc->hw.hw_addr; 3191 3192 device_printf(dev, "Adapter hardware address = %p \n", hw_addr); 3193 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n", 3194 E1000_READ_REG(&sc->hw, E1000_CTRL), 3195 E1000_READ_REG(&sc->hw, E1000_RCTL)); 3196 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n", 3197 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\ 3198 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) ); 3199 device_printf(dev, "Flow control watermarks high = %d low = %d\n", 3200 sc->hw.fc.high_water, sc->hw.fc.low_water); 3201 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n", 3202 E1000_READ_REG(&sc->hw, E1000_TIDV), 3203 E1000_READ_REG(&sc->hw, E1000_TADV)); 3204 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n", 3205 E1000_READ_REG(&sc->hw, E1000_RDTR), 3206 E1000_READ_REG(&sc->hw, E1000_RADV)); 3207 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 3208 E1000_READ_REG(&sc->hw, E1000_TDH(0)), 3209 E1000_READ_REG(&sc->hw, E1000_TDT(0))); 3210 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 3211 E1000_READ_REG(&sc->hw, E1000_RDH(0)), 3212 E1000_READ_REG(&sc->hw, E1000_RDT(0))); 3213 device_printf(dev, "Num Tx descriptors avail = %d\n", 3214 sc->num_tx_desc_avail); 3215 device_printf(dev, "Tx Descriptors not avail1 = %ld\n", 3216 sc->no_tx_desc_avail1); 3217 device_printf(dev, "Tx Descriptors not avail2 = %ld\n", 3218 sc->no_tx_desc_avail2); 3219 device_printf(dev, "Std mbuf failed = %ld\n", 3220 sc->mbuf_alloc_failed); 3221 device_printf(dev, "Std mbuf cluster failed = %ld\n", 3222 sc->rx_data[0].mbuf_cluster_failed); 3223 device_printf(dev, "Driver dropped packets = %ld\n", 3224 sc->dropped_pkts); 3225 device_printf(dev, "Driver tx dma failure in encap = %ld\n", 3226 sc->no_tx_dma_setup); 3227 3228 device_printf(dev, "TXCSUM try pullup = %lu\n", 3229 sc->tx_csum_try_pullup); 3230 device_printf(dev, "TXCSUM m_pullup(eh) called = %lu\n", 3231 sc->tx_csum_pullup1); 3232 device_printf(dev, "TXCSUM m_pullup(eh) failed = %lu\n", 3233 sc->tx_csum_pullup1_failed); 3234 device_printf(dev, "TXCSUM m_pullup(eh+ip) called = %lu\n", 3235 sc->tx_csum_pullup2); 3236 device_printf(dev, "TXCSUM m_pullup(eh+ip) failed = %lu\n", 3237 sc->tx_csum_pullup2_failed); 3238 device_printf(dev, "TXCSUM non-writable(eh) droped = %lu\n", 3239 sc->tx_csum_drop1); 3240 device_printf(dev, "TXCSUM non-writable(eh+ip) droped = %lu\n", 3241 sc->tx_csum_drop2); 3242 } 3243 3244 static void 3245 emx_print_hw_stats(struct emx_softc *sc) 3246 { 3247 device_t dev = sc->dev; 3248 3249 device_printf(dev, "Excessive collisions = %lld\n", 3250 (long long)sc->stats.ecol); 3251 #if (DEBUG_HW > 0) /* Dont output these errors normally */ 3252 device_printf(dev, "Symbol errors = %lld\n", 3253 (long long)sc->stats.symerrs); 3254 #endif 3255 device_printf(dev, "Sequence errors = %lld\n", 3256 (long long)sc->stats.sec); 3257 device_printf(dev, "Defer count = %lld\n", 3258 (long long)sc->stats.dc); 3259 device_printf(dev, "Missed Packets = %lld\n", 3260 (long long)sc->stats.mpc); 3261 device_printf(dev, "Receive No Buffers = %lld\n", 3262 (long long)sc->stats.rnbc); 3263 /* RLEC is inaccurate on some hardware, calculate our own. */ 3264 device_printf(dev, "Receive Length Errors = %lld\n", 3265 ((long long)sc->stats.roc + (long long)sc->stats.ruc)); 3266 device_printf(dev, "Receive errors = %lld\n", 3267 (long long)sc->stats.rxerrc); 3268 device_printf(dev, "Crc errors = %lld\n", 3269 (long long)sc->stats.crcerrs); 3270 device_printf(dev, "Alignment errors = %lld\n", 3271 (long long)sc->stats.algnerrc); 3272 device_printf(dev, "Collision/Carrier extension errors = %lld\n", 3273 (long long)sc->stats.cexterr); 3274 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns); 3275 device_printf(dev, "watchdog timeouts = %ld\n", 3276 sc->watchdog_events); 3277 device_printf(dev, "XON Rcvd = %lld\n", 3278 (long long)sc->stats.xonrxc); 3279 device_printf(dev, "XON Xmtd = %lld\n", 3280 (long long)sc->stats.xontxc); 3281 device_printf(dev, "XOFF Rcvd = %lld\n", 3282 (long long)sc->stats.xoffrxc); 3283 device_printf(dev, "XOFF Xmtd = %lld\n", 3284 (long long)sc->stats.xofftxc); 3285 device_printf(dev, "Good Packets Rcvd = %lld\n", 3286 (long long)sc->stats.gprc); 3287 device_printf(dev, "Good Packets Xmtd = %lld\n", 3288 (long long)sc->stats.gptc); 3289 } 3290 3291 static void 3292 emx_print_nvm_info(struct emx_softc *sc) 3293 { 3294 uint16_t eeprom_data; 3295 int i, j, row = 0; 3296 3297 /* Its a bit crude, but it gets the job done */ 3298 kprintf("\nInterface EEPROM Dump:\n"); 3299 kprintf("Offset\n0x0000 "); 3300 for (i = 0, j = 0; i < 32; i++, j++) { 3301 if (j == 8) { /* Make the offset block */ 3302 j = 0; ++row; 3303 kprintf("\n0x00%x0 ",row); 3304 } 3305 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data); 3306 kprintf("%04x ", eeprom_data); 3307 } 3308 kprintf("\n"); 3309 } 3310 3311 static int 3312 emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 3313 { 3314 struct emx_softc *sc; 3315 struct ifnet *ifp; 3316 int error, result; 3317 3318 result = -1; 3319 error = sysctl_handle_int(oidp, &result, 0, req); 3320 if (error || !req->newptr) 3321 return (error); 3322 3323 sc = (struct emx_softc *)arg1; 3324 ifp = &sc->arpcom.ac_if; 3325 3326 lwkt_serialize_enter(ifp->if_serializer); 3327 3328 if (result == 1) 3329 emx_print_debug_info(sc); 3330 3331 /* 3332 * This value will cause a hex dump of the 3333 * first 32 16-bit words of the EEPROM to 3334 * the screen. 3335 */ 3336 if (result == 2) 3337 emx_print_nvm_info(sc); 3338 3339 lwkt_serialize_exit(ifp->if_serializer); 3340 3341 return (error); 3342 } 3343 3344 static int 3345 emx_sysctl_stats(SYSCTL_HANDLER_ARGS) 3346 { 3347 int error, result; 3348 3349 result = -1; 3350 error = sysctl_handle_int(oidp, &result, 0, req); 3351 if (error || !req->newptr) 3352 return (error); 3353 3354 if (result == 1) { 3355 struct emx_softc *sc = (struct emx_softc *)arg1; 3356 struct ifnet *ifp = &sc->arpcom.ac_if; 3357 3358 lwkt_serialize_enter(ifp->if_serializer); 3359 emx_print_hw_stats(sc); 3360 lwkt_serialize_exit(ifp->if_serializer); 3361 } 3362 return (error); 3363 } 3364 3365 static void 3366 emx_add_sysctl(struct emx_softc *sc) 3367 { 3368 #ifdef PROFILE_SERIALIZER 3369 struct ifnet *ifp = &sc->arpcom.ac_if; 3370 #endif 3371 #ifdef EMX_RSS_DEBUG 3372 char rx_pkt[32]; 3373 int i; 3374 #endif 3375 3376 sysctl_ctx_init(&sc->sysctl_ctx); 3377 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 3378 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 3379 device_get_nameunit(sc->dev), 3380 CTLFLAG_RD, 0, ""); 3381 if (sc->sysctl_tree == NULL) { 3382 device_printf(sc->dev, "can't add sysctl node\n"); 3383 return; 3384 } 3385 3386 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3387 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 3388 emx_sysctl_debug_info, "I", "Debug Information"); 3389 3390 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3391 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 3392 emx_sysctl_stats, "I", "Statistics"); 3393 3394 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3395 OID_AUTO, "rxd", CTLFLAG_RD, 3396 &sc->rx_data[0].num_rx_desc, 0, NULL); 3397 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3398 OID_AUTO, "txd", CTLFLAG_RD, &sc->num_tx_desc, 0, NULL); 3399 3400 #ifdef PROFILE_SERIALIZER 3401 SYSCTL_ADD_UINT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3402 OID_AUTO, "serializer_sleep", CTLFLAG_RW, 3403 &ifp->if_serializer->sleep_cnt, 0, NULL); 3404 SYSCTL_ADD_UINT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3405 OID_AUTO, "serializer_tryfail", CTLFLAG_RW, 3406 &ifp->if_serializer->tryfail_cnt, 0, NULL); 3407 SYSCTL_ADD_UINT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3408 OID_AUTO, "serializer_enter", CTLFLAG_RW, 3409 &ifp->if_serializer->enter_cnt, 0, NULL); 3410 SYSCTL_ADD_UINT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3411 OID_AUTO, "serializer_try", CTLFLAG_RW, 3412 &ifp->if_serializer->try_cnt, 0, NULL); 3413 #endif 3414 3415 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3416 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW, 3417 sc, 0, emx_sysctl_int_throttle, "I", 3418 "interrupt throttling rate"); 3419 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3420 OID_AUTO, "int_tx_nsegs", CTLTYPE_INT|CTLFLAG_RW, 3421 sc, 0, emx_sysctl_int_tx_nsegs, "I", 3422 "# segments per TX interrupt"); 3423 3424 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3425 OID_AUTO, "rx_ring_inuse", CTLFLAG_RD, 3426 &sc->rx_ring_inuse, 0, "RX ring in use"); 3427 3428 #ifdef EMX_RSS_DEBUG 3429 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3430 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 3431 0, "RSS debug level"); 3432 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3433 ksnprintf(rx_pkt, sizeof(rx_pkt), "rx%d_pkt", i); 3434 SYSCTL_ADD_UINT(&sc->sysctl_ctx, 3435 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, 3436 rx_pkt, CTLFLAG_RW, 3437 &sc->rx_data[i].rx_pkts, 0, "RXed packets"); 3438 } 3439 #endif 3440 } 3441 3442 static int 3443 emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS) 3444 { 3445 struct emx_softc *sc = (void *)arg1; 3446 struct ifnet *ifp = &sc->arpcom.ac_if; 3447 int error, throttle; 3448 3449 throttle = sc->int_throttle_ceil; 3450 error = sysctl_handle_int(oidp, &throttle, 0, req); 3451 if (error || req->newptr == NULL) 3452 return error; 3453 if (throttle < 0 || throttle > 1000000000 / 256) 3454 return EINVAL; 3455 3456 if (throttle) { 3457 /* 3458 * Set the interrupt throttling rate in 256ns increments, 3459 * recalculate sysctl value assignment to get exact frequency. 3460 */ 3461 throttle = 1000000000 / 256 / throttle; 3462 3463 /* Upper 16bits of ITR is reserved and should be zero */ 3464 if (throttle & 0xffff0000) 3465 return EINVAL; 3466 } 3467 3468 lwkt_serialize_enter(ifp->if_serializer); 3469 3470 if (throttle) 3471 sc->int_throttle_ceil = 1000000000 / 256 / throttle; 3472 else 3473 sc->int_throttle_ceil = 0; 3474 3475 if (ifp->if_flags & IFF_RUNNING) 3476 E1000_WRITE_REG(&sc->hw, E1000_ITR, throttle); 3477 3478 lwkt_serialize_exit(ifp->if_serializer); 3479 3480 if (bootverbose) { 3481 if_printf(ifp, "Interrupt moderation set to %d/sec\n", 3482 sc->int_throttle_ceil); 3483 } 3484 return 0; 3485 } 3486 3487 static int 3488 emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS) 3489 { 3490 struct emx_softc *sc = (void *)arg1; 3491 struct ifnet *ifp = &sc->arpcom.ac_if; 3492 int error, segs; 3493 3494 segs = sc->tx_int_nsegs; 3495 error = sysctl_handle_int(oidp, &segs, 0, req); 3496 if (error || req->newptr == NULL) 3497 return error; 3498 if (segs <= 0) 3499 return EINVAL; 3500 3501 lwkt_serialize_enter(ifp->if_serializer); 3502 3503 /* 3504 * Don't allow int_tx_nsegs to become: 3505 * o Less the oact_tx_desc 3506 * o Too large that no TX desc will cause TX interrupt to 3507 * be generated (OACTIVE will never recover) 3508 * o Too small that will cause tx_dd[] overflow 3509 */ 3510 if (segs < sc->oact_tx_desc || 3511 segs >= sc->num_tx_desc - sc->oact_tx_desc || 3512 segs < sc->num_tx_desc / EMX_TXDD_SAFE) { 3513 error = EINVAL; 3514 } else { 3515 error = 0; 3516 sc->tx_int_nsegs = segs; 3517 } 3518 3519 lwkt_serialize_exit(ifp->if_serializer); 3520 3521 return error; 3522 } 3523 3524 static int 3525 emx_dma_alloc(struct emx_softc *sc) 3526 { 3527 int error, i; 3528 3529 /* 3530 * Create top level busdma tag 3531 */ 3532 error = bus_dma_tag_create(NULL, 1, 0, 3533 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 3534 NULL, NULL, 3535 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 3536 0, &sc->parent_dtag); 3537 if (error) { 3538 device_printf(sc->dev, "could not create top level DMA tag\n"); 3539 return error; 3540 } 3541 3542 /* 3543 * Allocate transmit descriptors ring and buffers 3544 */ 3545 error = emx_create_tx_ring(sc); 3546 if (error) { 3547 device_printf(sc->dev, "Could not setup transmit structures\n"); 3548 return error; 3549 } 3550 3551 /* 3552 * Allocate receive descriptors ring and buffers 3553 */ 3554 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3555 error = emx_create_rx_ring(sc, &sc->rx_data[i]); 3556 if (error) { 3557 device_printf(sc->dev, 3558 "Could not setup receive structures\n"); 3559 return error; 3560 } 3561 } 3562 return 0; 3563 } 3564 3565 static void 3566 emx_dma_free(struct emx_softc *sc) 3567 { 3568 int i; 3569 3570 emx_destroy_tx_ring(sc, sc->num_tx_desc); 3571 3572 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3573 emx_destroy_rx_ring(sc, &sc->rx_data[i], 3574 sc->rx_data[i].num_rx_desc); 3575 } 3576 3577 /* Free top level busdma tag */ 3578 if (sc->parent_dtag != NULL) 3579 bus_dma_tag_destroy(sc->parent_dtag); 3580 } 3581