1 /* 2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 3 * 4 * Copyright (c) 2001-2008, Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * 34 * Copyright (c) 2005 The DragonFly Project. All rights reserved. 35 * 36 * This code is derived from software contributed to The DragonFly Project 37 * by Matthew Dillon <dillon@backplane.com> 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in 47 * the documentation and/or other materials provided with the 48 * distribution. 49 * 3. Neither the name of The DragonFly Project nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific, prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 */ 66 67 #include "opt_ifpoll.h" 68 #include "opt_emx.h" 69 70 #include <sys/param.h> 71 #include <sys/bus.h> 72 #include <sys/endian.h> 73 #include <sys/interrupt.h> 74 #include <sys/kernel.h> 75 #include <sys/ktr.h> 76 #include <sys/malloc.h> 77 #include <sys/mbuf.h> 78 #include <sys/proc.h> 79 #include <sys/rman.h> 80 #include <sys/serialize.h> 81 #include <sys/serialize2.h> 82 #include <sys/socket.h> 83 #include <sys/sockio.h> 84 #include <sys/sysctl.h> 85 #include <sys/systm.h> 86 87 #include <net/bpf.h> 88 #include <net/ethernet.h> 89 #include <net/if.h> 90 #include <net/if_arp.h> 91 #include <net/if_dl.h> 92 #include <net/if_media.h> 93 #include <net/ifq_var.h> 94 #include <net/toeplitz.h> 95 #include <net/toeplitz2.h> 96 #include <net/vlan/if_vlan_var.h> 97 #include <net/vlan/if_vlan_ether.h> 98 #include <net/if_poll.h> 99 100 #include <netinet/in_systm.h> 101 #include <netinet/in.h> 102 #include <netinet/ip.h> 103 #include <netinet/tcp.h> 104 #include <netinet/udp.h> 105 106 #include <bus/pci/pcivar.h> 107 #include <bus/pci/pcireg.h> 108 109 #include <dev/netif/ig_hal/e1000_api.h> 110 #include <dev/netif/ig_hal/e1000_82571.h> 111 #include <dev/netif/emx/if_emx.h> 112 113 #ifdef EMX_RSS_DEBUG 114 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \ 115 do { \ 116 if (sc->rss_debug >= lvl) \ 117 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \ 118 } while (0) 119 #else /* !EMX_RSS_DEBUG */ 120 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0) 121 #endif /* EMX_RSS_DEBUG */ 122 123 #define EMX_TX_SERIALIZE 1 124 #define EMX_RX_SERIALIZE 2 125 126 #define EMX_NAME "Intel(R) PRO/1000 " 127 128 #define EMX_DEVICE(id) \ 129 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id } 130 #define EMX_DEVICE_NULL { 0, 0, NULL } 131 132 static const struct emx_device { 133 uint16_t vid; 134 uint16_t did; 135 const char *desc; 136 } emx_devices[] = { 137 EMX_DEVICE(82571EB_COPPER), 138 EMX_DEVICE(82571EB_FIBER), 139 EMX_DEVICE(82571EB_SERDES), 140 EMX_DEVICE(82571EB_SERDES_DUAL), 141 EMX_DEVICE(82571EB_SERDES_QUAD), 142 EMX_DEVICE(82571EB_QUAD_COPPER), 143 EMX_DEVICE(82571EB_QUAD_COPPER_BP), 144 EMX_DEVICE(82571EB_QUAD_COPPER_LP), 145 EMX_DEVICE(82571EB_QUAD_FIBER), 146 EMX_DEVICE(82571PT_QUAD_COPPER), 147 148 EMX_DEVICE(82572EI_COPPER), 149 EMX_DEVICE(82572EI_FIBER), 150 EMX_DEVICE(82572EI_SERDES), 151 EMX_DEVICE(82572EI), 152 153 EMX_DEVICE(82573E), 154 EMX_DEVICE(82573E_IAMT), 155 EMX_DEVICE(82573L), 156 157 EMX_DEVICE(80003ES2LAN_COPPER_SPT), 158 EMX_DEVICE(80003ES2LAN_SERDES_SPT), 159 EMX_DEVICE(80003ES2LAN_COPPER_DPT), 160 EMX_DEVICE(80003ES2LAN_SERDES_DPT), 161 162 EMX_DEVICE(82574L), 163 EMX_DEVICE(82574LA), 164 165 /* required last entry */ 166 EMX_DEVICE_NULL 167 }; 168 169 static int emx_probe(device_t); 170 static int emx_attach(device_t); 171 static int emx_detach(device_t); 172 static int emx_shutdown(device_t); 173 static int emx_suspend(device_t); 174 static int emx_resume(device_t); 175 176 static void emx_init(void *); 177 static void emx_stop(struct emx_softc *); 178 static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 179 static void emx_start(struct ifnet *); 180 #ifdef IFPOLL_ENABLE 181 static void emx_npoll(struct ifnet *, struct ifpoll_info *); 182 static void emx_npoll_status(struct ifnet *); 183 static void emx_npoll_tx(struct ifnet *, void *, int); 184 static void emx_npoll_rx(struct ifnet *, void *, int); 185 #endif 186 static void emx_watchdog(struct ifnet *); 187 static void emx_media_status(struct ifnet *, struct ifmediareq *); 188 static int emx_media_change(struct ifnet *); 189 static void emx_timer(void *); 190 static void emx_serialize(struct ifnet *, enum ifnet_serialize); 191 static void emx_deserialize(struct ifnet *, enum ifnet_serialize); 192 static int emx_tryserialize(struct ifnet *, enum ifnet_serialize); 193 #ifdef INVARIANTS 194 static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize, 195 boolean_t); 196 #endif 197 198 static void emx_intr(void *); 199 static void emx_intr_mask(void *); 200 static void emx_intr_body(struct emx_softc *, boolean_t); 201 static void emx_rxeof(struct emx_rxdata *, int); 202 static void emx_txeof(struct emx_txdata *); 203 static void emx_tx_collect(struct emx_txdata *); 204 static void emx_tx_purge(struct emx_softc *); 205 static void emx_enable_intr(struct emx_softc *); 206 static void emx_disable_intr(struct emx_softc *); 207 208 static int emx_dma_alloc(struct emx_softc *); 209 static void emx_dma_free(struct emx_softc *); 210 static void emx_init_tx_ring(struct emx_txdata *); 211 static int emx_init_rx_ring(struct emx_rxdata *); 212 static void emx_free_rx_ring(struct emx_rxdata *); 213 static int emx_create_tx_ring(struct emx_txdata *); 214 static int emx_create_rx_ring(struct emx_rxdata *); 215 static void emx_destroy_tx_ring(struct emx_txdata *, int); 216 static void emx_destroy_rx_ring(struct emx_rxdata *, int); 217 static int emx_newbuf(struct emx_rxdata *, int, int); 218 static int emx_encap(struct emx_txdata *, struct mbuf **); 219 static int emx_txcsum(struct emx_txdata *, struct mbuf *, 220 uint32_t *, uint32_t *); 221 static int emx_tso_pullup(struct emx_txdata *, struct mbuf **); 222 static int emx_tso_setup(struct emx_txdata *, struct mbuf *, 223 uint32_t *, uint32_t *); 224 225 static int emx_is_valid_eaddr(const uint8_t *); 226 static int emx_reset(struct emx_softc *); 227 static void emx_setup_ifp(struct emx_softc *); 228 static void emx_init_tx_unit(struct emx_softc *); 229 static void emx_init_rx_unit(struct emx_softc *); 230 static void emx_update_stats(struct emx_softc *); 231 static void emx_set_promisc(struct emx_softc *); 232 static void emx_disable_promisc(struct emx_softc *); 233 static void emx_set_multi(struct emx_softc *); 234 static void emx_update_link_status(struct emx_softc *); 235 static void emx_smartspeed(struct emx_softc *); 236 static void emx_set_itr(struct emx_softc *, uint32_t); 237 static void emx_disable_aspm(struct emx_softc *); 238 239 static void emx_print_debug_info(struct emx_softc *); 240 static void emx_print_nvm_info(struct emx_softc *); 241 static void emx_print_hw_stats(struct emx_softc *); 242 243 static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS); 244 static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 245 static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS); 246 static int emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS); 247 #ifdef IFPOLL_ENABLE 248 static int emx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS); 249 static int emx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS); 250 #endif 251 static void emx_add_sysctl(struct emx_softc *); 252 253 static void emx_serialize_skipmain(struct emx_softc *); 254 static void emx_deserialize_skipmain(struct emx_softc *); 255 256 /* Management and WOL Support */ 257 static void emx_get_mgmt(struct emx_softc *); 258 static void emx_rel_mgmt(struct emx_softc *); 259 static void emx_get_hw_control(struct emx_softc *); 260 static void emx_rel_hw_control(struct emx_softc *); 261 static void emx_enable_wol(device_t); 262 263 static device_method_t emx_methods[] = { 264 /* Device interface */ 265 DEVMETHOD(device_probe, emx_probe), 266 DEVMETHOD(device_attach, emx_attach), 267 DEVMETHOD(device_detach, emx_detach), 268 DEVMETHOD(device_shutdown, emx_shutdown), 269 DEVMETHOD(device_suspend, emx_suspend), 270 DEVMETHOD(device_resume, emx_resume), 271 { 0, 0 } 272 }; 273 274 static driver_t emx_driver = { 275 "emx", 276 emx_methods, 277 sizeof(struct emx_softc), 278 }; 279 280 static devclass_t emx_devclass; 281 282 DECLARE_DUMMY_MODULE(if_emx); 283 MODULE_DEPEND(emx, ig_hal, 1, 1, 1); 284 DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, NULL, NULL); 285 286 /* 287 * Tunables 288 */ 289 static int emx_int_throttle_ceil = EMX_DEFAULT_ITR; 290 static int emx_rxd = EMX_DEFAULT_RXD; 291 static int emx_txd = EMX_DEFAULT_TXD; 292 static int emx_smart_pwr_down = 0; 293 static int emx_rxr = 0; 294 295 /* Controls whether promiscuous also shows bad packets */ 296 static int emx_debug_sbp = 0; 297 298 static int emx_82573_workaround = 1; 299 static int emx_msi_enable = 1; 300 301 TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil); 302 TUNABLE_INT("hw.emx.rxd", &emx_rxd); 303 TUNABLE_INT("hw.emx.rxr", &emx_rxr); 304 TUNABLE_INT("hw.emx.txd", &emx_txd); 305 TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down); 306 TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp); 307 TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround); 308 TUNABLE_INT("hw.emx.msi.enable", &emx_msi_enable); 309 310 /* Global used in WOL setup with multiport cards */ 311 static int emx_global_quad_port_a = 0; 312 313 /* Set this to one to display debug statistics */ 314 static int emx_display_debug_stats = 0; 315 316 #if !defined(KTR_IF_EMX) 317 #define KTR_IF_EMX KTR_ALL 318 #endif 319 KTR_INFO_MASTER(if_emx); 320 KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin"); 321 KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end"); 322 KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet"); 323 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet"); 324 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean"); 325 #define logif(name) KTR_LOG(if_emx_ ## name) 326 327 static __inline void 328 emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf) 329 { 330 rxd->rxd_bufaddr = htole64(rxbuf->paddr); 331 /* DD bit must be cleared */ 332 rxd->rxd_staterr = 0; 333 } 334 335 static __inline void 336 emx_rxcsum(uint32_t staterr, struct mbuf *mp) 337 { 338 /* Ignore Checksum bit is set */ 339 if (staterr & E1000_RXD_STAT_IXSM) 340 return; 341 342 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) == 343 E1000_RXD_STAT_IPCS) 344 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID; 345 346 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) == 347 E1000_RXD_STAT_TCPCS) { 348 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 349 CSUM_PSEUDO_HDR | 350 CSUM_FRAG_NOT_CHECKED; 351 mp->m_pkthdr.csum_data = htons(0xffff); 352 } 353 } 354 355 static __inline struct pktinfo * 356 emx_rssinfo(struct mbuf *m, struct pktinfo *pi, 357 uint32_t mrq, uint32_t hash, uint32_t staterr) 358 { 359 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) { 360 case EMX_RXDMRQ_IPV4_TCP: 361 pi->pi_netisr = NETISR_IP; 362 pi->pi_flags = 0; 363 pi->pi_l3proto = IPPROTO_TCP; 364 break; 365 366 case EMX_RXDMRQ_IPV6_TCP: 367 pi->pi_netisr = NETISR_IPV6; 368 pi->pi_flags = 0; 369 pi->pi_l3proto = IPPROTO_TCP; 370 break; 371 372 case EMX_RXDMRQ_IPV4: 373 if (staterr & E1000_RXD_STAT_IXSM) 374 return NULL; 375 376 if ((staterr & 377 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) == 378 E1000_RXD_STAT_TCPCS) { 379 pi->pi_netisr = NETISR_IP; 380 pi->pi_flags = 0; 381 pi->pi_l3proto = IPPROTO_UDP; 382 break; 383 } 384 /* FALL THROUGH */ 385 default: 386 return NULL; 387 } 388 389 m->m_flags |= M_HASH; 390 m->m_pkthdr.hash = toeplitz_hash(hash); 391 return pi; 392 } 393 394 static int 395 emx_probe(device_t dev) 396 { 397 const struct emx_device *d; 398 uint16_t vid, did; 399 400 vid = pci_get_vendor(dev); 401 did = pci_get_device(dev); 402 403 for (d = emx_devices; d->desc != NULL; ++d) { 404 if (vid == d->vid && did == d->did) { 405 device_set_desc(dev, d->desc); 406 device_set_async_attach(dev, TRUE); 407 return 0; 408 } 409 } 410 return ENXIO; 411 } 412 413 static int 414 emx_attach(device_t dev) 415 { 416 struct emx_softc *sc = device_get_softc(dev); 417 struct ifnet *ifp = &sc->arpcom.ac_if; 418 int error = 0, i, throttle, msi_enable; 419 u_int intr_flags; 420 uint16_t eeprom_data, device_id, apme_mask; 421 driver_intr_t *intr_func; 422 #ifdef IFPOLL_ENABLE 423 int offset, offset_def; 424 #endif 425 426 /* 427 * Setup RX rings 428 */ 429 for (i = 0; i < EMX_NRX_RING; ++i) { 430 sc->rx_data[i].sc = sc; 431 sc->rx_data[i].idx = i; 432 } 433 434 /* 435 * Setup TX ring 436 */ 437 sc->tx_data.sc = sc; 438 sc->tx_data.idx = 0; 439 440 /* 441 * Initialize serializers 442 */ 443 lwkt_serialize_init(&sc->main_serialize); 444 lwkt_serialize_init(&sc->tx_data.tx_serialize); 445 for (i = 0; i < EMX_NRX_RING; ++i) 446 lwkt_serialize_init(&sc->rx_data[i].rx_serialize); 447 448 /* 449 * Initialize serializer array 450 */ 451 i = 0; 452 sc->serializes[i++] = &sc->main_serialize; 453 454 KKASSERT(i == EMX_TX_SERIALIZE); 455 sc->serializes[i++] = &sc->tx_data.tx_serialize; 456 457 KKASSERT(i == EMX_RX_SERIALIZE); 458 sc->serializes[i++] = &sc->rx_data[0].rx_serialize; 459 sc->serializes[i++] = &sc->rx_data[1].rx_serialize; 460 KKASSERT(i == EMX_NSERIALIZE); 461 462 callout_init_mp(&sc->timer); 463 464 sc->dev = sc->osdep.dev = dev; 465 466 /* 467 * Determine hardware and mac type 468 */ 469 sc->hw.vendor_id = pci_get_vendor(dev); 470 sc->hw.device_id = pci_get_device(dev); 471 sc->hw.revision_id = pci_get_revid(dev); 472 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev); 473 sc->hw.subsystem_device_id = pci_get_subdevice(dev); 474 475 if (e1000_set_mac_type(&sc->hw)) 476 return ENXIO; 477 478 /* 479 * Pullup extra 4bytes into the first data segment, see: 480 * 82571/82572 specification update errata #7 481 * 482 * NOTE: 483 * 4bytes instead of 2bytes, which are mentioned in the errata, 484 * are pulled; mainly to keep rest of the data properly aligned. 485 */ 486 if (sc->hw.mac.type == e1000_82571 || sc->hw.mac.type == e1000_82572) 487 sc->flags |= EMX_FLAG_TSO_PULLEX; 488 489 /* Enable bus mastering */ 490 pci_enable_busmaster(dev); 491 492 /* 493 * Allocate IO memory 494 */ 495 sc->memory_rid = EMX_BAR_MEM; 496 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 497 &sc->memory_rid, RF_ACTIVE); 498 if (sc->memory == NULL) { 499 device_printf(dev, "Unable to allocate bus resource: memory\n"); 500 error = ENXIO; 501 goto fail; 502 } 503 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); 504 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory); 505 506 /* XXX This is quite goofy, it is not actually used */ 507 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle; 508 509 /* 510 * Don't enable MSI-X on 82574, see: 511 * 82574 specification update errata #15 512 * 513 * Don't enable MSI on 82571/82572, see: 514 * 82571/82572 specification update errata #63 515 */ 516 msi_enable = emx_msi_enable; 517 if (msi_enable && 518 (sc->hw.mac.type == e1000_82571 || 519 sc->hw.mac.type == e1000_82572)) 520 msi_enable = 0; 521 522 /* 523 * Allocate interrupt 524 */ 525 sc->intr_type = pci_alloc_1intr(dev, msi_enable, 526 &sc->intr_rid, &intr_flags); 527 528 if (sc->intr_type == PCI_INTR_TYPE_LEGACY) { 529 int unshared; 530 531 unshared = device_getenv_int(dev, "irq.unshared", 0); 532 if (!unshared) { 533 sc->flags |= EMX_FLAG_SHARED_INTR; 534 if (bootverbose) 535 device_printf(dev, "IRQ shared\n"); 536 } else { 537 intr_flags &= ~RF_SHAREABLE; 538 if (bootverbose) 539 device_printf(dev, "IRQ unshared\n"); 540 } 541 } 542 543 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid, 544 intr_flags); 545 if (sc->intr_res == NULL) { 546 device_printf(dev, "Unable to allocate bus resource: " 547 "interrupt\n"); 548 error = ENXIO; 549 goto fail; 550 } 551 552 /* Save PCI command register for Shared Code */ 553 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 554 sc->hw.back = &sc->osdep; 555 556 /* Do Shared Code initialization */ 557 if (e1000_setup_init_funcs(&sc->hw, TRUE)) { 558 device_printf(dev, "Setup of Shared code failed\n"); 559 error = ENXIO; 560 goto fail; 561 } 562 e1000_get_bus_info(&sc->hw); 563 564 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG; 565 sc->hw.phy.autoneg_wait_to_complete = FALSE; 566 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT; 567 568 /* 569 * Interrupt throttle rate 570 */ 571 throttle = device_getenv_int(dev, "int_throttle_ceil", 572 emx_int_throttle_ceil); 573 if (throttle == 0) { 574 sc->int_throttle_ceil = 0; 575 } else { 576 if (throttle < 0) 577 throttle = EMX_DEFAULT_ITR; 578 579 /* Recalculate the tunable value to get the exact frequency. */ 580 throttle = 1000000000 / 256 / throttle; 581 582 /* Upper 16bits of ITR is reserved and should be zero */ 583 if (throttle & 0xffff0000) 584 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR; 585 586 sc->int_throttle_ceil = 1000000000 / 256 / throttle; 587 } 588 589 e1000_init_script_state_82541(&sc->hw, TRUE); 590 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE); 591 592 /* Copper options */ 593 if (sc->hw.phy.media_type == e1000_media_type_copper) { 594 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES; 595 sc->hw.phy.disable_polarity_correction = FALSE; 596 sc->hw.phy.ms_type = EMX_MASTER_SLAVE; 597 } 598 599 /* Set the frame limits assuming standard ethernet sized frames. */ 600 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN; 601 sc->min_frame_size = ETHER_MIN_LEN; 602 603 /* This controls when hardware reports transmit completion status. */ 604 sc->hw.mac.report_tx_early = 1; 605 606 /* Calculate # of RX rings */ 607 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", emx_rxr); 608 sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, EMX_NRX_RING); 609 610 /* Allocate RX/TX rings' busdma(9) stuffs */ 611 error = emx_dma_alloc(sc); 612 if (error) 613 goto fail; 614 615 /* Allocate multicast array memory. */ 616 sc->mta = kmalloc(ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX, 617 M_DEVBUF, M_WAITOK); 618 619 /* Indicate SOL/IDER usage */ 620 if (e1000_check_reset_block(&sc->hw)) { 621 device_printf(dev, 622 "PHY reset is blocked due to SOL/IDER session.\n"); 623 } 624 625 /* 626 * Start from a known state, this is important in reading the 627 * nvm and mac from that. 628 */ 629 e1000_reset_hw(&sc->hw); 630 631 /* Make sure we have a good EEPROM before we read from it */ 632 if (e1000_validate_nvm_checksum(&sc->hw) < 0) { 633 /* 634 * Some PCI-E parts fail the first check due to 635 * the link being in sleep state, call it again, 636 * if it fails a second time its a real issue. 637 */ 638 if (e1000_validate_nvm_checksum(&sc->hw) < 0) { 639 device_printf(dev, 640 "The EEPROM Checksum Is Not Valid\n"); 641 error = EIO; 642 goto fail; 643 } 644 } 645 646 /* Copy the permanent MAC address out of the EEPROM */ 647 if (e1000_read_mac_addr(&sc->hw) < 0) { 648 device_printf(dev, "EEPROM read error while reading MAC" 649 " address\n"); 650 error = EIO; 651 goto fail; 652 } 653 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) { 654 device_printf(dev, "Invalid MAC address\n"); 655 error = EIO; 656 goto fail; 657 } 658 659 /* Determine if we have to control management hardware */ 660 if (e1000_enable_mng_pass_thru(&sc->hw)) 661 sc->flags |= EMX_FLAG_HAS_MGMT; 662 663 /* 664 * Setup Wake-on-Lan 665 */ 666 apme_mask = EMX_EEPROM_APME; 667 eeprom_data = 0; 668 switch (sc->hw.mac.type) { 669 case e1000_82573: 670 sc->flags |= EMX_FLAG_HAS_AMT; 671 /* FALL THROUGH */ 672 673 case e1000_82571: 674 case e1000_82572: 675 case e1000_80003es2lan: 676 if (sc->hw.bus.func == 1) { 677 e1000_read_nvm(&sc->hw, 678 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 679 } else { 680 e1000_read_nvm(&sc->hw, 681 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 682 } 683 break; 684 685 default: 686 e1000_read_nvm(&sc->hw, 687 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 688 break; 689 } 690 if (eeprom_data & apme_mask) 691 sc->wol = E1000_WUFC_MAG | E1000_WUFC_MC; 692 693 /* 694 * We have the eeprom settings, now apply the special cases 695 * where the eeprom may be wrong or the board won't support 696 * wake on lan on a particular port 697 */ 698 device_id = pci_get_device(dev); 699 switch (device_id) { 700 case E1000_DEV_ID_82571EB_FIBER: 701 /* 702 * Wake events only supported on port A for dual fiber 703 * regardless of eeprom setting 704 */ 705 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 706 E1000_STATUS_FUNC_1) 707 sc->wol = 0; 708 break; 709 710 case E1000_DEV_ID_82571EB_QUAD_COPPER: 711 case E1000_DEV_ID_82571EB_QUAD_FIBER: 712 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 713 /* if quad port sc, disable WoL on all but port A */ 714 if (emx_global_quad_port_a != 0) 715 sc->wol = 0; 716 /* Reset for multiple quad port adapters */ 717 if (++emx_global_quad_port_a == 4) 718 emx_global_quad_port_a = 0; 719 break; 720 } 721 722 /* XXX disable wol */ 723 sc->wol = 0; 724 725 #ifdef IFPOLL_ENABLE 726 /* 727 * NPOLLING RX CPU offset 728 */ 729 if (sc->rx_ring_cnt == ncpus2) { 730 offset = 0; 731 } else { 732 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2; 733 offset = device_getenv_int(dev, "npoll.rxoff", offset_def); 734 if (offset >= ncpus2 || 735 offset % sc->rx_ring_cnt != 0) { 736 device_printf(dev, "invalid npoll.rxoff %d, use %d\n", 737 offset, offset_def); 738 offset = offset_def; 739 } 740 } 741 sc->rx_npoll_off = offset; 742 743 /* 744 * NPOLLING TX CPU offset 745 */ 746 offset_def = sc->rx_npoll_off; 747 offset = device_getenv_int(dev, "npoll.txoff", offset_def); 748 if (offset >= ncpus2) { 749 device_printf(dev, "invalid npoll.txoff %d, use %d\n", 750 offset, offset_def); 751 offset = offset_def; 752 } 753 sc->tx_npoll_off = offset; 754 #endif 755 756 /* Setup OS specific network interface */ 757 emx_setup_ifp(sc); 758 759 /* Add sysctl tree, must after em_setup_ifp() */ 760 emx_add_sysctl(sc); 761 762 /* Reset the hardware */ 763 error = emx_reset(sc); 764 if (error) { 765 device_printf(dev, "Unable to reset the hardware\n"); 766 goto fail; 767 } 768 769 /* Initialize statistics */ 770 emx_update_stats(sc); 771 772 sc->hw.mac.get_link_status = 1; 773 emx_update_link_status(sc); 774 775 sc->tx_data.spare_tx_desc = EMX_TX_SPARE; 776 777 /* 778 * Keep following relationship between spare_tx_desc, oact_tx_desc 779 * and tx_int_nsegs: 780 * (spare_tx_desc + EMX_TX_RESERVED) <= 781 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_int_nsegs 782 */ 783 sc->tx_data.oact_tx_desc = sc->tx_data.num_tx_desc / 8; 784 if (sc->tx_data.oact_tx_desc > EMX_TX_OACTIVE_MAX) 785 sc->tx_data.oact_tx_desc = EMX_TX_OACTIVE_MAX; 786 if (sc->tx_data.oact_tx_desc < 787 sc->tx_data.spare_tx_desc + EMX_TX_RESERVED) { 788 sc->tx_data.oact_tx_desc = sc->tx_data.spare_tx_desc + 789 EMX_TX_RESERVED; 790 } 791 792 sc->tx_data.tx_int_nsegs = sc->tx_data.num_tx_desc / 16; 793 if (sc->tx_data.tx_int_nsegs < sc->tx_data.oact_tx_desc) 794 sc->tx_data.tx_int_nsegs = sc->tx_data.oact_tx_desc; 795 796 /* Non-AMT based hardware can now take control from firmware */ 797 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) == 798 EMX_FLAG_HAS_MGMT) 799 emx_get_hw_control(sc); 800 801 /* 802 * Missing Interrupt Following ICR read: 803 * 804 * 82571/82572 specification update errata #76 805 * 82573 specification update errata #31 806 * 82574 specification update errata #12 807 */ 808 intr_func = emx_intr; 809 if ((sc->flags & EMX_FLAG_SHARED_INTR) && 810 (sc->hw.mac.type == e1000_82571 || 811 sc->hw.mac.type == e1000_82572 || 812 sc->hw.mac.type == e1000_82573 || 813 sc->hw.mac.type == e1000_82574)) 814 intr_func = emx_intr_mask; 815 816 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, intr_func, sc, 817 &sc->intr_tag, &sc->main_serialize); 818 if (error) { 819 device_printf(dev, "Failed to register interrupt handler"); 820 ether_ifdetach(&sc->arpcom.ac_if); 821 goto fail; 822 } 823 824 ifp->if_cpuid = rman_get_cpuid(sc->intr_res); 825 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 826 return (0); 827 fail: 828 emx_detach(dev); 829 return (error); 830 } 831 832 static int 833 emx_detach(device_t dev) 834 { 835 struct emx_softc *sc = device_get_softc(dev); 836 837 if (device_is_attached(dev)) { 838 struct ifnet *ifp = &sc->arpcom.ac_if; 839 840 ifnet_serialize_all(ifp); 841 842 emx_stop(sc); 843 844 e1000_phy_hw_reset(&sc->hw); 845 846 emx_rel_mgmt(sc); 847 emx_rel_hw_control(sc); 848 849 if (sc->wol) { 850 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 851 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 852 emx_enable_wol(dev); 853 } 854 855 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag); 856 857 ifnet_deserialize_all(ifp); 858 859 ether_ifdetach(ifp); 860 } else if (sc->memory != NULL) { 861 emx_rel_hw_control(sc); 862 } 863 bus_generic_detach(dev); 864 865 if (sc->intr_res != NULL) { 866 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid, 867 sc->intr_res); 868 } 869 870 if (sc->intr_type == PCI_INTR_TYPE_MSI) 871 pci_release_msi(dev); 872 873 if (sc->memory != NULL) { 874 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid, 875 sc->memory); 876 } 877 878 emx_dma_free(sc); 879 880 /* Free sysctl tree */ 881 if (sc->sysctl_tree != NULL) 882 sysctl_ctx_free(&sc->sysctl_ctx); 883 884 if (sc->mta != NULL) 885 kfree(sc->mta, M_DEVBUF); 886 887 return (0); 888 } 889 890 static int 891 emx_shutdown(device_t dev) 892 { 893 return emx_suspend(dev); 894 } 895 896 static int 897 emx_suspend(device_t dev) 898 { 899 struct emx_softc *sc = device_get_softc(dev); 900 struct ifnet *ifp = &sc->arpcom.ac_if; 901 902 ifnet_serialize_all(ifp); 903 904 emx_stop(sc); 905 906 emx_rel_mgmt(sc); 907 emx_rel_hw_control(sc); 908 909 if (sc->wol) { 910 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 911 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 912 emx_enable_wol(dev); 913 } 914 915 ifnet_deserialize_all(ifp); 916 917 return bus_generic_suspend(dev); 918 } 919 920 static int 921 emx_resume(device_t dev) 922 { 923 struct emx_softc *sc = device_get_softc(dev); 924 struct ifnet *ifp = &sc->arpcom.ac_if; 925 926 ifnet_serialize_all(ifp); 927 928 emx_init(sc); 929 emx_get_mgmt(sc); 930 if_devstart(ifp); 931 932 ifnet_deserialize_all(ifp); 933 934 return bus_generic_resume(dev); 935 } 936 937 static void 938 emx_start(struct ifnet *ifp) 939 { 940 struct emx_softc *sc = ifp->if_softc; 941 struct emx_txdata *tdata = &sc->tx_data; 942 struct mbuf *m_head; 943 944 ASSERT_SERIALIZED(&sc->tx_data.tx_serialize); 945 946 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 947 return; 948 949 if (!sc->link_active) { 950 ifq_purge(&ifp->if_snd); 951 return; 952 } 953 954 while (!ifq_is_empty(&ifp->if_snd)) { 955 /* Now do we at least have a minimal? */ 956 if (EMX_IS_OACTIVE(tdata)) { 957 emx_tx_collect(tdata); 958 if (EMX_IS_OACTIVE(tdata)) { 959 ifp->if_flags |= IFF_OACTIVE; 960 break; 961 } 962 } 963 964 logif(pkt_txqueue); 965 m_head = ifq_dequeue(&ifp->if_snd, NULL); 966 if (m_head == NULL) 967 break; 968 969 if (emx_encap(tdata, &m_head)) { 970 ifp->if_oerrors++; 971 emx_tx_collect(tdata); 972 continue; 973 } 974 975 /* Send a copy of the frame to the BPF listener */ 976 ETHER_BPF_MTAP(ifp, m_head); 977 978 /* Set timeout in case hardware has problems transmitting. */ 979 ifp->if_timer = EMX_TX_TIMEOUT; 980 } 981 } 982 983 static int 984 emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 985 { 986 struct emx_softc *sc = ifp->if_softc; 987 struct ifreq *ifr = (struct ifreq *)data; 988 uint16_t eeprom_data = 0; 989 int max_frame_size, mask, reinit; 990 int error = 0; 991 992 ASSERT_IFNET_SERIALIZED_ALL(ifp); 993 994 switch (command) { 995 case SIOCSIFMTU: 996 switch (sc->hw.mac.type) { 997 case e1000_82573: 998 /* 999 * 82573 only supports jumbo frames 1000 * if ASPM is disabled. 1001 */ 1002 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1, 1003 &eeprom_data); 1004 if (eeprom_data & NVM_WORD1A_ASPM_MASK) { 1005 max_frame_size = ETHER_MAX_LEN; 1006 break; 1007 } 1008 /* FALL THROUGH */ 1009 1010 /* Limit Jumbo Frame size */ 1011 case e1000_82571: 1012 case e1000_82572: 1013 case e1000_82574: 1014 case e1000_80003es2lan: 1015 max_frame_size = 9234; 1016 break; 1017 1018 default: 1019 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1020 break; 1021 } 1022 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN - 1023 ETHER_CRC_LEN) { 1024 error = EINVAL; 1025 break; 1026 } 1027 1028 ifp->if_mtu = ifr->ifr_mtu; 1029 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN + 1030 ETHER_CRC_LEN; 1031 1032 if (ifp->if_flags & IFF_RUNNING) 1033 emx_init(sc); 1034 break; 1035 1036 case SIOCSIFFLAGS: 1037 if (ifp->if_flags & IFF_UP) { 1038 if ((ifp->if_flags & IFF_RUNNING)) { 1039 if ((ifp->if_flags ^ sc->if_flags) & 1040 (IFF_PROMISC | IFF_ALLMULTI)) { 1041 emx_disable_promisc(sc); 1042 emx_set_promisc(sc); 1043 } 1044 } else { 1045 emx_init(sc); 1046 } 1047 } else if (ifp->if_flags & IFF_RUNNING) { 1048 emx_stop(sc); 1049 } 1050 sc->if_flags = ifp->if_flags; 1051 break; 1052 1053 case SIOCADDMULTI: 1054 case SIOCDELMULTI: 1055 if (ifp->if_flags & IFF_RUNNING) { 1056 emx_disable_intr(sc); 1057 emx_set_multi(sc); 1058 #ifdef IFPOLL_ENABLE 1059 if (!(ifp->if_flags & IFF_NPOLLING)) 1060 #endif 1061 emx_enable_intr(sc); 1062 } 1063 break; 1064 1065 case SIOCSIFMEDIA: 1066 /* Check SOL/IDER usage */ 1067 if (e1000_check_reset_block(&sc->hw)) { 1068 device_printf(sc->dev, "Media change is" 1069 " blocked due to SOL/IDER session.\n"); 1070 break; 1071 } 1072 /* FALL THROUGH */ 1073 1074 case SIOCGIFMEDIA: 1075 error = ifmedia_ioctl(ifp, ifr, &sc->media, command); 1076 break; 1077 1078 case SIOCSIFCAP: 1079 reinit = 0; 1080 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1081 if (mask & IFCAP_RXCSUM) { 1082 ifp->if_capenable ^= IFCAP_RXCSUM; 1083 reinit = 1; 1084 } 1085 if (mask & IFCAP_VLAN_HWTAGGING) { 1086 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1087 reinit = 1; 1088 } 1089 if (mask & IFCAP_TXCSUM) { 1090 ifp->if_capenable ^= IFCAP_TXCSUM; 1091 if (ifp->if_capenable & IFCAP_TXCSUM) 1092 ifp->if_hwassist |= EMX_CSUM_FEATURES; 1093 else 1094 ifp->if_hwassist &= ~EMX_CSUM_FEATURES; 1095 } 1096 if (mask & IFCAP_TSO) { 1097 ifp->if_capenable ^= IFCAP_TSO; 1098 if (ifp->if_capenable & IFCAP_TSO) 1099 ifp->if_hwassist |= CSUM_TSO; 1100 else 1101 ifp->if_hwassist &= ~CSUM_TSO; 1102 } 1103 if (mask & IFCAP_RSS) 1104 ifp->if_capenable ^= IFCAP_RSS; 1105 if (reinit && (ifp->if_flags & IFF_RUNNING)) 1106 emx_init(sc); 1107 break; 1108 1109 default: 1110 error = ether_ioctl(ifp, command, data); 1111 break; 1112 } 1113 return (error); 1114 } 1115 1116 static void 1117 emx_watchdog(struct ifnet *ifp) 1118 { 1119 struct emx_softc *sc = ifp->if_softc; 1120 1121 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1122 1123 /* 1124 * The timer is set to 5 every time start queues a packet. 1125 * Then txeof keeps resetting it as long as it cleans at 1126 * least one descriptor. 1127 * Finally, anytime all descriptors are clean the timer is 1128 * set to 0. 1129 */ 1130 1131 if (E1000_READ_REG(&sc->hw, E1000_TDT(0)) == 1132 E1000_READ_REG(&sc->hw, E1000_TDH(0))) { 1133 /* 1134 * If we reach here, all TX jobs are completed and 1135 * the TX engine should have been idled for some time. 1136 * We don't need to call if_devstart() here. 1137 */ 1138 ifp->if_flags &= ~IFF_OACTIVE; 1139 ifp->if_timer = 0; 1140 return; 1141 } 1142 1143 /* 1144 * If we are in this routine because of pause frames, then 1145 * don't reset the hardware. 1146 */ 1147 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) { 1148 ifp->if_timer = EMX_TX_TIMEOUT; 1149 return; 1150 } 1151 1152 if (e1000_check_for_link(&sc->hw) == 0) 1153 if_printf(ifp, "watchdog timeout -- resetting\n"); 1154 1155 ifp->if_oerrors++; 1156 1157 emx_init(sc); 1158 1159 if (!ifq_is_empty(&ifp->if_snd)) 1160 if_devstart(ifp); 1161 } 1162 1163 static void 1164 emx_init(void *xsc) 1165 { 1166 struct emx_softc *sc = xsc; 1167 struct ifnet *ifp = &sc->arpcom.ac_if; 1168 device_t dev = sc->dev; 1169 uint32_t pba; 1170 int i; 1171 1172 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1173 1174 emx_stop(sc); 1175 1176 /* 1177 * Packet Buffer Allocation (PBA) 1178 * Writing PBA sets the receive portion of the buffer 1179 * the remainder is used for the transmit buffer. 1180 */ 1181 switch (sc->hw.mac.type) { 1182 /* Total Packet Buffer on these is 48K */ 1183 case e1000_82571: 1184 case e1000_82572: 1185 case e1000_80003es2lan: 1186 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 1187 break; 1188 1189 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 1190 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 1191 break; 1192 1193 case e1000_82574: 1194 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 1195 break; 1196 1197 default: 1198 /* Devices before 82547 had a Packet Buffer of 64K. */ 1199 if (sc->max_frame_size > 8192) 1200 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1201 else 1202 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1203 } 1204 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba); 1205 1206 /* Get the latest mac address, User can use a LAA */ 1207 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN); 1208 1209 /* Put the address into the Receive Address Array */ 1210 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1211 1212 /* 1213 * With the 82571 sc, RAR[0] may be overwritten 1214 * when the other port is reset, we make a duplicate 1215 * in RAR[14] for that eventuality, this assures 1216 * the interface continues to function. 1217 */ 1218 if (sc->hw.mac.type == e1000_82571) { 1219 e1000_set_laa_state_82571(&sc->hw, TRUE); 1220 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 1221 E1000_RAR_ENTRIES - 1); 1222 } 1223 1224 /* Initialize the hardware */ 1225 if (emx_reset(sc)) { 1226 device_printf(dev, "Unable to reset the hardware\n"); 1227 /* XXX emx_stop()? */ 1228 return; 1229 } 1230 emx_update_link_status(sc); 1231 1232 /* Setup VLAN support, basic and offload if available */ 1233 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1234 1235 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 1236 uint32_t ctrl; 1237 1238 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL); 1239 ctrl |= E1000_CTRL_VME; 1240 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl); 1241 } 1242 1243 /* Configure for OS presence */ 1244 emx_get_mgmt(sc); 1245 1246 /* Prepare transmit descriptors and buffers */ 1247 emx_init_tx_ring(&sc->tx_data); 1248 emx_init_tx_unit(sc); 1249 1250 /* Setup Multicast table */ 1251 emx_set_multi(sc); 1252 1253 /* Prepare receive descriptors and buffers */ 1254 for (i = 0; i < sc->rx_ring_cnt; ++i) { 1255 if (emx_init_rx_ring(&sc->rx_data[i])) { 1256 device_printf(dev, 1257 "Could not setup receive structures\n"); 1258 emx_stop(sc); 1259 return; 1260 } 1261 } 1262 emx_init_rx_unit(sc); 1263 1264 /* Don't lose promiscuous settings */ 1265 emx_set_promisc(sc); 1266 1267 ifp->if_flags |= IFF_RUNNING; 1268 ifp->if_flags &= ~IFF_OACTIVE; 1269 1270 callout_reset(&sc->timer, hz, emx_timer, sc); 1271 e1000_clear_hw_cntrs_base_generic(&sc->hw); 1272 1273 /* MSI/X configuration for 82574 */ 1274 if (sc->hw.mac.type == e1000_82574) { 1275 int tmp; 1276 1277 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 1278 tmp |= E1000_CTRL_EXT_PBA_CLR; 1279 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp); 1280 /* 1281 * XXX MSIX 1282 * Set the IVAR - interrupt vector routing. 1283 * Each nibble represents a vector, high bit 1284 * is enable, other 3 bits are the MSIX table 1285 * entry, we map RXQ0 to 0, TXQ0 to 1, and 1286 * Link (other) to 2, hence the magic number. 1287 */ 1288 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908); 1289 } 1290 1291 #ifdef IFPOLL_ENABLE 1292 /* 1293 * Only enable interrupts if we are not polling, make sure 1294 * they are off otherwise. 1295 */ 1296 if (ifp->if_flags & IFF_NPOLLING) 1297 emx_disable_intr(sc); 1298 else 1299 #endif /* IFPOLL_ENABLE */ 1300 emx_enable_intr(sc); 1301 1302 /* AMT based hardware can now take control from firmware */ 1303 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) == 1304 (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) 1305 emx_get_hw_control(sc); 1306 1307 /* Don't reset the phy next time init gets called */ 1308 sc->hw.phy.reset_disable = TRUE; 1309 } 1310 1311 static void 1312 emx_intr(void *xsc) 1313 { 1314 emx_intr_body(xsc, TRUE); 1315 } 1316 1317 static void 1318 emx_intr_body(struct emx_softc *sc, boolean_t chk_asserted) 1319 { 1320 struct ifnet *ifp = &sc->arpcom.ac_if; 1321 uint32_t reg_icr; 1322 1323 logif(intr_beg); 1324 ASSERT_SERIALIZED(&sc->main_serialize); 1325 1326 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1327 1328 if (chk_asserted && (reg_icr & E1000_ICR_INT_ASSERTED) == 0) { 1329 logif(intr_end); 1330 return; 1331 } 1332 1333 /* 1334 * XXX: some laptops trigger several spurious interrupts 1335 * on emx(4) when in the resume cycle. The ICR register 1336 * reports all-ones value in this case. Processing such 1337 * interrupts would lead to a freeze. I don't know why. 1338 */ 1339 if (reg_icr == 0xffffffff) { 1340 logif(intr_end); 1341 return; 1342 } 1343 1344 if (ifp->if_flags & IFF_RUNNING) { 1345 if (reg_icr & 1346 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) { 1347 int i; 1348 1349 for (i = 0; i < sc->rx_ring_cnt; ++i) { 1350 lwkt_serialize_enter( 1351 &sc->rx_data[i].rx_serialize); 1352 emx_rxeof(&sc->rx_data[i], -1); 1353 lwkt_serialize_exit( 1354 &sc->rx_data[i].rx_serialize); 1355 } 1356 } 1357 if (reg_icr & E1000_ICR_TXDW) { 1358 lwkt_serialize_enter(&sc->tx_data.tx_serialize); 1359 emx_txeof(&sc->tx_data); 1360 if (!ifq_is_empty(&ifp->if_snd)) 1361 if_devstart(ifp); 1362 lwkt_serialize_exit(&sc->tx_data.tx_serialize); 1363 } 1364 } 1365 1366 /* Link status change */ 1367 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1368 emx_serialize_skipmain(sc); 1369 1370 callout_stop(&sc->timer); 1371 sc->hw.mac.get_link_status = 1; 1372 emx_update_link_status(sc); 1373 1374 /* Deal with TX cruft when link lost */ 1375 emx_tx_purge(sc); 1376 1377 callout_reset(&sc->timer, hz, emx_timer, sc); 1378 1379 emx_deserialize_skipmain(sc); 1380 } 1381 1382 if (reg_icr & E1000_ICR_RXO) 1383 sc->rx_overruns++; 1384 1385 logif(intr_end); 1386 } 1387 1388 static void 1389 emx_intr_mask(void *xsc) 1390 { 1391 struct emx_softc *sc = xsc; 1392 1393 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff); 1394 /* 1395 * NOTE: 1396 * ICR.INT_ASSERTED bit will never be set if IMS is 0, 1397 * so don't check it. 1398 */ 1399 emx_intr_body(sc, FALSE); 1400 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK); 1401 } 1402 1403 static void 1404 emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1405 { 1406 struct emx_softc *sc = ifp->if_softc; 1407 1408 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1409 1410 emx_update_link_status(sc); 1411 1412 ifmr->ifm_status = IFM_AVALID; 1413 ifmr->ifm_active = IFM_ETHER; 1414 1415 if (!sc->link_active) 1416 return; 1417 1418 ifmr->ifm_status |= IFM_ACTIVE; 1419 1420 if (sc->hw.phy.media_type == e1000_media_type_fiber || 1421 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 1422 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX; 1423 } else { 1424 switch (sc->link_speed) { 1425 case 10: 1426 ifmr->ifm_active |= IFM_10_T; 1427 break; 1428 case 100: 1429 ifmr->ifm_active |= IFM_100_TX; 1430 break; 1431 1432 case 1000: 1433 ifmr->ifm_active |= IFM_1000_T; 1434 break; 1435 } 1436 if (sc->link_duplex == FULL_DUPLEX) 1437 ifmr->ifm_active |= IFM_FDX; 1438 else 1439 ifmr->ifm_active |= IFM_HDX; 1440 } 1441 } 1442 1443 static int 1444 emx_media_change(struct ifnet *ifp) 1445 { 1446 struct emx_softc *sc = ifp->if_softc; 1447 struct ifmedia *ifm = &sc->media; 1448 1449 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1450 1451 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1452 return (EINVAL); 1453 1454 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1455 case IFM_AUTO: 1456 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG; 1457 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT; 1458 break; 1459 1460 case IFM_1000_LX: 1461 case IFM_1000_SX: 1462 case IFM_1000_T: 1463 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG; 1464 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1465 break; 1466 1467 case IFM_100_TX: 1468 sc->hw.mac.autoneg = FALSE; 1469 sc->hw.phy.autoneg_advertised = 0; 1470 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1471 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1472 else 1473 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1474 break; 1475 1476 case IFM_10_T: 1477 sc->hw.mac.autoneg = FALSE; 1478 sc->hw.phy.autoneg_advertised = 0; 1479 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1480 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1481 else 1482 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1483 break; 1484 1485 default: 1486 if_printf(ifp, "Unsupported media type\n"); 1487 break; 1488 } 1489 1490 /* 1491 * As the speed/duplex settings my have changed we need to 1492 * reset the PHY. 1493 */ 1494 sc->hw.phy.reset_disable = FALSE; 1495 1496 emx_init(sc); 1497 1498 return (0); 1499 } 1500 1501 static int 1502 emx_encap(struct emx_txdata *tdata, struct mbuf **m_headp) 1503 { 1504 bus_dma_segment_t segs[EMX_MAX_SCATTER]; 1505 bus_dmamap_t map; 1506 struct emx_txbuf *tx_buffer, *tx_buffer_mapped; 1507 struct e1000_tx_desc *ctxd = NULL; 1508 struct mbuf *m_head = *m_headp; 1509 uint32_t txd_upper, txd_lower, cmd = 0; 1510 int maxsegs, nsegs, i, j, first, last = 0, error; 1511 1512 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 1513 error = emx_tso_pullup(tdata, m_headp); 1514 if (error) 1515 return error; 1516 m_head = *m_headp; 1517 } 1518 1519 txd_upper = txd_lower = 0; 1520 1521 /* 1522 * Capture the first descriptor index, this descriptor 1523 * will have the index of the EOP which is the only one 1524 * that now gets a DONE bit writeback. 1525 */ 1526 first = tdata->next_avail_tx_desc; 1527 tx_buffer = &tdata->tx_buf[first]; 1528 tx_buffer_mapped = tx_buffer; 1529 map = tx_buffer->map; 1530 1531 maxsegs = tdata->num_tx_desc_avail - EMX_TX_RESERVED; 1532 KASSERT(maxsegs >= tdata->spare_tx_desc, ("not enough spare TX desc")); 1533 if (maxsegs > EMX_MAX_SCATTER) 1534 maxsegs = EMX_MAX_SCATTER; 1535 1536 error = bus_dmamap_load_mbuf_defrag(tdata->txtag, map, m_headp, 1537 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 1538 if (error) { 1539 m_freem(*m_headp); 1540 *m_headp = NULL; 1541 return error; 1542 } 1543 bus_dmamap_sync(tdata->txtag, map, BUS_DMASYNC_PREWRITE); 1544 1545 m_head = *m_headp; 1546 tdata->tx_nsegs += nsegs; 1547 1548 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 1549 /* TSO will consume one TX desc */ 1550 tdata->tx_nsegs += emx_tso_setup(tdata, m_head, 1551 &txd_upper, &txd_lower); 1552 } else if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) { 1553 /* TX csum offloading will consume one TX desc */ 1554 tdata->tx_nsegs += emx_txcsum(tdata, m_head, 1555 &txd_upper, &txd_lower); 1556 } 1557 i = tdata->next_avail_tx_desc; 1558 1559 /* Set up our transmit descriptors */ 1560 for (j = 0; j < nsegs; j++) { 1561 tx_buffer = &tdata->tx_buf[i]; 1562 ctxd = &tdata->tx_desc_base[i]; 1563 1564 ctxd->buffer_addr = htole64(segs[j].ds_addr); 1565 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS | 1566 txd_lower | segs[j].ds_len); 1567 ctxd->upper.data = htole32(txd_upper); 1568 1569 last = i; 1570 if (++i == tdata->num_tx_desc) 1571 i = 0; 1572 } 1573 1574 tdata->next_avail_tx_desc = i; 1575 1576 KKASSERT(tdata->num_tx_desc_avail > nsegs); 1577 tdata->num_tx_desc_avail -= nsegs; 1578 1579 /* Handle VLAN tag */ 1580 if (m_head->m_flags & M_VLANTAG) { 1581 /* Set the vlan id. */ 1582 ctxd->upper.fields.special = 1583 htole16(m_head->m_pkthdr.ether_vlantag); 1584 1585 /* Tell hardware to add tag */ 1586 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE); 1587 } 1588 1589 tx_buffer->m_head = m_head; 1590 tx_buffer_mapped->map = tx_buffer->map; 1591 tx_buffer->map = map; 1592 1593 if (tdata->tx_nsegs >= tdata->tx_int_nsegs) { 1594 tdata->tx_nsegs = 0; 1595 1596 /* 1597 * Report Status (RS) is turned on 1598 * every tx_int_nsegs descriptors. 1599 */ 1600 cmd = E1000_TXD_CMD_RS; 1601 1602 /* 1603 * Keep track of the descriptor, which will 1604 * be written back by hardware. 1605 */ 1606 tdata->tx_dd[tdata->tx_dd_tail] = last; 1607 EMX_INC_TXDD_IDX(tdata->tx_dd_tail); 1608 KKASSERT(tdata->tx_dd_tail != tdata->tx_dd_head); 1609 } 1610 1611 /* 1612 * Last Descriptor of Packet needs End Of Packet (EOP) 1613 */ 1614 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd); 1615 1616 /* 1617 * Advance the Transmit Descriptor Tail (TDT), this tells 1618 * the E1000 that this frame is available to transmit. 1619 */ 1620 E1000_WRITE_REG(&tdata->sc->hw, E1000_TDT(0), i); 1621 1622 return (0); 1623 } 1624 1625 static void 1626 emx_set_promisc(struct emx_softc *sc) 1627 { 1628 struct ifnet *ifp = &sc->arpcom.ac_if; 1629 uint32_t reg_rctl; 1630 1631 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1632 1633 if (ifp->if_flags & IFF_PROMISC) { 1634 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1635 /* Turn this on if you want to see bad packets */ 1636 if (emx_debug_sbp) 1637 reg_rctl |= E1000_RCTL_SBP; 1638 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1639 } else if (ifp->if_flags & IFF_ALLMULTI) { 1640 reg_rctl |= E1000_RCTL_MPE; 1641 reg_rctl &= ~E1000_RCTL_UPE; 1642 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1643 } 1644 } 1645 1646 static void 1647 emx_disable_promisc(struct emx_softc *sc) 1648 { 1649 uint32_t reg_rctl; 1650 1651 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1652 1653 reg_rctl &= ~E1000_RCTL_UPE; 1654 reg_rctl &= ~E1000_RCTL_MPE; 1655 reg_rctl &= ~E1000_RCTL_SBP; 1656 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1657 } 1658 1659 static void 1660 emx_set_multi(struct emx_softc *sc) 1661 { 1662 struct ifnet *ifp = &sc->arpcom.ac_if; 1663 struct ifmultiaddr *ifma; 1664 uint32_t reg_rctl = 0; 1665 uint8_t *mta; 1666 int mcnt = 0; 1667 1668 mta = sc->mta; 1669 bzero(mta, ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX); 1670 1671 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1672 if (ifma->ifma_addr->sa_family != AF_LINK) 1673 continue; 1674 1675 if (mcnt == EMX_MCAST_ADDR_MAX) 1676 break; 1677 1678 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1679 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1680 mcnt++; 1681 } 1682 1683 if (mcnt >= EMX_MCAST_ADDR_MAX) { 1684 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1685 reg_rctl |= E1000_RCTL_MPE; 1686 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1687 } else { 1688 e1000_update_mc_addr_list(&sc->hw, mta, mcnt); 1689 } 1690 } 1691 1692 /* 1693 * This routine checks for link status and updates statistics. 1694 */ 1695 static void 1696 emx_timer(void *xsc) 1697 { 1698 struct emx_softc *sc = xsc; 1699 struct ifnet *ifp = &sc->arpcom.ac_if; 1700 1701 lwkt_serialize_enter(&sc->main_serialize); 1702 1703 emx_update_link_status(sc); 1704 emx_update_stats(sc); 1705 1706 /* Reset LAA into RAR[0] on 82571 */ 1707 if (e1000_get_laa_state_82571(&sc->hw) == TRUE) 1708 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1709 1710 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING)) 1711 emx_print_hw_stats(sc); 1712 1713 emx_smartspeed(sc); 1714 1715 callout_reset(&sc->timer, hz, emx_timer, sc); 1716 1717 lwkt_serialize_exit(&sc->main_serialize); 1718 } 1719 1720 static void 1721 emx_update_link_status(struct emx_softc *sc) 1722 { 1723 struct e1000_hw *hw = &sc->hw; 1724 struct ifnet *ifp = &sc->arpcom.ac_if; 1725 device_t dev = sc->dev; 1726 uint32_t link_check = 0; 1727 1728 /* Get the cached link value or read phy for real */ 1729 switch (hw->phy.media_type) { 1730 case e1000_media_type_copper: 1731 if (hw->mac.get_link_status) { 1732 /* Do the work to read phy */ 1733 e1000_check_for_link(hw); 1734 link_check = !hw->mac.get_link_status; 1735 if (link_check) /* ESB2 fix */ 1736 e1000_cfg_on_link_up(hw); 1737 } else { 1738 link_check = TRUE; 1739 } 1740 break; 1741 1742 case e1000_media_type_fiber: 1743 e1000_check_for_link(hw); 1744 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU; 1745 break; 1746 1747 case e1000_media_type_internal_serdes: 1748 e1000_check_for_link(hw); 1749 link_check = sc->hw.mac.serdes_has_link; 1750 break; 1751 1752 case e1000_media_type_unknown: 1753 default: 1754 break; 1755 } 1756 1757 /* Now check for a transition */ 1758 if (link_check && sc->link_active == 0) { 1759 e1000_get_speed_and_duplex(hw, &sc->link_speed, 1760 &sc->link_duplex); 1761 1762 /* 1763 * Check if we should enable/disable SPEED_MODE bit on 1764 * 82571EB/82572EI 1765 */ 1766 if (sc->link_speed != SPEED_1000 && 1767 (hw->mac.type == e1000_82571 || 1768 hw->mac.type == e1000_82572)) { 1769 int tarc0; 1770 1771 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1772 tarc0 &= ~EMX_TARC_SPEED_MODE; 1773 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1774 } 1775 if (bootverbose) { 1776 device_printf(dev, "Link is up %d Mbps %s\n", 1777 sc->link_speed, 1778 ((sc->link_duplex == FULL_DUPLEX) ? 1779 "Full Duplex" : "Half Duplex")); 1780 } 1781 sc->link_active = 1; 1782 sc->smartspeed = 0; 1783 ifp->if_baudrate = sc->link_speed * 1000000; 1784 ifp->if_link_state = LINK_STATE_UP; 1785 if_link_state_change(ifp); 1786 } else if (!link_check && sc->link_active == 1) { 1787 ifp->if_baudrate = sc->link_speed = 0; 1788 sc->link_duplex = 0; 1789 if (bootverbose) 1790 device_printf(dev, "Link is Down\n"); 1791 sc->link_active = 0; 1792 #if 0 1793 /* Link down, disable watchdog */ 1794 if->if_timer = 0; 1795 #endif 1796 ifp->if_link_state = LINK_STATE_DOWN; 1797 if_link_state_change(ifp); 1798 } 1799 } 1800 1801 static void 1802 emx_stop(struct emx_softc *sc) 1803 { 1804 struct ifnet *ifp = &sc->arpcom.ac_if; 1805 struct emx_txdata *tdata = &sc->tx_data; 1806 int i; 1807 1808 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1809 1810 emx_disable_intr(sc); 1811 1812 callout_stop(&sc->timer); 1813 1814 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1815 ifp->if_timer = 0; 1816 1817 /* 1818 * Disable multiple receive queues. 1819 * 1820 * NOTE: 1821 * We should disable multiple receive queues before 1822 * resetting the hardware. 1823 */ 1824 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0); 1825 1826 e1000_reset_hw(&sc->hw); 1827 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0); 1828 1829 for (i = 0; i < tdata->num_tx_desc; i++) { 1830 struct emx_txbuf *tx_buffer = &tdata->tx_buf[i]; 1831 1832 if (tx_buffer->m_head != NULL) { 1833 bus_dmamap_unload(tdata->txtag, tx_buffer->map); 1834 m_freem(tx_buffer->m_head); 1835 tx_buffer->m_head = NULL; 1836 } 1837 } 1838 1839 for (i = 0; i < sc->rx_ring_cnt; ++i) 1840 emx_free_rx_ring(&sc->rx_data[i]); 1841 1842 tdata->csum_flags = 0; 1843 tdata->csum_lhlen = 0; 1844 tdata->csum_iphlen = 0; 1845 tdata->csum_thlen = 0; 1846 tdata->csum_mss = 0; 1847 tdata->csum_pktlen = 0; 1848 1849 tdata->tx_dd_head = 0; 1850 tdata->tx_dd_tail = 0; 1851 tdata->tx_nsegs = 0; 1852 } 1853 1854 static int 1855 emx_reset(struct emx_softc *sc) 1856 { 1857 device_t dev = sc->dev; 1858 uint16_t rx_buffer_size; 1859 1860 /* Set up smart power down as default off on newer adapters. */ 1861 if (!emx_smart_pwr_down && 1862 (sc->hw.mac.type == e1000_82571 || 1863 sc->hw.mac.type == e1000_82572)) { 1864 uint16_t phy_tmp = 0; 1865 1866 /* Speed up time to link by disabling smart power down. */ 1867 e1000_read_phy_reg(&sc->hw, 1868 IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 1869 phy_tmp &= ~IGP02E1000_PM_SPD; 1870 e1000_write_phy_reg(&sc->hw, 1871 IGP02E1000_PHY_POWER_MGMT, phy_tmp); 1872 } 1873 1874 /* 1875 * These parameters control the automatic generation (Tx) and 1876 * response (Rx) to Ethernet PAUSE frames. 1877 * - High water mark should allow for at least two frames to be 1878 * received after sending an XOFF. 1879 * - Low water mark works best when it is very near the high water mark. 1880 * This allows the receiver to restart by sending XON when it has 1881 * drained a bit. Here we use an arbitary value of 1500 which will 1882 * restart after one full frame is pulled from the buffer. There 1883 * could be several smaller frames in the buffer and if so they will 1884 * not trigger the XON until their total number reduces the buffer 1885 * by 1500. 1886 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 1887 */ 1888 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10; 1889 1890 sc->hw.fc.high_water = rx_buffer_size - 1891 roundup2(sc->max_frame_size, 1024); 1892 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500; 1893 1894 if (sc->hw.mac.type == e1000_80003es2lan) 1895 sc->hw.fc.pause_time = 0xFFFF; 1896 else 1897 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME; 1898 sc->hw.fc.send_xon = TRUE; 1899 sc->hw.fc.requested_mode = e1000_fc_full; 1900 1901 /* Issue a global reset */ 1902 e1000_reset_hw(&sc->hw); 1903 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0); 1904 emx_disable_aspm(sc); 1905 1906 if (e1000_init_hw(&sc->hw) < 0) { 1907 device_printf(dev, "Hardware Initialization Failed\n"); 1908 return (EIO); 1909 } 1910 1911 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1912 e1000_get_phy_info(&sc->hw); 1913 e1000_check_for_link(&sc->hw); 1914 1915 return (0); 1916 } 1917 1918 static void 1919 emx_setup_ifp(struct emx_softc *sc) 1920 { 1921 struct ifnet *ifp = &sc->arpcom.ac_if; 1922 1923 if_initname(ifp, device_get_name(sc->dev), 1924 device_get_unit(sc->dev)); 1925 ifp->if_softc = sc; 1926 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1927 ifp->if_init = emx_init; 1928 ifp->if_ioctl = emx_ioctl; 1929 ifp->if_start = emx_start; 1930 #ifdef IFPOLL_ENABLE 1931 ifp->if_npoll = emx_npoll; 1932 #endif 1933 ifp->if_watchdog = emx_watchdog; 1934 ifp->if_serialize = emx_serialize; 1935 ifp->if_deserialize = emx_deserialize; 1936 ifp->if_tryserialize = emx_tryserialize; 1937 #ifdef INVARIANTS 1938 ifp->if_serialize_assert = emx_serialize_assert; 1939 #endif 1940 ifq_set_maxlen(&ifp->if_snd, sc->tx_data.num_tx_desc - 1); 1941 ifq_set_ready(&ifp->if_snd); 1942 1943 ether_ifattach(ifp, sc->hw.mac.addr, NULL); 1944 1945 ifp->if_capabilities = IFCAP_HWCSUM | 1946 IFCAP_VLAN_HWTAGGING | 1947 IFCAP_VLAN_MTU | 1948 IFCAP_TSO; 1949 if (sc->rx_ring_cnt > 1) 1950 ifp->if_capabilities |= IFCAP_RSS; 1951 ifp->if_capenable = ifp->if_capabilities; 1952 ifp->if_hwassist = EMX_CSUM_FEATURES | CSUM_TSO; 1953 1954 /* 1955 * Tell the upper layer(s) we support long frames. 1956 */ 1957 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1958 1959 /* 1960 * Specify the media types supported by this sc and register 1961 * callbacks to update media and link information 1962 */ 1963 ifmedia_init(&sc->media, IFM_IMASK, 1964 emx_media_change, emx_media_status); 1965 if (sc->hw.phy.media_type == e1000_media_type_fiber || 1966 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 1967 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX, 1968 0, NULL); 1969 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL); 1970 } else { 1971 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 1972 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 1973 0, NULL); 1974 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 1975 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 1976 0, NULL); 1977 if (sc->hw.phy.type != e1000_phy_ife) { 1978 ifmedia_add(&sc->media, 1979 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 1980 ifmedia_add(&sc->media, 1981 IFM_ETHER | IFM_1000_T, 0, NULL); 1982 } 1983 } 1984 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 1985 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO); 1986 } 1987 1988 /* 1989 * Workaround for SmartSpeed on 82541 and 82547 controllers 1990 */ 1991 static void 1992 emx_smartspeed(struct emx_softc *sc) 1993 { 1994 uint16_t phy_tmp; 1995 1996 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp || 1997 sc->hw.mac.autoneg == 0 || 1998 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 1999 return; 2000 2001 if (sc->smartspeed == 0) { 2002 /* 2003 * If Master/Slave config fault is asserted twice, 2004 * we assume back-to-back 2005 */ 2006 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2007 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2008 return; 2009 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2010 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2011 e1000_read_phy_reg(&sc->hw, 2012 PHY_1000T_CTRL, &phy_tmp); 2013 if (phy_tmp & CR_1000T_MS_ENABLE) { 2014 phy_tmp &= ~CR_1000T_MS_ENABLE; 2015 e1000_write_phy_reg(&sc->hw, 2016 PHY_1000T_CTRL, phy_tmp); 2017 sc->smartspeed++; 2018 if (sc->hw.mac.autoneg && 2019 !e1000_phy_setup_autoneg(&sc->hw) && 2020 !e1000_read_phy_reg(&sc->hw, 2021 PHY_CONTROL, &phy_tmp)) { 2022 phy_tmp |= MII_CR_AUTO_NEG_EN | 2023 MII_CR_RESTART_AUTO_NEG; 2024 e1000_write_phy_reg(&sc->hw, 2025 PHY_CONTROL, phy_tmp); 2026 } 2027 } 2028 } 2029 return; 2030 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) { 2031 /* If still no link, perhaps using 2/3 pair cable */ 2032 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2033 phy_tmp |= CR_1000T_MS_ENABLE; 2034 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2035 if (sc->hw.mac.autoneg && 2036 !e1000_phy_setup_autoneg(&sc->hw) && 2037 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) { 2038 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG; 2039 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp); 2040 } 2041 } 2042 2043 /* Restart process after EMX_SMARTSPEED_MAX iterations */ 2044 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX) 2045 sc->smartspeed = 0; 2046 } 2047 2048 static int 2049 emx_create_tx_ring(struct emx_txdata *tdata) 2050 { 2051 device_t dev = tdata->sc->dev; 2052 struct emx_txbuf *tx_buffer; 2053 int error, i, tsize, ntxd; 2054 2055 /* 2056 * Validate number of transmit descriptors. It must not exceed 2057 * hardware maximum, and must be multiple of E1000_DBA_ALIGN. 2058 */ 2059 ntxd = device_getenv_int(dev, "txd", emx_txd); 2060 if ((ntxd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 || 2061 ntxd > EMX_MAX_TXD || ntxd < EMX_MIN_TXD) { 2062 device_printf(dev, "Using %d TX descriptors instead of %d!\n", 2063 EMX_DEFAULT_TXD, ntxd); 2064 tdata->num_tx_desc = EMX_DEFAULT_TXD; 2065 } else { 2066 tdata->num_tx_desc = ntxd; 2067 } 2068 2069 /* 2070 * Allocate Transmit Descriptor ring 2071 */ 2072 tsize = roundup2(tdata->num_tx_desc * sizeof(struct e1000_tx_desc), 2073 EMX_DBA_ALIGN); 2074 tdata->tx_desc_base = bus_dmamem_coherent_any(tdata->sc->parent_dtag, 2075 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK, 2076 &tdata->tx_desc_dtag, &tdata->tx_desc_dmap, 2077 &tdata->tx_desc_paddr); 2078 if (tdata->tx_desc_base == NULL) { 2079 device_printf(dev, "Unable to allocate tx_desc memory\n"); 2080 return ENOMEM; 2081 } 2082 2083 tsize = __VM_CACHELINE_ALIGN( 2084 sizeof(struct emx_txbuf) * tdata->num_tx_desc); 2085 tdata->tx_buf = kmalloc_cachealign(tsize, M_DEVBUF, M_WAITOK | M_ZERO); 2086 2087 /* 2088 * Create DMA tags for tx buffers 2089 */ 2090 error = bus_dma_tag_create(tdata->sc->parent_dtag, /* parent */ 2091 1, 0, /* alignment, bounds */ 2092 BUS_SPACE_MAXADDR, /* lowaddr */ 2093 BUS_SPACE_MAXADDR, /* highaddr */ 2094 NULL, NULL, /* filter, filterarg */ 2095 EMX_TSO_SIZE, /* maxsize */ 2096 EMX_MAX_SCATTER, /* nsegments */ 2097 EMX_MAX_SEGSIZE, /* maxsegsize */ 2098 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | 2099 BUS_DMA_ONEBPAGE, /* flags */ 2100 &tdata->txtag); 2101 if (error) { 2102 device_printf(dev, "Unable to allocate TX DMA tag\n"); 2103 kfree(tdata->tx_buf, M_DEVBUF); 2104 tdata->tx_buf = NULL; 2105 return error; 2106 } 2107 2108 /* 2109 * Create DMA maps for tx buffers 2110 */ 2111 for (i = 0; i < tdata->num_tx_desc; i++) { 2112 tx_buffer = &tdata->tx_buf[i]; 2113 2114 error = bus_dmamap_create(tdata->txtag, 2115 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 2116 &tx_buffer->map); 2117 if (error) { 2118 device_printf(dev, "Unable to create TX DMA map\n"); 2119 emx_destroy_tx_ring(tdata, i); 2120 return error; 2121 } 2122 } 2123 return (0); 2124 } 2125 2126 static void 2127 emx_init_tx_ring(struct emx_txdata *tdata) 2128 { 2129 /* Clear the old ring contents */ 2130 bzero(tdata->tx_desc_base, 2131 sizeof(struct e1000_tx_desc) * tdata->num_tx_desc); 2132 2133 /* Reset state */ 2134 tdata->next_avail_tx_desc = 0; 2135 tdata->next_tx_to_clean = 0; 2136 tdata->num_tx_desc_avail = tdata->num_tx_desc; 2137 } 2138 2139 static void 2140 emx_init_tx_unit(struct emx_softc *sc) 2141 { 2142 uint32_t tctl, tarc, tipg = 0; 2143 uint64_t bus_addr; 2144 2145 /* Setup the Base and Length of the Tx Descriptor Ring */ 2146 bus_addr = sc->tx_data.tx_desc_paddr; 2147 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(0), 2148 sc->tx_data.num_tx_desc * sizeof(struct e1000_tx_desc)); 2149 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(0), 2150 (uint32_t)(bus_addr >> 32)); 2151 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(0), 2152 (uint32_t)bus_addr); 2153 /* Setup the HW Tx Head and Tail descriptor pointers */ 2154 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), 0); 2155 E1000_WRITE_REG(&sc->hw, E1000_TDH(0), 0); 2156 2157 /* Set the default values for the Tx Inter Packet Gap timer */ 2158 switch (sc->hw.mac.type) { 2159 case e1000_80003es2lan: 2160 tipg = DEFAULT_82543_TIPG_IPGR1; 2161 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 2162 E1000_TIPG_IPGR2_SHIFT; 2163 break; 2164 2165 default: 2166 if (sc->hw.phy.media_type == e1000_media_type_fiber || 2167 sc->hw.phy.media_type == e1000_media_type_internal_serdes) 2168 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2169 else 2170 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2171 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2172 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2173 break; 2174 } 2175 2176 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg); 2177 2178 /* NOTE: 0 is not allowed for TIDV */ 2179 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1); 2180 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0); 2181 2182 if (sc->hw.mac.type == e1000_82571 || 2183 sc->hw.mac.type == e1000_82572) { 2184 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0)); 2185 tarc |= EMX_TARC_SPEED_MODE; 2186 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc); 2187 } else if (sc->hw.mac.type == e1000_80003es2lan) { 2188 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0)); 2189 tarc |= 1; 2190 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc); 2191 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1)); 2192 tarc |= 1; 2193 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc); 2194 } 2195 2196 /* Program the Transmit Control Register */ 2197 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL); 2198 tctl &= ~E1000_TCTL_CT; 2199 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 2200 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2201 tctl |= E1000_TCTL_MULR; 2202 2203 /* This write will effectively turn on the transmit unit. */ 2204 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl); 2205 } 2206 2207 static void 2208 emx_destroy_tx_ring(struct emx_txdata *tdata, int ndesc) 2209 { 2210 struct emx_txbuf *tx_buffer; 2211 int i; 2212 2213 /* Free Transmit Descriptor ring */ 2214 if (tdata->tx_desc_base) { 2215 bus_dmamap_unload(tdata->tx_desc_dtag, tdata->tx_desc_dmap); 2216 bus_dmamem_free(tdata->tx_desc_dtag, tdata->tx_desc_base, 2217 tdata->tx_desc_dmap); 2218 bus_dma_tag_destroy(tdata->tx_desc_dtag); 2219 2220 tdata->tx_desc_base = NULL; 2221 } 2222 2223 if (tdata->tx_buf == NULL) 2224 return; 2225 2226 for (i = 0; i < ndesc; i++) { 2227 tx_buffer = &tdata->tx_buf[i]; 2228 2229 KKASSERT(tx_buffer->m_head == NULL); 2230 bus_dmamap_destroy(tdata->txtag, tx_buffer->map); 2231 } 2232 bus_dma_tag_destroy(tdata->txtag); 2233 2234 kfree(tdata->tx_buf, M_DEVBUF); 2235 tdata->tx_buf = NULL; 2236 } 2237 2238 /* 2239 * The offload context needs to be set when we transfer the first 2240 * packet of a particular protocol (TCP/UDP). This routine has been 2241 * enhanced to deal with inserted VLAN headers. 2242 * 2243 * If the new packet's ether header length, ip header length and 2244 * csum offloading type are same as the previous packet, we should 2245 * avoid allocating a new csum context descriptor; mainly to take 2246 * advantage of the pipeline effect of the TX data read request. 2247 * 2248 * This function returns number of TX descrptors allocated for 2249 * csum context. 2250 */ 2251 static int 2252 emx_txcsum(struct emx_txdata *tdata, struct mbuf *mp, 2253 uint32_t *txd_upper, uint32_t *txd_lower) 2254 { 2255 struct e1000_context_desc *TXD; 2256 int curr_txd, ehdrlen, csum_flags; 2257 uint32_t cmd, hdr_len, ip_hlen; 2258 2259 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES; 2260 ip_hlen = mp->m_pkthdr.csum_iphlen; 2261 ehdrlen = mp->m_pkthdr.csum_lhlen; 2262 2263 if (tdata->csum_lhlen == ehdrlen && tdata->csum_iphlen == ip_hlen && 2264 tdata->csum_flags == csum_flags) { 2265 /* 2266 * Same csum offload context as the previous packets; 2267 * just return. 2268 */ 2269 *txd_upper = tdata->csum_txd_upper; 2270 *txd_lower = tdata->csum_txd_lower; 2271 return 0; 2272 } 2273 2274 /* 2275 * Setup a new csum offload context. 2276 */ 2277 2278 curr_txd = tdata->next_avail_tx_desc; 2279 TXD = (struct e1000_context_desc *)&tdata->tx_desc_base[curr_txd]; 2280 2281 cmd = 0; 2282 2283 /* Setup of IP header checksum. */ 2284 if (csum_flags & CSUM_IP) { 2285 /* 2286 * Start offset for header checksum calculation. 2287 * End offset for header checksum calculation. 2288 * Offset of place to put the checksum. 2289 */ 2290 TXD->lower_setup.ip_fields.ipcss = ehdrlen; 2291 TXD->lower_setup.ip_fields.ipcse = 2292 htole16(ehdrlen + ip_hlen - 1); 2293 TXD->lower_setup.ip_fields.ipcso = 2294 ehdrlen + offsetof(struct ip, ip_sum); 2295 cmd |= E1000_TXD_CMD_IP; 2296 *txd_upper |= E1000_TXD_POPTS_IXSM << 8; 2297 } 2298 hdr_len = ehdrlen + ip_hlen; 2299 2300 if (csum_flags & CSUM_TCP) { 2301 /* 2302 * Start offset for payload checksum calculation. 2303 * End offset for payload checksum calculation. 2304 * Offset of place to put the checksum. 2305 */ 2306 TXD->upper_setup.tcp_fields.tucss = hdr_len; 2307 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2308 TXD->upper_setup.tcp_fields.tucso = 2309 hdr_len + offsetof(struct tcphdr, th_sum); 2310 cmd |= E1000_TXD_CMD_TCP; 2311 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 2312 } else if (csum_flags & CSUM_UDP) { 2313 /* 2314 * Start offset for header checksum calculation. 2315 * End offset for header checksum calculation. 2316 * Offset of place to put the checksum. 2317 */ 2318 TXD->upper_setup.tcp_fields.tucss = hdr_len; 2319 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2320 TXD->upper_setup.tcp_fields.tucso = 2321 hdr_len + offsetof(struct udphdr, uh_sum); 2322 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 2323 } 2324 2325 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */ 2326 E1000_TXD_DTYP_D; /* Data descr */ 2327 2328 /* Save the information for this csum offloading context */ 2329 tdata->csum_lhlen = ehdrlen; 2330 tdata->csum_iphlen = ip_hlen; 2331 tdata->csum_flags = csum_flags; 2332 tdata->csum_txd_upper = *txd_upper; 2333 tdata->csum_txd_lower = *txd_lower; 2334 2335 TXD->tcp_seg_setup.data = htole32(0); 2336 TXD->cmd_and_length = 2337 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd); 2338 2339 if (++curr_txd == tdata->num_tx_desc) 2340 curr_txd = 0; 2341 2342 KKASSERT(tdata->num_tx_desc_avail > 0); 2343 tdata->num_tx_desc_avail--; 2344 2345 tdata->next_avail_tx_desc = curr_txd; 2346 return 1; 2347 } 2348 2349 static void 2350 emx_txeof(struct emx_txdata *tdata) 2351 { 2352 struct ifnet *ifp = &tdata->sc->arpcom.ac_if; 2353 struct emx_txbuf *tx_buffer; 2354 int first, num_avail; 2355 2356 if (tdata->tx_dd_head == tdata->tx_dd_tail) 2357 return; 2358 2359 if (tdata->num_tx_desc_avail == tdata->num_tx_desc) 2360 return; 2361 2362 num_avail = tdata->num_tx_desc_avail; 2363 first = tdata->next_tx_to_clean; 2364 2365 while (tdata->tx_dd_head != tdata->tx_dd_tail) { 2366 int dd_idx = tdata->tx_dd[tdata->tx_dd_head]; 2367 struct e1000_tx_desc *tx_desc; 2368 2369 tx_desc = &tdata->tx_desc_base[dd_idx]; 2370 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) { 2371 EMX_INC_TXDD_IDX(tdata->tx_dd_head); 2372 2373 if (++dd_idx == tdata->num_tx_desc) 2374 dd_idx = 0; 2375 2376 while (first != dd_idx) { 2377 logif(pkt_txclean); 2378 2379 num_avail++; 2380 2381 tx_buffer = &tdata->tx_buf[first]; 2382 if (tx_buffer->m_head) { 2383 ifp->if_opackets++; 2384 bus_dmamap_unload(tdata->txtag, 2385 tx_buffer->map); 2386 m_freem(tx_buffer->m_head); 2387 tx_buffer->m_head = NULL; 2388 } 2389 2390 if (++first == tdata->num_tx_desc) 2391 first = 0; 2392 } 2393 } else { 2394 break; 2395 } 2396 } 2397 tdata->next_tx_to_clean = first; 2398 tdata->num_tx_desc_avail = num_avail; 2399 2400 if (tdata->tx_dd_head == tdata->tx_dd_tail) { 2401 tdata->tx_dd_head = 0; 2402 tdata->tx_dd_tail = 0; 2403 } 2404 2405 if (!EMX_IS_OACTIVE(tdata)) { 2406 ifp->if_flags &= ~IFF_OACTIVE; 2407 2408 /* All clean, turn off the timer */ 2409 if (tdata->num_tx_desc_avail == tdata->num_tx_desc) 2410 ifp->if_timer = 0; 2411 } 2412 } 2413 2414 static void 2415 emx_tx_collect(struct emx_txdata *tdata) 2416 { 2417 struct ifnet *ifp = &tdata->sc->arpcom.ac_if; 2418 struct emx_txbuf *tx_buffer; 2419 int tdh, first, num_avail, dd_idx = -1; 2420 2421 if (tdata->num_tx_desc_avail == tdata->num_tx_desc) 2422 return; 2423 2424 tdh = E1000_READ_REG(&tdata->sc->hw, E1000_TDH(0)); 2425 if (tdh == tdata->next_tx_to_clean) 2426 return; 2427 2428 if (tdata->tx_dd_head != tdata->tx_dd_tail) 2429 dd_idx = tdata->tx_dd[tdata->tx_dd_head]; 2430 2431 num_avail = tdata->num_tx_desc_avail; 2432 first = tdata->next_tx_to_clean; 2433 2434 while (first != tdh) { 2435 logif(pkt_txclean); 2436 2437 num_avail++; 2438 2439 tx_buffer = &tdata->tx_buf[first]; 2440 if (tx_buffer->m_head) { 2441 ifp->if_opackets++; 2442 bus_dmamap_unload(tdata->txtag, 2443 tx_buffer->map); 2444 m_freem(tx_buffer->m_head); 2445 tx_buffer->m_head = NULL; 2446 } 2447 2448 if (first == dd_idx) { 2449 EMX_INC_TXDD_IDX(tdata->tx_dd_head); 2450 if (tdata->tx_dd_head == tdata->tx_dd_tail) { 2451 tdata->tx_dd_head = 0; 2452 tdata->tx_dd_tail = 0; 2453 dd_idx = -1; 2454 } else { 2455 dd_idx = tdata->tx_dd[tdata->tx_dd_head]; 2456 } 2457 } 2458 2459 if (++first == tdata->num_tx_desc) 2460 first = 0; 2461 } 2462 tdata->next_tx_to_clean = first; 2463 tdata->num_tx_desc_avail = num_avail; 2464 2465 if (!EMX_IS_OACTIVE(tdata)) { 2466 ifp->if_flags &= ~IFF_OACTIVE; 2467 2468 /* All clean, turn off the timer */ 2469 if (tdata->num_tx_desc_avail == tdata->num_tx_desc) 2470 ifp->if_timer = 0; 2471 } 2472 } 2473 2474 /* 2475 * When Link is lost sometimes there is work still in the TX ring 2476 * which will result in a watchdog, rather than allow that do an 2477 * attempted cleanup and then reinit here. Note that this has been 2478 * seens mostly with fiber adapters. 2479 */ 2480 static void 2481 emx_tx_purge(struct emx_softc *sc) 2482 { 2483 struct ifnet *ifp = &sc->arpcom.ac_if; 2484 2485 if (!sc->link_active && ifp->if_timer) { 2486 emx_tx_collect(&sc->tx_data); 2487 if (ifp->if_timer) { 2488 if_printf(ifp, "Link lost, TX pending, reinit\n"); 2489 ifp->if_timer = 0; 2490 emx_init(sc); 2491 } 2492 } 2493 } 2494 2495 static int 2496 emx_newbuf(struct emx_rxdata *rdata, int i, int init) 2497 { 2498 struct mbuf *m; 2499 bus_dma_segment_t seg; 2500 bus_dmamap_t map; 2501 struct emx_rxbuf *rx_buffer; 2502 int error, nseg; 2503 2504 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 2505 if (m == NULL) { 2506 if (init) { 2507 if_printf(&rdata->sc->arpcom.ac_if, 2508 "Unable to allocate RX mbuf\n"); 2509 } 2510 return (ENOBUFS); 2511 } 2512 m->m_len = m->m_pkthdr.len = MCLBYTES; 2513 2514 if (rdata->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN) 2515 m_adj(m, ETHER_ALIGN); 2516 2517 error = bus_dmamap_load_mbuf_segment(rdata->rxtag, 2518 rdata->rx_sparemap, m, 2519 &seg, 1, &nseg, BUS_DMA_NOWAIT); 2520 if (error) { 2521 m_freem(m); 2522 if (init) { 2523 if_printf(&rdata->sc->arpcom.ac_if, 2524 "Unable to load RX mbuf\n"); 2525 } 2526 return (error); 2527 } 2528 2529 rx_buffer = &rdata->rx_buf[i]; 2530 if (rx_buffer->m_head != NULL) 2531 bus_dmamap_unload(rdata->rxtag, rx_buffer->map); 2532 2533 map = rx_buffer->map; 2534 rx_buffer->map = rdata->rx_sparemap; 2535 rdata->rx_sparemap = map; 2536 2537 rx_buffer->m_head = m; 2538 rx_buffer->paddr = seg.ds_addr; 2539 2540 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer); 2541 return (0); 2542 } 2543 2544 static int 2545 emx_create_rx_ring(struct emx_rxdata *rdata) 2546 { 2547 device_t dev = rdata->sc->dev; 2548 struct emx_rxbuf *rx_buffer; 2549 int i, error, rsize, nrxd; 2550 2551 /* 2552 * Validate number of receive descriptors. It must not exceed 2553 * hardware maximum, and must be multiple of E1000_DBA_ALIGN. 2554 */ 2555 nrxd = device_getenv_int(dev, "rxd", emx_rxd); 2556 if ((nrxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 || 2557 nrxd > EMX_MAX_RXD || nrxd < EMX_MIN_RXD) { 2558 device_printf(dev, "Using %d RX descriptors instead of %d!\n", 2559 EMX_DEFAULT_RXD, nrxd); 2560 rdata->num_rx_desc = EMX_DEFAULT_RXD; 2561 } else { 2562 rdata->num_rx_desc = nrxd; 2563 } 2564 2565 /* 2566 * Allocate Receive Descriptor ring 2567 */ 2568 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t), 2569 EMX_DBA_ALIGN); 2570 rdata->rx_desc = bus_dmamem_coherent_any(rdata->sc->parent_dtag, 2571 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK, 2572 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap, 2573 &rdata->rx_desc_paddr); 2574 if (rdata->rx_desc == NULL) { 2575 device_printf(dev, "Unable to allocate rx_desc memory\n"); 2576 return ENOMEM; 2577 } 2578 2579 rsize = __VM_CACHELINE_ALIGN( 2580 sizeof(struct emx_rxbuf) * rdata->num_rx_desc); 2581 rdata->rx_buf = kmalloc_cachealign(rsize, M_DEVBUF, M_WAITOK | M_ZERO); 2582 2583 /* 2584 * Create DMA tag for rx buffers 2585 */ 2586 error = bus_dma_tag_create(rdata->sc->parent_dtag, /* parent */ 2587 1, 0, /* alignment, bounds */ 2588 BUS_SPACE_MAXADDR, /* lowaddr */ 2589 BUS_SPACE_MAXADDR, /* highaddr */ 2590 NULL, NULL, /* filter, filterarg */ 2591 MCLBYTES, /* maxsize */ 2592 1, /* nsegments */ 2593 MCLBYTES, /* maxsegsize */ 2594 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */ 2595 &rdata->rxtag); 2596 if (error) { 2597 device_printf(dev, "Unable to allocate RX DMA tag\n"); 2598 kfree(rdata->rx_buf, M_DEVBUF); 2599 rdata->rx_buf = NULL; 2600 return error; 2601 } 2602 2603 /* 2604 * Create spare DMA map for rx buffers 2605 */ 2606 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK, 2607 &rdata->rx_sparemap); 2608 if (error) { 2609 device_printf(dev, "Unable to create spare RX DMA map\n"); 2610 bus_dma_tag_destroy(rdata->rxtag); 2611 kfree(rdata->rx_buf, M_DEVBUF); 2612 rdata->rx_buf = NULL; 2613 return error; 2614 } 2615 2616 /* 2617 * Create DMA maps for rx buffers 2618 */ 2619 for (i = 0; i < rdata->num_rx_desc; i++) { 2620 rx_buffer = &rdata->rx_buf[i]; 2621 2622 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK, 2623 &rx_buffer->map); 2624 if (error) { 2625 device_printf(dev, "Unable to create RX DMA map\n"); 2626 emx_destroy_rx_ring(rdata, i); 2627 return error; 2628 } 2629 } 2630 return (0); 2631 } 2632 2633 static void 2634 emx_free_rx_ring(struct emx_rxdata *rdata) 2635 { 2636 int i; 2637 2638 for (i = 0; i < rdata->num_rx_desc; i++) { 2639 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i]; 2640 2641 if (rx_buffer->m_head != NULL) { 2642 bus_dmamap_unload(rdata->rxtag, rx_buffer->map); 2643 m_freem(rx_buffer->m_head); 2644 rx_buffer->m_head = NULL; 2645 } 2646 } 2647 2648 if (rdata->fmp != NULL) 2649 m_freem(rdata->fmp); 2650 rdata->fmp = NULL; 2651 rdata->lmp = NULL; 2652 } 2653 2654 static int 2655 emx_init_rx_ring(struct emx_rxdata *rdata) 2656 { 2657 int i, error; 2658 2659 /* Reset descriptor ring */ 2660 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc); 2661 2662 /* Allocate new ones. */ 2663 for (i = 0; i < rdata->num_rx_desc; i++) { 2664 error = emx_newbuf(rdata, i, 1); 2665 if (error) 2666 return (error); 2667 } 2668 2669 /* Setup our descriptor pointers */ 2670 rdata->next_rx_desc_to_check = 0; 2671 2672 return (0); 2673 } 2674 2675 static void 2676 emx_init_rx_unit(struct emx_softc *sc) 2677 { 2678 struct ifnet *ifp = &sc->arpcom.ac_if; 2679 uint64_t bus_addr; 2680 uint32_t rctl, itr, rfctl; 2681 int i; 2682 2683 /* 2684 * Make sure receives are disabled while setting 2685 * up the descriptor ring 2686 */ 2687 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2688 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2689 2690 /* 2691 * Set the interrupt throttling rate. Value is calculated 2692 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns) 2693 */ 2694 if (sc->int_throttle_ceil) 2695 itr = 1000000000 / 256 / sc->int_throttle_ceil; 2696 else 2697 itr = 0; 2698 emx_set_itr(sc, itr); 2699 2700 /* Use extended RX descriptor */ 2701 rfctl = E1000_RFCTL_EXTEN; 2702 2703 /* Disable accelerated ackknowledge */ 2704 if (sc->hw.mac.type == e1000_82574) 2705 rfctl |= E1000_RFCTL_ACK_DIS; 2706 2707 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl); 2708 2709 /* 2710 * Receive Checksum Offload for TCP and UDP 2711 * 2712 * Checksum offloading is also enabled if multiple receive 2713 * queue is to be supported, since we need it to figure out 2714 * packet type. 2715 */ 2716 if ((ifp->if_capenable & IFCAP_RXCSUM) || 2717 sc->rx_ring_cnt > 1) { 2718 uint32_t rxcsum; 2719 2720 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM); 2721 2722 /* 2723 * NOTE: 2724 * PCSD must be enabled to enable multiple 2725 * receive queues. 2726 */ 2727 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL | 2728 E1000_RXCSUM_PCSD; 2729 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum); 2730 } 2731 2732 /* 2733 * Configure multiple receive queue (RSS) 2734 */ 2735 if (sc->rx_ring_cnt > 1) { 2736 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE]; 2737 uint32_t reta; 2738 2739 KASSERT(sc->rx_ring_cnt == EMX_NRX_RING, 2740 ("invalid number of RX ring (%d)", sc->rx_ring_cnt)); 2741 2742 /* 2743 * NOTE: 2744 * When we reach here, RSS has already been disabled 2745 * in emx_stop(), so we could safely configure RSS key 2746 * and redirect table. 2747 */ 2748 2749 /* 2750 * Configure RSS key 2751 */ 2752 toeplitz_get_key(key, sizeof(key)); 2753 for (i = 0; i < EMX_NRSSRK; ++i) { 2754 uint32_t rssrk; 2755 2756 rssrk = EMX_RSSRK_VAL(key, i); 2757 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk); 2758 2759 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk); 2760 } 2761 2762 /* 2763 * Configure RSS redirect table in following fashion: 2764 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2765 */ 2766 reta = 0; 2767 for (i = 0; i < EMX_RETA_SIZE; ++i) { 2768 uint32_t q; 2769 2770 q = (i % sc->rx_ring_cnt) << EMX_RETA_RINGIDX_SHIFT; 2771 reta |= q << (8 * i); 2772 } 2773 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta); 2774 2775 for (i = 0; i < EMX_NRETA; ++i) 2776 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta); 2777 2778 /* 2779 * Enable multiple receive queues. 2780 * Enable IPv4 RSS standard hash functions. 2781 * Disable RSS interrupt. 2782 */ 2783 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 2784 E1000_MRQC_ENABLE_RSS_2Q | 2785 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2786 E1000_MRQC_RSS_FIELD_IPV4); 2787 } 2788 2789 /* 2790 * XXX TEMPORARY WORKAROUND: on some systems with 82573 2791 * long latencies are observed, like Lenovo X60. This 2792 * change eliminates the problem, but since having positive 2793 * values in RDTR is a known source of problems on other 2794 * platforms another solution is being sought. 2795 */ 2796 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) { 2797 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573); 2798 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573); 2799 } 2800 2801 for (i = 0; i < sc->rx_ring_cnt; ++i) { 2802 struct emx_rxdata *rdata = &sc->rx_data[i]; 2803 2804 /* 2805 * Setup the Base and Length of the Rx Descriptor Ring 2806 */ 2807 bus_addr = rdata->rx_desc_paddr; 2808 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i), 2809 rdata->num_rx_desc * sizeof(emx_rxdesc_t)); 2810 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i), 2811 (uint32_t)(bus_addr >> 32)); 2812 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i), 2813 (uint32_t)bus_addr); 2814 2815 /* 2816 * Setup the HW Rx Head and Tail Descriptor Pointers 2817 */ 2818 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0); 2819 E1000_WRITE_REG(&sc->hw, E1000_RDT(i), 2820 sc->rx_data[i].num_rx_desc - 1); 2821 } 2822 2823 /* Setup the Receive Control Register */ 2824 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 2825 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 2826 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC | 2827 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 2828 2829 /* Make sure VLAN Filters are off */ 2830 rctl &= ~E1000_RCTL_VFE; 2831 2832 /* Don't store bad paket */ 2833 rctl &= ~E1000_RCTL_SBP; 2834 2835 /* MCLBYTES */ 2836 rctl |= E1000_RCTL_SZ_2048; 2837 2838 if (ifp->if_mtu > ETHERMTU) 2839 rctl |= E1000_RCTL_LPE; 2840 else 2841 rctl &= ~E1000_RCTL_LPE; 2842 2843 /* Enable Receives */ 2844 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl); 2845 } 2846 2847 static void 2848 emx_destroy_rx_ring(struct emx_rxdata *rdata, int ndesc) 2849 { 2850 struct emx_rxbuf *rx_buffer; 2851 int i; 2852 2853 /* Free Receive Descriptor ring */ 2854 if (rdata->rx_desc) { 2855 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap); 2856 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc, 2857 rdata->rx_desc_dmap); 2858 bus_dma_tag_destroy(rdata->rx_desc_dtag); 2859 2860 rdata->rx_desc = NULL; 2861 } 2862 2863 if (rdata->rx_buf == NULL) 2864 return; 2865 2866 for (i = 0; i < ndesc; i++) { 2867 rx_buffer = &rdata->rx_buf[i]; 2868 2869 KKASSERT(rx_buffer->m_head == NULL); 2870 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map); 2871 } 2872 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap); 2873 bus_dma_tag_destroy(rdata->rxtag); 2874 2875 kfree(rdata->rx_buf, M_DEVBUF); 2876 rdata->rx_buf = NULL; 2877 } 2878 2879 static void 2880 emx_rxeof(struct emx_rxdata *rdata, int count) 2881 { 2882 struct ifnet *ifp = &rdata->sc->arpcom.ac_if; 2883 uint32_t staterr; 2884 emx_rxdesc_t *current_desc; 2885 struct mbuf *mp; 2886 int i; 2887 2888 i = rdata->next_rx_desc_to_check; 2889 current_desc = &rdata->rx_desc[i]; 2890 staterr = le32toh(current_desc->rxd_staterr); 2891 2892 if (!(staterr & E1000_RXD_STAT_DD)) 2893 return; 2894 2895 while ((staterr & E1000_RXD_STAT_DD) && count != 0) { 2896 struct pktinfo *pi = NULL, pi0; 2897 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i]; 2898 struct mbuf *m = NULL; 2899 int eop, len; 2900 2901 logif(pkt_receive); 2902 2903 mp = rx_buf->m_head; 2904 2905 /* 2906 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT 2907 * needs to access the last received byte in the mbuf. 2908 */ 2909 bus_dmamap_sync(rdata->rxtag, rx_buf->map, 2910 BUS_DMASYNC_POSTREAD); 2911 2912 len = le16toh(current_desc->rxd_length); 2913 if (staterr & E1000_RXD_STAT_EOP) { 2914 count--; 2915 eop = 1; 2916 } else { 2917 eop = 0; 2918 } 2919 2920 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) { 2921 uint16_t vlan = 0; 2922 uint32_t mrq, rss_hash; 2923 2924 /* 2925 * Save several necessary information, 2926 * before emx_newbuf() destroy it. 2927 */ 2928 if ((staterr & E1000_RXD_STAT_VP) && eop) 2929 vlan = le16toh(current_desc->rxd_vlan); 2930 2931 mrq = le32toh(current_desc->rxd_mrq); 2932 rss_hash = le32toh(current_desc->rxd_rss); 2933 2934 EMX_RSS_DPRINTF(rdata->sc, 10, 2935 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n", 2936 rdata->idx, mrq, rss_hash); 2937 2938 if (emx_newbuf(rdata, i, 0) != 0) { 2939 ifp->if_iqdrops++; 2940 goto discard; 2941 } 2942 2943 /* Assign correct length to the current fragment */ 2944 mp->m_len = len; 2945 2946 if (rdata->fmp == NULL) { 2947 mp->m_pkthdr.len = len; 2948 rdata->fmp = mp; /* Store the first mbuf */ 2949 rdata->lmp = mp; 2950 } else { 2951 /* 2952 * Chain mbuf's together 2953 */ 2954 rdata->lmp->m_next = mp; 2955 rdata->lmp = rdata->lmp->m_next; 2956 rdata->fmp->m_pkthdr.len += len; 2957 } 2958 2959 if (eop) { 2960 rdata->fmp->m_pkthdr.rcvif = ifp; 2961 ifp->if_ipackets++; 2962 2963 if (ifp->if_capenable & IFCAP_RXCSUM) 2964 emx_rxcsum(staterr, rdata->fmp); 2965 2966 if (staterr & E1000_RXD_STAT_VP) { 2967 rdata->fmp->m_pkthdr.ether_vlantag = 2968 vlan; 2969 rdata->fmp->m_flags |= M_VLANTAG; 2970 } 2971 m = rdata->fmp; 2972 rdata->fmp = NULL; 2973 rdata->lmp = NULL; 2974 2975 if (ifp->if_capenable & IFCAP_RSS) { 2976 pi = emx_rssinfo(m, &pi0, mrq, 2977 rss_hash, staterr); 2978 } 2979 #ifdef EMX_RSS_DEBUG 2980 rdata->rx_pkts++; 2981 #endif 2982 } 2983 } else { 2984 ifp->if_ierrors++; 2985 discard: 2986 emx_setup_rxdesc(current_desc, rx_buf); 2987 if (rdata->fmp != NULL) { 2988 m_freem(rdata->fmp); 2989 rdata->fmp = NULL; 2990 rdata->lmp = NULL; 2991 } 2992 m = NULL; 2993 } 2994 2995 if (m != NULL) 2996 ether_input_pkt(ifp, m, pi); 2997 2998 /* Advance our pointers to the next descriptor. */ 2999 if (++i == rdata->num_rx_desc) 3000 i = 0; 3001 3002 current_desc = &rdata->rx_desc[i]; 3003 staterr = le32toh(current_desc->rxd_staterr); 3004 } 3005 rdata->next_rx_desc_to_check = i; 3006 3007 /* Advance the E1000's Receive Queue "Tail Pointer". */ 3008 if (--i < 0) 3009 i = rdata->num_rx_desc - 1; 3010 E1000_WRITE_REG(&rdata->sc->hw, E1000_RDT(rdata->idx), i); 3011 } 3012 3013 static void 3014 emx_enable_intr(struct emx_softc *sc) 3015 { 3016 uint32_t ims_mask = IMS_ENABLE_MASK; 3017 3018 lwkt_serialize_handler_enable(&sc->main_serialize); 3019 3020 #if 0 3021 if (sc->hw.mac.type == e1000_82574) { 3022 E1000_WRITE_REG(hw, EMX_EIAC, EM_MSIX_MASK); 3023 ims_mask |= EM_MSIX_MASK; 3024 } 3025 #endif 3026 E1000_WRITE_REG(&sc->hw, E1000_IMS, ims_mask); 3027 } 3028 3029 static void 3030 emx_disable_intr(struct emx_softc *sc) 3031 { 3032 if (sc->hw.mac.type == e1000_82574) 3033 E1000_WRITE_REG(&sc->hw, EMX_EIAC, 0); 3034 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff); 3035 3036 lwkt_serialize_handler_disable(&sc->main_serialize); 3037 } 3038 3039 /* 3040 * Bit of a misnomer, what this really means is 3041 * to enable OS management of the system... aka 3042 * to disable special hardware management features 3043 */ 3044 static void 3045 emx_get_mgmt(struct emx_softc *sc) 3046 { 3047 /* A shared code workaround */ 3048 if (sc->flags & EMX_FLAG_HAS_MGMT) { 3049 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H); 3050 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3051 3052 /* disable hardware interception of ARP */ 3053 manc &= ~(E1000_MANC_ARP_EN); 3054 3055 /* enable receiving management packets to the host */ 3056 manc |= E1000_MANC_EN_MNG2HOST; 3057 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3058 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3059 manc2h |= E1000_MNG2HOST_PORT_623; 3060 manc2h |= E1000_MNG2HOST_PORT_664; 3061 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h); 3062 3063 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3064 } 3065 } 3066 3067 /* 3068 * Give control back to hardware management 3069 * controller if there is one. 3070 */ 3071 static void 3072 emx_rel_mgmt(struct emx_softc *sc) 3073 { 3074 if (sc->flags & EMX_FLAG_HAS_MGMT) { 3075 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3076 3077 /* re-enable hardware interception of ARP */ 3078 manc |= E1000_MANC_ARP_EN; 3079 manc &= ~E1000_MANC_EN_MNG2HOST; 3080 3081 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3082 } 3083 } 3084 3085 /* 3086 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3087 * For ASF and Pass Through versions of f/w this means that 3088 * the driver is loaded. For AMT version (only with 82573) 3089 * of the f/w this means that the network i/f is open. 3090 */ 3091 static void 3092 emx_get_hw_control(struct emx_softc *sc) 3093 { 3094 /* Let firmware know the driver has taken over */ 3095 if (sc->hw.mac.type == e1000_82573) { 3096 uint32_t swsm; 3097 3098 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3099 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3100 swsm | E1000_SWSM_DRV_LOAD); 3101 } else { 3102 uint32_t ctrl_ext; 3103 3104 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3105 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3106 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3107 } 3108 sc->flags |= EMX_FLAG_HW_CTRL; 3109 } 3110 3111 /* 3112 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3113 * For ASF and Pass Through versions of f/w this means that the 3114 * driver is no longer loaded. For AMT version (only with 82573) 3115 * of the f/w this means that the network i/f is closed. 3116 */ 3117 static void 3118 emx_rel_hw_control(struct emx_softc *sc) 3119 { 3120 if ((sc->flags & EMX_FLAG_HW_CTRL) == 0) 3121 return; 3122 sc->flags &= ~EMX_FLAG_HW_CTRL; 3123 3124 /* Let firmware taken over control of h/w */ 3125 if (sc->hw.mac.type == e1000_82573) { 3126 uint32_t swsm; 3127 3128 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3129 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3130 swsm & ~E1000_SWSM_DRV_LOAD); 3131 } else { 3132 uint32_t ctrl_ext; 3133 3134 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3135 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3136 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3137 } 3138 } 3139 3140 static int 3141 emx_is_valid_eaddr(const uint8_t *addr) 3142 { 3143 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 }; 3144 3145 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN)) 3146 return (FALSE); 3147 3148 return (TRUE); 3149 } 3150 3151 /* 3152 * Enable PCI Wake On Lan capability 3153 */ 3154 void 3155 emx_enable_wol(device_t dev) 3156 { 3157 uint16_t cap, status; 3158 uint8_t id; 3159 3160 /* First find the capabilities pointer*/ 3161 cap = pci_read_config(dev, PCIR_CAP_PTR, 2); 3162 3163 /* Read the PM Capabilities */ 3164 id = pci_read_config(dev, cap, 1); 3165 if (id != PCIY_PMG) /* Something wrong */ 3166 return; 3167 3168 /* 3169 * OK, we have the power capabilities, 3170 * so now get the status register 3171 */ 3172 cap += PCIR_POWER_STATUS; 3173 status = pci_read_config(dev, cap, 2); 3174 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3175 pci_write_config(dev, cap, status, 2); 3176 } 3177 3178 static void 3179 emx_update_stats(struct emx_softc *sc) 3180 { 3181 struct ifnet *ifp = &sc->arpcom.ac_if; 3182 3183 if (sc->hw.phy.media_type == e1000_media_type_copper || 3184 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3185 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS); 3186 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC); 3187 } 3188 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS); 3189 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC); 3190 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC); 3191 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL); 3192 3193 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC); 3194 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL); 3195 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC); 3196 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC); 3197 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC); 3198 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC); 3199 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC); 3200 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC); 3201 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC); 3202 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC); 3203 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64); 3204 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127); 3205 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255); 3206 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511); 3207 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023); 3208 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522); 3209 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC); 3210 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC); 3211 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC); 3212 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC); 3213 3214 /* For the 64-bit byte counters the low dword must be read first. */ 3215 /* Both registers clear on the read of the high dword */ 3216 3217 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH); 3218 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH); 3219 3220 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC); 3221 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC); 3222 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC); 3223 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC); 3224 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC); 3225 3226 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH); 3227 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH); 3228 3229 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR); 3230 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT); 3231 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64); 3232 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127); 3233 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255); 3234 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511); 3235 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023); 3236 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522); 3237 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC); 3238 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC); 3239 3240 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC); 3241 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC); 3242 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS); 3243 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR); 3244 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC); 3245 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC); 3246 3247 ifp->if_collisions = sc->stats.colc; 3248 3249 /* Rx Errors */ 3250 ifp->if_ierrors = sc->stats.rxerrc + 3251 sc->stats.crcerrs + sc->stats.algnerrc + 3252 sc->stats.ruc + sc->stats.roc + 3253 sc->stats.mpc + sc->stats.cexterr; 3254 3255 /* Tx Errors */ 3256 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol; 3257 } 3258 3259 static void 3260 emx_print_debug_info(struct emx_softc *sc) 3261 { 3262 device_t dev = sc->dev; 3263 uint8_t *hw_addr = sc->hw.hw_addr; 3264 3265 device_printf(dev, "Adapter hardware address = %p \n", hw_addr); 3266 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n", 3267 E1000_READ_REG(&sc->hw, E1000_CTRL), 3268 E1000_READ_REG(&sc->hw, E1000_RCTL)); 3269 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n", 3270 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\ 3271 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) ); 3272 device_printf(dev, "Flow control watermarks high = %d low = %d\n", 3273 sc->hw.fc.high_water, sc->hw.fc.low_water); 3274 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n", 3275 E1000_READ_REG(&sc->hw, E1000_TIDV), 3276 E1000_READ_REG(&sc->hw, E1000_TADV)); 3277 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n", 3278 E1000_READ_REG(&sc->hw, E1000_RDTR), 3279 E1000_READ_REG(&sc->hw, E1000_RADV)); 3280 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 3281 E1000_READ_REG(&sc->hw, E1000_TDH(0)), 3282 E1000_READ_REG(&sc->hw, E1000_TDT(0))); 3283 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 3284 E1000_READ_REG(&sc->hw, E1000_RDH(0)), 3285 E1000_READ_REG(&sc->hw, E1000_RDT(0))); 3286 device_printf(dev, "Num Tx descriptors avail = %d\n", 3287 sc->tx_data.num_tx_desc_avail); 3288 3289 device_printf(dev, "TSO segments %lu\n", sc->tx_data.tso_segments); 3290 device_printf(dev, "TSO ctx reused %lu\n", sc->tx_data.tso_ctx_reused); 3291 } 3292 3293 static void 3294 emx_print_hw_stats(struct emx_softc *sc) 3295 { 3296 device_t dev = sc->dev; 3297 3298 device_printf(dev, "Excessive collisions = %lld\n", 3299 (long long)sc->stats.ecol); 3300 #if (DEBUG_HW > 0) /* Dont output these errors normally */ 3301 device_printf(dev, "Symbol errors = %lld\n", 3302 (long long)sc->stats.symerrs); 3303 #endif 3304 device_printf(dev, "Sequence errors = %lld\n", 3305 (long long)sc->stats.sec); 3306 device_printf(dev, "Defer count = %lld\n", 3307 (long long)sc->stats.dc); 3308 device_printf(dev, "Missed Packets = %lld\n", 3309 (long long)sc->stats.mpc); 3310 device_printf(dev, "Receive No Buffers = %lld\n", 3311 (long long)sc->stats.rnbc); 3312 /* RLEC is inaccurate on some hardware, calculate our own. */ 3313 device_printf(dev, "Receive Length Errors = %lld\n", 3314 ((long long)sc->stats.roc + (long long)sc->stats.ruc)); 3315 device_printf(dev, "Receive errors = %lld\n", 3316 (long long)sc->stats.rxerrc); 3317 device_printf(dev, "Crc errors = %lld\n", 3318 (long long)sc->stats.crcerrs); 3319 device_printf(dev, "Alignment errors = %lld\n", 3320 (long long)sc->stats.algnerrc); 3321 device_printf(dev, "Collision/Carrier extension errors = %lld\n", 3322 (long long)sc->stats.cexterr); 3323 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns); 3324 device_printf(dev, "XON Rcvd = %lld\n", 3325 (long long)sc->stats.xonrxc); 3326 device_printf(dev, "XON Xmtd = %lld\n", 3327 (long long)sc->stats.xontxc); 3328 device_printf(dev, "XOFF Rcvd = %lld\n", 3329 (long long)sc->stats.xoffrxc); 3330 device_printf(dev, "XOFF Xmtd = %lld\n", 3331 (long long)sc->stats.xofftxc); 3332 device_printf(dev, "Good Packets Rcvd = %lld\n", 3333 (long long)sc->stats.gprc); 3334 device_printf(dev, "Good Packets Xmtd = %lld\n", 3335 (long long)sc->stats.gptc); 3336 } 3337 3338 static void 3339 emx_print_nvm_info(struct emx_softc *sc) 3340 { 3341 uint16_t eeprom_data; 3342 int i, j, row = 0; 3343 3344 /* Its a bit crude, but it gets the job done */ 3345 kprintf("\nInterface EEPROM Dump:\n"); 3346 kprintf("Offset\n0x0000 "); 3347 for (i = 0, j = 0; i < 32; i++, j++) { 3348 if (j == 8) { /* Make the offset block */ 3349 j = 0; ++row; 3350 kprintf("\n0x00%x0 ",row); 3351 } 3352 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data); 3353 kprintf("%04x ", eeprom_data); 3354 } 3355 kprintf("\n"); 3356 } 3357 3358 static int 3359 emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 3360 { 3361 struct emx_softc *sc; 3362 struct ifnet *ifp; 3363 int error, result; 3364 3365 result = -1; 3366 error = sysctl_handle_int(oidp, &result, 0, req); 3367 if (error || !req->newptr) 3368 return (error); 3369 3370 sc = (struct emx_softc *)arg1; 3371 ifp = &sc->arpcom.ac_if; 3372 3373 ifnet_serialize_all(ifp); 3374 3375 if (result == 1) 3376 emx_print_debug_info(sc); 3377 3378 /* 3379 * This value will cause a hex dump of the 3380 * first 32 16-bit words of the EEPROM to 3381 * the screen. 3382 */ 3383 if (result == 2) 3384 emx_print_nvm_info(sc); 3385 3386 ifnet_deserialize_all(ifp); 3387 3388 return (error); 3389 } 3390 3391 static int 3392 emx_sysctl_stats(SYSCTL_HANDLER_ARGS) 3393 { 3394 int error, result; 3395 3396 result = -1; 3397 error = sysctl_handle_int(oidp, &result, 0, req); 3398 if (error || !req->newptr) 3399 return (error); 3400 3401 if (result == 1) { 3402 struct emx_softc *sc = (struct emx_softc *)arg1; 3403 struct ifnet *ifp = &sc->arpcom.ac_if; 3404 3405 ifnet_serialize_all(ifp); 3406 emx_print_hw_stats(sc); 3407 ifnet_deserialize_all(ifp); 3408 } 3409 return (error); 3410 } 3411 3412 static void 3413 emx_add_sysctl(struct emx_softc *sc) 3414 { 3415 #ifdef EMX_RSS_DEBUG 3416 char rx_pkt[32]; 3417 int i; 3418 #endif 3419 3420 sysctl_ctx_init(&sc->sysctl_ctx); 3421 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 3422 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 3423 device_get_nameunit(sc->dev), 3424 CTLFLAG_RD, 0, ""); 3425 if (sc->sysctl_tree == NULL) { 3426 device_printf(sc->dev, "can't add sysctl node\n"); 3427 return; 3428 } 3429 3430 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3431 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 3432 emx_sysctl_debug_info, "I", "Debug Information"); 3433 3434 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3435 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 3436 emx_sysctl_stats, "I", "Statistics"); 3437 3438 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3439 OID_AUTO, "rxd", CTLFLAG_RD, 3440 &sc->rx_data[0].num_rx_desc, 0, NULL); 3441 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3442 OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_data.num_tx_desc, 0, NULL); 3443 3444 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3445 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW, 3446 sc, 0, emx_sysctl_int_throttle, "I", 3447 "interrupt throttling rate"); 3448 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3449 OID_AUTO, "int_tx_nsegs", CTLTYPE_INT|CTLFLAG_RW, 3450 sc, 0, emx_sysctl_int_tx_nsegs, "I", 3451 "# segments per TX interrupt"); 3452 3453 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3454 OID_AUTO, "rx_ring_cnt", CTLFLAG_RD, 3455 &sc->rx_ring_cnt, 0, "RX ring count"); 3456 3457 #ifdef IFPOLL_ENABLE 3458 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3459 OID_AUTO, "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW, 3460 sc, 0, emx_sysctl_npoll_rxoff, "I", 3461 "NPOLLING RX cpu offset"); 3462 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3463 OID_AUTO, "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW, 3464 sc, 0, emx_sysctl_npoll_txoff, "I", 3465 "NPOLLING TX cpu offset"); 3466 #endif 3467 3468 #ifdef EMX_RSS_DEBUG 3469 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3470 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 3471 0, "RSS debug level"); 3472 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3473 ksnprintf(rx_pkt, sizeof(rx_pkt), "rx%d_pkt", i); 3474 SYSCTL_ADD_UINT(&sc->sysctl_ctx, 3475 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, 3476 rx_pkt, CTLFLAG_RW, 3477 &sc->rx_data[i].rx_pkts, 0, "RXed packets"); 3478 } 3479 #endif 3480 } 3481 3482 static int 3483 emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS) 3484 { 3485 struct emx_softc *sc = (void *)arg1; 3486 struct ifnet *ifp = &sc->arpcom.ac_if; 3487 int error, throttle; 3488 3489 throttle = sc->int_throttle_ceil; 3490 error = sysctl_handle_int(oidp, &throttle, 0, req); 3491 if (error || req->newptr == NULL) 3492 return error; 3493 if (throttle < 0 || throttle > 1000000000 / 256) 3494 return EINVAL; 3495 3496 if (throttle) { 3497 /* 3498 * Set the interrupt throttling rate in 256ns increments, 3499 * recalculate sysctl value assignment to get exact frequency. 3500 */ 3501 throttle = 1000000000 / 256 / throttle; 3502 3503 /* Upper 16bits of ITR is reserved and should be zero */ 3504 if (throttle & 0xffff0000) 3505 return EINVAL; 3506 } 3507 3508 ifnet_serialize_all(ifp); 3509 3510 if (throttle) 3511 sc->int_throttle_ceil = 1000000000 / 256 / throttle; 3512 else 3513 sc->int_throttle_ceil = 0; 3514 3515 if (ifp->if_flags & IFF_RUNNING) 3516 emx_set_itr(sc, throttle); 3517 3518 ifnet_deserialize_all(ifp); 3519 3520 if (bootverbose) { 3521 if_printf(ifp, "Interrupt moderation set to %d/sec\n", 3522 sc->int_throttle_ceil); 3523 } 3524 return 0; 3525 } 3526 3527 static int 3528 emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS) 3529 { 3530 struct emx_softc *sc = (void *)arg1; 3531 struct ifnet *ifp = &sc->arpcom.ac_if; 3532 int error, segs; 3533 3534 segs = sc->tx_data.tx_int_nsegs; 3535 error = sysctl_handle_int(oidp, &segs, 0, req); 3536 if (error || req->newptr == NULL) 3537 return error; 3538 if (segs <= 0) 3539 return EINVAL; 3540 3541 ifnet_serialize_all(ifp); 3542 3543 /* 3544 * Don't allow int_tx_nsegs to become: 3545 * o Less the oact_tx_desc 3546 * o Too large that no TX desc will cause TX interrupt to 3547 * be generated (OACTIVE will never recover) 3548 * o Too small that will cause tx_dd[] overflow 3549 */ 3550 if (segs < sc->tx_data.oact_tx_desc || 3551 segs >= sc->tx_data.num_tx_desc - sc->tx_data.oact_tx_desc || 3552 segs < sc->tx_data.num_tx_desc / EMX_TXDD_SAFE) { 3553 error = EINVAL; 3554 } else { 3555 error = 0; 3556 sc->tx_data.tx_int_nsegs = segs; 3557 } 3558 3559 ifnet_deserialize_all(ifp); 3560 3561 return error; 3562 } 3563 3564 #ifdef IFPOLL_ENABLE 3565 3566 static int 3567 emx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS) 3568 { 3569 struct emx_softc *sc = (void *)arg1; 3570 struct ifnet *ifp = &sc->arpcom.ac_if; 3571 int error, off; 3572 3573 off = sc->rx_npoll_off; 3574 error = sysctl_handle_int(oidp, &off, 0, req); 3575 if (error || req->newptr == NULL) 3576 return error; 3577 if (off < 0) 3578 return EINVAL; 3579 3580 ifnet_serialize_all(ifp); 3581 if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) { 3582 error = EINVAL; 3583 } else { 3584 error = 0; 3585 sc->rx_npoll_off = off; 3586 } 3587 ifnet_deserialize_all(ifp); 3588 3589 return error; 3590 } 3591 3592 static int 3593 emx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS) 3594 { 3595 struct emx_softc *sc = (void *)arg1; 3596 struct ifnet *ifp = &sc->arpcom.ac_if; 3597 int error, off; 3598 3599 off = sc->tx_npoll_off; 3600 error = sysctl_handle_int(oidp, &off, 0, req); 3601 if (error || req->newptr == NULL) 3602 return error; 3603 if (off < 0) 3604 return EINVAL; 3605 3606 ifnet_serialize_all(ifp); 3607 if (off >= ncpus2) { 3608 error = EINVAL; 3609 } else { 3610 error = 0; 3611 sc->tx_npoll_off = off; 3612 } 3613 ifnet_deserialize_all(ifp); 3614 3615 return error; 3616 } 3617 3618 #endif /* IFPOLL_ENABLE */ 3619 3620 static int 3621 emx_dma_alloc(struct emx_softc *sc) 3622 { 3623 int error, i; 3624 3625 /* 3626 * Create top level busdma tag 3627 */ 3628 error = bus_dma_tag_create(NULL, 1, 0, 3629 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 3630 NULL, NULL, 3631 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 3632 0, &sc->parent_dtag); 3633 if (error) { 3634 device_printf(sc->dev, "could not create top level DMA tag\n"); 3635 return error; 3636 } 3637 3638 /* 3639 * Allocate transmit descriptors ring and buffers 3640 */ 3641 error = emx_create_tx_ring(&sc->tx_data); 3642 if (error) { 3643 device_printf(sc->dev, "Could not setup transmit structures\n"); 3644 return error; 3645 } 3646 3647 /* 3648 * Allocate receive descriptors ring and buffers 3649 */ 3650 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3651 error = emx_create_rx_ring(&sc->rx_data[i]); 3652 if (error) { 3653 device_printf(sc->dev, 3654 "Could not setup receive structures\n"); 3655 return error; 3656 } 3657 } 3658 return 0; 3659 } 3660 3661 static void 3662 emx_dma_free(struct emx_softc *sc) 3663 { 3664 int i; 3665 3666 emx_destroy_tx_ring(&sc->tx_data, sc->tx_data.num_tx_desc); 3667 3668 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3669 emx_destroy_rx_ring(&sc->rx_data[i], 3670 sc->rx_data[i].num_rx_desc); 3671 } 3672 3673 /* Free top level busdma tag */ 3674 if (sc->parent_dtag != NULL) 3675 bus_dma_tag_destroy(sc->parent_dtag); 3676 } 3677 3678 static void 3679 emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz) 3680 { 3681 struct emx_softc *sc = ifp->if_softc; 3682 3683 ifnet_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 3684 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz); 3685 } 3686 3687 static void 3688 emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz) 3689 { 3690 struct emx_softc *sc = ifp->if_softc; 3691 3692 ifnet_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 3693 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz); 3694 } 3695 3696 static int 3697 emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz) 3698 { 3699 struct emx_softc *sc = ifp->if_softc; 3700 3701 return ifnet_serialize_array_try(sc->serializes, EMX_NSERIALIZE, 3702 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz); 3703 } 3704 3705 static void 3706 emx_serialize_skipmain(struct emx_softc *sc) 3707 { 3708 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1); 3709 } 3710 3711 static void 3712 emx_deserialize_skipmain(struct emx_softc *sc) 3713 { 3714 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1); 3715 } 3716 3717 #ifdef INVARIANTS 3718 3719 static void 3720 emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz, 3721 boolean_t serialized) 3722 { 3723 struct emx_softc *sc = ifp->if_softc; 3724 3725 ifnet_serialize_array_assert(sc->serializes, EMX_NSERIALIZE, 3726 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz, serialized); 3727 } 3728 3729 #endif /* INVARIANTS */ 3730 3731 #ifdef IFPOLL_ENABLE 3732 3733 static void 3734 emx_npoll_status(struct ifnet *ifp) 3735 { 3736 struct emx_softc *sc = ifp->if_softc; 3737 uint32_t reg_icr; 3738 3739 ASSERT_SERIALIZED(&sc->main_serialize); 3740 3741 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 3742 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 3743 callout_stop(&sc->timer); 3744 sc->hw.mac.get_link_status = 1; 3745 emx_update_link_status(sc); 3746 callout_reset(&sc->timer, hz, emx_timer, sc); 3747 } 3748 } 3749 3750 static void 3751 emx_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused) 3752 { 3753 struct emx_txdata *tdata = arg; 3754 3755 ASSERT_SERIALIZED(&tdata->tx_serialize); 3756 3757 emx_txeof(tdata); 3758 if (!ifq_is_empty(&ifp->if_snd)) 3759 if_devstart(ifp); 3760 } 3761 3762 static void 3763 emx_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle) 3764 { 3765 struct emx_rxdata *rdata = arg; 3766 3767 ASSERT_SERIALIZED(&rdata->rx_serialize); 3768 3769 emx_rxeof(rdata, cycle); 3770 } 3771 3772 static void 3773 emx_npoll(struct ifnet *ifp, struct ifpoll_info *info) 3774 { 3775 struct emx_softc *sc = ifp->if_softc; 3776 3777 ASSERT_IFNET_SERIALIZED_ALL(ifp); 3778 3779 if (info) { 3780 int i, off; 3781 3782 info->ifpi_status.status_func = emx_npoll_status; 3783 info->ifpi_status.serializer = &sc->main_serialize; 3784 3785 off = sc->tx_npoll_off; 3786 KKASSERT(off < ncpus2); 3787 info->ifpi_tx[off].poll_func = emx_npoll_tx; 3788 info->ifpi_tx[off].arg = &sc->tx_data; 3789 info->ifpi_tx[off].serializer = &sc->tx_data.tx_serialize; 3790 3791 off = sc->rx_npoll_off; 3792 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3793 struct emx_rxdata *rdata = &sc->rx_data[i]; 3794 int idx = i + off; 3795 3796 KKASSERT(idx < ncpus2); 3797 info->ifpi_rx[idx].poll_func = emx_npoll_rx; 3798 info->ifpi_rx[idx].arg = rdata; 3799 info->ifpi_rx[idx].serializer = &rdata->rx_serialize; 3800 } 3801 3802 if (ifp->if_flags & IFF_RUNNING) 3803 emx_disable_intr(sc); 3804 ifp->if_npoll_cpuid = sc->tx_npoll_off; 3805 } else { 3806 if (ifp->if_flags & IFF_RUNNING) 3807 emx_enable_intr(sc); 3808 ifp->if_npoll_cpuid = -1; 3809 } 3810 } 3811 3812 #endif /* IFPOLL_ENABLE */ 3813 3814 static void 3815 emx_set_itr(struct emx_softc *sc, uint32_t itr) 3816 { 3817 E1000_WRITE_REG(&sc->hw, E1000_ITR, itr); 3818 if (sc->hw.mac.type == e1000_82574) { 3819 int i; 3820 3821 /* 3822 * When using MSIX interrupts we need to 3823 * throttle using the EITR register 3824 */ 3825 for (i = 0; i < 4; ++i) 3826 E1000_WRITE_REG(&sc->hw, E1000_EITR_82574(i), itr); 3827 } 3828 } 3829 3830 /* 3831 * Disable the L0s, 82574L Errata #20 3832 */ 3833 static void 3834 emx_disable_aspm(struct emx_softc *sc) 3835 { 3836 uint16_t link_cap, link_ctrl, disable; 3837 uint8_t pcie_ptr, reg; 3838 device_t dev = sc->dev; 3839 3840 switch (sc->hw.mac.type) { 3841 case e1000_82571: 3842 case e1000_82572: 3843 case e1000_82573: 3844 /* 3845 * 82573 specification update 3846 * errata #8 disable L0s 3847 * errata #41 disable L1 3848 * 3849 * 82571/82572 specification update 3850 # errata #13 disable L1 3851 * errata #68 disable L0s 3852 */ 3853 disable = PCIEM_LNKCTL_ASPM_L0S | PCIEM_LNKCTL_ASPM_L1; 3854 break; 3855 3856 case e1000_82574: 3857 /* 3858 * 82574 specification update errata #20 3859 * 3860 * There is no need to disable L1 3861 */ 3862 disable = PCIEM_LNKCTL_ASPM_L0S; 3863 break; 3864 3865 default: 3866 return; 3867 } 3868 3869 pcie_ptr = pci_get_pciecap_ptr(dev); 3870 if (pcie_ptr == 0) 3871 return; 3872 3873 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2); 3874 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0) 3875 return; 3876 3877 if (bootverbose) 3878 if_printf(&sc->arpcom.ac_if, "disable ASPM %#02x\n", disable); 3879 3880 reg = pcie_ptr + PCIER_LINKCTRL; 3881 link_ctrl = pci_read_config(dev, reg, 2); 3882 link_ctrl &= ~disable; 3883 pci_write_config(dev, reg, link_ctrl, 2); 3884 } 3885 3886 static int 3887 emx_tso_pullup(struct emx_txdata *tdata, struct mbuf **mp) 3888 { 3889 int iphlen, hoff, thoff, ex = 0; 3890 struct mbuf *m; 3891 struct ip *ip; 3892 3893 m = *mp; 3894 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable")); 3895 3896 iphlen = m->m_pkthdr.csum_iphlen; 3897 thoff = m->m_pkthdr.csum_thlen; 3898 hoff = m->m_pkthdr.csum_lhlen; 3899 3900 KASSERT(iphlen > 0, ("invalid ip hlen")); 3901 KASSERT(thoff > 0, ("invalid tcp hlen")); 3902 KASSERT(hoff > 0, ("invalid ether hlen")); 3903 3904 if (tdata->sc->flags & EMX_FLAG_TSO_PULLEX) 3905 ex = 4; 3906 3907 if (m->m_len < hoff + iphlen + thoff + ex) { 3908 m = m_pullup(m, hoff + iphlen + thoff + ex); 3909 if (m == NULL) { 3910 *mp = NULL; 3911 return ENOBUFS; 3912 } 3913 *mp = m; 3914 } 3915 ip = mtodoff(m, struct ip *, hoff); 3916 ip->ip_len = 0; 3917 3918 return 0; 3919 } 3920 3921 static int 3922 emx_tso_setup(struct emx_txdata *tdata, struct mbuf *mp, 3923 uint32_t *txd_upper, uint32_t *txd_lower) 3924 { 3925 struct e1000_context_desc *TXD; 3926 int hoff, iphlen, thoff, hlen; 3927 int mss, pktlen, curr_txd; 3928 3929 #ifdef EMX_TSO_DEBUG 3930 tdata->tso_segments++; 3931 #endif 3932 3933 iphlen = mp->m_pkthdr.csum_iphlen; 3934 thoff = mp->m_pkthdr.csum_thlen; 3935 hoff = mp->m_pkthdr.csum_lhlen; 3936 mss = mp->m_pkthdr.tso_segsz; 3937 pktlen = mp->m_pkthdr.len; 3938 3939 if (tdata->csum_flags == CSUM_TSO && 3940 tdata->csum_iphlen == iphlen && 3941 tdata->csum_lhlen == hoff && 3942 tdata->csum_thlen == thoff && 3943 tdata->csum_mss == mss && 3944 tdata->csum_pktlen == pktlen) { 3945 *txd_upper = tdata->csum_txd_upper; 3946 *txd_lower = tdata->csum_txd_lower; 3947 #ifdef EMX_TSO_DEBUG 3948 tdata->tso_ctx_reused++; 3949 #endif 3950 return 0; 3951 } 3952 hlen = hoff + iphlen + thoff; 3953 3954 /* 3955 * Setup a new TSO context. 3956 */ 3957 3958 curr_txd = tdata->next_avail_tx_desc; 3959 TXD = (struct e1000_context_desc *)&tdata->tx_desc_base[curr_txd]; 3960 3961 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */ 3962 E1000_TXD_DTYP_D | /* Data descr type */ 3963 E1000_TXD_CMD_TSE; /* Do TSE on this packet */ 3964 3965 /* IP and/or TCP header checksum calculation and insertion. */ 3966 *txd_upper = (E1000_TXD_POPTS_IXSM | E1000_TXD_POPTS_TXSM) << 8; 3967 3968 /* 3969 * Start offset for header checksum calculation. 3970 * End offset for header checksum calculation. 3971 * Offset of place put the checksum. 3972 */ 3973 TXD->lower_setup.ip_fields.ipcss = hoff; 3974 TXD->lower_setup.ip_fields.ipcse = htole16(hoff + iphlen - 1); 3975 TXD->lower_setup.ip_fields.ipcso = hoff + offsetof(struct ip, ip_sum); 3976 3977 /* 3978 * Start offset for payload checksum calculation. 3979 * End offset for payload checksum calculation. 3980 * Offset of place to put the checksum. 3981 */ 3982 TXD->upper_setup.tcp_fields.tucss = hoff + iphlen; 3983 TXD->upper_setup.tcp_fields.tucse = 0; 3984 TXD->upper_setup.tcp_fields.tucso = 3985 hoff + iphlen + offsetof(struct tcphdr, th_sum); 3986 3987 /* 3988 * Payload size per packet w/o any headers. 3989 * Length of all headers up to payload. 3990 */ 3991 TXD->tcp_seg_setup.fields.mss = htole16(mss); 3992 TXD->tcp_seg_setup.fields.hdr_len = hlen; 3993 TXD->cmd_and_length = htole32(E1000_TXD_CMD_IFCS | 3994 E1000_TXD_CMD_DEXT | /* Extended descr */ 3995 E1000_TXD_CMD_TSE | /* TSE context */ 3996 E1000_TXD_CMD_IP | /* Do IP csum */ 3997 E1000_TXD_CMD_TCP | /* Do TCP checksum */ 3998 (pktlen - hlen)); /* Total len */ 3999 4000 /* Save the information for this TSO context */ 4001 tdata->csum_flags = CSUM_TSO; 4002 tdata->csum_lhlen = hoff; 4003 tdata->csum_iphlen = iphlen; 4004 tdata->csum_thlen = thoff; 4005 tdata->csum_mss = mss; 4006 tdata->csum_pktlen = pktlen; 4007 tdata->csum_txd_upper = *txd_upper; 4008 tdata->csum_txd_lower = *txd_lower; 4009 4010 if (++curr_txd == tdata->num_tx_desc) 4011 curr_txd = 0; 4012 4013 KKASSERT(tdata->num_tx_desc_avail > 0); 4014 tdata->num_tx_desc_avail--; 4015 4016 tdata->next_avail_tx_desc = curr_txd; 4017 return 1; 4018 } 4019