1 /* 2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 3 * 4 * Copyright (c) 2001-2008, Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * 34 * Copyright (c) 2005 The DragonFly Project. All rights reserved. 35 * 36 * This code is derived from software contributed to The DragonFly Project 37 * by Matthew Dillon <dillon@backplane.com> 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in 47 * the documentation and/or other materials provided with the 48 * distribution. 49 * 3. Neither the name of The DragonFly Project nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific, prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 */ 66 67 #include "opt_ifpoll.h" 68 #include "opt_emx.h" 69 70 #include <sys/param.h> 71 #include <sys/bus.h> 72 #include <sys/endian.h> 73 #include <sys/interrupt.h> 74 #include <sys/kernel.h> 75 #include <sys/ktr.h> 76 #include <sys/malloc.h> 77 #include <sys/mbuf.h> 78 #include <sys/proc.h> 79 #include <sys/rman.h> 80 #include <sys/serialize.h> 81 #include <sys/serialize2.h> 82 #include <sys/socket.h> 83 #include <sys/sockio.h> 84 #include <sys/sysctl.h> 85 #include <sys/systm.h> 86 87 #include <net/bpf.h> 88 #include <net/ethernet.h> 89 #include <net/if.h> 90 #include <net/if_arp.h> 91 #include <net/if_dl.h> 92 #include <net/if_media.h> 93 #include <net/ifq_var.h> 94 #include <net/toeplitz.h> 95 #include <net/toeplitz2.h> 96 #include <net/vlan/if_vlan_var.h> 97 #include <net/vlan/if_vlan_ether.h> 98 #include <net/if_poll.h> 99 100 #include <netinet/in_systm.h> 101 #include <netinet/in.h> 102 #include <netinet/ip.h> 103 #include <netinet/tcp.h> 104 #include <netinet/udp.h> 105 106 #include <bus/pci/pcivar.h> 107 #include <bus/pci/pcireg.h> 108 109 #include <dev/netif/ig_hal/e1000_api.h> 110 #include <dev/netif/ig_hal/e1000_82571.h> 111 #include <dev/netif/emx/if_emx.h> 112 113 #define DEBUG_HW 0 114 115 #ifdef EMX_RSS_DEBUG 116 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \ 117 do { \ 118 if (sc->rss_debug >= lvl) \ 119 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \ 120 } while (0) 121 #else /* !EMX_RSS_DEBUG */ 122 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0) 123 #endif /* EMX_RSS_DEBUG */ 124 125 #define EMX_NAME "Intel(R) PRO/1000 " 126 127 #define EMX_DEVICE(id) \ 128 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id } 129 #define EMX_DEVICE_NULL { 0, 0, NULL } 130 131 static const struct emx_device { 132 uint16_t vid; 133 uint16_t did; 134 const char *desc; 135 } emx_devices[] = { 136 EMX_DEVICE(82571EB_COPPER), 137 EMX_DEVICE(82571EB_FIBER), 138 EMX_DEVICE(82571EB_SERDES), 139 EMX_DEVICE(82571EB_SERDES_DUAL), 140 EMX_DEVICE(82571EB_SERDES_QUAD), 141 EMX_DEVICE(82571EB_QUAD_COPPER), 142 EMX_DEVICE(82571EB_QUAD_COPPER_BP), 143 EMX_DEVICE(82571EB_QUAD_COPPER_LP), 144 EMX_DEVICE(82571EB_QUAD_FIBER), 145 EMX_DEVICE(82571PT_QUAD_COPPER), 146 147 EMX_DEVICE(82572EI_COPPER), 148 EMX_DEVICE(82572EI_FIBER), 149 EMX_DEVICE(82572EI_SERDES), 150 EMX_DEVICE(82572EI), 151 152 EMX_DEVICE(82573E), 153 EMX_DEVICE(82573E_IAMT), 154 EMX_DEVICE(82573L), 155 156 EMX_DEVICE(80003ES2LAN_COPPER_SPT), 157 EMX_DEVICE(80003ES2LAN_SERDES_SPT), 158 EMX_DEVICE(80003ES2LAN_COPPER_DPT), 159 EMX_DEVICE(80003ES2LAN_SERDES_DPT), 160 161 EMX_DEVICE(82574L), 162 EMX_DEVICE(82574LA), 163 164 /* required last entry */ 165 EMX_DEVICE_NULL 166 }; 167 168 static int emx_probe(device_t); 169 static int emx_attach(device_t); 170 static int emx_detach(device_t); 171 static int emx_shutdown(device_t); 172 static int emx_suspend(device_t); 173 static int emx_resume(device_t); 174 175 static void emx_init(void *); 176 static void emx_stop(struct emx_softc *); 177 static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 178 static void emx_start(struct ifnet *, struct ifaltq_subque *); 179 #ifdef IFPOLL_ENABLE 180 static void emx_npoll(struct ifnet *, struct ifpoll_info *); 181 static void emx_npoll_status(struct ifnet *); 182 static void emx_npoll_tx(struct ifnet *, void *, int); 183 static void emx_npoll_rx(struct ifnet *, void *, int); 184 #endif 185 static void emx_watchdog(struct ifaltq_subque *); 186 static void emx_media_status(struct ifnet *, struct ifmediareq *); 187 static int emx_media_change(struct ifnet *); 188 static void emx_timer(void *); 189 static void emx_serialize(struct ifnet *, enum ifnet_serialize); 190 static void emx_deserialize(struct ifnet *, enum ifnet_serialize); 191 static int emx_tryserialize(struct ifnet *, enum ifnet_serialize); 192 #ifdef INVARIANTS 193 static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize, 194 boolean_t); 195 #endif 196 197 static void emx_intr(void *); 198 static void emx_intr_mask(void *); 199 static void emx_intr_body(struct emx_softc *, boolean_t); 200 static void emx_rxeof(struct emx_rxdata *, int); 201 static void emx_txeof(struct emx_txdata *); 202 static void emx_tx_collect(struct emx_txdata *); 203 static void emx_tx_purge(struct emx_softc *); 204 static void emx_enable_intr(struct emx_softc *); 205 static void emx_disable_intr(struct emx_softc *); 206 207 static int emx_dma_alloc(struct emx_softc *); 208 static void emx_dma_free(struct emx_softc *); 209 static void emx_init_tx_ring(struct emx_txdata *); 210 static int emx_init_rx_ring(struct emx_rxdata *); 211 static void emx_free_tx_ring(struct emx_txdata *); 212 static void emx_free_rx_ring(struct emx_rxdata *); 213 static int emx_create_tx_ring(struct emx_txdata *); 214 static int emx_create_rx_ring(struct emx_rxdata *); 215 static void emx_destroy_tx_ring(struct emx_txdata *, int); 216 static void emx_destroy_rx_ring(struct emx_rxdata *, int); 217 static int emx_newbuf(struct emx_rxdata *, int, int); 218 static int emx_encap(struct emx_txdata *, struct mbuf **, int *, int *); 219 static int emx_txcsum(struct emx_txdata *, struct mbuf *, 220 uint32_t *, uint32_t *); 221 static int emx_tso_pullup(struct emx_txdata *, struct mbuf **); 222 static int emx_tso_setup(struct emx_txdata *, struct mbuf *, 223 uint32_t *, uint32_t *); 224 static int emx_get_txring_inuse(const struct emx_softc *, boolean_t); 225 226 static int emx_is_valid_eaddr(const uint8_t *); 227 static int emx_reset(struct emx_softc *); 228 static void emx_setup_ifp(struct emx_softc *); 229 static void emx_init_tx_unit(struct emx_softc *); 230 static void emx_init_rx_unit(struct emx_softc *); 231 static void emx_update_stats(struct emx_softc *); 232 static void emx_set_promisc(struct emx_softc *); 233 static void emx_disable_promisc(struct emx_softc *); 234 static void emx_set_multi(struct emx_softc *); 235 static void emx_update_link_status(struct emx_softc *); 236 static void emx_smartspeed(struct emx_softc *); 237 static void emx_set_itr(struct emx_softc *, uint32_t); 238 static void emx_disable_aspm(struct emx_softc *); 239 240 static void emx_print_debug_info(struct emx_softc *); 241 static void emx_print_nvm_info(struct emx_softc *); 242 static void emx_print_hw_stats(struct emx_softc *); 243 244 static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS); 245 static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 246 static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS); 247 static int emx_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS); 248 static int emx_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS); 249 #ifdef IFPOLL_ENABLE 250 static int emx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS); 251 static int emx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS); 252 #endif 253 static void emx_add_sysctl(struct emx_softc *); 254 255 static void emx_serialize_skipmain(struct emx_softc *); 256 static void emx_deserialize_skipmain(struct emx_softc *); 257 258 /* Management and WOL Support */ 259 static void emx_get_mgmt(struct emx_softc *); 260 static void emx_rel_mgmt(struct emx_softc *); 261 static void emx_get_hw_control(struct emx_softc *); 262 static void emx_rel_hw_control(struct emx_softc *); 263 static void emx_enable_wol(device_t); 264 265 static device_method_t emx_methods[] = { 266 /* Device interface */ 267 DEVMETHOD(device_probe, emx_probe), 268 DEVMETHOD(device_attach, emx_attach), 269 DEVMETHOD(device_detach, emx_detach), 270 DEVMETHOD(device_shutdown, emx_shutdown), 271 DEVMETHOD(device_suspend, emx_suspend), 272 DEVMETHOD(device_resume, emx_resume), 273 DEVMETHOD_END 274 }; 275 276 static driver_t emx_driver = { 277 "emx", 278 emx_methods, 279 sizeof(struct emx_softc), 280 }; 281 282 static devclass_t emx_devclass; 283 284 DECLARE_DUMMY_MODULE(if_emx); 285 MODULE_DEPEND(emx, ig_hal, 1, 1, 1); 286 DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, NULL, NULL); 287 288 /* 289 * Tunables 290 */ 291 static int emx_int_throttle_ceil = EMX_DEFAULT_ITR; 292 static int emx_rxd = EMX_DEFAULT_RXD; 293 static int emx_txd = EMX_DEFAULT_TXD; 294 static int emx_smart_pwr_down = 0; 295 static int emx_rxr = 0; 296 static int emx_txr = 1; 297 298 /* Controls whether promiscuous also shows bad packets */ 299 static int emx_debug_sbp = 0; 300 301 static int emx_82573_workaround = 1; 302 static int emx_msi_enable = 1; 303 304 TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil); 305 TUNABLE_INT("hw.emx.rxd", &emx_rxd); 306 TUNABLE_INT("hw.emx.rxr", &emx_rxr); 307 TUNABLE_INT("hw.emx.txd", &emx_txd); 308 TUNABLE_INT("hw.emx.txr", &emx_txr); 309 TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down); 310 TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp); 311 TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround); 312 TUNABLE_INT("hw.emx.msi.enable", &emx_msi_enable); 313 314 /* Global used in WOL setup with multiport cards */ 315 static int emx_global_quad_port_a = 0; 316 317 /* Set this to one to display debug statistics */ 318 static int emx_display_debug_stats = 0; 319 320 #if !defined(KTR_IF_EMX) 321 #define KTR_IF_EMX KTR_ALL 322 #endif 323 KTR_INFO_MASTER(if_emx); 324 KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin"); 325 KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end"); 326 KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet"); 327 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet"); 328 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean"); 329 #define logif(name) KTR_LOG(if_emx_ ## name) 330 331 static __inline void 332 emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf) 333 { 334 rxd->rxd_bufaddr = htole64(rxbuf->paddr); 335 /* DD bit must be cleared */ 336 rxd->rxd_staterr = 0; 337 } 338 339 static __inline void 340 emx_rxcsum(uint32_t staterr, struct mbuf *mp) 341 { 342 /* Ignore Checksum bit is set */ 343 if (staterr & E1000_RXD_STAT_IXSM) 344 return; 345 346 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) == 347 E1000_RXD_STAT_IPCS) 348 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID; 349 350 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) == 351 E1000_RXD_STAT_TCPCS) { 352 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 353 CSUM_PSEUDO_HDR | 354 CSUM_FRAG_NOT_CHECKED; 355 mp->m_pkthdr.csum_data = htons(0xffff); 356 } 357 } 358 359 static __inline struct pktinfo * 360 emx_rssinfo(struct mbuf *m, struct pktinfo *pi, 361 uint32_t mrq, uint32_t hash, uint32_t staterr) 362 { 363 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) { 364 case EMX_RXDMRQ_IPV4_TCP: 365 pi->pi_netisr = NETISR_IP; 366 pi->pi_flags = 0; 367 pi->pi_l3proto = IPPROTO_TCP; 368 break; 369 370 case EMX_RXDMRQ_IPV6_TCP: 371 pi->pi_netisr = NETISR_IPV6; 372 pi->pi_flags = 0; 373 pi->pi_l3proto = IPPROTO_TCP; 374 break; 375 376 case EMX_RXDMRQ_IPV4: 377 if (staterr & E1000_RXD_STAT_IXSM) 378 return NULL; 379 380 if ((staterr & 381 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) == 382 E1000_RXD_STAT_TCPCS) { 383 pi->pi_netisr = NETISR_IP; 384 pi->pi_flags = 0; 385 pi->pi_l3proto = IPPROTO_UDP; 386 break; 387 } 388 /* FALL THROUGH */ 389 default: 390 return NULL; 391 } 392 393 m->m_flags |= M_HASH; 394 m->m_pkthdr.hash = toeplitz_hash(hash); 395 return pi; 396 } 397 398 static int 399 emx_probe(device_t dev) 400 { 401 const struct emx_device *d; 402 uint16_t vid, did; 403 404 vid = pci_get_vendor(dev); 405 did = pci_get_device(dev); 406 407 for (d = emx_devices; d->desc != NULL; ++d) { 408 if (vid == d->vid && did == d->did) { 409 device_set_desc(dev, d->desc); 410 device_set_async_attach(dev, TRUE); 411 return 0; 412 } 413 } 414 return ENXIO; 415 } 416 417 static int 418 emx_attach(device_t dev) 419 { 420 struct emx_softc *sc = device_get_softc(dev); 421 int error = 0, i, throttle, msi_enable, tx_ring_max; 422 u_int intr_flags; 423 uint16_t eeprom_data, device_id, apme_mask; 424 driver_intr_t *intr_func; 425 #ifdef IFPOLL_ENABLE 426 int offset, offset_def; 427 #endif 428 429 /* 430 * Setup RX rings 431 */ 432 for (i = 0; i < EMX_NRX_RING; ++i) { 433 sc->rx_data[i].sc = sc; 434 sc->rx_data[i].idx = i; 435 } 436 437 /* 438 * Setup TX ring 439 */ 440 for (i = 0; i < EMX_NTX_RING; ++i) { 441 sc->tx_data[i].sc = sc; 442 sc->tx_data[i].idx = i; 443 } 444 445 /* 446 * Initialize serializers 447 */ 448 lwkt_serialize_init(&sc->main_serialize); 449 for (i = 0; i < EMX_NTX_RING; ++i) 450 lwkt_serialize_init(&sc->tx_data[i].tx_serialize); 451 for (i = 0; i < EMX_NRX_RING; ++i) 452 lwkt_serialize_init(&sc->rx_data[i].rx_serialize); 453 454 /* 455 * Initialize serializer array 456 */ 457 i = 0; 458 459 KKASSERT(i < EMX_NSERIALIZE); 460 sc->serializes[i++] = &sc->main_serialize; 461 462 KKASSERT(i < EMX_NSERIALIZE); 463 sc->serializes[i++] = &sc->tx_data[0].tx_serialize; 464 KKASSERT(i < EMX_NSERIALIZE); 465 sc->serializes[i++] = &sc->tx_data[1].tx_serialize; 466 467 KKASSERT(i < EMX_NSERIALIZE); 468 sc->serializes[i++] = &sc->rx_data[0].rx_serialize; 469 KKASSERT(i < EMX_NSERIALIZE); 470 sc->serializes[i++] = &sc->rx_data[1].rx_serialize; 471 472 KKASSERT(i == EMX_NSERIALIZE); 473 474 callout_init_mp(&sc->timer); 475 476 sc->dev = sc->osdep.dev = dev; 477 478 /* 479 * Determine hardware and mac type 480 */ 481 sc->hw.vendor_id = pci_get_vendor(dev); 482 sc->hw.device_id = pci_get_device(dev); 483 sc->hw.revision_id = pci_get_revid(dev); 484 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev); 485 sc->hw.subsystem_device_id = pci_get_subdevice(dev); 486 487 if (e1000_set_mac_type(&sc->hw)) 488 return ENXIO; 489 490 /* Enable bus mastering */ 491 pci_enable_busmaster(dev); 492 493 /* 494 * Allocate IO memory 495 */ 496 sc->memory_rid = EMX_BAR_MEM; 497 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 498 &sc->memory_rid, RF_ACTIVE); 499 if (sc->memory == NULL) { 500 device_printf(dev, "Unable to allocate bus resource: memory\n"); 501 error = ENXIO; 502 goto fail; 503 } 504 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); 505 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory); 506 507 /* XXX This is quite goofy, it is not actually used */ 508 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle; 509 510 /* 511 * Don't enable MSI-X on 82574, see: 512 * 82574 specification update errata #15 513 * 514 * Don't enable MSI on 82571/82572, see: 515 * 82571/82572 specification update errata #63 516 */ 517 msi_enable = emx_msi_enable; 518 if (msi_enable && 519 (sc->hw.mac.type == e1000_82571 || 520 sc->hw.mac.type == e1000_82572)) 521 msi_enable = 0; 522 523 /* 524 * Allocate interrupt 525 */ 526 sc->intr_type = pci_alloc_1intr(dev, msi_enable, 527 &sc->intr_rid, &intr_flags); 528 529 if (sc->intr_type == PCI_INTR_TYPE_LEGACY) { 530 int unshared; 531 532 unshared = device_getenv_int(dev, "irq.unshared", 0); 533 if (!unshared) { 534 sc->flags |= EMX_FLAG_SHARED_INTR; 535 if (bootverbose) 536 device_printf(dev, "IRQ shared\n"); 537 } else { 538 intr_flags &= ~RF_SHAREABLE; 539 if (bootverbose) 540 device_printf(dev, "IRQ unshared\n"); 541 } 542 } 543 544 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid, 545 intr_flags); 546 if (sc->intr_res == NULL) { 547 device_printf(dev, "Unable to allocate bus resource: " 548 "interrupt\n"); 549 error = ENXIO; 550 goto fail; 551 } 552 553 /* Save PCI command register for Shared Code */ 554 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 555 sc->hw.back = &sc->osdep; 556 557 /* Do Shared Code initialization */ 558 if (e1000_setup_init_funcs(&sc->hw, TRUE)) { 559 device_printf(dev, "Setup of Shared code failed\n"); 560 error = ENXIO; 561 goto fail; 562 } 563 e1000_get_bus_info(&sc->hw); 564 565 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG; 566 sc->hw.phy.autoneg_wait_to_complete = FALSE; 567 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT; 568 569 /* 570 * Interrupt throttle rate 571 */ 572 throttle = device_getenv_int(dev, "int_throttle_ceil", 573 emx_int_throttle_ceil); 574 if (throttle == 0) { 575 sc->int_throttle_ceil = 0; 576 } else { 577 if (throttle < 0) 578 throttle = EMX_DEFAULT_ITR; 579 580 /* Recalculate the tunable value to get the exact frequency. */ 581 throttle = 1000000000 / 256 / throttle; 582 583 /* Upper 16bits of ITR is reserved and should be zero */ 584 if (throttle & 0xffff0000) 585 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR; 586 587 sc->int_throttle_ceil = 1000000000 / 256 / throttle; 588 } 589 590 e1000_init_script_state_82541(&sc->hw, TRUE); 591 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE); 592 593 /* Copper options */ 594 if (sc->hw.phy.media_type == e1000_media_type_copper) { 595 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES; 596 sc->hw.phy.disable_polarity_correction = FALSE; 597 sc->hw.phy.ms_type = EMX_MASTER_SLAVE; 598 } 599 600 /* Set the frame limits assuming standard ethernet sized frames. */ 601 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN; 602 sc->min_frame_size = ETHER_MIN_LEN; 603 604 /* This controls when hardware reports transmit completion status. */ 605 sc->hw.mac.report_tx_early = 1; 606 607 /* Calculate # of RX rings */ 608 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", emx_rxr); 609 sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, EMX_NRX_RING); 610 611 /* 612 * Calculate # of TX rings 613 * 614 * NOTE: 615 * Don't enable multiple TX queues on 82574; it always gives 616 * watchdog timeout on TX queue0, when multiple TCP streams are 617 * received. It was originally suspected that the hardware TX 618 * checksum offloading caused this watchdog timeout, since only 619 * TCP ACKs are sent during TCP receiving tests. However, even 620 * if the hardware TX checksum offloading is disable, TX queue0 621 * still will give watchdog. 622 */ 623 tx_ring_max = 1; 624 if (sc->hw.mac.type == e1000_82571 || 625 sc->hw.mac.type == e1000_82572 || 626 sc->hw.mac.type == e1000_80003es2lan) 627 tx_ring_max = EMX_NTX_RING; 628 sc->tx_ring_cnt = device_getenv_int(dev, "txr", emx_txr); 629 sc->tx_ring_cnt = if_ring_count2(sc->tx_ring_cnt, tx_ring_max); 630 631 /* Allocate RX/TX rings' busdma(9) stuffs */ 632 error = emx_dma_alloc(sc); 633 if (error) 634 goto fail; 635 636 /* Allocate multicast array memory. */ 637 sc->mta = kmalloc(ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX, 638 M_DEVBUF, M_WAITOK); 639 640 /* Indicate SOL/IDER usage */ 641 if (e1000_check_reset_block(&sc->hw)) { 642 device_printf(dev, 643 "PHY reset is blocked due to SOL/IDER session.\n"); 644 } 645 646 /* 647 * Start from a known state, this is important in reading the 648 * nvm and mac from that. 649 */ 650 e1000_reset_hw(&sc->hw); 651 652 /* Make sure we have a good EEPROM before we read from it */ 653 if (e1000_validate_nvm_checksum(&sc->hw) < 0) { 654 /* 655 * Some PCI-E parts fail the first check due to 656 * the link being in sleep state, call it again, 657 * if it fails a second time its a real issue. 658 */ 659 if (e1000_validate_nvm_checksum(&sc->hw) < 0) { 660 device_printf(dev, 661 "The EEPROM Checksum Is Not Valid\n"); 662 error = EIO; 663 goto fail; 664 } 665 } 666 667 /* Copy the permanent MAC address out of the EEPROM */ 668 if (e1000_read_mac_addr(&sc->hw) < 0) { 669 device_printf(dev, "EEPROM read error while reading MAC" 670 " address\n"); 671 error = EIO; 672 goto fail; 673 } 674 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) { 675 device_printf(dev, "Invalid MAC address\n"); 676 error = EIO; 677 goto fail; 678 } 679 680 /* Determine if we have to control management hardware */ 681 if (e1000_enable_mng_pass_thru(&sc->hw)) 682 sc->flags |= EMX_FLAG_HAS_MGMT; 683 684 /* 685 * Setup Wake-on-Lan 686 */ 687 apme_mask = EMX_EEPROM_APME; 688 eeprom_data = 0; 689 switch (sc->hw.mac.type) { 690 case e1000_82573: 691 sc->flags |= EMX_FLAG_HAS_AMT; 692 /* FALL THROUGH */ 693 694 case e1000_82571: 695 case e1000_82572: 696 case e1000_80003es2lan: 697 if (sc->hw.bus.func == 1) { 698 e1000_read_nvm(&sc->hw, 699 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 700 } else { 701 e1000_read_nvm(&sc->hw, 702 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 703 } 704 break; 705 706 default: 707 e1000_read_nvm(&sc->hw, 708 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 709 break; 710 } 711 if (eeprom_data & apme_mask) 712 sc->wol = E1000_WUFC_MAG | E1000_WUFC_MC; 713 714 /* 715 * We have the eeprom settings, now apply the special cases 716 * where the eeprom may be wrong or the board won't support 717 * wake on lan on a particular port 718 */ 719 device_id = pci_get_device(dev); 720 switch (device_id) { 721 case E1000_DEV_ID_82571EB_FIBER: 722 /* 723 * Wake events only supported on port A for dual fiber 724 * regardless of eeprom setting 725 */ 726 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 727 E1000_STATUS_FUNC_1) 728 sc->wol = 0; 729 break; 730 731 case E1000_DEV_ID_82571EB_QUAD_COPPER: 732 case E1000_DEV_ID_82571EB_QUAD_FIBER: 733 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 734 /* if quad port sc, disable WoL on all but port A */ 735 if (emx_global_quad_port_a != 0) 736 sc->wol = 0; 737 /* Reset for multiple quad port adapters */ 738 if (++emx_global_quad_port_a == 4) 739 emx_global_quad_port_a = 0; 740 break; 741 } 742 743 /* XXX disable wol */ 744 sc->wol = 0; 745 746 #ifdef IFPOLL_ENABLE 747 /* 748 * NPOLLING RX CPU offset 749 */ 750 if (sc->rx_ring_cnt == ncpus2) { 751 offset = 0; 752 } else { 753 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2; 754 offset = device_getenv_int(dev, "npoll.rxoff", offset_def); 755 if (offset >= ncpus2 || 756 offset % sc->rx_ring_cnt != 0) { 757 device_printf(dev, "invalid npoll.rxoff %d, use %d\n", 758 offset, offset_def); 759 offset = offset_def; 760 } 761 } 762 sc->rx_npoll_off = offset; 763 764 /* 765 * NPOLLING TX CPU offset 766 */ 767 if (sc->tx_ring_cnt == ncpus2) { 768 offset = 0; 769 } else { 770 offset_def = (sc->tx_ring_cnt * device_get_unit(dev)) % ncpus2; 771 offset = device_getenv_int(dev, "npoll.txoff", offset_def); 772 if (offset >= ncpus2 || 773 offset % sc->tx_ring_cnt != 0) { 774 device_printf(dev, "invalid npoll.txoff %d, use %d\n", 775 offset, offset_def); 776 offset = offset_def; 777 } 778 } 779 sc->tx_npoll_off = offset; 780 #endif 781 sc->tx_ring_inuse = emx_get_txring_inuse(sc, FALSE); 782 783 /* Setup OS specific network interface */ 784 emx_setup_ifp(sc); 785 786 /* Add sysctl tree, must after em_setup_ifp() */ 787 emx_add_sysctl(sc); 788 789 /* Reset the hardware */ 790 error = emx_reset(sc); 791 if (error) { 792 device_printf(dev, "Unable to reset the hardware\n"); 793 goto fail; 794 } 795 796 /* Initialize statistics */ 797 emx_update_stats(sc); 798 799 sc->hw.mac.get_link_status = 1; 800 emx_update_link_status(sc); 801 802 /* Non-AMT based hardware can now take control from firmware */ 803 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) == 804 EMX_FLAG_HAS_MGMT) 805 emx_get_hw_control(sc); 806 807 /* 808 * Missing Interrupt Following ICR read: 809 * 810 * 82571/82572 specification update errata #76 811 * 82573 specification update errata #31 812 * 82574 specification update errata #12 813 */ 814 intr_func = emx_intr; 815 if ((sc->flags & EMX_FLAG_SHARED_INTR) && 816 (sc->hw.mac.type == e1000_82571 || 817 sc->hw.mac.type == e1000_82572 || 818 sc->hw.mac.type == e1000_82573 || 819 sc->hw.mac.type == e1000_82574)) 820 intr_func = emx_intr_mask; 821 822 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, intr_func, sc, 823 &sc->intr_tag, &sc->main_serialize); 824 if (error) { 825 device_printf(dev, "Failed to register interrupt handler"); 826 ether_ifdetach(&sc->arpcom.ac_if); 827 goto fail; 828 } 829 return (0); 830 fail: 831 emx_detach(dev); 832 return (error); 833 } 834 835 static int 836 emx_detach(device_t dev) 837 { 838 struct emx_softc *sc = device_get_softc(dev); 839 840 if (device_is_attached(dev)) { 841 struct ifnet *ifp = &sc->arpcom.ac_if; 842 843 ifnet_serialize_all(ifp); 844 845 emx_stop(sc); 846 847 e1000_phy_hw_reset(&sc->hw); 848 849 emx_rel_mgmt(sc); 850 emx_rel_hw_control(sc); 851 852 if (sc->wol) { 853 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 854 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 855 emx_enable_wol(dev); 856 } 857 858 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag); 859 860 ifnet_deserialize_all(ifp); 861 862 ether_ifdetach(ifp); 863 } else if (sc->memory != NULL) { 864 emx_rel_hw_control(sc); 865 } 866 bus_generic_detach(dev); 867 868 if (sc->intr_res != NULL) { 869 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid, 870 sc->intr_res); 871 } 872 873 if (sc->intr_type == PCI_INTR_TYPE_MSI) 874 pci_release_msi(dev); 875 876 if (sc->memory != NULL) { 877 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid, 878 sc->memory); 879 } 880 881 emx_dma_free(sc); 882 883 /* Free sysctl tree */ 884 if (sc->sysctl_tree != NULL) 885 sysctl_ctx_free(&sc->sysctl_ctx); 886 887 if (sc->mta != NULL) 888 kfree(sc->mta, M_DEVBUF); 889 890 return (0); 891 } 892 893 static int 894 emx_shutdown(device_t dev) 895 { 896 return emx_suspend(dev); 897 } 898 899 static int 900 emx_suspend(device_t dev) 901 { 902 struct emx_softc *sc = device_get_softc(dev); 903 struct ifnet *ifp = &sc->arpcom.ac_if; 904 905 ifnet_serialize_all(ifp); 906 907 emx_stop(sc); 908 909 emx_rel_mgmt(sc); 910 emx_rel_hw_control(sc); 911 912 if (sc->wol) { 913 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 914 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 915 emx_enable_wol(dev); 916 } 917 918 ifnet_deserialize_all(ifp); 919 920 return bus_generic_suspend(dev); 921 } 922 923 static int 924 emx_resume(device_t dev) 925 { 926 struct emx_softc *sc = device_get_softc(dev); 927 struct ifnet *ifp = &sc->arpcom.ac_if; 928 int i; 929 930 ifnet_serialize_all(ifp); 931 932 emx_init(sc); 933 emx_get_mgmt(sc); 934 for (i = 0; i < sc->tx_ring_inuse; ++i) 935 ifsq_devstart_sched(sc->tx_data[i].ifsq); 936 937 ifnet_deserialize_all(ifp); 938 939 return bus_generic_resume(dev); 940 } 941 942 static void 943 emx_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 944 { 945 struct emx_softc *sc = ifp->if_softc; 946 struct emx_txdata *tdata = ifsq_get_priv(ifsq); 947 struct mbuf *m_head; 948 int idx = -1, nsegs = 0; 949 950 KKASSERT(tdata->ifsq == ifsq); 951 ASSERT_SERIALIZED(&tdata->tx_serialize); 952 953 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq)) 954 return; 955 956 if (!sc->link_active || (tdata->tx_flags & EMX_TXFLAG_ENABLED) == 0) { 957 ifsq_purge(ifsq); 958 return; 959 } 960 961 while (!ifsq_is_empty(ifsq)) { 962 /* Now do we at least have a minimal? */ 963 if (EMX_IS_OACTIVE(tdata)) { 964 emx_tx_collect(tdata); 965 if (EMX_IS_OACTIVE(tdata)) { 966 ifsq_set_oactive(ifsq); 967 break; 968 } 969 } 970 971 logif(pkt_txqueue); 972 m_head = ifsq_dequeue(ifsq, NULL); 973 if (m_head == NULL) 974 break; 975 976 if (emx_encap(tdata, &m_head, &nsegs, &idx)) { 977 IFNET_STAT_INC(ifp, oerrors, 1); 978 emx_tx_collect(tdata); 979 continue; 980 } 981 982 if (nsegs >= tdata->tx_wreg_nsegs) { 983 E1000_WRITE_REG(&sc->hw, E1000_TDT(tdata->idx), idx); 984 nsegs = 0; 985 idx = -1; 986 } 987 988 /* Send a copy of the frame to the BPF listener */ 989 ETHER_BPF_MTAP(ifp, m_head); 990 991 /* Set timeout in case hardware has problems transmitting. */ 992 tdata->tx_watchdog.wd_timer = EMX_TX_TIMEOUT; 993 } 994 if (idx >= 0) 995 E1000_WRITE_REG(&sc->hw, E1000_TDT(tdata->idx), idx); 996 } 997 998 static int 999 emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1000 { 1001 struct emx_softc *sc = ifp->if_softc; 1002 struct ifreq *ifr = (struct ifreq *)data; 1003 uint16_t eeprom_data = 0; 1004 int max_frame_size, mask, reinit; 1005 int error = 0; 1006 1007 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1008 1009 switch (command) { 1010 case SIOCSIFMTU: 1011 switch (sc->hw.mac.type) { 1012 case e1000_82573: 1013 /* 1014 * 82573 only supports jumbo frames 1015 * if ASPM is disabled. 1016 */ 1017 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1, 1018 &eeprom_data); 1019 if (eeprom_data & NVM_WORD1A_ASPM_MASK) { 1020 max_frame_size = ETHER_MAX_LEN; 1021 break; 1022 } 1023 /* FALL THROUGH */ 1024 1025 /* Limit Jumbo Frame size */ 1026 case e1000_82571: 1027 case e1000_82572: 1028 case e1000_82574: 1029 case e1000_80003es2lan: 1030 max_frame_size = 9234; 1031 break; 1032 1033 default: 1034 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1035 break; 1036 } 1037 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN - 1038 ETHER_CRC_LEN) { 1039 error = EINVAL; 1040 break; 1041 } 1042 1043 ifp->if_mtu = ifr->ifr_mtu; 1044 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN + 1045 ETHER_CRC_LEN; 1046 1047 if (ifp->if_flags & IFF_RUNNING) 1048 emx_init(sc); 1049 break; 1050 1051 case SIOCSIFFLAGS: 1052 if (ifp->if_flags & IFF_UP) { 1053 if ((ifp->if_flags & IFF_RUNNING)) { 1054 if ((ifp->if_flags ^ sc->if_flags) & 1055 (IFF_PROMISC | IFF_ALLMULTI)) { 1056 emx_disable_promisc(sc); 1057 emx_set_promisc(sc); 1058 } 1059 } else { 1060 emx_init(sc); 1061 } 1062 } else if (ifp->if_flags & IFF_RUNNING) { 1063 emx_stop(sc); 1064 } 1065 sc->if_flags = ifp->if_flags; 1066 break; 1067 1068 case SIOCADDMULTI: 1069 case SIOCDELMULTI: 1070 if (ifp->if_flags & IFF_RUNNING) { 1071 emx_disable_intr(sc); 1072 emx_set_multi(sc); 1073 #ifdef IFPOLL_ENABLE 1074 if (!(ifp->if_flags & IFF_NPOLLING)) 1075 #endif 1076 emx_enable_intr(sc); 1077 } 1078 break; 1079 1080 case SIOCSIFMEDIA: 1081 /* Check SOL/IDER usage */ 1082 if (e1000_check_reset_block(&sc->hw)) { 1083 device_printf(sc->dev, "Media change is" 1084 " blocked due to SOL/IDER session.\n"); 1085 break; 1086 } 1087 /* FALL THROUGH */ 1088 1089 case SIOCGIFMEDIA: 1090 error = ifmedia_ioctl(ifp, ifr, &sc->media, command); 1091 break; 1092 1093 case SIOCSIFCAP: 1094 reinit = 0; 1095 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1096 if (mask & IFCAP_RXCSUM) { 1097 ifp->if_capenable ^= IFCAP_RXCSUM; 1098 reinit = 1; 1099 } 1100 if (mask & IFCAP_VLAN_HWTAGGING) { 1101 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1102 reinit = 1; 1103 } 1104 if (mask & IFCAP_TXCSUM) { 1105 ifp->if_capenable ^= IFCAP_TXCSUM; 1106 if (ifp->if_capenable & IFCAP_TXCSUM) 1107 ifp->if_hwassist |= EMX_CSUM_FEATURES; 1108 else 1109 ifp->if_hwassist &= ~EMX_CSUM_FEATURES; 1110 } 1111 if (mask & IFCAP_TSO) { 1112 ifp->if_capenable ^= IFCAP_TSO; 1113 if (ifp->if_capenable & IFCAP_TSO) 1114 ifp->if_hwassist |= CSUM_TSO; 1115 else 1116 ifp->if_hwassist &= ~CSUM_TSO; 1117 } 1118 if (mask & IFCAP_RSS) 1119 ifp->if_capenable ^= IFCAP_RSS; 1120 if (reinit && (ifp->if_flags & IFF_RUNNING)) 1121 emx_init(sc); 1122 break; 1123 1124 default: 1125 error = ether_ioctl(ifp, command, data); 1126 break; 1127 } 1128 return (error); 1129 } 1130 1131 static void 1132 emx_watchdog(struct ifaltq_subque *ifsq) 1133 { 1134 struct emx_txdata *tdata = ifsq_get_priv(ifsq); 1135 struct ifnet *ifp = ifsq_get_ifp(ifsq); 1136 struct emx_softc *sc = ifp->if_softc; 1137 int i; 1138 1139 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1140 1141 /* 1142 * The timer is set to 5 every time start queues a packet. 1143 * Then txeof keeps resetting it as long as it cleans at 1144 * least one descriptor. 1145 * Finally, anytime all descriptors are clean the timer is 1146 * set to 0. 1147 */ 1148 1149 if (E1000_READ_REG(&sc->hw, E1000_TDT(tdata->idx)) == 1150 E1000_READ_REG(&sc->hw, E1000_TDH(tdata->idx))) { 1151 /* 1152 * If we reach here, all TX jobs are completed and 1153 * the TX engine should have been idled for some time. 1154 * We don't need to call ifsq_devstart_sched() here. 1155 */ 1156 ifsq_clr_oactive(ifsq); 1157 tdata->tx_watchdog.wd_timer = 0; 1158 return; 1159 } 1160 1161 /* 1162 * If we are in this routine because of pause frames, then 1163 * don't reset the hardware. 1164 */ 1165 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) { 1166 tdata->tx_watchdog.wd_timer = EMX_TX_TIMEOUT; 1167 return; 1168 } 1169 1170 if_printf(ifp, "TX %d watchdog timeout -- resetting\n", tdata->idx); 1171 1172 IFNET_STAT_INC(ifp, oerrors, 1); 1173 1174 emx_init(sc); 1175 for (i = 0; i < sc->tx_ring_inuse; ++i) 1176 ifsq_devstart_sched(sc->tx_data[i].ifsq); 1177 } 1178 1179 static void 1180 emx_init(void *xsc) 1181 { 1182 struct emx_softc *sc = xsc; 1183 struct ifnet *ifp = &sc->arpcom.ac_if; 1184 device_t dev = sc->dev; 1185 boolean_t polling; 1186 int i; 1187 1188 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1189 1190 emx_stop(sc); 1191 1192 /* Get the latest mac address, User can use a LAA */ 1193 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN); 1194 1195 /* Put the address into the Receive Address Array */ 1196 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1197 1198 /* 1199 * With the 82571 sc, RAR[0] may be overwritten 1200 * when the other port is reset, we make a duplicate 1201 * in RAR[14] for that eventuality, this assures 1202 * the interface continues to function. 1203 */ 1204 if (sc->hw.mac.type == e1000_82571) { 1205 e1000_set_laa_state_82571(&sc->hw, TRUE); 1206 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 1207 E1000_RAR_ENTRIES - 1); 1208 } 1209 1210 /* Initialize the hardware */ 1211 if (emx_reset(sc)) { 1212 device_printf(dev, "Unable to reset the hardware\n"); 1213 /* XXX emx_stop()? */ 1214 return; 1215 } 1216 emx_update_link_status(sc); 1217 1218 /* Setup VLAN support, basic and offload if available */ 1219 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1220 1221 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 1222 uint32_t ctrl; 1223 1224 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL); 1225 ctrl |= E1000_CTRL_VME; 1226 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl); 1227 } 1228 1229 /* Configure for OS presence */ 1230 emx_get_mgmt(sc); 1231 1232 polling = FALSE; 1233 #ifdef IFPOLL_ENABLE 1234 if (ifp->if_flags & IFF_NPOLLING) 1235 polling = TRUE; 1236 #endif 1237 sc->tx_ring_inuse = emx_get_txring_inuse(sc, polling); 1238 ifq_set_subq_mask(&ifp->if_snd, sc->tx_ring_inuse - 1); 1239 1240 /* Prepare transmit descriptors and buffers */ 1241 for (i = 0; i < sc->tx_ring_inuse; ++i) 1242 emx_init_tx_ring(&sc->tx_data[i]); 1243 emx_init_tx_unit(sc); 1244 1245 /* Setup Multicast table */ 1246 emx_set_multi(sc); 1247 1248 /* Prepare receive descriptors and buffers */ 1249 for (i = 0; i < sc->rx_ring_cnt; ++i) { 1250 if (emx_init_rx_ring(&sc->rx_data[i])) { 1251 device_printf(dev, 1252 "Could not setup receive structures\n"); 1253 emx_stop(sc); 1254 return; 1255 } 1256 } 1257 emx_init_rx_unit(sc); 1258 1259 /* Don't lose promiscuous settings */ 1260 emx_set_promisc(sc); 1261 1262 ifp->if_flags |= IFF_RUNNING; 1263 for (i = 0; i < sc->tx_ring_inuse; ++i) { 1264 ifsq_clr_oactive(sc->tx_data[i].ifsq); 1265 ifsq_watchdog_start(&sc->tx_data[i].tx_watchdog); 1266 } 1267 1268 callout_reset(&sc->timer, hz, emx_timer, sc); 1269 e1000_clear_hw_cntrs_base_generic(&sc->hw); 1270 1271 /* MSI/X configuration for 82574 */ 1272 if (sc->hw.mac.type == e1000_82574) { 1273 int tmp; 1274 1275 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 1276 tmp |= E1000_CTRL_EXT_PBA_CLR; 1277 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp); 1278 /* 1279 * XXX MSIX 1280 * Set the IVAR - interrupt vector routing. 1281 * Each nibble represents a vector, high bit 1282 * is enable, other 3 bits are the MSIX table 1283 * entry, we map RXQ0 to 0, TXQ0 to 1, and 1284 * Link (other) to 2, hence the magic number. 1285 */ 1286 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908); 1287 } 1288 1289 /* 1290 * Only enable interrupts if we are not polling, make sure 1291 * they are off otherwise. 1292 */ 1293 if (polling) 1294 emx_disable_intr(sc); 1295 else 1296 emx_enable_intr(sc); 1297 1298 /* AMT based hardware can now take control from firmware */ 1299 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) == 1300 (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) 1301 emx_get_hw_control(sc); 1302 } 1303 1304 static void 1305 emx_intr(void *xsc) 1306 { 1307 emx_intr_body(xsc, TRUE); 1308 } 1309 1310 static void 1311 emx_intr_body(struct emx_softc *sc, boolean_t chk_asserted) 1312 { 1313 struct ifnet *ifp = &sc->arpcom.ac_if; 1314 uint32_t reg_icr; 1315 1316 logif(intr_beg); 1317 ASSERT_SERIALIZED(&sc->main_serialize); 1318 1319 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1320 1321 if (chk_asserted && (reg_icr & E1000_ICR_INT_ASSERTED) == 0) { 1322 logif(intr_end); 1323 return; 1324 } 1325 1326 /* 1327 * XXX: some laptops trigger several spurious interrupts 1328 * on emx(4) when in the resume cycle. The ICR register 1329 * reports all-ones value in this case. Processing such 1330 * interrupts would lead to a freeze. I don't know why. 1331 */ 1332 if (reg_icr == 0xffffffff) { 1333 logif(intr_end); 1334 return; 1335 } 1336 1337 if (ifp->if_flags & IFF_RUNNING) { 1338 if (reg_icr & 1339 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) { 1340 int i; 1341 1342 for (i = 0; i < sc->rx_ring_cnt; ++i) { 1343 lwkt_serialize_enter( 1344 &sc->rx_data[i].rx_serialize); 1345 emx_rxeof(&sc->rx_data[i], -1); 1346 lwkt_serialize_exit( 1347 &sc->rx_data[i].rx_serialize); 1348 } 1349 } 1350 if (reg_icr & E1000_ICR_TXDW) { 1351 struct emx_txdata *tdata = &sc->tx_data[0]; 1352 1353 lwkt_serialize_enter(&tdata->tx_serialize); 1354 emx_txeof(tdata); 1355 if (!ifsq_is_empty(tdata->ifsq)) 1356 ifsq_devstart(tdata->ifsq); 1357 lwkt_serialize_exit(&tdata->tx_serialize); 1358 } 1359 } 1360 1361 /* Link status change */ 1362 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1363 emx_serialize_skipmain(sc); 1364 1365 callout_stop(&sc->timer); 1366 sc->hw.mac.get_link_status = 1; 1367 emx_update_link_status(sc); 1368 1369 /* Deal with TX cruft when link lost */ 1370 emx_tx_purge(sc); 1371 1372 callout_reset(&sc->timer, hz, emx_timer, sc); 1373 1374 emx_deserialize_skipmain(sc); 1375 } 1376 1377 if (reg_icr & E1000_ICR_RXO) 1378 sc->rx_overruns++; 1379 1380 logif(intr_end); 1381 } 1382 1383 static void 1384 emx_intr_mask(void *xsc) 1385 { 1386 struct emx_softc *sc = xsc; 1387 1388 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff); 1389 /* 1390 * NOTE: 1391 * ICR.INT_ASSERTED bit will never be set if IMS is 0, 1392 * so don't check it. 1393 */ 1394 emx_intr_body(sc, FALSE); 1395 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK); 1396 } 1397 1398 static void 1399 emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1400 { 1401 struct emx_softc *sc = ifp->if_softc; 1402 1403 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1404 1405 emx_update_link_status(sc); 1406 1407 ifmr->ifm_status = IFM_AVALID; 1408 ifmr->ifm_active = IFM_ETHER; 1409 1410 if (!sc->link_active) 1411 return; 1412 1413 ifmr->ifm_status |= IFM_ACTIVE; 1414 1415 if (sc->hw.phy.media_type == e1000_media_type_fiber || 1416 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 1417 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX; 1418 } else { 1419 switch (sc->link_speed) { 1420 case 10: 1421 ifmr->ifm_active |= IFM_10_T; 1422 break; 1423 case 100: 1424 ifmr->ifm_active |= IFM_100_TX; 1425 break; 1426 1427 case 1000: 1428 ifmr->ifm_active |= IFM_1000_T; 1429 break; 1430 } 1431 if (sc->link_duplex == FULL_DUPLEX) 1432 ifmr->ifm_active |= IFM_FDX; 1433 else 1434 ifmr->ifm_active |= IFM_HDX; 1435 } 1436 } 1437 1438 static int 1439 emx_media_change(struct ifnet *ifp) 1440 { 1441 struct emx_softc *sc = ifp->if_softc; 1442 struct ifmedia *ifm = &sc->media; 1443 1444 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1445 1446 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1447 return (EINVAL); 1448 1449 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1450 case IFM_AUTO: 1451 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG; 1452 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT; 1453 break; 1454 1455 case IFM_1000_LX: 1456 case IFM_1000_SX: 1457 case IFM_1000_T: 1458 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG; 1459 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1460 break; 1461 1462 case IFM_100_TX: 1463 sc->hw.mac.autoneg = FALSE; 1464 sc->hw.phy.autoneg_advertised = 0; 1465 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1466 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1467 else 1468 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1469 break; 1470 1471 case IFM_10_T: 1472 sc->hw.mac.autoneg = FALSE; 1473 sc->hw.phy.autoneg_advertised = 0; 1474 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1475 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1476 else 1477 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1478 break; 1479 1480 default: 1481 if_printf(ifp, "Unsupported media type\n"); 1482 break; 1483 } 1484 1485 emx_init(sc); 1486 1487 return (0); 1488 } 1489 1490 static int 1491 emx_encap(struct emx_txdata *tdata, struct mbuf **m_headp, 1492 int *segs_used, int *idx) 1493 { 1494 bus_dma_segment_t segs[EMX_MAX_SCATTER]; 1495 bus_dmamap_t map; 1496 struct emx_txbuf *tx_buffer, *tx_buffer_mapped; 1497 struct e1000_tx_desc *ctxd = NULL; 1498 struct mbuf *m_head = *m_headp; 1499 uint32_t txd_upper, txd_lower, cmd = 0; 1500 int maxsegs, nsegs, i, j, first, last = 0, error; 1501 1502 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 1503 error = emx_tso_pullup(tdata, m_headp); 1504 if (error) 1505 return error; 1506 m_head = *m_headp; 1507 } 1508 1509 txd_upper = txd_lower = 0; 1510 1511 /* 1512 * Capture the first descriptor index, this descriptor 1513 * will have the index of the EOP which is the only one 1514 * that now gets a DONE bit writeback. 1515 */ 1516 first = tdata->next_avail_tx_desc; 1517 tx_buffer = &tdata->tx_buf[first]; 1518 tx_buffer_mapped = tx_buffer; 1519 map = tx_buffer->map; 1520 1521 maxsegs = tdata->num_tx_desc_avail - EMX_TX_RESERVED; 1522 KASSERT(maxsegs >= tdata->spare_tx_desc, ("not enough spare TX desc")); 1523 if (maxsegs > EMX_MAX_SCATTER) 1524 maxsegs = EMX_MAX_SCATTER; 1525 1526 error = bus_dmamap_load_mbuf_defrag(tdata->txtag, map, m_headp, 1527 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 1528 if (error) { 1529 m_freem(*m_headp); 1530 *m_headp = NULL; 1531 return error; 1532 } 1533 bus_dmamap_sync(tdata->txtag, map, BUS_DMASYNC_PREWRITE); 1534 1535 m_head = *m_headp; 1536 tdata->tx_nsegs += nsegs; 1537 *segs_used += nsegs; 1538 1539 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 1540 /* TSO will consume one TX desc */ 1541 i = emx_tso_setup(tdata, m_head, &txd_upper, &txd_lower); 1542 tdata->tx_nsegs += i; 1543 *segs_used += i; 1544 } else if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) { 1545 /* TX csum offloading will consume one TX desc */ 1546 i = emx_txcsum(tdata, m_head, &txd_upper, &txd_lower); 1547 tdata->tx_nsegs += i; 1548 *segs_used += i; 1549 } 1550 1551 /* Handle VLAN tag */ 1552 if (m_head->m_flags & M_VLANTAG) { 1553 /* Set the vlan id. */ 1554 txd_upper |= (htole16(m_head->m_pkthdr.ether_vlantag) << 16); 1555 /* Tell hardware to add tag */ 1556 txd_lower |= htole32(E1000_TXD_CMD_VLE); 1557 } 1558 1559 i = tdata->next_avail_tx_desc; 1560 1561 /* Set up our transmit descriptors */ 1562 for (j = 0; j < nsegs; j++) { 1563 tx_buffer = &tdata->tx_buf[i]; 1564 ctxd = &tdata->tx_desc_base[i]; 1565 1566 ctxd->buffer_addr = htole64(segs[j].ds_addr); 1567 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS | 1568 txd_lower | segs[j].ds_len); 1569 ctxd->upper.data = htole32(txd_upper); 1570 1571 last = i; 1572 if (++i == tdata->num_tx_desc) 1573 i = 0; 1574 } 1575 1576 tdata->next_avail_tx_desc = i; 1577 1578 KKASSERT(tdata->num_tx_desc_avail > nsegs); 1579 tdata->num_tx_desc_avail -= nsegs; 1580 1581 tx_buffer->m_head = m_head; 1582 tx_buffer_mapped->map = tx_buffer->map; 1583 tx_buffer->map = map; 1584 1585 if (tdata->tx_nsegs >= tdata->tx_intr_nsegs) { 1586 tdata->tx_nsegs = 0; 1587 1588 /* 1589 * Report Status (RS) is turned on 1590 * every tx_intr_nsegs descriptors. 1591 */ 1592 cmd = E1000_TXD_CMD_RS; 1593 1594 /* 1595 * Keep track of the descriptor, which will 1596 * be written back by hardware. 1597 */ 1598 tdata->tx_dd[tdata->tx_dd_tail] = last; 1599 EMX_INC_TXDD_IDX(tdata->tx_dd_tail); 1600 KKASSERT(tdata->tx_dd_tail != tdata->tx_dd_head); 1601 } 1602 1603 /* 1604 * Last Descriptor of Packet needs End Of Packet (EOP) 1605 */ 1606 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd); 1607 1608 /* 1609 * Defer TDT updating, until enough descriptors are setup 1610 */ 1611 *idx = i; 1612 1613 #ifdef EMX_TSS_DEBUG 1614 tdata->tx_pkts++; 1615 #endif 1616 1617 return (0); 1618 } 1619 1620 static void 1621 emx_set_promisc(struct emx_softc *sc) 1622 { 1623 struct ifnet *ifp = &sc->arpcom.ac_if; 1624 uint32_t reg_rctl; 1625 1626 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1627 1628 if (ifp->if_flags & IFF_PROMISC) { 1629 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1630 /* Turn this on if you want to see bad packets */ 1631 if (emx_debug_sbp) 1632 reg_rctl |= E1000_RCTL_SBP; 1633 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1634 } else if (ifp->if_flags & IFF_ALLMULTI) { 1635 reg_rctl |= E1000_RCTL_MPE; 1636 reg_rctl &= ~E1000_RCTL_UPE; 1637 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1638 } 1639 } 1640 1641 static void 1642 emx_disable_promisc(struct emx_softc *sc) 1643 { 1644 uint32_t reg_rctl; 1645 1646 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1647 1648 reg_rctl &= ~E1000_RCTL_UPE; 1649 reg_rctl &= ~E1000_RCTL_MPE; 1650 reg_rctl &= ~E1000_RCTL_SBP; 1651 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1652 } 1653 1654 static void 1655 emx_set_multi(struct emx_softc *sc) 1656 { 1657 struct ifnet *ifp = &sc->arpcom.ac_if; 1658 struct ifmultiaddr *ifma; 1659 uint32_t reg_rctl = 0; 1660 uint8_t *mta; 1661 int mcnt = 0; 1662 1663 mta = sc->mta; 1664 bzero(mta, ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX); 1665 1666 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1667 if (ifma->ifma_addr->sa_family != AF_LINK) 1668 continue; 1669 1670 if (mcnt == EMX_MCAST_ADDR_MAX) 1671 break; 1672 1673 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1674 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1675 mcnt++; 1676 } 1677 1678 if (mcnt >= EMX_MCAST_ADDR_MAX) { 1679 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1680 reg_rctl |= E1000_RCTL_MPE; 1681 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1682 } else { 1683 e1000_update_mc_addr_list(&sc->hw, mta, mcnt); 1684 } 1685 } 1686 1687 /* 1688 * This routine checks for link status and updates statistics. 1689 */ 1690 static void 1691 emx_timer(void *xsc) 1692 { 1693 struct emx_softc *sc = xsc; 1694 struct ifnet *ifp = &sc->arpcom.ac_if; 1695 1696 lwkt_serialize_enter(&sc->main_serialize); 1697 1698 emx_update_link_status(sc); 1699 emx_update_stats(sc); 1700 1701 /* Reset LAA into RAR[0] on 82571 */ 1702 if (e1000_get_laa_state_82571(&sc->hw) == TRUE) 1703 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1704 1705 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING)) 1706 emx_print_hw_stats(sc); 1707 1708 emx_smartspeed(sc); 1709 1710 callout_reset(&sc->timer, hz, emx_timer, sc); 1711 1712 lwkt_serialize_exit(&sc->main_serialize); 1713 } 1714 1715 static void 1716 emx_update_link_status(struct emx_softc *sc) 1717 { 1718 struct e1000_hw *hw = &sc->hw; 1719 struct ifnet *ifp = &sc->arpcom.ac_if; 1720 device_t dev = sc->dev; 1721 uint32_t link_check = 0; 1722 1723 /* Get the cached link value or read phy for real */ 1724 switch (hw->phy.media_type) { 1725 case e1000_media_type_copper: 1726 if (hw->mac.get_link_status) { 1727 /* Do the work to read phy */ 1728 e1000_check_for_link(hw); 1729 link_check = !hw->mac.get_link_status; 1730 if (link_check) /* ESB2 fix */ 1731 e1000_cfg_on_link_up(hw); 1732 } else { 1733 link_check = TRUE; 1734 } 1735 break; 1736 1737 case e1000_media_type_fiber: 1738 e1000_check_for_link(hw); 1739 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU; 1740 break; 1741 1742 case e1000_media_type_internal_serdes: 1743 e1000_check_for_link(hw); 1744 link_check = sc->hw.mac.serdes_has_link; 1745 break; 1746 1747 case e1000_media_type_unknown: 1748 default: 1749 break; 1750 } 1751 1752 /* Now check for a transition */ 1753 if (link_check && sc->link_active == 0) { 1754 e1000_get_speed_and_duplex(hw, &sc->link_speed, 1755 &sc->link_duplex); 1756 1757 /* 1758 * Check if we should enable/disable SPEED_MODE bit on 1759 * 82571EB/82572EI 1760 */ 1761 if (sc->link_speed != SPEED_1000 && 1762 (hw->mac.type == e1000_82571 || 1763 hw->mac.type == e1000_82572)) { 1764 int tarc0; 1765 1766 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1767 tarc0 &= ~EMX_TARC_SPEED_MODE; 1768 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1769 } 1770 if (bootverbose) { 1771 device_printf(dev, "Link is up %d Mbps %s\n", 1772 sc->link_speed, 1773 ((sc->link_duplex == FULL_DUPLEX) ? 1774 "Full Duplex" : "Half Duplex")); 1775 } 1776 sc->link_active = 1; 1777 sc->smartspeed = 0; 1778 ifp->if_baudrate = sc->link_speed * 1000000; 1779 ifp->if_link_state = LINK_STATE_UP; 1780 if_link_state_change(ifp); 1781 } else if (!link_check && sc->link_active == 1) { 1782 ifp->if_baudrate = sc->link_speed = 0; 1783 sc->link_duplex = 0; 1784 if (bootverbose) 1785 device_printf(dev, "Link is Down\n"); 1786 sc->link_active = 0; 1787 ifp->if_link_state = LINK_STATE_DOWN; 1788 if_link_state_change(ifp); 1789 } 1790 } 1791 1792 static void 1793 emx_stop(struct emx_softc *sc) 1794 { 1795 struct ifnet *ifp = &sc->arpcom.ac_if; 1796 int i; 1797 1798 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1799 1800 emx_disable_intr(sc); 1801 1802 callout_stop(&sc->timer); 1803 1804 ifp->if_flags &= ~IFF_RUNNING; 1805 for (i = 0; i < sc->tx_ring_cnt; ++i) { 1806 struct emx_txdata *tdata = &sc->tx_data[i]; 1807 1808 ifsq_clr_oactive(tdata->ifsq); 1809 ifsq_watchdog_stop(&tdata->tx_watchdog); 1810 tdata->tx_flags &= ~EMX_TXFLAG_ENABLED; 1811 } 1812 1813 /* 1814 * Disable multiple receive queues. 1815 * 1816 * NOTE: 1817 * We should disable multiple receive queues before 1818 * resetting the hardware. 1819 */ 1820 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0); 1821 1822 e1000_reset_hw(&sc->hw); 1823 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0); 1824 1825 for (i = 0; i < sc->tx_ring_cnt; ++i) 1826 emx_free_tx_ring(&sc->tx_data[i]); 1827 for (i = 0; i < sc->rx_ring_cnt; ++i) 1828 emx_free_rx_ring(&sc->rx_data[i]); 1829 } 1830 1831 static int 1832 emx_reset(struct emx_softc *sc) 1833 { 1834 device_t dev = sc->dev; 1835 uint16_t rx_buffer_size; 1836 uint32_t pba; 1837 1838 /* Set up smart power down as default off on newer adapters. */ 1839 if (!emx_smart_pwr_down && 1840 (sc->hw.mac.type == e1000_82571 || 1841 sc->hw.mac.type == e1000_82572)) { 1842 uint16_t phy_tmp = 0; 1843 1844 /* Speed up time to link by disabling smart power down. */ 1845 e1000_read_phy_reg(&sc->hw, 1846 IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 1847 phy_tmp &= ~IGP02E1000_PM_SPD; 1848 e1000_write_phy_reg(&sc->hw, 1849 IGP02E1000_PHY_POWER_MGMT, phy_tmp); 1850 } 1851 1852 /* 1853 * Packet Buffer Allocation (PBA) 1854 * Writing PBA sets the receive portion of the buffer 1855 * the remainder is used for the transmit buffer. 1856 */ 1857 switch (sc->hw.mac.type) { 1858 /* Total Packet Buffer on these is 48K */ 1859 case e1000_82571: 1860 case e1000_82572: 1861 case e1000_80003es2lan: 1862 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 1863 break; 1864 1865 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 1866 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 1867 break; 1868 1869 case e1000_82574: 1870 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 1871 break; 1872 1873 default: 1874 /* Devices before 82547 had a Packet Buffer of 64K. */ 1875 if (sc->max_frame_size > 8192) 1876 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1877 else 1878 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1879 } 1880 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba); 1881 1882 /* 1883 * These parameters control the automatic generation (Tx) and 1884 * response (Rx) to Ethernet PAUSE frames. 1885 * - High water mark should allow for at least two frames to be 1886 * received after sending an XOFF. 1887 * - Low water mark works best when it is very near the high water mark. 1888 * This allows the receiver to restart by sending XON when it has 1889 * drained a bit. Here we use an arbitary value of 1500 which will 1890 * restart after one full frame is pulled from the buffer. There 1891 * could be several smaller frames in the buffer and if so they will 1892 * not trigger the XON until their total number reduces the buffer 1893 * by 1500. 1894 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 1895 */ 1896 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10; 1897 1898 sc->hw.fc.high_water = rx_buffer_size - 1899 roundup2(sc->max_frame_size, 1024); 1900 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500; 1901 1902 if (sc->hw.mac.type == e1000_80003es2lan) 1903 sc->hw.fc.pause_time = 0xFFFF; 1904 else 1905 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME; 1906 sc->hw.fc.send_xon = TRUE; 1907 sc->hw.fc.requested_mode = e1000_fc_full; 1908 1909 /* Issue a global reset */ 1910 e1000_reset_hw(&sc->hw); 1911 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0); 1912 emx_disable_aspm(sc); 1913 1914 if (e1000_init_hw(&sc->hw) < 0) { 1915 device_printf(dev, "Hardware Initialization Failed\n"); 1916 return (EIO); 1917 } 1918 1919 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1920 e1000_get_phy_info(&sc->hw); 1921 e1000_check_for_link(&sc->hw); 1922 1923 return (0); 1924 } 1925 1926 static void 1927 emx_setup_ifp(struct emx_softc *sc) 1928 { 1929 struct ifnet *ifp = &sc->arpcom.ac_if; 1930 int i; 1931 1932 if_initname(ifp, device_get_name(sc->dev), 1933 device_get_unit(sc->dev)); 1934 ifp->if_softc = sc; 1935 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1936 ifp->if_init = emx_init; 1937 ifp->if_ioctl = emx_ioctl; 1938 ifp->if_start = emx_start; 1939 #ifdef IFPOLL_ENABLE 1940 ifp->if_npoll = emx_npoll; 1941 #endif 1942 ifp->if_serialize = emx_serialize; 1943 ifp->if_deserialize = emx_deserialize; 1944 ifp->if_tryserialize = emx_tryserialize; 1945 #ifdef INVARIANTS 1946 ifp->if_serialize_assert = emx_serialize_assert; 1947 #endif 1948 1949 ifq_set_maxlen(&ifp->if_snd, sc->tx_data[0].num_tx_desc - 1); 1950 ifq_set_ready(&ifp->if_snd); 1951 ifq_set_subq_cnt(&ifp->if_snd, sc->tx_ring_cnt); 1952 1953 ifp->if_mapsubq = ifq_mapsubq_mask; 1954 ifq_set_subq_mask(&ifp->if_snd, 0); 1955 1956 ether_ifattach(ifp, sc->hw.mac.addr, NULL); 1957 1958 ifp->if_capabilities = IFCAP_HWCSUM | 1959 IFCAP_VLAN_HWTAGGING | 1960 IFCAP_VLAN_MTU | 1961 IFCAP_TSO; 1962 if (sc->rx_ring_cnt > 1) 1963 ifp->if_capabilities |= IFCAP_RSS; 1964 ifp->if_capenable = ifp->if_capabilities; 1965 ifp->if_hwassist = EMX_CSUM_FEATURES | CSUM_TSO; 1966 1967 /* 1968 * Tell the upper layer(s) we support long frames. 1969 */ 1970 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1971 1972 for (i = 0; i < sc->tx_ring_cnt; ++i) { 1973 struct ifaltq_subque *ifsq = ifq_get_subq(&ifp->if_snd, i); 1974 struct emx_txdata *tdata = &sc->tx_data[i]; 1975 1976 ifsq_set_cpuid(ifsq, rman_get_cpuid(sc->intr_res)); 1977 ifsq_set_priv(ifsq, tdata); 1978 ifsq_set_hw_serialize(ifsq, &tdata->tx_serialize); 1979 tdata->ifsq = ifsq; 1980 1981 ifsq_watchdog_init(&tdata->tx_watchdog, ifsq, emx_watchdog); 1982 } 1983 1984 /* 1985 * Specify the media types supported by this sc and register 1986 * callbacks to update media and link information 1987 */ 1988 ifmedia_init(&sc->media, IFM_IMASK, 1989 emx_media_change, emx_media_status); 1990 if (sc->hw.phy.media_type == e1000_media_type_fiber || 1991 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 1992 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX, 1993 0, NULL); 1994 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL); 1995 } else { 1996 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 1997 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 1998 0, NULL); 1999 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 2000 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 2001 0, NULL); 2002 if (sc->hw.phy.type != e1000_phy_ife) { 2003 ifmedia_add(&sc->media, 2004 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2005 ifmedia_add(&sc->media, 2006 IFM_ETHER | IFM_1000_T, 0, NULL); 2007 } 2008 } 2009 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2010 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO); 2011 } 2012 2013 /* 2014 * Workaround for SmartSpeed on 82541 and 82547 controllers 2015 */ 2016 static void 2017 emx_smartspeed(struct emx_softc *sc) 2018 { 2019 uint16_t phy_tmp; 2020 2021 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp || 2022 sc->hw.mac.autoneg == 0 || 2023 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2024 return; 2025 2026 if (sc->smartspeed == 0) { 2027 /* 2028 * If Master/Slave config fault is asserted twice, 2029 * we assume back-to-back 2030 */ 2031 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2032 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2033 return; 2034 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2035 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2036 e1000_read_phy_reg(&sc->hw, 2037 PHY_1000T_CTRL, &phy_tmp); 2038 if (phy_tmp & CR_1000T_MS_ENABLE) { 2039 phy_tmp &= ~CR_1000T_MS_ENABLE; 2040 e1000_write_phy_reg(&sc->hw, 2041 PHY_1000T_CTRL, phy_tmp); 2042 sc->smartspeed++; 2043 if (sc->hw.mac.autoneg && 2044 !e1000_phy_setup_autoneg(&sc->hw) && 2045 !e1000_read_phy_reg(&sc->hw, 2046 PHY_CONTROL, &phy_tmp)) { 2047 phy_tmp |= MII_CR_AUTO_NEG_EN | 2048 MII_CR_RESTART_AUTO_NEG; 2049 e1000_write_phy_reg(&sc->hw, 2050 PHY_CONTROL, phy_tmp); 2051 } 2052 } 2053 } 2054 return; 2055 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) { 2056 /* If still no link, perhaps using 2/3 pair cable */ 2057 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2058 phy_tmp |= CR_1000T_MS_ENABLE; 2059 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2060 if (sc->hw.mac.autoneg && 2061 !e1000_phy_setup_autoneg(&sc->hw) && 2062 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) { 2063 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG; 2064 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp); 2065 } 2066 } 2067 2068 /* Restart process after EMX_SMARTSPEED_MAX iterations */ 2069 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX) 2070 sc->smartspeed = 0; 2071 } 2072 2073 static int 2074 emx_create_tx_ring(struct emx_txdata *tdata) 2075 { 2076 device_t dev = tdata->sc->dev; 2077 struct emx_txbuf *tx_buffer; 2078 int error, i, tsize, ntxd; 2079 2080 /* 2081 * Validate number of transmit descriptors. It must not exceed 2082 * hardware maximum, and must be multiple of E1000_DBA_ALIGN. 2083 */ 2084 ntxd = device_getenv_int(dev, "txd", emx_txd); 2085 if ((ntxd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 || 2086 ntxd > EMX_MAX_TXD || ntxd < EMX_MIN_TXD) { 2087 device_printf(dev, "Using %d TX descriptors instead of %d!\n", 2088 EMX_DEFAULT_TXD, ntxd); 2089 tdata->num_tx_desc = EMX_DEFAULT_TXD; 2090 } else { 2091 tdata->num_tx_desc = ntxd; 2092 } 2093 2094 /* 2095 * Allocate Transmit Descriptor ring 2096 */ 2097 tsize = roundup2(tdata->num_tx_desc * sizeof(struct e1000_tx_desc), 2098 EMX_DBA_ALIGN); 2099 tdata->tx_desc_base = bus_dmamem_coherent_any(tdata->sc->parent_dtag, 2100 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK, 2101 &tdata->tx_desc_dtag, &tdata->tx_desc_dmap, 2102 &tdata->tx_desc_paddr); 2103 if (tdata->tx_desc_base == NULL) { 2104 device_printf(dev, "Unable to allocate tx_desc memory\n"); 2105 return ENOMEM; 2106 } 2107 2108 tsize = __VM_CACHELINE_ALIGN( 2109 sizeof(struct emx_txbuf) * tdata->num_tx_desc); 2110 tdata->tx_buf = kmalloc_cachealign(tsize, M_DEVBUF, M_WAITOK | M_ZERO); 2111 2112 /* 2113 * Create DMA tags for tx buffers 2114 */ 2115 error = bus_dma_tag_create(tdata->sc->parent_dtag, /* parent */ 2116 1, 0, /* alignment, bounds */ 2117 BUS_SPACE_MAXADDR, /* lowaddr */ 2118 BUS_SPACE_MAXADDR, /* highaddr */ 2119 NULL, NULL, /* filter, filterarg */ 2120 EMX_TSO_SIZE, /* maxsize */ 2121 EMX_MAX_SCATTER, /* nsegments */ 2122 EMX_MAX_SEGSIZE, /* maxsegsize */ 2123 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | 2124 BUS_DMA_ONEBPAGE, /* flags */ 2125 &tdata->txtag); 2126 if (error) { 2127 device_printf(dev, "Unable to allocate TX DMA tag\n"); 2128 kfree(tdata->tx_buf, M_DEVBUF); 2129 tdata->tx_buf = NULL; 2130 return error; 2131 } 2132 2133 /* 2134 * Create DMA maps for tx buffers 2135 */ 2136 for (i = 0; i < tdata->num_tx_desc; i++) { 2137 tx_buffer = &tdata->tx_buf[i]; 2138 2139 error = bus_dmamap_create(tdata->txtag, 2140 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 2141 &tx_buffer->map); 2142 if (error) { 2143 device_printf(dev, "Unable to create TX DMA map\n"); 2144 emx_destroy_tx_ring(tdata, i); 2145 return error; 2146 } 2147 } 2148 2149 /* 2150 * Setup TX parameters 2151 */ 2152 tdata->spare_tx_desc = EMX_TX_SPARE; 2153 tdata->tx_wreg_nsegs = EMX_DEFAULT_TXWREG; 2154 2155 /* 2156 * Keep following relationship between spare_tx_desc, oact_tx_desc 2157 * and tx_intr_nsegs: 2158 * (spare_tx_desc + EMX_TX_RESERVED) <= 2159 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_intr_nsegs 2160 */ 2161 tdata->oact_tx_desc = tdata->num_tx_desc / 8; 2162 if (tdata->oact_tx_desc > EMX_TX_OACTIVE_MAX) 2163 tdata->oact_tx_desc = EMX_TX_OACTIVE_MAX; 2164 if (tdata->oact_tx_desc < tdata->spare_tx_desc + EMX_TX_RESERVED) 2165 tdata->oact_tx_desc = tdata->spare_tx_desc + EMX_TX_RESERVED; 2166 2167 tdata->tx_intr_nsegs = tdata->num_tx_desc / 16; 2168 if (tdata->tx_intr_nsegs < tdata->oact_tx_desc) 2169 tdata->tx_intr_nsegs = tdata->oact_tx_desc; 2170 2171 /* 2172 * Pullup extra 4bytes into the first data segment, see: 2173 * 82571/82572 specification update errata #7 2174 * 2175 * NOTE: 2176 * 4bytes instead of 2bytes, which are mentioned in the errata, 2177 * are pulled; mainly to keep rest of the data properly aligned. 2178 */ 2179 if (tdata->sc->hw.mac.type == e1000_82571 || 2180 tdata->sc->hw.mac.type == e1000_82572) 2181 tdata->tx_flags |= EMX_TXFLAG_TSO_PULLEX; 2182 2183 return (0); 2184 } 2185 2186 static void 2187 emx_init_tx_ring(struct emx_txdata *tdata) 2188 { 2189 /* Clear the old ring contents */ 2190 bzero(tdata->tx_desc_base, 2191 sizeof(struct e1000_tx_desc) * tdata->num_tx_desc); 2192 2193 /* Reset state */ 2194 tdata->next_avail_tx_desc = 0; 2195 tdata->next_tx_to_clean = 0; 2196 tdata->num_tx_desc_avail = tdata->num_tx_desc; 2197 2198 tdata->tx_flags |= EMX_TXFLAG_ENABLED; 2199 if (tdata->sc->tx_ring_inuse > 1) { 2200 tdata->tx_flags |= EMX_TXFLAG_FORCECTX; 2201 if (bootverbose) { 2202 if_printf(&tdata->sc->arpcom.ac_if, 2203 "TX %d force ctx setup\n", tdata->idx); 2204 } 2205 } 2206 } 2207 2208 static void 2209 emx_init_tx_unit(struct emx_softc *sc) 2210 { 2211 uint32_t tctl, tarc, tipg = 0; 2212 int i; 2213 2214 for (i = 0; i < sc->tx_ring_inuse; ++i) { 2215 struct emx_txdata *tdata = &sc->tx_data[i]; 2216 uint64_t bus_addr; 2217 2218 /* Setup the Base and Length of the Tx Descriptor Ring */ 2219 bus_addr = tdata->tx_desc_paddr; 2220 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(i), 2221 tdata->num_tx_desc * sizeof(struct e1000_tx_desc)); 2222 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(i), 2223 (uint32_t)(bus_addr >> 32)); 2224 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(i), 2225 (uint32_t)bus_addr); 2226 /* Setup the HW Tx Head and Tail descriptor pointers */ 2227 E1000_WRITE_REG(&sc->hw, E1000_TDT(i), 0); 2228 E1000_WRITE_REG(&sc->hw, E1000_TDH(i), 0); 2229 } 2230 2231 /* Set the default values for the Tx Inter Packet Gap timer */ 2232 switch (sc->hw.mac.type) { 2233 case e1000_80003es2lan: 2234 tipg = DEFAULT_82543_TIPG_IPGR1; 2235 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 2236 E1000_TIPG_IPGR2_SHIFT; 2237 break; 2238 2239 default: 2240 if (sc->hw.phy.media_type == e1000_media_type_fiber || 2241 sc->hw.phy.media_type == e1000_media_type_internal_serdes) 2242 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2243 else 2244 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2245 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2246 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2247 break; 2248 } 2249 2250 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg); 2251 2252 /* NOTE: 0 is not allowed for TIDV */ 2253 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1); 2254 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0); 2255 2256 if (sc->hw.mac.type == e1000_82571 || 2257 sc->hw.mac.type == e1000_82572) { 2258 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0)); 2259 tarc |= EMX_TARC_SPEED_MODE; 2260 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc); 2261 } else if (sc->hw.mac.type == e1000_80003es2lan) { 2262 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0)); 2263 tarc |= 1; 2264 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc); 2265 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1)); 2266 tarc |= 1; 2267 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc); 2268 } 2269 2270 /* Program the Transmit Control Register */ 2271 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL); 2272 tctl &= ~E1000_TCTL_CT; 2273 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 2274 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2275 tctl |= E1000_TCTL_MULR; 2276 2277 /* This write will effectively turn on the transmit unit. */ 2278 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl); 2279 2280 if (sc->hw.mac.type == e1000_82571 || 2281 sc->hw.mac.type == e1000_82572 || 2282 sc->hw.mac.type == e1000_80003es2lan) { 2283 /* Bit 28 of TARC1 must be cleared when MULR is enabled */ 2284 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1)); 2285 tarc &= ~(1 << 28); 2286 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc); 2287 } 2288 2289 if (sc->tx_ring_inuse > 1) { 2290 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0)); 2291 tarc &= ~EMX_TARC_COUNT_MASK; 2292 tarc |= 1; 2293 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc); 2294 2295 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1)); 2296 tarc &= ~EMX_TARC_COUNT_MASK; 2297 tarc |= 1; 2298 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc); 2299 } 2300 } 2301 2302 static void 2303 emx_destroy_tx_ring(struct emx_txdata *tdata, int ndesc) 2304 { 2305 struct emx_txbuf *tx_buffer; 2306 int i; 2307 2308 /* Free Transmit Descriptor ring */ 2309 if (tdata->tx_desc_base) { 2310 bus_dmamap_unload(tdata->tx_desc_dtag, tdata->tx_desc_dmap); 2311 bus_dmamem_free(tdata->tx_desc_dtag, tdata->tx_desc_base, 2312 tdata->tx_desc_dmap); 2313 bus_dma_tag_destroy(tdata->tx_desc_dtag); 2314 2315 tdata->tx_desc_base = NULL; 2316 } 2317 2318 if (tdata->tx_buf == NULL) 2319 return; 2320 2321 for (i = 0; i < ndesc; i++) { 2322 tx_buffer = &tdata->tx_buf[i]; 2323 2324 KKASSERT(tx_buffer->m_head == NULL); 2325 bus_dmamap_destroy(tdata->txtag, tx_buffer->map); 2326 } 2327 bus_dma_tag_destroy(tdata->txtag); 2328 2329 kfree(tdata->tx_buf, M_DEVBUF); 2330 tdata->tx_buf = NULL; 2331 } 2332 2333 /* 2334 * The offload context needs to be set when we transfer the first 2335 * packet of a particular protocol (TCP/UDP). This routine has been 2336 * enhanced to deal with inserted VLAN headers. 2337 * 2338 * If the new packet's ether header length, ip header length and 2339 * csum offloading type are same as the previous packet, we should 2340 * avoid allocating a new csum context descriptor; mainly to take 2341 * advantage of the pipeline effect of the TX data read request. 2342 * 2343 * This function returns number of TX descrptors allocated for 2344 * csum context. 2345 */ 2346 static int 2347 emx_txcsum(struct emx_txdata *tdata, struct mbuf *mp, 2348 uint32_t *txd_upper, uint32_t *txd_lower) 2349 { 2350 struct e1000_context_desc *TXD; 2351 int curr_txd, ehdrlen, csum_flags; 2352 uint32_t cmd, hdr_len, ip_hlen; 2353 2354 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES; 2355 ip_hlen = mp->m_pkthdr.csum_iphlen; 2356 ehdrlen = mp->m_pkthdr.csum_lhlen; 2357 2358 if ((tdata->tx_flags & EMX_TXFLAG_FORCECTX) == 0 && 2359 tdata->csum_lhlen == ehdrlen && tdata->csum_iphlen == ip_hlen && 2360 tdata->csum_flags == csum_flags) { 2361 /* 2362 * Same csum offload context as the previous packets; 2363 * just return. 2364 */ 2365 *txd_upper = tdata->csum_txd_upper; 2366 *txd_lower = tdata->csum_txd_lower; 2367 return 0; 2368 } 2369 2370 /* 2371 * Setup a new csum offload context. 2372 */ 2373 2374 curr_txd = tdata->next_avail_tx_desc; 2375 TXD = (struct e1000_context_desc *)&tdata->tx_desc_base[curr_txd]; 2376 2377 cmd = 0; 2378 2379 /* Setup of IP header checksum. */ 2380 if (csum_flags & CSUM_IP) { 2381 /* 2382 * Start offset for header checksum calculation. 2383 * End offset for header checksum calculation. 2384 * Offset of place to put the checksum. 2385 */ 2386 TXD->lower_setup.ip_fields.ipcss = ehdrlen; 2387 TXD->lower_setup.ip_fields.ipcse = 2388 htole16(ehdrlen + ip_hlen - 1); 2389 TXD->lower_setup.ip_fields.ipcso = 2390 ehdrlen + offsetof(struct ip, ip_sum); 2391 cmd |= E1000_TXD_CMD_IP; 2392 *txd_upper |= E1000_TXD_POPTS_IXSM << 8; 2393 } 2394 hdr_len = ehdrlen + ip_hlen; 2395 2396 if (csum_flags & CSUM_TCP) { 2397 /* 2398 * Start offset for payload checksum calculation. 2399 * End offset for payload checksum calculation. 2400 * Offset of place to put the checksum. 2401 */ 2402 TXD->upper_setup.tcp_fields.tucss = hdr_len; 2403 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2404 TXD->upper_setup.tcp_fields.tucso = 2405 hdr_len + offsetof(struct tcphdr, th_sum); 2406 cmd |= E1000_TXD_CMD_TCP; 2407 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 2408 } else if (csum_flags & CSUM_UDP) { 2409 /* 2410 * Start offset for header checksum calculation. 2411 * End offset for header checksum calculation. 2412 * Offset of place to put the checksum. 2413 */ 2414 TXD->upper_setup.tcp_fields.tucss = hdr_len; 2415 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2416 TXD->upper_setup.tcp_fields.tucso = 2417 hdr_len + offsetof(struct udphdr, uh_sum); 2418 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 2419 } 2420 2421 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */ 2422 E1000_TXD_DTYP_D; /* Data descr */ 2423 2424 /* Save the information for this csum offloading context */ 2425 tdata->csum_lhlen = ehdrlen; 2426 tdata->csum_iphlen = ip_hlen; 2427 tdata->csum_flags = csum_flags; 2428 tdata->csum_txd_upper = *txd_upper; 2429 tdata->csum_txd_lower = *txd_lower; 2430 2431 TXD->tcp_seg_setup.data = htole32(0); 2432 TXD->cmd_and_length = 2433 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd); 2434 2435 if (++curr_txd == tdata->num_tx_desc) 2436 curr_txd = 0; 2437 2438 KKASSERT(tdata->num_tx_desc_avail > 0); 2439 tdata->num_tx_desc_avail--; 2440 2441 tdata->next_avail_tx_desc = curr_txd; 2442 return 1; 2443 } 2444 2445 static void 2446 emx_txeof(struct emx_txdata *tdata) 2447 { 2448 struct ifnet *ifp = &tdata->sc->arpcom.ac_if; 2449 struct emx_txbuf *tx_buffer; 2450 int first, num_avail; 2451 2452 if (tdata->tx_dd_head == tdata->tx_dd_tail) 2453 return; 2454 2455 if (tdata->num_tx_desc_avail == tdata->num_tx_desc) 2456 return; 2457 2458 num_avail = tdata->num_tx_desc_avail; 2459 first = tdata->next_tx_to_clean; 2460 2461 while (tdata->tx_dd_head != tdata->tx_dd_tail) { 2462 int dd_idx = tdata->tx_dd[tdata->tx_dd_head]; 2463 struct e1000_tx_desc *tx_desc; 2464 2465 tx_desc = &tdata->tx_desc_base[dd_idx]; 2466 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) { 2467 EMX_INC_TXDD_IDX(tdata->tx_dd_head); 2468 2469 if (++dd_idx == tdata->num_tx_desc) 2470 dd_idx = 0; 2471 2472 while (first != dd_idx) { 2473 logif(pkt_txclean); 2474 2475 num_avail++; 2476 2477 tx_buffer = &tdata->tx_buf[first]; 2478 if (tx_buffer->m_head) { 2479 IFNET_STAT_INC(ifp, opackets, 1); 2480 bus_dmamap_unload(tdata->txtag, 2481 tx_buffer->map); 2482 m_freem(tx_buffer->m_head); 2483 tx_buffer->m_head = NULL; 2484 } 2485 2486 if (++first == tdata->num_tx_desc) 2487 first = 0; 2488 } 2489 } else { 2490 break; 2491 } 2492 } 2493 tdata->next_tx_to_clean = first; 2494 tdata->num_tx_desc_avail = num_avail; 2495 2496 if (tdata->tx_dd_head == tdata->tx_dd_tail) { 2497 tdata->tx_dd_head = 0; 2498 tdata->tx_dd_tail = 0; 2499 } 2500 2501 if (!EMX_IS_OACTIVE(tdata)) { 2502 ifsq_clr_oactive(tdata->ifsq); 2503 2504 /* All clean, turn off the timer */ 2505 if (tdata->num_tx_desc_avail == tdata->num_tx_desc) 2506 tdata->tx_watchdog.wd_timer = 0; 2507 } 2508 } 2509 2510 static void 2511 emx_tx_collect(struct emx_txdata *tdata) 2512 { 2513 struct ifnet *ifp = &tdata->sc->arpcom.ac_if; 2514 struct emx_txbuf *tx_buffer; 2515 int tdh, first, num_avail, dd_idx = -1; 2516 2517 if (tdata->num_tx_desc_avail == tdata->num_tx_desc) 2518 return; 2519 2520 tdh = E1000_READ_REG(&tdata->sc->hw, E1000_TDH(tdata->idx)); 2521 if (tdh == tdata->next_tx_to_clean) 2522 return; 2523 2524 if (tdata->tx_dd_head != tdata->tx_dd_tail) 2525 dd_idx = tdata->tx_dd[tdata->tx_dd_head]; 2526 2527 num_avail = tdata->num_tx_desc_avail; 2528 first = tdata->next_tx_to_clean; 2529 2530 while (first != tdh) { 2531 logif(pkt_txclean); 2532 2533 num_avail++; 2534 2535 tx_buffer = &tdata->tx_buf[first]; 2536 if (tx_buffer->m_head) { 2537 IFNET_STAT_INC(ifp, opackets, 1); 2538 bus_dmamap_unload(tdata->txtag, 2539 tx_buffer->map); 2540 m_freem(tx_buffer->m_head); 2541 tx_buffer->m_head = NULL; 2542 } 2543 2544 if (first == dd_idx) { 2545 EMX_INC_TXDD_IDX(tdata->tx_dd_head); 2546 if (tdata->tx_dd_head == tdata->tx_dd_tail) { 2547 tdata->tx_dd_head = 0; 2548 tdata->tx_dd_tail = 0; 2549 dd_idx = -1; 2550 } else { 2551 dd_idx = tdata->tx_dd[tdata->tx_dd_head]; 2552 } 2553 } 2554 2555 if (++first == tdata->num_tx_desc) 2556 first = 0; 2557 } 2558 tdata->next_tx_to_clean = first; 2559 tdata->num_tx_desc_avail = num_avail; 2560 2561 if (!EMX_IS_OACTIVE(tdata)) { 2562 ifsq_clr_oactive(tdata->ifsq); 2563 2564 /* All clean, turn off the timer */ 2565 if (tdata->num_tx_desc_avail == tdata->num_tx_desc) 2566 tdata->tx_watchdog.wd_timer = 0; 2567 } 2568 } 2569 2570 /* 2571 * When Link is lost sometimes there is work still in the TX ring 2572 * which will result in a watchdog, rather than allow that do an 2573 * attempted cleanup and then reinit here. Note that this has been 2574 * seens mostly with fiber adapters. 2575 */ 2576 static void 2577 emx_tx_purge(struct emx_softc *sc) 2578 { 2579 int i; 2580 2581 if (sc->link_active) 2582 return; 2583 2584 for (i = 0; i < sc->tx_ring_inuse; ++i) { 2585 struct emx_txdata *tdata = &sc->tx_data[i]; 2586 2587 if (tdata->tx_watchdog.wd_timer) { 2588 emx_tx_collect(tdata); 2589 if (tdata->tx_watchdog.wd_timer) { 2590 if_printf(&sc->arpcom.ac_if, 2591 "Link lost, TX pending, reinit\n"); 2592 emx_init(sc); 2593 return; 2594 } 2595 } 2596 } 2597 } 2598 2599 static int 2600 emx_newbuf(struct emx_rxdata *rdata, int i, int init) 2601 { 2602 struct mbuf *m; 2603 bus_dma_segment_t seg; 2604 bus_dmamap_t map; 2605 struct emx_rxbuf *rx_buffer; 2606 int error, nseg; 2607 2608 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 2609 if (m == NULL) { 2610 if (init) { 2611 if_printf(&rdata->sc->arpcom.ac_if, 2612 "Unable to allocate RX mbuf\n"); 2613 } 2614 return (ENOBUFS); 2615 } 2616 m->m_len = m->m_pkthdr.len = MCLBYTES; 2617 2618 if (rdata->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN) 2619 m_adj(m, ETHER_ALIGN); 2620 2621 error = bus_dmamap_load_mbuf_segment(rdata->rxtag, 2622 rdata->rx_sparemap, m, 2623 &seg, 1, &nseg, BUS_DMA_NOWAIT); 2624 if (error) { 2625 m_freem(m); 2626 if (init) { 2627 if_printf(&rdata->sc->arpcom.ac_if, 2628 "Unable to load RX mbuf\n"); 2629 } 2630 return (error); 2631 } 2632 2633 rx_buffer = &rdata->rx_buf[i]; 2634 if (rx_buffer->m_head != NULL) 2635 bus_dmamap_unload(rdata->rxtag, rx_buffer->map); 2636 2637 map = rx_buffer->map; 2638 rx_buffer->map = rdata->rx_sparemap; 2639 rdata->rx_sparemap = map; 2640 2641 rx_buffer->m_head = m; 2642 rx_buffer->paddr = seg.ds_addr; 2643 2644 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer); 2645 return (0); 2646 } 2647 2648 static int 2649 emx_create_rx_ring(struct emx_rxdata *rdata) 2650 { 2651 device_t dev = rdata->sc->dev; 2652 struct emx_rxbuf *rx_buffer; 2653 int i, error, rsize, nrxd; 2654 2655 /* 2656 * Validate number of receive descriptors. It must not exceed 2657 * hardware maximum, and must be multiple of E1000_DBA_ALIGN. 2658 */ 2659 nrxd = device_getenv_int(dev, "rxd", emx_rxd); 2660 if ((nrxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 || 2661 nrxd > EMX_MAX_RXD || nrxd < EMX_MIN_RXD) { 2662 device_printf(dev, "Using %d RX descriptors instead of %d!\n", 2663 EMX_DEFAULT_RXD, nrxd); 2664 rdata->num_rx_desc = EMX_DEFAULT_RXD; 2665 } else { 2666 rdata->num_rx_desc = nrxd; 2667 } 2668 2669 /* 2670 * Allocate Receive Descriptor ring 2671 */ 2672 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t), 2673 EMX_DBA_ALIGN); 2674 rdata->rx_desc = bus_dmamem_coherent_any(rdata->sc->parent_dtag, 2675 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK, 2676 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap, 2677 &rdata->rx_desc_paddr); 2678 if (rdata->rx_desc == NULL) { 2679 device_printf(dev, "Unable to allocate rx_desc memory\n"); 2680 return ENOMEM; 2681 } 2682 2683 rsize = __VM_CACHELINE_ALIGN( 2684 sizeof(struct emx_rxbuf) * rdata->num_rx_desc); 2685 rdata->rx_buf = kmalloc_cachealign(rsize, M_DEVBUF, M_WAITOK | M_ZERO); 2686 2687 /* 2688 * Create DMA tag for rx buffers 2689 */ 2690 error = bus_dma_tag_create(rdata->sc->parent_dtag, /* parent */ 2691 1, 0, /* alignment, bounds */ 2692 BUS_SPACE_MAXADDR, /* lowaddr */ 2693 BUS_SPACE_MAXADDR, /* highaddr */ 2694 NULL, NULL, /* filter, filterarg */ 2695 MCLBYTES, /* maxsize */ 2696 1, /* nsegments */ 2697 MCLBYTES, /* maxsegsize */ 2698 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */ 2699 &rdata->rxtag); 2700 if (error) { 2701 device_printf(dev, "Unable to allocate RX DMA tag\n"); 2702 kfree(rdata->rx_buf, M_DEVBUF); 2703 rdata->rx_buf = NULL; 2704 return error; 2705 } 2706 2707 /* 2708 * Create spare DMA map for rx buffers 2709 */ 2710 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK, 2711 &rdata->rx_sparemap); 2712 if (error) { 2713 device_printf(dev, "Unable to create spare RX DMA map\n"); 2714 bus_dma_tag_destroy(rdata->rxtag); 2715 kfree(rdata->rx_buf, M_DEVBUF); 2716 rdata->rx_buf = NULL; 2717 return error; 2718 } 2719 2720 /* 2721 * Create DMA maps for rx buffers 2722 */ 2723 for (i = 0; i < rdata->num_rx_desc; i++) { 2724 rx_buffer = &rdata->rx_buf[i]; 2725 2726 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK, 2727 &rx_buffer->map); 2728 if (error) { 2729 device_printf(dev, "Unable to create RX DMA map\n"); 2730 emx_destroy_rx_ring(rdata, i); 2731 return error; 2732 } 2733 } 2734 return (0); 2735 } 2736 2737 static void 2738 emx_free_rx_ring(struct emx_rxdata *rdata) 2739 { 2740 int i; 2741 2742 for (i = 0; i < rdata->num_rx_desc; i++) { 2743 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i]; 2744 2745 if (rx_buffer->m_head != NULL) { 2746 bus_dmamap_unload(rdata->rxtag, rx_buffer->map); 2747 m_freem(rx_buffer->m_head); 2748 rx_buffer->m_head = NULL; 2749 } 2750 } 2751 2752 if (rdata->fmp != NULL) 2753 m_freem(rdata->fmp); 2754 rdata->fmp = NULL; 2755 rdata->lmp = NULL; 2756 } 2757 2758 static void 2759 emx_free_tx_ring(struct emx_txdata *tdata) 2760 { 2761 int i; 2762 2763 for (i = 0; i < tdata->num_tx_desc; i++) { 2764 struct emx_txbuf *tx_buffer = &tdata->tx_buf[i]; 2765 2766 if (tx_buffer->m_head != NULL) { 2767 bus_dmamap_unload(tdata->txtag, tx_buffer->map); 2768 m_freem(tx_buffer->m_head); 2769 tx_buffer->m_head = NULL; 2770 } 2771 } 2772 2773 tdata->tx_flags &= ~EMX_TXFLAG_FORCECTX; 2774 2775 tdata->csum_flags = 0; 2776 tdata->csum_lhlen = 0; 2777 tdata->csum_iphlen = 0; 2778 tdata->csum_thlen = 0; 2779 tdata->csum_mss = 0; 2780 tdata->csum_pktlen = 0; 2781 2782 tdata->tx_dd_head = 0; 2783 tdata->tx_dd_tail = 0; 2784 tdata->tx_nsegs = 0; 2785 } 2786 2787 static int 2788 emx_init_rx_ring(struct emx_rxdata *rdata) 2789 { 2790 int i, error; 2791 2792 /* Reset descriptor ring */ 2793 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc); 2794 2795 /* Allocate new ones. */ 2796 for (i = 0; i < rdata->num_rx_desc; i++) { 2797 error = emx_newbuf(rdata, i, 1); 2798 if (error) 2799 return (error); 2800 } 2801 2802 /* Setup our descriptor pointers */ 2803 rdata->next_rx_desc_to_check = 0; 2804 2805 return (0); 2806 } 2807 2808 static void 2809 emx_init_rx_unit(struct emx_softc *sc) 2810 { 2811 struct ifnet *ifp = &sc->arpcom.ac_if; 2812 uint64_t bus_addr; 2813 uint32_t rctl, itr, rfctl; 2814 int i; 2815 2816 /* 2817 * Make sure receives are disabled while setting 2818 * up the descriptor ring 2819 */ 2820 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2821 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2822 2823 /* 2824 * Set the interrupt throttling rate. Value is calculated 2825 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns) 2826 */ 2827 if (sc->int_throttle_ceil) 2828 itr = 1000000000 / 256 / sc->int_throttle_ceil; 2829 else 2830 itr = 0; 2831 emx_set_itr(sc, itr); 2832 2833 /* Use extended RX descriptor */ 2834 rfctl = E1000_RFCTL_EXTEN; 2835 2836 /* Disable accelerated ackknowledge */ 2837 if (sc->hw.mac.type == e1000_82574) 2838 rfctl |= E1000_RFCTL_ACK_DIS; 2839 2840 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl); 2841 2842 /* 2843 * Receive Checksum Offload for TCP and UDP 2844 * 2845 * Checksum offloading is also enabled if multiple receive 2846 * queue is to be supported, since we need it to figure out 2847 * packet type. 2848 */ 2849 if ((ifp->if_capenable & IFCAP_RXCSUM) || 2850 sc->rx_ring_cnt > 1) { 2851 uint32_t rxcsum; 2852 2853 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM); 2854 2855 /* 2856 * NOTE: 2857 * PCSD must be enabled to enable multiple 2858 * receive queues. 2859 */ 2860 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL | 2861 E1000_RXCSUM_PCSD; 2862 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum); 2863 } 2864 2865 /* 2866 * Configure multiple receive queue (RSS) 2867 */ 2868 if (sc->rx_ring_cnt > 1) { 2869 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE]; 2870 uint32_t reta; 2871 2872 KASSERT(sc->rx_ring_cnt == EMX_NRX_RING, 2873 ("invalid number of RX ring (%d)", sc->rx_ring_cnt)); 2874 2875 /* 2876 * NOTE: 2877 * When we reach here, RSS has already been disabled 2878 * in emx_stop(), so we could safely configure RSS key 2879 * and redirect table. 2880 */ 2881 2882 /* 2883 * Configure RSS key 2884 */ 2885 toeplitz_get_key(key, sizeof(key)); 2886 for (i = 0; i < EMX_NRSSRK; ++i) { 2887 uint32_t rssrk; 2888 2889 rssrk = EMX_RSSRK_VAL(key, i); 2890 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk); 2891 2892 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk); 2893 } 2894 2895 /* 2896 * Configure RSS redirect table in following fashion: 2897 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2898 */ 2899 reta = 0; 2900 for (i = 0; i < EMX_RETA_SIZE; ++i) { 2901 uint32_t q; 2902 2903 q = (i % sc->rx_ring_cnt) << EMX_RETA_RINGIDX_SHIFT; 2904 reta |= q << (8 * i); 2905 } 2906 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta); 2907 2908 for (i = 0; i < EMX_NRETA; ++i) 2909 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta); 2910 2911 /* 2912 * Enable multiple receive queues. 2913 * Enable IPv4 RSS standard hash functions. 2914 * Disable RSS interrupt. 2915 */ 2916 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 2917 E1000_MRQC_ENABLE_RSS_2Q | 2918 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2919 E1000_MRQC_RSS_FIELD_IPV4); 2920 } 2921 2922 /* 2923 * XXX TEMPORARY WORKAROUND: on some systems with 82573 2924 * long latencies are observed, like Lenovo X60. This 2925 * change eliminates the problem, but since having positive 2926 * values in RDTR is a known source of problems on other 2927 * platforms another solution is being sought. 2928 */ 2929 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) { 2930 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573); 2931 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573); 2932 } 2933 2934 for (i = 0; i < sc->rx_ring_cnt; ++i) { 2935 struct emx_rxdata *rdata = &sc->rx_data[i]; 2936 2937 /* 2938 * Setup the Base and Length of the Rx Descriptor Ring 2939 */ 2940 bus_addr = rdata->rx_desc_paddr; 2941 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i), 2942 rdata->num_rx_desc * sizeof(emx_rxdesc_t)); 2943 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i), 2944 (uint32_t)(bus_addr >> 32)); 2945 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i), 2946 (uint32_t)bus_addr); 2947 2948 /* 2949 * Setup the HW Rx Head and Tail Descriptor Pointers 2950 */ 2951 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0); 2952 E1000_WRITE_REG(&sc->hw, E1000_RDT(i), 2953 sc->rx_data[i].num_rx_desc - 1); 2954 } 2955 2956 /* Setup the Receive Control Register */ 2957 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 2958 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 2959 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC | 2960 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 2961 2962 /* Make sure VLAN Filters are off */ 2963 rctl &= ~E1000_RCTL_VFE; 2964 2965 /* Don't store bad paket */ 2966 rctl &= ~E1000_RCTL_SBP; 2967 2968 /* MCLBYTES */ 2969 rctl |= E1000_RCTL_SZ_2048; 2970 2971 if (ifp->if_mtu > ETHERMTU) 2972 rctl |= E1000_RCTL_LPE; 2973 else 2974 rctl &= ~E1000_RCTL_LPE; 2975 2976 /* Enable Receives */ 2977 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl); 2978 } 2979 2980 static void 2981 emx_destroy_rx_ring(struct emx_rxdata *rdata, int ndesc) 2982 { 2983 struct emx_rxbuf *rx_buffer; 2984 int i; 2985 2986 /* Free Receive Descriptor ring */ 2987 if (rdata->rx_desc) { 2988 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap); 2989 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc, 2990 rdata->rx_desc_dmap); 2991 bus_dma_tag_destroy(rdata->rx_desc_dtag); 2992 2993 rdata->rx_desc = NULL; 2994 } 2995 2996 if (rdata->rx_buf == NULL) 2997 return; 2998 2999 for (i = 0; i < ndesc; i++) { 3000 rx_buffer = &rdata->rx_buf[i]; 3001 3002 KKASSERT(rx_buffer->m_head == NULL); 3003 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map); 3004 } 3005 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap); 3006 bus_dma_tag_destroy(rdata->rxtag); 3007 3008 kfree(rdata->rx_buf, M_DEVBUF); 3009 rdata->rx_buf = NULL; 3010 } 3011 3012 static void 3013 emx_rxeof(struct emx_rxdata *rdata, int count) 3014 { 3015 struct ifnet *ifp = &rdata->sc->arpcom.ac_if; 3016 uint32_t staterr; 3017 emx_rxdesc_t *current_desc; 3018 struct mbuf *mp; 3019 int i; 3020 3021 i = rdata->next_rx_desc_to_check; 3022 current_desc = &rdata->rx_desc[i]; 3023 staterr = le32toh(current_desc->rxd_staterr); 3024 3025 if (!(staterr & E1000_RXD_STAT_DD)) 3026 return; 3027 3028 while ((staterr & E1000_RXD_STAT_DD) && count != 0) { 3029 struct pktinfo *pi = NULL, pi0; 3030 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i]; 3031 struct mbuf *m = NULL; 3032 int eop, len; 3033 3034 logif(pkt_receive); 3035 3036 mp = rx_buf->m_head; 3037 3038 /* 3039 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT 3040 * needs to access the last received byte in the mbuf. 3041 */ 3042 bus_dmamap_sync(rdata->rxtag, rx_buf->map, 3043 BUS_DMASYNC_POSTREAD); 3044 3045 len = le16toh(current_desc->rxd_length); 3046 if (staterr & E1000_RXD_STAT_EOP) { 3047 count--; 3048 eop = 1; 3049 } else { 3050 eop = 0; 3051 } 3052 3053 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) { 3054 uint16_t vlan = 0; 3055 uint32_t mrq, rss_hash; 3056 3057 /* 3058 * Save several necessary information, 3059 * before emx_newbuf() destroy it. 3060 */ 3061 if ((staterr & E1000_RXD_STAT_VP) && eop) 3062 vlan = le16toh(current_desc->rxd_vlan); 3063 3064 mrq = le32toh(current_desc->rxd_mrq); 3065 rss_hash = le32toh(current_desc->rxd_rss); 3066 3067 EMX_RSS_DPRINTF(rdata->sc, 10, 3068 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n", 3069 rdata->idx, mrq, rss_hash); 3070 3071 if (emx_newbuf(rdata, i, 0) != 0) { 3072 IFNET_STAT_INC(ifp, iqdrops, 1); 3073 goto discard; 3074 } 3075 3076 /* Assign correct length to the current fragment */ 3077 mp->m_len = len; 3078 3079 if (rdata->fmp == NULL) { 3080 mp->m_pkthdr.len = len; 3081 rdata->fmp = mp; /* Store the first mbuf */ 3082 rdata->lmp = mp; 3083 } else { 3084 /* 3085 * Chain mbuf's together 3086 */ 3087 rdata->lmp->m_next = mp; 3088 rdata->lmp = rdata->lmp->m_next; 3089 rdata->fmp->m_pkthdr.len += len; 3090 } 3091 3092 if (eop) { 3093 rdata->fmp->m_pkthdr.rcvif = ifp; 3094 IFNET_STAT_INC(ifp, ipackets, 1); 3095 3096 if (ifp->if_capenable & IFCAP_RXCSUM) 3097 emx_rxcsum(staterr, rdata->fmp); 3098 3099 if (staterr & E1000_RXD_STAT_VP) { 3100 rdata->fmp->m_pkthdr.ether_vlantag = 3101 vlan; 3102 rdata->fmp->m_flags |= M_VLANTAG; 3103 } 3104 m = rdata->fmp; 3105 rdata->fmp = NULL; 3106 rdata->lmp = NULL; 3107 3108 if (ifp->if_capenable & IFCAP_RSS) { 3109 pi = emx_rssinfo(m, &pi0, mrq, 3110 rss_hash, staterr); 3111 } 3112 #ifdef EMX_RSS_DEBUG 3113 rdata->rx_pkts++; 3114 #endif 3115 } 3116 } else { 3117 IFNET_STAT_INC(ifp, ierrors, 1); 3118 discard: 3119 emx_setup_rxdesc(current_desc, rx_buf); 3120 if (rdata->fmp != NULL) { 3121 m_freem(rdata->fmp); 3122 rdata->fmp = NULL; 3123 rdata->lmp = NULL; 3124 } 3125 m = NULL; 3126 } 3127 3128 if (m != NULL) 3129 ether_input_pkt(ifp, m, pi); 3130 3131 /* Advance our pointers to the next descriptor. */ 3132 if (++i == rdata->num_rx_desc) 3133 i = 0; 3134 3135 current_desc = &rdata->rx_desc[i]; 3136 staterr = le32toh(current_desc->rxd_staterr); 3137 } 3138 rdata->next_rx_desc_to_check = i; 3139 3140 /* Advance the E1000's Receive Queue "Tail Pointer". */ 3141 if (--i < 0) 3142 i = rdata->num_rx_desc - 1; 3143 E1000_WRITE_REG(&rdata->sc->hw, E1000_RDT(rdata->idx), i); 3144 } 3145 3146 static void 3147 emx_enable_intr(struct emx_softc *sc) 3148 { 3149 uint32_t ims_mask = IMS_ENABLE_MASK; 3150 3151 lwkt_serialize_handler_enable(&sc->main_serialize); 3152 3153 #if 0 3154 if (sc->hw.mac.type == e1000_82574) { 3155 E1000_WRITE_REG(hw, EMX_EIAC, EM_MSIX_MASK); 3156 ims_mask |= EM_MSIX_MASK; 3157 } 3158 #endif 3159 E1000_WRITE_REG(&sc->hw, E1000_IMS, ims_mask); 3160 } 3161 3162 static void 3163 emx_disable_intr(struct emx_softc *sc) 3164 { 3165 if (sc->hw.mac.type == e1000_82574) 3166 E1000_WRITE_REG(&sc->hw, EMX_EIAC, 0); 3167 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff); 3168 3169 lwkt_serialize_handler_disable(&sc->main_serialize); 3170 } 3171 3172 /* 3173 * Bit of a misnomer, what this really means is 3174 * to enable OS management of the system... aka 3175 * to disable special hardware management features 3176 */ 3177 static void 3178 emx_get_mgmt(struct emx_softc *sc) 3179 { 3180 /* A shared code workaround */ 3181 if (sc->flags & EMX_FLAG_HAS_MGMT) { 3182 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H); 3183 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3184 3185 /* disable hardware interception of ARP */ 3186 manc &= ~(E1000_MANC_ARP_EN); 3187 3188 /* enable receiving management packets to the host */ 3189 manc |= E1000_MANC_EN_MNG2HOST; 3190 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3191 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3192 manc2h |= E1000_MNG2HOST_PORT_623; 3193 manc2h |= E1000_MNG2HOST_PORT_664; 3194 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h); 3195 3196 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3197 } 3198 } 3199 3200 /* 3201 * Give control back to hardware management 3202 * controller if there is one. 3203 */ 3204 static void 3205 emx_rel_mgmt(struct emx_softc *sc) 3206 { 3207 if (sc->flags & EMX_FLAG_HAS_MGMT) { 3208 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3209 3210 /* re-enable hardware interception of ARP */ 3211 manc |= E1000_MANC_ARP_EN; 3212 manc &= ~E1000_MANC_EN_MNG2HOST; 3213 3214 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3215 } 3216 } 3217 3218 /* 3219 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3220 * For ASF and Pass Through versions of f/w this means that 3221 * the driver is loaded. For AMT version (only with 82573) 3222 * of the f/w this means that the network i/f is open. 3223 */ 3224 static void 3225 emx_get_hw_control(struct emx_softc *sc) 3226 { 3227 /* Let firmware know the driver has taken over */ 3228 if (sc->hw.mac.type == e1000_82573) { 3229 uint32_t swsm; 3230 3231 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3232 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3233 swsm | E1000_SWSM_DRV_LOAD); 3234 } else { 3235 uint32_t ctrl_ext; 3236 3237 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3238 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3239 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3240 } 3241 sc->flags |= EMX_FLAG_HW_CTRL; 3242 } 3243 3244 /* 3245 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3246 * For ASF and Pass Through versions of f/w this means that the 3247 * driver is no longer loaded. For AMT version (only with 82573) 3248 * of the f/w this means that the network i/f is closed. 3249 */ 3250 static void 3251 emx_rel_hw_control(struct emx_softc *sc) 3252 { 3253 if ((sc->flags & EMX_FLAG_HW_CTRL) == 0) 3254 return; 3255 sc->flags &= ~EMX_FLAG_HW_CTRL; 3256 3257 /* Let firmware taken over control of h/w */ 3258 if (sc->hw.mac.type == e1000_82573) { 3259 uint32_t swsm; 3260 3261 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3262 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3263 swsm & ~E1000_SWSM_DRV_LOAD); 3264 } else { 3265 uint32_t ctrl_ext; 3266 3267 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3268 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3269 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3270 } 3271 } 3272 3273 static int 3274 emx_is_valid_eaddr(const uint8_t *addr) 3275 { 3276 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 }; 3277 3278 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN)) 3279 return (FALSE); 3280 3281 return (TRUE); 3282 } 3283 3284 /* 3285 * Enable PCI Wake On Lan capability 3286 */ 3287 void 3288 emx_enable_wol(device_t dev) 3289 { 3290 uint16_t cap, status; 3291 uint8_t id; 3292 3293 /* First find the capabilities pointer*/ 3294 cap = pci_read_config(dev, PCIR_CAP_PTR, 2); 3295 3296 /* Read the PM Capabilities */ 3297 id = pci_read_config(dev, cap, 1); 3298 if (id != PCIY_PMG) /* Something wrong */ 3299 return; 3300 3301 /* 3302 * OK, we have the power capabilities, 3303 * so now get the status register 3304 */ 3305 cap += PCIR_POWER_STATUS; 3306 status = pci_read_config(dev, cap, 2); 3307 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3308 pci_write_config(dev, cap, status, 2); 3309 } 3310 3311 static void 3312 emx_update_stats(struct emx_softc *sc) 3313 { 3314 struct ifnet *ifp = &sc->arpcom.ac_if; 3315 3316 if (sc->hw.phy.media_type == e1000_media_type_copper || 3317 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3318 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS); 3319 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC); 3320 } 3321 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS); 3322 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC); 3323 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC); 3324 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL); 3325 3326 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC); 3327 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL); 3328 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC); 3329 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC); 3330 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC); 3331 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC); 3332 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC); 3333 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC); 3334 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC); 3335 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC); 3336 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64); 3337 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127); 3338 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255); 3339 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511); 3340 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023); 3341 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522); 3342 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC); 3343 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC); 3344 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC); 3345 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC); 3346 3347 /* For the 64-bit byte counters the low dword must be read first. */ 3348 /* Both registers clear on the read of the high dword */ 3349 3350 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH); 3351 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH); 3352 3353 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC); 3354 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC); 3355 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC); 3356 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC); 3357 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC); 3358 3359 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH); 3360 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH); 3361 3362 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR); 3363 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT); 3364 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64); 3365 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127); 3366 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255); 3367 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511); 3368 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023); 3369 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522); 3370 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC); 3371 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC); 3372 3373 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC); 3374 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC); 3375 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS); 3376 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR); 3377 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC); 3378 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC); 3379 3380 IFNET_STAT_SET(ifp, collisions, sc->stats.colc); 3381 3382 /* Rx Errors */ 3383 IFNET_STAT_SET(ifp, ierrors, 3384 sc->stats.rxerrc + sc->stats.crcerrs + sc->stats.algnerrc + 3385 sc->stats.ruc + sc->stats.roc + sc->stats.mpc + sc->stats.cexterr); 3386 3387 /* Tx Errors */ 3388 IFNET_STAT_SET(ifp, oerrors, sc->stats.ecol + sc->stats.latecol); 3389 } 3390 3391 static void 3392 emx_print_debug_info(struct emx_softc *sc) 3393 { 3394 device_t dev = sc->dev; 3395 uint8_t *hw_addr = sc->hw.hw_addr; 3396 int i; 3397 3398 device_printf(dev, "Adapter hardware address = %p \n", hw_addr); 3399 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n", 3400 E1000_READ_REG(&sc->hw, E1000_CTRL), 3401 E1000_READ_REG(&sc->hw, E1000_RCTL)); 3402 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n", 3403 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\ 3404 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) ); 3405 device_printf(dev, "Flow control watermarks high = %d low = %d\n", 3406 sc->hw.fc.high_water, sc->hw.fc.low_water); 3407 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n", 3408 E1000_READ_REG(&sc->hw, E1000_TIDV), 3409 E1000_READ_REG(&sc->hw, E1000_TADV)); 3410 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n", 3411 E1000_READ_REG(&sc->hw, E1000_RDTR), 3412 E1000_READ_REG(&sc->hw, E1000_RADV)); 3413 3414 for (i = 0; i < sc->tx_ring_cnt; ++i) { 3415 device_printf(dev, "hw %d tdh = %d, hw tdt = %d\n", i, 3416 E1000_READ_REG(&sc->hw, E1000_TDH(i)), 3417 E1000_READ_REG(&sc->hw, E1000_TDT(i))); 3418 } 3419 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3420 device_printf(dev, "hw %d rdh = %d, hw rdt = %d\n", i, 3421 E1000_READ_REG(&sc->hw, E1000_RDH(i)), 3422 E1000_READ_REG(&sc->hw, E1000_RDT(i))); 3423 } 3424 3425 for (i = 0; i < sc->tx_ring_cnt; ++i) { 3426 device_printf(dev, "TX %d Tx descriptors avail = %d\n", i, 3427 sc->tx_data[i].num_tx_desc_avail); 3428 device_printf(dev, "TX %d TSO segments = %lu\n", i, 3429 sc->tx_data[i].tso_segments); 3430 device_printf(dev, "TX %d TSO ctx reused = %lu\n", i, 3431 sc->tx_data[i].tso_ctx_reused); 3432 } 3433 } 3434 3435 static void 3436 emx_print_hw_stats(struct emx_softc *sc) 3437 { 3438 device_t dev = sc->dev; 3439 3440 device_printf(dev, "Excessive collisions = %lld\n", 3441 (long long)sc->stats.ecol); 3442 #if (DEBUG_HW > 0) /* Dont output these errors normally */ 3443 device_printf(dev, "Symbol errors = %lld\n", 3444 (long long)sc->stats.symerrs); 3445 #endif 3446 device_printf(dev, "Sequence errors = %lld\n", 3447 (long long)sc->stats.sec); 3448 device_printf(dev, "Defer count = %lld\n", 3449 (long long)sc->stats.dc); 3450 device_printf(dev, "Missed Packets = %lld\n", 3451 (long long)sc->stats.mpc); 3452 device_printf(dev, "Receive No Buffers = %lld\n", 3453 (long long)sc->stats.rnbc); 3454 /* RLEC is inaccurate on some hardware, calculate our own. */ 3455 device_printf(dev, "Receive Length Errors = %lld\n", 3456 ((long long)sc->stats.roc + (long long)sc->stats.ruc)); 3457 device_printf(dev, "Receive errors = %lld\n", 3458 (long long)sc->stats.rxerrc); 3459 device_printf(dev, "Crc errors = %lld\n", 3460 (long long)sc->stats.crcerrs); 3461 device_printf(dev, "Alignment errors = %lld\n", 3462 (long long)sc->stats.algnerrc); 3463 device_printf(dev, "Collision/Carrier extension errors = %lld\n", 3464 (long long)sc->stats.cexterr); 3465 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns); 3466 device_printf(dev, "XON Rcvd = %lld\n", 3467 (long long)sc->stats.xonrxc); 3468 device_printf(dev, "XON Xmtd = %lld\n", 3469 (long long)sc->stats.xontxc); 3470 device_printf(dev, "XOFF Rcvd = %lld\n", 3471 (long long)sc->stats.xoffrxc); 3472 device_printf(dev, "XOFF Xmtd = %lld\n", 3473 (long long)sc->stats.xofftxc); 3474 device_printf(dev, "Good Packets Rcvd = %lld\n", 3475 (long long)sc->stats.gprc); 3476 device_printf(dev, "Good Packets Xmtd = %lld\n", 3477 (long long)sc->stats.gptc); 3478 } 3479 3480 static void 3481 emx_print_nvm_info(struct emx_softc *sc) 3482 { 3483 uint16_t eeprom_data; 3484 int i, j, row = 0; 3485 3486 /* Its a bit crude, but it gets the job done */ 3487 kprintf("\nInterface EEPROM Dump:\n"); 3488 kprintf("Offset\n0x0000 "); 3489 for (i = 0, j = 0; i < 32; i++, j++) { 3490 if (j == 8) { /* Make the offset block */ 3491 j = 0; ++row; 3492 kprintf("\n0x00%x0 ",row); 3493 } 3494 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data); 3495 kprintf("%04x ", eeprom_data); 3496 } 3497 kprintf("\n"); 3498 } 3499 3500 static int 3501 emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 3502 { 3503 struct emx_softc *sc; 3504 struct ifnet *ifp; 3505 int error, result; 3506 3507 result = -1; 3508 error = sysctl_handle_int(oidp, &result, 0, req); 3509 if (error || !req->newptr) 3510 return (error); 3511 3512 sc = (struct emx_softc *)arg1; 3513 ifp = &sc->arpcom.ac_if; 3514 3515 ifnet_serialize_all(ifp); 3516 3517 if (result == 1) 3518 emx_print_debug_info(sc); 3519 3520 /* 3521 * This value will cause a hex dump of the 3522 * first 32 16-bit words of the EEPROM to 3523 * the screen. 3524 */ 3525 if (result == 2) 3526 emx_print_nvm_info(sc); 3527 3528 ifnet_deserialize_all(ifp); 3529 3530 return (error); 3531 } 3532 3533 static int 3534 emx_sysctl_stats(SYSCTL_HANDLER_ARGS) 3535 { 3536 int error, result; 3537 3538 result = -1; 3539 error = sysctl_handle_int(oidp, &result, 0, req); 3540 if (error || !req->newptr) 3541 return (error); 3542 3543 if (result == 1) { 3544 struct emx_softc *sc = (struct emx_softc *)arg1; 3545 struct ifnet *ifp = &sc->arpcom.ac_if; 3546 3547 ifnet_serialize_all(ifp); 3548 emx_print_hw_stats(sc); 3549 ifnet_deserialize_all(ifp); 3550 } 3551 return (error); 3552 } 3553 3554 static void 3555 emx_add_sysctl(struct emx_softc *sc) 3556 { 3557 #if defined(EMX_RSS_DEBUG) || defined(EMX_TSS_DEBUG) 3558 char pkt_desc[32]; 3559 int i; 3560 #endif 3561 3562 sysctl_ctx_init(&sc->sysctl_ctx); 3563 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 3564 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 3565 device_get_nameunit(sc->dev), 3566 CTLFLAG_RD, 0, ""); 3567 if (sc->sysctl_tree == NULL) { 3568 device_printf(sc->dev, "can't add sysctl node\n"); 3569 return; 3570 } 3571 3572 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3573 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 3574 emx_sysctl_debug_info, "I", "Debug Information"); 3575 3576 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3577 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 3578 emx_sysctl_stats, "I", "Statistics"); 3579 3580 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3581 OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_data[0].num_rx_desc, 0, 3582 "# of RX descs"); 3583 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3584 OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_data[0].num_tx_desc, 0, 3585 "# of TX descs"); 3586 3587 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3588 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 3589 emx_sysctl_int_throttle, "I", "interrupt throttling rate"); 3590 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3591 OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 3592 emx_sysctl_tx_intr_nsegs, "I", "# segments per TX interrupt"); 3593 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3594 OID_AUTO, "tx_wreg_nsegs", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 3595 emx_sysctl_tx_wreg_nsegs, "I", 3596 "# segments sent before write to hardware register"); 3597 3598 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3599 OID_AUTO, "rx_ring_cnt", CTLFLAG_RD, &sc->rx_ring_cnt, 0, 3600 "# of RX rings"); 3601 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3602 OID_AUTO, "tx_ring_cnt", CTLFLAG_RD, &sc->tx_ring_cnt, 0, 3603 "# of TX rings"); 3604 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3605 OID_AUTO, "tx_ring_inuse", CTLFLAG_RD, &sc->tx_ring_inuse, 0, 3606 "# of TX rings used"); 3607 3608 #ifdef IFPOLL_ENABLE 3609 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3610 OID_AUTO, "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW, 3611 sc, 0, emx_sysctl_npoll_rxoff, "I", 3612 "NPOLLING RX cpu offset"); 3613 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3614 OID_AUTO, "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW, 3615 sc, 0, emx_sysctl_npoll_txoff, "I", 3616 "NPOLLING TX cpu offset"); 3617 #endif 3618 3619 #ifdef EMX_RSS_DEBUG 3620 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3621 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 3622 0, "RSS debug level"); 3623 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3624 ksnprintf(pkt_desc, sizeof(pkt_desc), "rx%d_pkt", i); 3625 SYSCTL_ADD_ULONG(&sc->sysctl_ctx, 3626 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, 3627 pkt_desc, CTLFLAG_RW, &sc->rx_data[i].rx_pkts, 3628 "RXed packets"); 3629 } 3630 #endif 3631 #ifdef EMX_TSS_DEBUG 3632 for (i = 0; i < sc->tx_ring_cnt; ++i) { 3633 ksnprintf(pkt_desc, sizeof(pkt_desc), "tx%d_pkt", i); 3634 SYSCTL_ADD_ULONG(&sc->sysctl_ctx, 3635 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, 3636 pkt_desc, CTLFLAG_RW, &sc->tx_data[i].tx_pkts, 3637 "TXed packets"); 3638 } 3639 #endif 3640 } 3641 3642 static int 3643 emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS) 3644 { 3645 struct emx_softc *sc = (void *)arg1; 3646 struct ifnet *ifp = &sc->arpcom.ac_if; 3647 int error, throttle; 3648 3649 throttle = sc->int_throttle_ceil; 3650 error = sysctl_handle_int(oidp, &throttle, 0, req); 3651 if (error || req->newptr == NULL) 3652 return error; 3653 if (throttle < 0 || throttle > 1000000000 / 256) 3654 return EINVAL; 3655 3656 if (throttle) { 3657 /* 3658 * Set the interrupt throttling rate in 256ns increments, 3659 * recalculate sysctl value assignment to get exact frequency. 3660 */ 3661 throttle = 1000000000 / 256 / throttle; 3662 3663 /* Upper 16bits of ITR is reserved and should be zero */ 3664 if (throttle & 0xffff0000) 3665 return EINVAL; 3666 } 3667 3668 ifnet_serialize_all(ifp); 3669 3670 if (throttle) 3671 sc->int_throttle_ceil = 1000000000 / 256 / throttle; 3672 else 3673 sc->int_throttle_ceil = 0; 3674 3675 if (ifp->if_flags & IFF_RUNNING) 3676 emx_set_itr(sc, throttle); 3677 3678 ifnet_deserialize_all(ifp); 3679 3680 if (bootverbose) { 3681 if_printf(ifp, "Interrupt moderation set to %d/sec\n", 3682 sc->int_throttle_ceil); 3683 } 3684 return 0; 3685 } 3686 3687 static int 3688 emx_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS) 3689 { 3690 struct emx_softc *sc = (void *)arg1; 3691 struct ifnet *ifp = &sc->arpcom.ac_if; 3692 struct emx_txdata *tdata = &sc->tx_data[0]; 3693 int error, segs; 3694 3695 segs = tdata->tx_intr_nsegs; 3696 error = sysctl_handle_int(oidp, &segs, 0, req); 3697 if (error || req->newptr == NULL) 3698 return error; 3699 if (segs <= 0) 3700 return EINVAL; 3701 3702 ifnet_serialize_all(ifp); 3703 3704 /* 3705 * Don't allow tx_intr_nsegs to become: 3706 * o Less the oact_tx_desc 3707 * o Too large that no TX desc will cause TX interrupt to 3708 * be generated (OACTIVE will never recover) 3709 * o Too small that will cause tx_dd[] overflow 3710 */ 3711 if (segs < tdata->oact_tx_desc || 3712 segs >= tdata->num_tx_desc - tdata->oact_tx_desc || 3713 segs < tdata->num_tx_desc / EMX_TXDD_SAFE) { 3714 error = EINVAL; 3715 } else { 3716 int i; 3717 3718 error = 0; 3719 for (i = 0; i < sc->tx_ring_cnt; ++i) 3720 sc->tx_data[i].tx_intr_nsegs = segs; 3721 } 3722 3723 ifnet_deserialize_all(ifp); 3724 3725 return error; 3726 } 3727 3728 static int 3729 emx_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS) 3730 { 3731 struct emx_softc *sc = (void *)arg1; 3732 struct ifnet *ifp = &sc->arpcom.ac_if; 3733 int error, nsegs, i; 3734 3735 nsegs = sc->tx_data[0].tx_wreg_nsegs; 3736 error = sysctl_handle_int(oidp, &nsegs, 0, req); 3737 if (error || req->newptr == NULL) 3738 return error; 3739 3740 ifnet_serialize_all(ifp); 3741 for (i = 0; i < sc->tx_ring_cnt; ++i) 3742 sc->tx_data[i].tx_wreg_nsegs =nsegs; 3743 ifnet_deserialize_all(ifp); 3744 3745 return 0; 3746 } 3747 3748 #ifdef IFPOLL_ENABLE 3749 3750 static int 3751 emx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS) 3752 { 3753 struct emx_softc *sc = (void *)arg1; 3754 struct ifnet *ifp = &sc->arpcom.ac_if; 3755 int error, off; 3756 3757 off = sc->rx_npoll_off; 3758 error = sysctl_handle_int(oidp, &off, 0, req); 3759 if (error || req->newptr == NULL) 3760 return error; 3761 if (off < 0) 3762 return EINVAL; 3763 3764 ifnet_serialize_all(ifp); 3765 if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) { 3766 error = EINVAL; 3767 } else { 3768 error = 0; 3769 sc->rx_npoll_off = off; 3770 } 3771 ifnet_deserialize_all(ifp); 3772 3773 return error; 3774 } 3775 3776 static int 3777 emx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS) 3778 { 3779 struct emx_softc *sc = (void *)arg1; 3780 struct ifnet *ifp = &sc->arpcom.ac_if; 3781 int error, off; 3782 3783 off = sc->tx_npoll_off; 3784 error = sysctl_handle_int(oidp, &off, 0, req); 3785 if (error || req->newptr == NULL) 3786 return error; 3787 if (off < 0) 3788 return EINVAL; 3789 3790 ifnet_serialize_all(ifp); 3791 if (off >= ncpus2 || off % sc->tx_ring_cnt != 0) { 3792 error = EINVAL; 3793 } else { 3794 error = 0; 3795 sc->tx_npoll_off = off; 3796 } 3797 ifnet_deserialize_all(ifp); 3798 3799 return error; 3800 } 3801 3802 #endif /* IFPOLL_ENABLE */ 3803 3804 static int 3805 emx_dma_alloc(struct emx_softc *sc) 3806 { 3807 int error, i; 3808 3809 /* 3810 * Create top level busdma tag 3811 */ 3812 error = bus_dma_tag_create(NULL, 1, 0, 3813 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 3814 NULL, NULL, 3815 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 3816 0, &sc->parent_dtag); 3817 if (error) { 3818 device_printf(sc->dev, "could not create top level DMA tag\n"); 3819 return error; 3820 } 3821 3822 /* 3823 * Allocate transmit descriptors ring and buffers 3824 */ 3825 for (i = 0; i < sc->tx_ring_cnt; ++i) { 3826 error = emx_create_tx_ring(&sc->tx_data[i]); 3827 if (error) { 3828 device_printf(sc->dev, 3829 "Could not setup transmit structures\n"); 3830 return error; 3831 } 3832 } 3833 3834 /* 3835 * Allocate receive descriptors ring and buffers 3836 */ 3837 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3838 error = emx_create_rx_ring(&sc->rx_data[i]); 3839 if (error) { 3840 device_printf(sc->dev, 3841 "Could not setup receive structures\n"); 3842 return error; 3843 } 3844 } 3845 return 0; 3846 } 3847 3848 static void 3849 emx_dma_free(struct emx_softc *sc) 3850 { 3851 int i; 3852 3853 for (i = 0; i < sc->tx_ring_cnt; ++i) { 3854 emx_destroy_tx_ring(&sc->tx_data[i], 3855 sc->tx_data[i].num_tx_desc); 3856 } 3857 3858 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3859 emx_destroy_rx_ring(&sc->rx_data[i], 3860 sc->rx_data[i].num_rx_desc); 3861 } 3862 3863 /* Free top level busdma tag */ 3864 if (sc->parent_dtag != NULL) 3865 bus_dma_tag_destroy(sc->parent_dtag); 3866 } 3867 3868 static void 3869 emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz) 3870 { 3871 struct emx_softc *sc = ifp->if_softc; 3872 3873 ifnet_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, slz); 3874 } 3875 3876 static void 3877 emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz) 3878 { 3879 struct emx_softc *sc = ifp->if_softc; 3880 3881 ifnet_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, slz); 3882 } 3883 3884 static int 3885 emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz) 3886 { 3887 struct emx_softc *sc = ifp->if_softc; 3888 3889 return ifnet_serialize_array_try(sc->serializes, EMX_NSERIALIZE, slz); 3890 } 3891 3892 static void 3893 emx_serialize_skipmain(struct emx_softc *sc) 3894 { 3895 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1); 3896 } 3897 3898 static void 3899 emx_deserialize_skipmain(struct emx_softc *sc) 3900 { 3901 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1); 3902 } 3903 3904 #ifdef INVARIANTS 3905 3906 static void 3907 emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz, 3908 boolean_t serialized) 3909 { 3910 struct emx_softc *sc = ifp->if_softc; 3911 3912 ifnet_serialize_array_assert(sc->serializes, EMX_NSERIALIZE, 3913 slz, serialized); 3914 } 3915 3916 #endif /* INVARIANTS */ 3917 3918 #ifdef IFPOLL_ENABLE 3919 3920 static void 3921 emx_npoll_status(struct ifnet *ifp) 3922 { 3923 struct emx_softc *sc = ifp->if_softc; 3924 uint32_t reg_icr; 3925 3926 ASSERT_SERIALIZED(&sc->main_serialize); 3927 3928 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 3929 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 3930 callout_stop(&sc->timer); 3931 sc->hw.mac.get_link_status = 1; 3932 emx_update_link_status(sc); 3933 callout_reset(&sc->timer, hz, emx_timer, sc); 3934 } 3935 } 3936 3937 static void 3938 emx_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused) 3939 { 3940 struct emx_txdata *tdata = arg; 3941 3942 ASSERT_SERIALIZED(&tdata->tx_serialize); 3943 3944 emx_txeof(tdata); 3945 if (!ifsq_is_empty(tdata->ifsq)) 3946 ifsq_devstart(tdata->ifsq); 3947 } 3948 3949 static void 3950 emx_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle) 3951 { 3952 struct emx_rxdata *rdata = arg; 3953 3954 ASSERT_SERIALIZED(&rdata->rx_serialize); 3955 3956 emx_rxeof(rdata, cycle); 3957 } 3958 3959 static void 3960 emx_npoll(struct ifnet *ifp, struct ifpoll_info *info) 3961 { 3962 struct emx_softc *sc = ifp->if_softc; 3963 int i, txr_cnt; 3964 3965 ASSERT_IFNET_SERIALIZED_ALL(ifp); 3966 3967 if (info) { 3968 int off; 3969 3970 info->ifpi_status.status_func = emx_npoll_status; 3971 info->ifpi_status.serializer = &sc->main_serialize; 3972 3973 txr_cnt = emx_get_txring_inuse(sc, TRUE); 3974 off = sc->tx_npoll_off; 3975 for (i = 0; i < txr_cnt; ++i) { 3976 struct emx_txdata *tdata = &sc->tx_data[i]; 3977 int idx = i + off; 3978 3979 KKASSERT(idx < ncpus2); 3980 info->ifpi_tx[idx].poll_func = emx_npoll_tx; 3981 info->ifpi_tx[idx].arg = tdata; 3982 info->ifpi_tx[idx].serializer = &tdata->tx_serialize; 3983 ifsq_set_cpuid(tdata->ifsq, idx); 3984 } 3985 3986 off = sc->rx_npoll_off; 3987 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3988 struct emx_rxdata *rdata = &sc->rx_data[i]; 3989 int idx = i + off; 3990 3991 KKASSERT(idx < ncpus2); 3992 info->ifpi_rx[idx].poll_func = emx_npoll_rx; 3993 info->ifpi_rx[idx].arg = rdata; 3994 info->ifpi_rx[idx].serializer = &rdata->rx_serialize; 3995 } 3996 3997 if (ifp->if_flags & IFF_RUNNING) { 3998 if (txr_cnt == sc->tx_ring_inuse) 3999 emx_disable_intr(sc); 4000 else 4001 emx_init(sc); 4002 } 4003 } else { 4004 for (i = 0; i < sc->tx_ring_cnt; ++i) { 4005 struct emx_txdata *tdata = &sc->tx_data[i]; 4006 4007 ifsq_set_cpuid(tdata->ifsq, 4008 rman_get_cpuid(sc->intr_res)); 4009 } 4010 4011 if (ifp->if_flags & IFF_RUNNING) { 4012 txr_cnt = emx_get_txring_inuse(sc, FALSE); 4013 if (txr_cnt == sc->tx_ring_inuse) 4014 emx_enable_intr(sc); 4015 else 4016 emx_init(sc); 4017 } 4018 } 4019 } 4020 4021 #endif /* IFPOLL_ENABLE */ 4022 4023 static void 4024 emx_set_itr(struct emx_softc *sc, uint32_t itr) 4025 { 4026 E1000_WRITE_REG(&sc->hw, E1000_ITR, itr); 4027 if (sc->hw.mac.type == e1000_82574) { 4028 int i; 4029 4030 /* 4031 * When using MSIX interrupts we need to 4032 * throttle using the EITR register 4033 */ 4034 for (i = 0; i < 4; ++i) 4035 E1000_WRITE_REG(&sc->hw, E1000_EITR_82574(i), itr); 4036 } 4037 } 4038 4039 /* 4040 * Disable the L0s, 82574L Errata #20 4041 */ 4042 static void 4043 emx_disable_aspm(struct emx_softc *sc) 4044 { 4045 uint16_t link_cap, link_ctrl, disable; 4046 uint8_t pcie_ptr, reg; 4047 device_t dev = sc->dev; 4048 4049 switch (sc->hw.mac.type) { 4050 case e1000_82571: 4051 case e1000_82572: 4052 case e1000_82573: 4053 /* 4054 * 82573 specification update 4055 * errata #8 disable L0s 4056 * errata #41 disable L1 4057 * 4058 * 82571/82572 specification update 4059 # errata #13 disable L1 4060 * errata #68 disable L0s 4061 */ 4062 disable = PCIEM_LNKCTL_ASPM_L0S | PCIEM_LNKCTL_ASPM_L1; 4063 break; 4064 4065 case e1000_82574: 4066 /* 4067 * 82574 specification update errata #20 4068 * 4069 * There is no need to disable L1 4070 */ 4071 disable = PCIEM_LNKCTL_ASPM_L0S; 4072 break; 4073 4074 default: 4075 return; 4076 } 4077 4078 pcie_ptr = pci_get_pciecap_ptr(dev); 4079 if (pcie_ptr == 0) 4080 return; 4081 4082 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2); 4083 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0) 4084 return; 4085 4086 if (bootverbose) 4087 if_printf(&sc->arpcom.ac_if, "disable ASPM %#02x\n", disable); 4088 4089 reg = pcie_ptr + PCIER_LINKCTRL; 4090 link_ctrl = pci_read_config(dev, reg, 2); 4091 link_ctrl &= ~disable; 4092 pci_write_config(dev, reg, link_ctrl, 2); 4093 } 4094 4095 static int 4096 emx_tso_pullup(struct emx_txdata *tdata, struct mbuf **mp) 4097 { 4098 int iphlen, hoff, thoff, ex = 0; 4099 struct mbuf *m; 4100 struct ip *ip; 4101 4102 m = *mp; 4103 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable")); 4104 4105 iphlen = m->m_pkthdr.csum_iphlen; 4106 thoff = m->m_pkthdr.csum_thlen; 4107 hoff = m->m_pkthdr.csum_lhlen; 4108 4109 KASSERT(iphlen > 0, ("invalid ip hlen")); 4110 KASSERT(thoff > 0, ("invalid tcp hlen")); 4111 KASSERT(hoff > 0, ("invalid ether hlen")); 4112 4113 if (tdata->tx_flags & EMX_TXFLAG_TSO_PULLEX) 4114 ex = 4; 4115 4116 if (m->m_len < hoff + iphlen + thoff + ex) { 4117 m = m_pullup(m, hoff + iphlen + thoff + ex); 4118 if (m == NULL) { 4119 *mp = NULL; 4120 return ENOBUFS; 4121 } 4122 *mp = m; 4123 } 4124 ip = mtodoff(m, struct ip *, hoff); 4125 ip->ip_len = 0; 4126 4127 return 0; 4128 } 4129 4130 static int 4131 emx_tso_setup(struct emx_txdata *tdata, struct mbuf *mp, 4132 uint32_t *txd_upper, uint32_t *txd_lower) 4133 { 4134 struct e1000_context_desc *TXD; 4135 int hoff, iphlen, thoff, hlen; 4136 int mss, pktlen, curr_txd; 4137 4138 #ifdef EMX_TSO_DEBUG 4139 tdata->tso_segments++; 4140 #endif 4141 4142 iphlen = mp->m_pkthdr.csum_iphlen; 4143 thoff = mp->m_pkthdr.csum_thlen; 4144 hoff = mp->m_pkthdr.csum_lhlen; 4145 mss = mp->m_pkthdr.tso_segsz; 4146 pktlen = mp->m_pkthdr.len; 4147 4148 if ((tdata->tx_flags & EMX_TXFLAG_FORCECTX) == 0 && 4149 tdata->csum_flags == CSUM_TSO && 4150 tdata->csum_iphlen == iphlen && 4151 tdata->csum_lhlen == hoff && 4152 tdata->csum_thlen == thoff && 4153 tdata->csum_mss == mss && 4154 tdata->csum_pktlen == pktlen) { 4155 *txd_upper = tdata->csum_txd_upper; 4156 *txd_lower = tdata->csum_txd_lower; 4157 #ifdef EMX_TSO_DEBUG 4158 tdata->tso_ctx_reused++; 4159 #endif 4160 return 0; 4161 } 4162 hlen = hoff + iphlen + thoff; 4163 4164 /* 4165 * Setup a new TSO context. 4166 */ 4167 4168 curr_txd = tdata->next_avail_tx_desc; 4169 TXD = (struct e1000_context_desc *)&tdata->tx_desc_base[curr_txd]; 4170 4171 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */ 4172 E1000_TXD_DTYP_D | /* Data descr type */ 4173 E1000_TXD_CMD_TSE; /* Do TSE on this packet */ 4174 4175 /* IP and/or TCP header checksum calculation and insertion. */ 4176 *txd_upper = (E1000_TXD_POPTS_IXSM | E1000_TXD_POPTS_TXSM) << 8; 4177 4178 /* 4179 * Start offset for header checksum calculation. 4180 * End offset for header checksum calculation. 4181 * Offset of place put the checksum. 4182 */ 4183 TXD->lower_setup.ip_fields.ipcss = hoff; 4184 TXD->lower_setup.ip_fields.ipcse = htole16(hoff + iphlen - 1); 4185 TXD->lower_setup.ip_fields.ipcso = hoff + offsetof(struct ip, ip_sum); 4186 4187 /* 4188 * Start offset for payload checksum calculation. 4189 * End offset for payload checksum calculation. 4190 * Offset of place to put the checksum. 4191 */ 4192 TXD->upper_setup.tcp_fields.tucss = hoff + iphlen; 4193 TXD->upper_setup.tcp_fields.tucse = 0; 4194 TXD->upper_setup.tcp_fields.tucso = 4195 hoff + iphlen + offsetof(struct tcphdr, th_sum); 4196 4197 /* 4198 * Payload size per packet w/o any headers. 4199 * Length of all headers up to payload. 4200 */ 4201 TXD->tcp_seg_setup.fields.mss = htole16(mss); 4202 TXD->tcp_seg_setup.fields.hdr_len = hlen; 4203 TXD->cmd_and_length = htole32(E1000_TXD_CMD_IFCS | 4204 E1000_TXD_CMD_DEXT | /* Extended descr */ 4205 E1000_TXD_CMD_TSE | /* TSE context */ 4206 E1000_TXD_CMD_IP | /* Do IP csum */ 4207 E1000_TXD_CMD_TCP | /* Do TCP checksum */ 4208 (pktlen - hlen)); /* Total len */ 4209 4210 /* Save the information for this TSO context */ 4211 tdata->csum_flags = CSUM_TSO; 4212 tdata->csum_lhlen = hoff; 4213 tdata->csum_iphlen = iphlen; 4214 tdata->csum_thlen = thoff; 4215 tdata->csum_mss = mss; 4216 tdata->csum_pktlen = pktlen; 4217 tdata->csum_txd_upper = *txd_upper; 4218 tdata->csum_txd_lower = *txd_lower; 4219 4220 if (++curr_txd == tdata->num_tx_desc) 4221 curr_txd = 0; 4222 4223 KKASSERT(tdata->num_tx_desc_avail > 0); 4224 tdata->num_tx_desc_avail--; 4225 4226 tdata->next_avail_tx_desc = curr_txd; 4227 return 1; 4228 } 4229 4230 static int 4231 emx_get_txring_inuse(const struct emx_softc *sc, boolean_t polling) 4232 { 4233 if (polling) 4234 return sc->tx_ring_cnt; 4235 else 4236 return 1; 4237 } 4238