1 /* 2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved. 3 * 4 * Copyright (c) 2001-2008, Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * 34 * Copyright (c) 2005 The DragonFly Project. All rights reserved. 35 * 36 * This code is derived from software contributed to The DragonFly Project 37 * by Matthew Dillon <dillon@backplane.com> 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in 47 * the documentation and/or other materials provided with the 48 * distribution. 49 * 3. Neither the name of The DragonFly Project nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific, prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 */ 66 67 #include "opt_ifpoll.h" 68 #include "opt_rss.h" 69 #include "opt_emx.h" 70 71 #include <sys/param.h> 72 #include <sys/bus.h> 73 #include <sys/endian.h> 74 #include <sys/interrupt.h> 75 #include <sys/kernel.h> 76 #include <sys/ktr.h> 77 #include <sys/malloc.h> 78 #include <sys/mbuf.h> 79 #include <sys/proc.h> 80 #include <sys/rman.h> 81 #include <sys/serialize.h> 82 #include <sys/serialize2.h> 83 #include <sys/socket.h> 84 #include <sys/sockio.h> 85 #include <sys/sysctl.h> 86 #include <sys/systm.h> 87 88 #include <net/bpf.h> 89 #include <net/ethernet.h> 90 #include <net/if.h> 91 #include <net/if_arp.h> 92 #include <net/if_dl.h> 93 #include <net/if_media.h> 94 #include <net/ifq_var.h> 95 #include <net/toeplitz.h> 96 #include <net/toeplitz2.h> 97 #include <net/vlan/if_vlan_var.h> 98 #include <net/vlan/if_vlan_ether.h> 99 #include <net/if_poll.h> 100 101 #include <netinet/in_systm.h> 102 #include <netinet/in.h> 103 #include <netinet/ip.h> 104 #include <netinet/tcp.h> 105 #include <netinet/udp.h> 106 107 #include <bus/pci/pcivar.h> 108 #include <bus/pci/pcireg.h> 109 110 #include <dev/netif/ig_hal/e1000_api.h> 111 #include <dev/netif/ig_hal/e1000_82571.h> 112 #include <dev/netif/emx/if_emx.h> 113 114 #ifdef EMX_RSS_DEBUG 115 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \ 116 do { \ 117 if (sc->rss_debug >= lvl) \ 118 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \ 119 } while (0) 120 #else /* !EMX_RSS_DEBUG */ 121 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0) 122 #endif /* EMX_RSS_DEBUG */ 123 124 #define EMX_NAME "Intel(R) PRO/1000 " 125 126 #define EMX_DEVICE(id) \ 127 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id } 128 #define EMX_DEVICE_NULL { 0, 0, NULL } 129 130 static const struct emx_device { 131 uint16_t vid; 132 uint16_t did; 133 const char *desc; 134 } emx_devices[] = { 135 EMX_DEVICE(82571EB_COPPER), 136 EMX_DEVICE(82571EB_FIBER), 137 EMX_DEVICE(82571EB_SERDES), 138 EMX_DEVICE(82571EB_SERDES_DUAL), 139 EMX_DEVICE(82571EB_SERDES_QUAD), 140 EMX_DEVICE(82571EB_QUAD_COPPER), 141 EMX_DEVICE(82571EB_QUAD_COPPER_BP), 142 EMX_DEVICE(82571EB_QUAD_COPPER_LP), 143 EMX_DEVICE(82571EB_QUAD_FIBER), 144 EMX_DEVICE(82571PT_QUAD_COPPER), 145 146 EMX_DEVICE(82572EI_COPPER), 147 EMX_DEVICE(82572EI_FIBER), 148 EMX_DEVICE(82572EI_SERDES), 149 EMX_DEVICE(82572EI), 150 151 EMX_DEVICE(82573E), 152 EMX_DEVICE(82573E_IAMT), 153 EMX_DEVICE(82573L), 154 155 EMX_DEVICE(80003ES2LAN_COPPER_SPT), 156 EMX_DEVICE(80003ES2LAN_SERDES_SPT), 157 EMX_DEVICE(80003ES2LAN_COPPER_DPT), 158 EMX_DEVICE(80003ES2LAN_SERDES_DPT), 159 160 EMX_DEVICE(82574L), 161 EMX_DEVICE(82574LA), 162 163 /* required last entry */ 164 EMX_DEVICE_NULL 165 }; 166 167 static int emx_probe(device_t); 168 static int emx_attach(device_t); 169 static int emx_detach(device_t); 170 static int emx_shutdown(device_t); 171 static int emx_suspend(device_t); 172 static int emx_resume(device_t); 173 174 static void emx_init(void *); 175 static void emx_stop(struct emx_softc *); 176 static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 177 static void emx_start(struct ifnet *); 178 #ifdef IFPOLL_ENABLE 179 static void emx_qpoll(struct ifnet *, struct ifpoll_info *); 180 #endif 181 static void emx_watchdog(struct ifnet *); 182 static void emx_media_status(struct ifnet *, struct ifmediareq *); 183 static int emx_media_change(struct ifnet *); 184 static void emx_timer(void *); 185 static void emx_serialize(struct ifnet *, enum ifnet_serialize); 186 static void emx_deserialize(struct ifnet *, enum ifnet_serialize); 187 static int emx_tryserialize(struct ifnet *, enum ifnet_serialize); 188 #ifdef INVARIANTS 189 static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize, 190 boolean_t); 191 #endif 192 193 static void emx_intr(void *); 194 static void emx_rxeof(struct emx_softc *, int, int); 195 static void emx_txeof(struct emx_softc *); 196 static void emx_tx_collect(struct emx_softc *); 197 static void emx_tx_purge(struct emx_softc *); 198 static void emx_enable_intr(struct emx_softc *); 199 static void emx_disable_intr(struct emx_softc *); 200 201 static int emx_dma_alloc(struct emx_softc *); 202 static void emx_dma_free(struct emx_softc *); 203 static void emx_init_tx_ring(struct emx_softc *); 204 static int emx_init_rx_ring(struct emx_softc *, struct emx_rxdata *); 205 static void emx_free_rx_ring(struct emx_softc *, struct emx_rxdata *); 206 static int emx_create_tx_ring(struct emx_softc *); 207 static int emx_create_rx_ring(struct emx_softc *, struct emx_rxdata *); 208 static void emx_destroy_tx_ring(struct emx_softc *, int); 209 static void emx_destroy_rx_ring(struct emx_softc *, 210 struct emx_rxdata *, int); 211 static int emx_newbuf(struct emx_softc *, struct emx_rxdata *, int, int); 212 static int emx_encap(struct emx_softc *, struct mbuf **); 213 static int emx_txcsum_pullup(struct emx_softc *, struct mbuf **); 214 static int emx_txcsum(struct emx_softc *, struct mbuf *, 215 uint32_t *, uint32_t *); 216 217 static int emx_is_valid_eaddr(const uint8_t *); 218 static int emx_reset(struct emx_softc *); 219 static void emx_setup_ifp(struct emx_softc *); 220 static void emx_init_tx_unit(struct emx_softc *); 221 static void emx_init_rx_unit(struct emx_softc *); 222 static void emx_update_stats(struct emx_softc *); 223 static void emx_set_promisc(struct emx_softc *); 224 static void emx_disable_promisc(struct emx_softc *); 225 static void emx_set_multi(struct emx_softc *); 226 static void emx_update_link_status(struct emx_softc *); 227 static void emx_smartspeed(struct emx_softc *); 228 static void emx_set_itr(struct emx_softc *, uint32_t); 229 230 static void emx_print_debug_info(struct emx_softc *); 231 static void emx_print_nvm_info(struct emx_softc *); 232 static void emx_print_hw_stats(struct emx_softc *); 233 234 static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS); 235 static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 236 static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS); 237 static int emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS); 238 static void emx_add_sysctl(struct emx_softc *); 239 240 static void emx_serialize_skipmain(struct emx_softc *); 241 static void emx_deserialize_skipmain(struct emx_softc *); 242 243 /* Management and WOL Support */ 244 static void emx_get_mgmt(struct emx_softc *); 245 static void emx_rel_mgmt(struct emx_softc *); 246 static void emx_get_hw_control(struct emx_softc *); 247 static void emx_rel_hw_control(struct emx_softc *); 248 static void emx_enable_wol(device_t); 249 250 static device_method_t emx_methods[] = { 251 /* Device interface */ 252 DEVMETHOD(device_probe, emx_probe), 253 DEVMETHOD(device_attach, emx_attach), 254 DEVMETHOD(device_detach, emx_detach), 255 DEVMETHOD(device_shutdown, emx_shutdown), 256 DEVMETHOD(device_suspend, emx_suspend), 257 DEVMETHOD(device_resume, emx_resume), 258 { 0, 0 } 259 }; 260 261 static driver_t emx_driver = { 262 "emx", 263 emx_methods, 264 sizeof(struct emx_softc), 265 }; 266 267 static devclass_t emx_devclass; 268 269 DECLARE_DUMMY_MODULE(if_emx); 270 MODULE_DEPEND(emx, ig_hal, 1, 1, 1); 271 DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, NULL, NULL); 272 273 /* 274 * Tunables 275 */ 276 static int emx_int_throttle_ceil = EMX_DEFAULT_ITR; 277 static int emx_rxd = EMX_DEFAULT_RXD; 278 static int emx_txd = EMX_DEFAULT_TXD; 279 static int emx_smart_pwr_down = 0; 280 281 /* Controls whether promiscuous also shows bad packets */ 282 static int emx_debug_sbp = FALSE; 283 284 static int emx_82573_workaround = 1; 285 static int emx_msi_enable = 1; 286 287 TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil); 288 TUNABLE_INT("hw.emx.rxd", &emx_rxd); 289 TUNABLE_INT("hw.emx.txd", &emx_txd); 290 TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down); 291 TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp); 292 TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround); 293 TUNABLE_INT("hw.emx.msi.enable", &emx_msi_enable); 294 295 /* Global used in WOL setup with multiport cards */ 296 static int emx_global_quad_port_a = 0; 297 298 /* Set this to one to display debug statistics */ 299 static int emx_display_debug_stats = 0; 300 301 #if !defined(KTR_IF_EMX) 302 #define KTR_IF_EMX KTR_ALL 303 #endif 304 KTR_INFO_MASTER(if_emx); 305 KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin"); 306 KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end"); 307 KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet"); 308 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet"); 309 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean"); 310 #define logif(name) KTR_LOG(if_emx_ ## name) 311 312 static __inline void 313 emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf) 314 { 315 rxd->rxd_bufaddr = htole64(rxbuf->paddr); 316 /* DD bit must be cleared */ 317 rxd->rxd_staterr = 0; 318 } 319 320 static __inline void 321 emx_rxcsum(uint32_t staterr, struct mbuf *mp) 322 { 323 /* Ignore Checksum bit is set */ 324 if (staterr & E1000_RXD_STAT_IXSM) 325 return; 326 327 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) == 328 E1000_RXD_STAT_IPCS) 329 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID; 330 331 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) == 332 E1000_RXD_STAT_TCPCS) { 333 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 334 CSUM_PSEUDO_HDR | 335 CSUM_FRAG_NOT_CHECKED; 336 mp->m_pkthdr.csum_data = htons(0xffff); 337 } 338 } 339 340 static __inline struct pktinfo * 341 emx_rssinfo(struct mbuf *m, struct pktinfo *pi, 342 uint32_t mrq, uint32_t hash, uint32_t staterr) 343 { 344 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) { 345 case EMX_RXDMRQ_IPV4_TCP: 346 pi->pi_netisr = NETISR_IP; 347 pi->pi_flags = 0; 348 pi->pi_l3proto = IPPROTO_TCP; 349 break; 350 351 case EMX_RXDMRQ_IPV6_TCP: 352 pi->pi_netisr = NETISR_IPV6; 353 pi->pi_flags = 0; 354 pi->pi_l3proto = IPPROTO_TCP; 355 break; 356 357 case EMX_RXDMRQ_IPV4: 358 if (staterr & E1000_RXD_STAT_IXSM) 359 return NULL; 360 361 if ((staterr & 362 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) == 363 E1000_RXD_STAT_TCPCS) { 364 pi->pi_netisr = NETISR_IP; 365 pi->pi_flags = 0; 366 pi->pi_l3proto = IPPROTO_UDP; 367 break; 368 } 369 /* FALL THROUGH */ 370 default: 371 return NULL; 372 } 373 374 m->m_flags |= M_HASH; 375 m->m_pkthdr.hash = toeplitz_hash(hash); 376 return pi; 377 } 378 379 static int 380 emx_probe(device_t dev) 381 { 382 const struct emx_device *d; 383 uint16_t vid, did; 384 385 vid = pci_get_vendor(dev); 386 did = pci_get_device(dev); 387 388 for (d = emx_devices; d->desc != NULL; ++d) { 389 if (vid == d->vid && did == d->did) { 390 device_set_desc(dev, d->desc); 391 device_set_async_attach(dev, TRUE); 392 return 0; 393 } 394 } 395 return ENXIO; 396 } 397 398 static int 399 emx_attach(device_t dev) 400 { 401 struct emx_softc *sc = device_get_softc(dev); 402 struct ifnet *ifp = &sc->arpcom.ac_if; 403 int error = 0, i; 404 u_int intr_flags; 405 uint16_t eeprom_data, device_id, apme_mask; 406 407 lwkt_serialize_init(&sc->main_serialize); 408 lwkt_serialize_init(&sc->tx_serialize); 409 for (i = 0; i < EMX_NRX_RING; ++i) 410 lwkt_serialize_init(&sc->rx_data[i].rx_serialize); 411 412 i = 0; 413 sc->serializes[i++] = &sc->main_serialize; 414 sc->serializes[i++] = &sc->tx_serialize; 415 sc->serializes[i++] = &sc->rx_data[0].rx_serialize; 416 sc->serializes[i++] = &sc->rx_data[1].rx_serialize; 417 KKASSERT(i == EMX_NSERIALIZE); 418 419 callout_init_mp(&sc->timer); 420 421 sc->dev = sc->osdep.dev = dev; 422 423 /* 424 * Determine hardware and mac type 425 */ 426 sc->hw.vendor_id = pci_get_vendor(dev); 427 sc->hw.device_id = pci_get_device(dev); 428 sc->hw.revision_id = pci_get_revid(dev); 429 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev); 430 sc->hw.subsystem_device_id = pci_get_subdevice(dev); 431 432 if (e1000_set_mac_type(&sc->hw)) 433 return ENXIO; 434 435 /* Enable bus mastering */ 436 pci_enable_busmaster(dev); 437 438 /* 439 * Allocate IO memory 440 */ 441 sc->memory_rid = EMX_BAR_MEM; 442 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 443 &sc->memory_rid, RF_ACTIVE); 444 if (sc->memory == NULL) { 445 device_printf(dev, "Unable to allocate bus resource: memory\n"); 446 error = ENXIO; 447 goto fail; 448 } 449 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); 450 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory); 451 452 /* XXX This is quite goofy, it is not actually used */ 453 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle; 454 455 /* 456 * Allocate interrupt 457 */ 458 sc->intr_type = pci_alloc_1intr(dev, emx_msi_enable, 459 &sc->intr_rid, &intr_flags); 460 461 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid, 462 intr_flags); 463 if (sc->intr_res == NULL) { 464 device_printf(dev, "Unable to allocate bus resource: " 465 "interrupt\n"); 466 error = ENXIO; 467 goto fail; 468 } 469 470 /* Save PCI command register for Shared Code */ 471 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 472 sc->hw.back = &sc->osdep; 473 474 /* Do Shared Code initialization */ 475 if (e1000_setup_init_funcs(&sc->hw, TRUE)) { 476 device_printf(dev, "Setup of Shared code failed\n"); 477 error = ENXIO; 478 goto fail; 479 } 480 e1000_get_bus_info(&sc->hw); 481 482 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG; 483 sc->hw.phy.autoneg_wait_to_complete = FALSE; 484 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT; 485 486 /* 487 * Interrupt throttle rate 488 */ 489 if (emx_int_throttle_ceil == 0) { 490 sc->int_throttle_ceil = 0; 491 } else { 492 int throttle = emx_int_throttle_ceil; 493 494 if (throttle < 0) 495 throttle = EMX_DEFAULT_ITR; 496 497 /* Recalculate the tunable value to get the exact frequency. */ 498 throttle = 1000000000 / 256 / throttle; 499 500 /* Upper 16bits of ITR is reserved and should be zero */ 501 if (throttle & 0xffff0000) 502 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR; 503 504 sc->int_throttle_ceil = 1000000000 / 256 / throttle; 505 } 506 507 e1000_init_script_state_82541(&sc->hw, TRUE); 508 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE); 509 510 /* Copper options */ 511 if (sc->hw.phy.media_type == e1000_media_type_copper) { 512 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES; 513 sc->hw.phy.disable_polarity_correction = FALSE; 514 sc->hw.phy.ms_type = EMX_MASTER_SLAVE; 515 } 516 517 /* Set the frame limits assuming standard ethernet sized frames. */ 518 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN; 519 sc->min_frame_size = ETHER_MIN_LEN; 520 521 /* This controls when hardware reports transmit completion status. */ 522 sc->hw.mac.report_tx_early = 1; 523 524 /* Calculate # of RX rings */ 525 if (ncpus > 1) 526 sc->rx_ring_cnt = EMX_NRX_RING; 527 else 528 sc->rx_ring_cnt = 1; 529 sc->rx_ring_inuse = sc->rx_ring_cnt; 530 531 /* Allocate RX/TX rings' busdma(9) stuffs */ 532 error = emx_dma_alloc(sc); 533 if (error) 534 goto fail; 535 536 /* Allocate multicast array memory. */ 537 sc->mta = kmalloc(ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX, 538 M_DEVBUF, M_WAITOK); 539 540 /* Indicate SOL/IDER usage */ 541 if (e1000_check_reset_block(&sc->hw)) { 542 device_printf(dev, 543 "PHY reset is blocked due to SOL/IDER session.\n"); 544 } 545 546 /* 547 * Start from a known state, this is important in reading the 548 * nvm and mac from that. 549 */ 550 e1000_reset_hw(&sc->hw); 551 552 /* Make sure we have a good EEPROM before we read from it */ 553 if (e1000_validate_nvm_checksum(&sc->hw) < 0) { 554 /* 555 * Some PCI-E parts fail the first check due to 556 * the link being in sleep state, call it again, 557 * if it fails a second time its a real issue. 558 */ 559 if (e1000_validate_nvm_checksum(&sc->hw) < 0) { 560 device_printf(dev, 561 "The EEPROM Checksum Is Not Valid\n"); 562 error = EIO; 563 goto fail; 564 } 565 } 566 567 /* Copy the permanent MAC address out of the EEPROM */ 568 if (e1000_read_mac_addr(&sc->hw) < 0) { 569 device_printf(dev, "EEPROM read error while reading MAC" 570 " address\n"); 571 error = EIO; 572 goto fail; 573 } 574 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) { 575 device_printf(dev, "Invalid MAC address\n"); 576 error = EIO; 577 goto fail; 578 } 579 580 /* Determine if we have to control management hardware */ 581 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw); 582 583 /* 584 * Setup Wake-on-Lan 585 */ 586 apme_mask = EMX_EEPROM_APME; 587 eeprom_data = 0; 588 switch (sc->hw.mac.type) { 589 case e1000_82573: 590 sc->has_amt = 1; 591 /* FALL THROUGH */ 592 593 case e1000_82571: 594 case e1000_82572: 595 case e1000_80003es2lan: 596 if (sc->hw.bus.func == 1) { 597 e1000_read_nvm(&sc->hw, 598 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 599 } else { 600 e1000_read_nvm(&sc->hw, 601 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 602 } 603 break; 604 605 default: 606 e1000_read_nvm(&sc->hw, 607 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 608 break; 609 } 610 if (eeprom_data & apme_mask) 611 sc->wol = E1000_WUFC_MAG | E1000_WUFC_MC; 612 613 /* 614 * We have the eeprom settings, now apply the special cases 615 * where the eeprom may be wrong or the board won't support 616 * wake on lan on a particular port 617 */ 618 device_id = pci_get_device(dev); 619 switch (device_id) { 620 case E1000_DEV_ID_82571EB_FIBER: 621 /* 622 * Wake events only supported on port A for dual fiber 623 * regardless of eeprom setting 624 */ 625 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 626 E1000_STATUS_FUNC_1) 627 sc->wol = 0; 628 break; 629 630 case E1000_DEV_ID_82571EB_QUAD_COPPER: 631 case E1000_DEV_ID_82571EB_QUAD_FIBER: 632 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 633 /* if quad port sc, disable WoL on all but port A */ 634 if (emx_global_quad_port_a != 0) 635 sc->wol = 0; 636 /* Reset for multiple quad port adapters */ 637 if (++emx_global_quad_port_a == 4) 638 emx_global_quad_port_a = 0; 639 break; 640 } 641 642 /* XXX disable wol */ 643 sc->wol = 0; 644 645 /* Setup OS specific network interface */ 646 emx_setup_ifp(sc); 647 648 /* Add sysctl tree, must after em_setup_ifp() */ 649 emx_add_sysctl(sc); 650 651 /* Reset the hardware */ 652 error = emx_reset(sc); 653 if (error) { 654 device_printf(dev, "Unable to reset the hardware\n"); 655 goto fail; 656 } 657 658 /* Initialize statistics */ 659 emx_update_stats(sc); 660 661 sc->hw.mac.get_link_status = 1; 662 emx_update_link_status(sc); 663 664 sc->spare_tx_desc = EMX_TX_SPARE; 665 666 /* 667 * Keep following relationship between spare_tx_desc, oact_tx_desc 668 * and tx_int_nsegs: 669 * (spare_tx_desc + EMX_TX_RESERVED) <= 670 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_int_nsegs 671 */ 672 sc->oact_tx_desc = sc->num_tx_desc / 8; 673 if (sc->oact_tx_desc > EMX_TX_OACTIVE_MAX) 674 sc->oact_tx_desc = EMX_TX_OACTIVE_MAX; 675 if (sc->oact_tx_desc < sc->spare_tx_desc + EMX_TX_RESERVED) 676 sc->oact_tx_desc = sc->spare_tx_desc + EMX_TX_RESERVED; 677 678 sc->tx_int_nsegs = sc->num_tx_desc / 16; 679 if (sc->tx_int_nsegs < sc->oact_tx_desc) 680 sc->tx_int_nsegs = sc->oact_tx_desc; 681 682 /* Non-AMT based hardware can now take control from firmware */ 683 if (sc->has_manage && !sc->has_amt) 684 emx_get_hw_control(sc); 685 686 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, emx_intr, sc, 687 &sc->intr_tag, &sc->main_serialize); 688 if (error) { 689 device_printf(dev, "Failed to register interrupt handler"); 690 ether_ifdetach(&sc->arpcom.ac_if); 691 goto fail; 692 } 693 694 ifp->if_cpuid = rman_get_cpuid(sc->intr_res); 695 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 696 return (0); 697 fail: 698 emx_detach(dev); 699 return (error); 700 } 701 702 static int 703 emx_detach(device_t dev) 704 { 705 struct emx_softc *sc = device_get_softc(dev); 706 707 if (device_is_attached(dev)) { 708 struct ifnet *ifp = &sc->arpcom.ac_if; 709 710 ifnet_serialize_all(ifp); 711 712 emx_stop(sc); 713 714 e1000_phy_hw_reset(&sc->hw); 715 716 emx_rel_mgmt(sc); 717 emx_rel_hw_control(sc); 718 719 if (sc->wol) { 720 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 721 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 722 emx_enable_wol(dev); 723 } 724 725 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag); 726 727 ifnet_deserialize_all(ifp); 728 729 ether_ifdetach(ifp); 730 } else { 731 emx_rel_hw_control(sc); 732 } 733 bus_generic_detach(dev); 734 735 if (sc->intr_res != NULL) { 736 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid, 737 sc->intr_res); 738 } 739 740 if (sc->intr_type == PCI_INTR_TYPE_MSI) 741 pci_release_msi(dev); 742 743 if (sc->memory != NULL) { 744 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid, 745 sc->memory); 746 } 747 748 emx_dma_free(sc); 749 750 /* Free sysctl tree */ 751 if (sc->sysctl_tree != NULL) 752 sysctl_ctx_free(&sc->sysctl_ctx); 753 754 return (0); 755 } 756 757 static int 758 emx_shutdown(device_t dev) 759 { 760 return emx_suspend(dev); 761 } 762 763 static int 764 emx_suspend(device_t dev) 765 { 766 struct emx_softc *sc = device_get_softc(dev); 767 struct ifnet *ifp = &sc->arpcom.ac_if; 768 769 ifnet_serialize_all(ifp); 770 771 emx_stop(sc); 772 773 emx_rel_mgmt(sc); 774 emx_rel_hw_control(sc); 775 776 if (sc->wol) { 777 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 778 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 779 emx_enable_wol(dev); 780 } 781 782 ifnet_deserialize_all(ifp); 783 784 return bus_generic_suspend(dev); 785 } 786 787 static int 788 emx_resume(device_t dev) 789 { 790 struct emx_softc *sc = device_get_softc(dev); 791 struct ifnet *ifp = &sc->arpcom.ac_if; 792 793 ifnet_serialize_all(ifp); 794 795 emx_init(sc); 796 emx_get_mgmt(sc); 797 if_devstart(ifp); 798 799 ifnet_deserialize_all(ifp); 800 801 return bus_generic_resume(dev); 802 } 803 804 static void 805 emx_start(struct ifnet *ifp) 806 { 807 struct emx_softc *sc = ifp->if_softc; 808 struct mbuf *m_head; 809 810 ASSERT_SERIALIZED(&sc->tx_serialize); 811 812 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 813 return; 814 815 if (!sc->link_active) { 816 ifq_purge(&ifp->if_snd); 817 return; 818 } 819 820 while (!ifq_is_empty(&ifp->if_snd)) { 821 /* Now do we at least have a minimal? */ 822 if (EMX_IS_OACTIVE(sc)) { 823 emx_tx_collect(sc); 824 if (EMX_IS_OACTIVE(sc)) { 825 ifp->if_flags |= IFF_OACTIVE; 826 sc->no_tx_desc_avail1++; 827 break; 828 } 829 } 830 831 logif(pkt_txqueue); 832 m_head = ifq_dequeue(&ifp->if_snd, NULL); 833 if (m_head == NULL) 834 break; 835 836 if (emx_encap(sc, &m_head)) { 837 ifp->if_oerrors++; 838 emx_tx_collect(sc); 839 continue; 840 } 841 842 /* Send a copy of the frame to the BPF listener */ 843 ETHER_BPF_MTAP(ifp, m_head); 844 845 /* Set timeout in case hardware has problems transmitting. */ 846 ifp->if_timer = EMX_TX_TIMEOUT; 847 } 848 } 849 850 static int 851 emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 852 { 853 struct emx_softc *sc = ifp->if_softc; 854 struct ifreq *ifr = (struct ifreq *)data; 855 uint16_t eeprom_data = 0; 856 int max_frame_size, mask, reinit; 857 int error = 0; 858 859 ASSERT_IFNET_SERIALIZED_ALL(ifp); 860 861 switch (command) { 862 case SIOCSIFMTU: 863 switch (sc->hw.mac.type) { 864 case e1000_82573: 865 /* 866 * 82573 only supports jumbo frames 867 * if ASPM is disabled. 868 */ 869 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1, 870 &eeprom_data); 871 if (eeprom_data & NVM_WORD1A_ASPM_MASK) { 872 max_frame_size = ETHER_MAX_LEN; 873 break; 874 } 875 /* FALL THROUGH */ 876 877 /* Limit Jumbo Frame size */ 878 case e1000_82571: 879 case e1000_82572: 880 case e1000_82574: 881 case e1000_80003es2lan: 882 max_frame_size = 9234; 883 break; 884 885 default: 886 max_frame_size = MAX_JUMBO_FRAME_SIZE; 887 break; 888 } 889 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN - 890 ETHER_CRC_LEN) { 891 error = EINVAL; 892 break; 893 } 894 895 ifp->if_mtu = ifr->ifr_mtu; 896 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN + 897 ETHER_CRC_LEN; 898 899 if (ifp->if_flags & IFF_RUNNING) 900 emx_init(sc); 901 break; 902 903 case SIOCSIFFLAGS: 904 if (ifp->if_flags & IFF_UP) { 905 if ((ifp->if_flags & IFF_RUNNING)) { 906 if ((ifp->if_flags ^ sc->if_flags) & 907 (IFF_PROMISC | IFF_ALLMULTI)) { 908 emx_disable_promisc(sc); 909 emx_set_promisc(sc); 910 } 911 } else { 912 emx_init(sc); 913 } 914 } else if (ifp->if_flags & IFF_RUNNING) { 915 emx_stop(sc); 916 } 917 sc->if_flags = ifp->if_flags; 918 break; 919 920 case SIOCADDMULTI: 921 case SIOCDELMULTI: 922 if (ifp->if_flags & IFF_RUNNING) { 923 emx_disable_intr(sc); 924 emx_set_multi(sc); 925 #ifdef IFPOLL_ENABLE 926 if (!(ifp->if_flags & IFF_NPOLLING)) 927 #endif 928 emx_enable_intr(sc); 929 } 930 break; 931 932 case SIOCSIFMEDIA: 933 /* Check SOL/IDER usage */ 934 if (e1000_check_reset_block(&sc->hw)) { 935 device_printf(sc->dev, "Media change is" 936 " blocked due to SOL/IDER session.\n"); 937 break; 938 } 939 /* FALL THROUGH */ 940 941 case SIOCGIFMEDIA: 942 error = ifmedia_ioctl(ifp, ifr, &sc->media, command); 943 break; 944 945 case SIOCSIFCAP: 946 reinit = 0; 947 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 948 if (mask & IFCAP_HWCSUM) { 949 ifp->if_capenable ^= (mask & IFCAP_HWCSUM); 950 reinit = 1; 951 } 952 if (mask & IFCAP_VLAN_HWTAGGING) { 953 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 954 reinit = 1; 955 } 956 if (mask & IFCAP_RSS) { 957 ifp->if_capenable ^= IFCAP_RSS; 958 reinit = 1; 959 } 960 if (reinit && (ifp->if_flags & IFF_RUNNING)) 961 emx_init(sc); 962 break; 963 964 default: 965 error = ether_ioctl(ifp, command, data); 966 break; 967 } 968 return (error); 969 } 970 971 static void 972 emx_watchdog(struct ifnet *ifp) 973 { 974 struct emx_softc *sc = ifp->if_softc; 975 976 ASSERT_IFNET_SERIALIZED_ALL(ifp); 977 978 /* 979 * The timer is set to 5 every time start queues a packet. 980 * Then txeof keeps resetting it as long as it cleans at 981 * least one descriptor. 982 * Finally, anytime all descriptors are clean the timer is 983 * set to 0. 984 */ 985 986 if (E1000_READ_REG(&sc->hw, E1000_TDT(0)) == 987 E1000_READ_REG(&sc->hw, E1000_TDH(0))) { 988 /* 989 * If we reach here, all TX jobs are completed and 990 * the TX engine should have been idled for some time. 991 * We don't need to call if_devstart() here. 992 */ 993 ifp->if_flags &= ~IFF_OACTIVE; 994 ifp->if_timer = 0; 995 return; 996 } 997 998 /* 999 * If we are in this routine because of pause frames, then 1000 * don't reset the hardware. 1001 */ 1002 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) { 1003 ifp->if_timer = EMX_TX_TIMEOUT; 1004 return; 1005 } 1006 1007 if (e1000_check_for_link(&sc->hw) == 0) 1008 if_printf(ifp, "watchdog timeout -- resetting\n"); 1009 1010 ifp->if_oerrors++; 1011 sc->watchdog_events++; 1012 1013 emx_init(sc); 1014 1015 if (!ifq_is_empty(&ifp->if_snd)) 1016 if_devstart(ifp); 1017 } 1018 1019 static void 1020 emx_init(void *xsc) 1021 { 1022 struct emx_softc *sc = xsc; 1023 struct ifnet *ifp = &sc->arpcom.ac_if; 1024 device_t dev = sc->dev; 1025 uint32_t pba; 1026 int i; 1027 1028 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1029 1030 emx_stop(sc); 1031 1032 /* 1033 * Packet Buffer Allocation (PBA) 1034 * Writing PBA sets the receive portion of the buffer 1035 * the remainder is used for the transmit buffer. 1036 */ 1037 switch (sc->hw.mac.type) { 1038 /* Total Packet Buffer on these is 48K */ 1039 case e1000_82571: 1040 case e1000_82572: 1041 case e1000_80003es2lan: 1042 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 1043 break; 1044 1045 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 1046 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 1047 break; 1048 1049 case e1000_82574: 1050 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 1051 break; 1052 1053 default: 1054 /* Devices before 82547 had a Packet Buffer of 64K. */ 1055 if (sc->max_frame_size > 8192) 1056 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1057 else 1058 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1059 } 1060 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba); 1061 1062 /* Get the latest mac address, User can use a LAA */ 1063 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN); 1064 1065 /* Put the address into the Receive Address Array */ 1066 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1067 1068 /* 1069 * With the 82571 sc, RAR[0] may be overwritten 1070 * when the other port is reset, we make a duplicate 1071 * in RAR[14] for that eventuality, this assures 1072 * the interface continues to function. 1073 */ 1074 if (sc->hw.mac.type == e1000_82571) { 1075 e1000_set_laa_state_82571(&sc->hw, TRUE); 1076 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 1077 E1000_RAR_ENTRIES - 1); 1078 } 1079 1080 /* Initialize the hardware */ 1081 if (emx_reset(sc)) { 1082 device_printf(dev, "Unable to reset the hardware\n"); 1083 /* XXX emx_stop()? */ 1084 return; 1085 } 1086 emx_update_link_status(sc); 1087 1088 /* Setup VLAN support, basic and offload if available */ 1089 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1090 1091 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 1092 uint32_t ctrl; 1093 1094 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL); 1095 ctrl |= E1000_CTRL_VME; 1096 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl); 1097 } 1098 1099 /* Set hardware offload abilities */ 1100 if (ifp->if_capenable & IFCAP_TXCSUM) 1101 ifp->if_hwassist = EMX_CSUM_FEATURES; 1102 else 1103 ifp->if_hwassist = 0; 1104 1105 /* Configure for OS presence */ 1106 emx_get_mgmt(sc); 1107 1108 /* Prepare transmit descriptors and buffers */ 1109 emx_init_tx_ring(sc); 1110 emx_init_tx_unit(sc); 1111 1112 /* Setup Multicast table */ 1113 emx_set_multi(sc); 1114 1115 /* 1116 * Adjust # of RX ring to be used based on IFCAP_RSS 1117 */ 1118 if (ifp->if_capenable & IFCAP_RSS) 1119 sc->rx_ring_inuse = sc->rx_ring_cnt; 1120 else 1121 sc->rx_ring_inuse = 1; 1122 1123 /* Prepare receive descriptors and buffers */ 1124 for (i = 0; i < sc->rx_ring_inuse; ++i) { 1125 if (emx_init_rx_ring(sc, &sc->rx_data[i])) { 1126 device_printf(dev, 1127 "Could not setup receive structures\n"); 1128 emx_stop(sc); 1129 return; 1130 } 1131 } 1132 emx_init_rx_unit(sc); 1133 1134 /* Don't lose promiscuous settings */ 1135 emx_set_promisc(sc); 1136 1137 ifp->if_flags |= IFF_RUNNING; 1138 ifp->if_flags &= ~IFF_OACTIVE; 1139 1140 callout_reset(&sc->timer, hz, emx_timer, sc); 1141 e1000_clear_hw_cntrs_base_generic(&sc->hw); 1142 1143 /* MSI/X configuration for 82574 */ 1144 if (sc->hw.mac.type == e1000_82574) { 1145 int tmp; 1146 1147 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 1148 tmp |= E1000_CTRL_EXT_PBA_CLR; 1149 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp); 1150 /* 1151 * XXX MSIX 1152 * Set the IVAR - interrupt vector routing. 1153 * Each nibble represents a vector, high bit 1154 * is enable, other 3 bits are the MSIX table 1155 * entry, we map RXQ0 to 0, TXQ0 to 1, and 1156 * Link (other) to 2, hence the magic number. 1157 */ 1158 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908); 1159 } 1160 1161 #ifdef IFPOLL_ENABLE 1162 /* 1163 * Only enable interrupts if we are not polling, make sure 1164 * they are off otherwise. 1165 */ 1166 if (ifp->if_flags & IFF_NPOLLING) 1167 emx_disable_intr(sc); 1168 else 1169 #endif /* IFPOLL_ENABLE */ 1170 emx_enable_intr(sc); 1171 1172 /* AMT based hardware can now take control from firmware */ 1173 if (sc->has_manage && sc->has_amt) 1174 emx_get_hw_control(sc); 1175 1176 /* Don't reset the phy next time init gets called */ 1177 sc->hw.phy.reset_disable = TRUE; 1178 } 1179 1180 static void 1181 emx_intr(void *xsc) 1182 { 1183 struct emx_softc *sc = xsc; 1184 struct ifnet *ifp = &sc->arpcom.ac_if; 1185 uint32_t reg_icr; 1186 1187 logif(intr_beg); 1188 ASSERT_SERIALIZED(&sc->main_serialize); 1189 1190 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1191 1192 if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0) { 1193 logif(intr_end); 1194 return; 1195 } 1196 1197 /* 1198 * XXX: some laptops trigger several spurious interrupts 1199 * on emx(4) when in the resume cycle. The ICR register 1200 * reports all-ones value in this case. Processing such 1201 * interrupts would lead to a freeze. I don't know why. 1202 */ 1203 if (reg_icr == 0xffffffff) { 1204 logif(intr_end); 1205 return; 1206 } 1207 1208 if (ifp->if_flags & IFF_RUNNING) { 1209 if (reg_icr & 1210 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) { 1211 int i; 1212 1213 for (i = 0; i < sc->rx_ring_inuse; ++i) { 1214 lwkt_serialize_enter( 1215 &sc->rx_data[i].rx_serialize); 1216 emx_rxeof(sc, i, -1); 1217 lwkt_serialize_exit( 1218 &sc->rx_data[i].rx_serialize); 1219 } 1220 } 1221 if (reg_icr & E1000_ICR_TXDW) { 1222 lwkt_serialize_enter(&sc->tx_serialize); 1223 emx_txeof(sc); 1224 if (!ifq_is_empty(&ifp->if_snd)) 1225 if_devstart(ifp); 1226 lwkt_serialize_exit(&sc->tx_serialize); 1227 } 1228 } 1229 1230 /* Link status change */ 1231 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1232 emx_serialize_skipmain(sc); 1233 1234 callout_stop(&sc->timer); 1235 sc->hw.mac.get_link_status = 1; 1236 emx_update_link_status(sc); 1237 1238 /* Deal with TX cruft when link lost */ 1239 emx_tx_purge(sc); 1240 1241 callout_reset(&sc->timer, hz, emx_timer, sc); 1242 1243 emx_deserialize_skipmain(sc); 1244 } 1245 1246 if (reg_icr & E1000_ICR_RXO) 1247 sc->rx_overruns++; 1248 1249 logif(intr_end); 1250 } 1251 1252 static void 1253 emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1254 { 1255 struct emx_softc *sc = ifp->if_softc; 1256 1257 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1258 1259 emx_update_link_status(sc); 1260 1261 ifmr->ifm_status = IFM_AVALID; 1262 ifmr->ifm_active = IFM_ETHER; 1263 1264 if (!sc->link_active) 1265 return; 1266 1267 ifmr->ifm_status |= IFM_ACTIVE; 1268 1269 if (sc->hw.phy.media_type == e1000_media_type_fiber || 1270 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 1271 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX; 1272 } else { 1273 switch (sc->link_speed) { 1274 case 10: 1275 ifmr->ifm_active |= IFM_10_T; 1276 break; 1277 case 100: 1278 ifmr->ifm_active |= IFM_100_TX; 1279 break; 1280 1281 case 1000: 1282 ifmr->ifm_active |= IFM_1000_T; 1283 break; 1284 } 1285 if (sc->link_duplex == FULL_DUPLEX) 1286 ifmr->ifm_active |= IFM_FDX; 1287 else 1288 ifmr->ifm_active |= IFM_HDX; 1289 } 1290 } 1291 1292 static int 1293 emx_media_change(struct ifnet *ifp) 1294 { 1295 struct emx_softc *sc = ifp->if_softc; 1296 struct ifmedia *ifm = &sc->media; 1297 1298 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1299 1300 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1301 return (EINVAL); 1302 1303 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1304 case IFM_AUTO: 1305 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG; 1306 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT; 1307 break; 1308 1309 case IFM_1000_LX: 1310 case IFM_1000_SX: 1311 case IFM_1000_T: 1312 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG; 1313 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1314 break; 1315 1316 case IFM_100_TX: 1317 sc->hw.mac.autoneg = FALSE; 1318 sc->hw.phy.autoneg_advertised = 0; 1319 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1320 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1321 else 1322 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1323 break; 1324 1325 case IFM_10_T: 1326 sc->hw.mac.autoneg = FALSE; 1327 sc->hw.phy.autoneg_advertised = 0; 1328 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1329 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1330 else 1331 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1332 break; 1333 1334 default: 1335 if_printf(ifp, "Unsupported media type\n"); 1336 break; 1337 } 1338 1339 /* 1340 * As the speed/duplex settings my have changed we need to 1341 * reset the PHY. 1342 */ 1343 sc->hw.phy.reset_disable = FALSE; 1344 1345 emx_init(sc); 1346 1347 return (0); 1348 } 1349 1350 static int 1351 emx_encap(struct emx_softc *sc, struct mbuf **m_headp) 1352 { 1353 bus_dma_segment_t segs[EMX_MAX_SCATTER]; 1354 bus_dmamap_t map; 1355 struct emx_txbuf *tx_buffer, *tx_buffer_mapped; 1356 struct e1000_tx_desc *ctxd = NULL; 1357 struct mbuf *m_head = *m_headp; 1358 uint32_t txd_upper, txd_lower, cmd = 0; 1359 int maxsegs, nsegs, i, j, first, last = 0, error; 1360 1361 if (m_head->m_len < EMX_TXCSUM_MINHL && 1362 (m_head->m_flags & EMX_CSUM_FEATURES)) { 1363 /* 1364 * Make sure that ethernet header and ip.ip_hl are in 1365 * contiguous memory, since if TXCSUM is enabled, later 1366 * TX context descriptor's setup need to access ip.ip_hl. 1367 */ 1368 error = emx_txcsum_pullup(sc, m_headp); 1369 if (error) { 1370 KKASSERT(*m_headp == NULL); 1371 return error; 1372 } 1373 m_head = *m_headp; 1374 } 1375 1376 txd_upper = txd_lower = 0; 1377 1378 /* 1379 * Capture the first descriptor index, this descriptor 1380 * will have the index of the EOP which is the only one 1381 * that now gets a DONE bit writeback. 1382 */ 1383 first = sc->next_avail_tx_desc; 1384 tx_buffer = &sc->tx_buf[first]; 1385 tx_buffer_mapped = tx_buffer; 1386 map = tx_buffer->map; 1387 1388 maxsegs = sc->num_tx_desc_avail - EMX_TX_RESERVED; 1389 KASSERT(maxsegs >= sc->spare_tx_desc, ("not enough spare TX desc\n")); 1390 if (maxsegs > EMX_MAX_SCATTER) 1391 maxsegs = EMX_MAX_SCATTER; 1392 1393 error = bus_dmamap_load_mbuf_defrag(sc->txtag, map, m_headp, 1394 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 1395 if (error) { 1396 if (error == ENOBUFS) 1397 sc->mbuf_alloc_failed++; 1398 else 1399 sc->no_tx_dma_setup++; 1400 1401 m_freem(*m_headp); 1402 *m_headp = NULL; 1403 return error; 1404 } 1405 bus_dmamap_sync(sc->txtag, map, BUS_DMASYNC_PREWRITE); 1406 1407 m_head = *m_headp; 1408 sc->tx_nsegs += nsegs; 1409 1410 if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) { 1411 /* TX csum offloading will consume one TX desc */ 1412 sc->tx_nsegs += emx_txcsum(sc, m_head, &txd_upper, &txd_lower); 1413 } 1414 i = sc->next_avail_tx_desc; 1415 1416 /* Set up our transmit descriptors */ 1417 for (j = 0; j < nsegs; j++) { 1418 tx_buffer = &sc->tx_buf[i]; 1419 ctxd = &sc->tx_desc_base[i]; 1420 1421 ctxd->buffer_addr = htole64(segs[j].ds_addr); 1422 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS | 1423 txd_lower | segs[j].ds_len); 1424 ctxd->upper.data = htole32(txd_upper); 1425 1426 last = i; 1427 if (++i == sc->num_tx_desc) 1428 i = 0; 1429 } 1430 1431 sc->next_avail_tx_desc = i; 1432 1433 KKASSERT(sc->num_tx_desc_avail > nsegs); 1434 sc->num_tx_desc_avail -= nsegs; 1435 1436 /* Handle VLAN tag */ 1437 if (m_head->m_flags & M_VLANTAG) { 1438 /* Set the vlan id. */ 1439 ctxd->upper.fields.special = 1440 htole16(m_head->m_pkthdr.ether_vlantag); 1441 1442 /* Tell hardware to add tag */ 1443 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE); 1444 } 1445 1446 tx_buffer->m_head = m_head; 1447 tx_buffer_mapped->map = tx_buffer->map; 1448 tx_buffer->map = map; 1449 1450 if (sc->tx_nsegs >= sc->tx_int_nsegs) { 1451 sc->tx_nsegs = 0; 1452 1453 /* 1454 * Report Status (RS) is turned on 1455 * every tx_int_nsegs descriptors. 1456 */ 1457 cmd = E1000_TXD_CMD_RS; 1458 1459 /* 1460 * Keep track of the descriptor, which will 1461 * be written back by hardware. 1462 */ 1463 sc->tx_dd[sc->tx_dd_tail] = last; 1464 EMX_INC_TXDD_IDX(sc->tx_dd_tail); 1465 KKASSERT(sc->tx_dd_tail != sc->tx_dd_head); 1466 } 1467 1468 /* 1469 * Last Descriptor of Packet needs End Of Packet (EOP) 1470 */ 1471 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd); 1472 1473 /* 1474 * Advance the Transmit Descriptor Tail (TDT), this tells 1475 * the E1000 that this frame is available to transmit. 1476 */ 1477 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), i); 1478 1479 return (0); 1480 } 1481 1482 static void 1483 emx_set_promisc(struct emx_softc *sc) 1484 { 1485 struct ifnet *ifp = &sc->arpcom.ac_if; 1486 uint32_t reg_rctl; 1487 1488 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1489 1490 if (ifp->if_flags & IFF_PROMISC) { 1491 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1492 /* Turn this on if you want to see bad packets */ 1493 if (emx_debug_sbp) 1494 reg_rctl |= E1000_RCTL_SBP; 1495 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1496 } else if (ifp->if_flags & IFF_ALLMULTI) { 1497 reg_rctl |= E1000_RCTL_MPE; 1498 reg_rctl &= ~E1000_RCTL_UPE; 1499 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1500 } 1501 } 1502 1503 static void 1504 emx_disable_promisc(struct emx_softc *sc) 1505 { 1506 uint32_t reg_rctl; 1507 1508 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1509 1510 reg_rctl &= ~E1000_RCTL_UPE; 1511 reg_rctl &= ~E1000_RCTL_MPE; 1512 reg_rctl &= ~E1000_RCTL_SBP; 1513 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1514 } 1515 1516 static void 1517 emx_set_multi(struct emx_softc *sc) 1518 { 1519 struct ifnet *ifp = &sc->arpcom.ac_if; 1520 struct ifmultiaddr *ifma; 1521 uint32_t reg_rctl = 0; 1522 uint8_t *mta; 1523 int mcnt = 0; 1524 1525 mta = sc->mta; 1526 bzero(mta, ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX); 1527 1528 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1529 if (ifma->ifma_addr->sa_family != AF_LINK) 1530 continue; 1531 1532 if (mcnt == EMX_MCAST_ADDR_MAX) 1533 break; 1534 1535 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1536 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1537 mcnt++; 1538 } 1539 1540 if (mcnt >= EMX_MCAST_ADDR_MAX) { 1541 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1542 reg_rctl |= E1000_RCTL_MPE; 1543 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1544 } else { 1545 e1000_update_mc_addr_list(&sc->hw, mta, mcnt); 1546 } 1547 } 1548 1549 /* 1550 * This routine checks for link status and updates statistics. 1551 */ 1552 static void 1553 emx_timer(void *xsc) 1554 { 1555 struct emx_softc *sc = xsc; 1556 struct ifnet *ifp = &sc->arpcom.ac_if; 1557 1558 ifnet_serialize_all(ifp); 1559 1560 emx_update_link_status(sc); 1561 emx_update_stats(sc); 1562 1563 /* Reset LAA into RAR[0] on 82571 */ 1564 if (e1000_get_laa_state_82571(&sc->hw) == TRUE) 1565 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1566 1567 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING)) 1568 emx_print_hw_stats(sc); 1569 1570 emx_smartspeed(sc); 1571 1572 callout_reset(&sc->timer, hz, emx_timer, sc); 1573 1574 ifnet_deserialize_all(ifp); 1575 } 1576 1577 static void 1578 emx_update_link_status(struct emx_softc *sc) 1579 { 1580 struct e1000_hw *hw = &sc->hw; 1581 struct ifnet *ifp = &sc->arpcom.ac_if; 1582 device_t dev = sc->dev; 1583 uint32_t link_check = 0; 1584 1585 /* Get the cached link value or read phy for real */ 1586 switch (hw->phy.media_type) { 1587 case e1000_media_type_copper: 1588 if (hw->mac.get_link_status) { 1589 /* Do the work to read phy */ 1590 e1000_check_for_link(hw); 1591 link_check = !hw->mac.get_link_status; 1592 if (link_check) /* ESB2 fix */ 1593 e1000_cfg_on_link_up(hw); 1594 } else { 1595 link_check = TRUE; 1596 } 1597 break; 1598 1599 case e1000_media_type_fiber: 1600 e1000_check_for_link(hw); 1601 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU; 1602 break; 1603 1604 case e1000_media_type_internal_serdes: 1605 e1000_check_for_link(hw); 1606 link_check = sc->hw.mac.serdes_has_link; 1607 break; 1608 1609 case e1000_media_type_unknown: 1610 default: 1611 break; 1612 } 1613 1614 /* Now check for a transition */ 1615 if (link_check && sc->link_active == 0) { 1616 e1000_get_speed_and_duplex(hw, &sc->link_speed, 1617 &sc->link_duplex); 1618 1619 /* 1620 * Check if we should enable/disable SPEED_MODE bit on 1621 * 82571EB/82572EI 1622 */ 1623 if (sc->link_speed != SPEED_1000 && 1624 (hw->mac.type == e1000_82571 || 1625 hw->mac.type == e1000_82572)) { 1626 int tarc0; 1627 1628 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1629 tarc0 &= ~EMX_TARC_SPEED_MODE; 1630 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1631 } 1632 if (bootverbose) { 1633 device_printf(dev, "Link is up %d Mbps %s\n", 1634 sc->link_speed, 1635 ((sc->link_duplex == FULL_DUPLEX) ? 1636 "Full Duplex" : "Half Duplex")); 1637 } 1638 sc->link_active = 1; 1639 sc->smartspeed = 0; 1640 ifp->if_baudrate = sc->link_speed * 1000000; 1641 ifp->if_link_state = LINK_STATE_UP; 1642 if_link_state_change(ifp); 1643 } else if (!link_check && sc->link_active == 1) { 1644 ifp->if_baudrate = sc->link_speed = 0; 1645 sc->link_duplex = 0; 1646 if (bootverbose) 1647 device_printf(dev, "Link is Down\n"); 1648 sc->link_active = 0; 1649 #if 0 1650 /* Link down, disable watchdog */ 1651 if->if_timer = 0; 1652 #endif 1653 ifp->if_link_state = LINK_STATE_DOWN; 1654 if_link_state_change(ifp); 1655 } 1656 } 1657 1658 static void 1659 emx_stop(struct emx_softc *sc) 1660 { 1661 struct ifnet *ifp = &sc->arpcom.ac_if; 1662 int i; 1663 1664 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1665 1666 emx_disable_intr(sc); 1667 1668 callout_stop(&sc->timer); 1669 1670 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1671 ifp->if_timer = 0; 1672 1673 /* 1674 * Disable multiple receive queues. 1675 * 1676 * NOTE: 1677 * We should disable multiple receive queues before 1678 * resetting the hardware. 1679 */ 1680 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0); 1681 1682 e1000_reset_hw(&sc->hw); 1683 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0); 1684 1685 for (i = 0; i < sc->num_tx_desc; i++) { 1686 struct emx_txbuf *tx_buffer = &sc->tx_buf[i]; 1687 1688 if (tx_buffer->m_head != NULL) { 1689 bus_dmamap_unload(sc->txtag, tx_buffer->map); 1690 m_freem(tx_buffer->m_head); 1691 tx_buffer->m_head = NULL; 1692 } 1693 } 1694 1695 for (i = 0; i < sc->rx_ring_inuse; ++i) 1696 emx_free_rx_ring(sc, &sc->rx_data[i]); 1697 1698 sc->csum_flags = 0; 1699 sc->csum_ehlen = 0; 1700 sc->csum_iphlen = 0; 1701 1702 sc->tx_dd_head = 0; 1703 sc->tx_dd_tail = 0; 1704 sc->tx_nsegs = 0; 1705 } 1706 1707 static int 1708 emx_reset(struct emx_softc *sc) 1709 { 1710 device_t dev = sc->dev; 1711 uint16_t rx_buffer_size; 1712 1713 /* Set up smart power down as default off on newer adapters. */ 1714 if (!emx_smart_pwr_down && 1715 (sc->hw.mac.type == e1000_82571 || 1716 sc->hw.mac.type == e1000_82572)) { 1717 uint16_t phy_tmp = 0; 1718 1719 /* Speed up time to link by disabling smart power down. */ 1720 e1000_read_phy_reg(&sc->hw, 1721 IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 1722 phy_tmp &= ~IGP02E1000_PM_SPD; 1723 e1000_write_phy_reg(&sc->hw, 1724 IGP02E1000_PHY_POWER_MGMT, phy_tmp); 1725 } 1726 1727 /* 1728 * These parameters control the automatic generation (Tx) and 1729 * response (Rx) to Ethernet PAUSE frames. 1730 * - High water mark should allow for at least two frames to be 1731 * received after sending an XOFF. 1732 * - Low water mark works best when it is very near the high water mark. 1733 * This allows the receiver to restart by sending XON when it has 1734 * drained a bit. Here we use an arbitary value of 1500 which will 1735 * restart after one full frame is pulled from the buffer. There 1736 * could be several smaller frames in the buffer and if so they will 1737 * not trigger the XON until their total number reduces the buffer 1738 * by 1500. 1739 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 1740 */ 1741 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10; 1742 1743 sc->hw.fc.high_water = rx_buffer_size - 1744 roundup2(sc->max_frame_size, 1024); 1745 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500; 1746 1747 if (sc->hw.mac.type == e1000_80003es2lan) 1748 sc->hw.fc.pause_time = 0xFFFF; 1749 else 1750 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME; 1751 sc->hw.fc.send_xon = TRUE; 1752 sc->hw.fc.requested_mode = e1000_fc_full; 1753 1754 /* Issue a global reset */ 1755 e1000_reset_hw(&sc->hw); 1756 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0); 1757 1758 if (e1000_init_hw(&sc->hw) < 0) { 1759 device_printf(dev, "Hardware Initialization Failed\n"); 1760 return (EIO); 1761 } 1762 1763 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1764 e1000_get_phy_info(&sc->hw); 1765 e1000_check_for_link(&sc->hw); 1766 1767 return (0); 1768 } 1769 1770 static void 1771 emx_setup_ifp(struct emx_softc *sc) 1772 { 1773 struct ifnet *ifp = &sc->arpcom.ac_if; 1774 1775 if_initname(ifp, device_get_name(sc->dev), 1776 device_get_unit(sc->dev)); 1777 ifp->if_softc = sc; 1778 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1779 ifp->if_init = emx_init; 1780 ifp->if_ioctl = emx_ioctl; 1781 ifp->if_start = emx_start; 1782 #ifdef IFPOLL_ENABLE 1783 ifp->if_qpoll = emx_qpoll; 1784 #endif 1785 ifp->if_watchdog = emx_watchdog; 1786 ifp->if_serialize = emx_serialize; 1787 ifp->if_deserialize = emx_deserialize; 1788 ifp->if_tryserialize = emx_tryserialize; 1789 #ifdef INVARIANTS 1790 ifp->if_serialize_assert = emx_serialize_assert; 1791 #endif 1792 ifq_set_maxlen(&ifp->if_snd, sc->num_tx_desc - 1); 1793 ifq_set_ready(&ifp->if_snd); 1794 1795 ether_ifattach(ifp, sc->hw.mac.addr, NULL); 1796 1797 ifp->if_capabilities = IFCAP_HWCSUM | 1798 IFCAP_VLAN_HWTAGGING | 1799 IFCAP_VLAN_MTU; 1800 if (sc->rx_ring_cnt > 1) 1801 ifp->if_capabilities |= IFCAP_RSS; 1802 ifp->if_capenable = ifp->if_capabilities; 1803 ifp->if_hwassist = EMX_CSUM_FEATURES; 1804 1805 /* 1806 * Tell the upper layer(s) we support long frames. 1807 */ 1808 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1809 1810 /* 1811 * Specify the media types supported by this sc and register 1812 * callbacks to update media and link information 1813 */ 1814 ifmedia_init(&sc->media, IFM_IMASK, 1815 emx_media_change, emx_media_status); 1816 if (sc->hw.phy.media_type == e1000_media_type_fiber || 1817 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 1818 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX, 1819 0, NULL); 1820 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL); 1821 } else { 1822 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 1823 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 1824 0, NULL); 1825 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 1826 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 1827 0, NULL); 1828 if (sc->hw.phy.type != e1000_phy_ife) { 1829 ifmedia_add(&sc->media, 1830 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 1831 ifmedia_add(&sc->media, 1832 IFM_ETHER | IFM_1000_T, 0, NULL); 1833 } 1834 } 1835 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 1836 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO); 1837 } 1838 1839 /* 1840 * Workaround for SmartSpeed on 82541 and 82547 controllers 1841 */ 1842 static void 1843 emx_smartspeed(struct emx_softc *sc) 1844 { 1845 uint16_t phy_tmp; 1846 1847 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp || 1848 sc->hw.mac.autoneg == 0 || 1849 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 1850 return; 1851 1852 if (sc->smartspeed == 0) { 1853 /* 1854 * If Master/Slave config fault is asserted twice, 1855 * we assume back-to-back 1856 */ 1857 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 1858 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 1859 return; 1860 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 1861 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 1862 e1000_read_phy_reg(&sc->hw, 1863 PHY_1000T_CTRL, &phy_tmp); 1864 if (phy_tmp & CR_1000T_MS_ENABLE) { 1865 phy_tmp &= ~CR_1000T_MS_ENABLE; 1866 e1000_write_phy_reg(&sc->hw, 1867 PHY_1000T_CTRL, phy_tmp); 1868 sc->smartspeed++; 1869 if (sc->hw.mac.autoneg && 1870 !e1000_phy_setup_autoneg(&sc->hw) && 1871 !e1000_read_phy_reg(&sc->hw, 1872 PHY_CONTROL, &phy_tmp)) { 1873 phy_tmp |= MII_CR_AUTO_NEG_EN | 1874 MII_CR_RESTART_AUTO_NEG; 1875 e1000_write_phy_reg(&sc->hw, 1876 PHY_CONTROL, phy_tmp); 1877 } 1878 } 1879 } 1880 return; 1881 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) { 1882 /* If still no link, perhaps using 2/3 pair cable */ 1883 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 1884 phy_tmp |= CR_1000T_MS_ENABLE; 1885 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 1886 if (sc->hw.mac.autoneg && 1887 !e1000_phy_setup_autoneg(&sc->hw) && 1888 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) { 1889 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG; 1890 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp); 1891 } 1892 } 1893 1894 /* Restart process after EMX_SMARTSPEED_MAX iterations */ 1895 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX) 1896 sc->smartspeed = 0; 1897 } 1898 1899 static int 1900 emx_create_tx_ring(struct emx_softc *sc) 1901 { 1902 device_t dev = sc->dev; 1903 struct emx_txbuf *tx_buffer; 1904 int error, i, tsize; 1905 1906 /* 1907 * Validate number of transmit descriptors. It must not exceed 1908 * hardware maximum, and must be multiple of E1000_DBA_ALIGN. 1909 */ 1910 if ((emx_txd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 || 1911 emx_txd > EMX_MAX_TXD || emx_txd < EMX_MIN_TXD) { 1912 device_printf(dev, "Using %d TX descriptors instead of %d!\n", 1913 EMX_DEFAULT_TXD, emx_txd); 1914 sc->num_tx_desc = EMX_DEFAULT_TXD; 1915 } else { 1916 sc->num_tx_desc = emx_txd; 1917 } 1918 1919 /* 1920 * Allocate Transmit Descriptor ring 1921 */ 1922 tsize = roundup2(sc->num_tx_desc * sizeof(struct e1000_tx_desc), 1923 EMX_DBA_ALIGN); 1924 sc->tx_desc_base = bus_dmamem_coherent_any(sc->parent_dtag, 1925 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK, 1926 &sc->tx_desc_dtag, &sc->tx_desc_dmap, 1927 &sc->tx_desc_paddr); 1928 if (sc->tx_desc_base == NULL) { 1929 device_printf(dev, "Unable to allocate tx_desc memory\n"); 1930 return ENOMEM; 1931 } 1932 1933 sc->tx_buf = kmalloc(sizeof(struct emx_txbuf) * sc->num_tx_desc, 1934 M_DEVBUF, M_WAITOK | M_ZERO); 1935 1936 /* 1937 * Create DMA tags for tx buffers 1938 */ 1939 error = bus_dma_tag_create(sc->parent_dtag, /* parent */ 1940 1, 0, /* alignment, bounds */ 1941 BUS_SPACE_MAXADDR, /* lowaddr */ 1942 BUS_SPACE_MAXADDR, /* highaddr */ 1943 NULL, NULL, /* filter, filterarg */ 1944 EMX_TSO_SIZE, /* maxsize */ 1945 EMX_MAX_SCATTER, /* nsegments */ 1946 EMX_MAX_SEGSIZE, /* maxsegsize */ 1947 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | 1948 BUS_DMA_ONEBPAGE, /* flags */ 1949 &sc->txtag); 1950 if (error) { 1951 device_printf(dev, "Unable to allocate TX DMA tag\n"); 1952 kfree(sc->tx_buf, M_DEVBUF); 1953 sc->tx_buf = NULL; 1954 return error; 1955 } 1956 1957 /* 1958 * Create DMA maps for tx buffers 1959 */ 1960 for (i = 0; i < sc->num_tx_desc; i++) { 1961 tx_buffer = &sc->tx_buf[i]; 1962 1963 error = bus_dmamap_create(sc->txtag, 1964 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 1965 &tx_buffer->map); 1966 if (error) { 1967 device_printf(dev, "Unable to create TX DMA map\n"); 1968 emx_destroy_tx_ring(sc, i); 1969 return error; 1970 } 1971 } 1972 return (0); 1973 } 1974 1975 static void 1976 emx_init_tx_ring(struct emx_softc *sc) 1977 { 1978 /* Clear the old ring contents */ 1979 bzero(sc->tx_desc_base, 1980 sizeof(struct e1000_tx_desc) * sc->num_tx_desc); 1981 1982 /* Reset state */ 1983 sc->next_avail_tx_desc = 0; 1984 sc->next_tx_to_clean = 0; 1985 sc->num_tx_desc_avail = sc->num_tx_desc; 1986 } 1987 1988 static void 1989 emx_init_tx_unit(struct emx_softc *sc) 1990 { 1991 uint32_t tctl, tarc, tipg = 0; 1992 uint64_t bus_addr; 1993 1994 /* Setup the Base and Length of the Tx Descriptor Ring */ 1995 bus_addr = sc->tx_desc_paddr; 1996 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(0), 1997 sc->num_tx_desc * sizeof(struct e1000_tx_desc)); 1998 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(0), 1999 (uint32_t)(bus_addr >> 32)); 2000 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(0), 2001 (uint32_t)bus_addr); 2002 /* Setup the HW Tx Head and Tail descriptor pointers */ 2003 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), 0); 2004 E1000_WRITE_REG(&sc->hw, E1000_TDH(0), 0); 2005 2006 /* Set the default values for the Tx Inter Packet Gap timer */ 2007 switch (sc->hw.mac.type) { 2008 case e1000_80003es2lan: 2009 tipg = DEFAULT_82543_TIPG_IPGR1; 2010 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 2011 E1000_TIPG_IPGR2_SHIFT; 2012 break; 2013 2014 default: 2015 if (sc->hw.phy.media_type == e1000_media_type_fiber || 2016 sc->hw.phy.media_type == e1000_media_type_internal_serdes) 2017 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2018 else 2019 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2020 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2021 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2022 break; 2023 } 2024 2025 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg); 2026 2027 /* NOTE: 0 is not allowed for TIDV */ 2028 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1); 2029 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0); 2030 2031 if (sc->hw.mac.type == e1000_82571 || 2032 sc->hw.mac.type == e1000_82572) { 2033 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0)); 2034 tarc |= EMX_TARC_SPEED_MODE; 2035 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc); 2036 } else if (sc->hw.mac.type == e1000_80003es2lan) { 2037 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0)); 2038 tarc |= 1; 2039 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc); 2040 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1)); 2041 tarc |= 1; 2042 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc); 2043 } 2044 2045 /* Program the Transmit Control Register */ 2046 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL); 2047 tctl &= ~E1000_TCTL_CT; 2048 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 2049 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2050 tctl |= E1000_TCTL_MULR; 2051 2052 /* This write will effectively turn on the transmit unit. */ 2053 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl); 2054 } 2055 2056 static void 2057 emx_destroy_tx_ring(struct emx_softc *sc, int ndesc) 2058 { 2059 struct emx_txbuf *tx_buffer; 2060 int i; 2061 2062 /* Free Transmit Descriptor ring */ 2063 if (sc->tx_desc_base) { 2064 bus_dmamap_unload(sc->tx_desc_dtag, sc->tx_desc_dmap); 2065 bus_dmamem_free(sc->tx_desc_dtag, sc->tx_desc_base, 2066 sc->tx_desc_dmap); 2067 bus_dma_tag_destroy(sc->tx_desc_dtag); 2068 2069 sc->tx_desc_base = NULL; 2070 } 2071 2072 if (sc->tx_buf == NULL) 2073 return; 2074 2075 for (i = 0; i < ndesc; i++) { 2076 tx_buffer = &sc->tx_buf[i]; 2077 2078 KKASSERT(tx_buffer->m_head == NULL); 2079 bus_dmamap_destroy(sc->txtag, tx_buffer->map); 2080 } 2081 bus_dma_tag_destroy(sc->txtag); 2082 2083 kfree(sc->tx_buf, M_DEVBUF); 2084 sc->tx_buf = NULL; 2085 } 2086 2087 /* 2088 * The offload context needs to be set when we transfer the first 2089 * packet of a particular protocol (TCP/UDP). This routine has been 2090 * enhanced to deal with inserted VLAN headers. 2091 * 2092 * If the new packet's ether header length, ip header length and 2093 * csum offloading type are same as the previous packet, we should 2094 * avoid allocating a new csum context descriptor; mainly to take 2095 * advantage of the pipeline effect of the TX data read request. 2096 * 2097 * This function returns number of TX descrptors allocated for 2098 * csum context. 2099 */ 2100 static int 2101 emx_txcsum(struct emx_softc *sc, struct mbuf *mp, 2102 uint32_t *txd_upper, uint32_t *txd_lower) 2103 { 2104 struct e1000_context_desc *TXD; 2105 struct emx_txbuf *tx_buffer; 2106 struct ether_vlan_header *eh; 2107 struct ip *ip; 2108 int curr_txd, ehdrlen, csum_flags; 2109 uint32_t cmd, hdr_len, ip_hlen; 2110 uint16_t etype; 2111 2112 /* 2113 * Determine where frame payload starts. 2114 * Jump over vlan headers if already present, 2115 * helpful for QinQ too. 2116 */ 2117 KASSERT(mp->m_len >= ETHER_HDR_LEN, 2118 ("emx_txcsum_pullup is not called (eh)?\n")); 2119 eh = mtod(mp, struct ether_vlan_header *); 2120 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2121 KASSERT(mp->m_len >= ETHER_HDR_LEN + EVL_ENCAPLEN, 2122 ("emx_txcsum_pullup is not called (evh)?\n")); 2123 etype = ntohs(eh->evl_proto); 2124 ehdrlen = ETHER_HDR_LEN + EVL_ENCAPLEN; 2125 } else { 2126 etype = ntohs(eh->evl_encap_proto); 2127 ehdrlen = ETHER_HDR_LEN; 2128 } 2129 2130 /* 2131 * We only support TCP/UDP for IPv4 for the moment. 2132 * TODO: Support SCTP too when it hits the tree. 2133 */ 2134 if (etype != ETHERTYPE_IP) 2135 return 0; 2136 2137 KASSERT(mp->m_len >= ehdrlen + EMX_IPVHL_SIZE, 2138 ("emx_txcsum_pullup is not called (eh+ip_vhl)?\n")); 2139 2140 /* NOTE: We could only safely access ip.ip_vhl part */ 2141 ip = (struct ip *)(mp->m_data + ehdrlen); 2142 ip_hlen = ip->ip_hl << 2; 2143 2144 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES; 2145 2146 if (sc->csum_ehlen == ehdrlen && sc->csum_iphlen == ip_hlen && 2147 sc->csum_flags == csum_flags) { 2148 /* 2149 * Same csum offload context as the previous packets; 2150 * just return. 2151 */ 2152 *txd_upper = sc->csum_txd_upper; 2153 *txd_lower = sc->csum_txd_lower; 2154 return 0; 2155 } 2156 2157 /* 2158 * Setup a new csum offload context. 2159 */ 2160 2161 curr_txd = sc->next_avail_tx_desc; 2162 tx_buffer = &sc->tx_buf[curr_txd]; 2163 TXD = (struct e1000_context_desc *)&sc->tx_desc_base[curr_txd]; 2164 2165 cmd = 0; 2166 2167 /* Setup of IP header checksum. */ 2168 if (csum_flags & CSUM_IP) { 2169 /* 2170 * Start offset for header checksum calculation. 2171 * End offset for header checksum calculation. 2172 * Offset of place to put the checksum. 2173 */ 2174 TXD->lower_setup.ip_fields.ipcss = ehdrlen; 2175 TXD->lower_setup.ip_fields.ipcse = 2176 htole16(ehdrlen + ip_hlen - 1); 2177 TXD->lower_setup.ip_fields.ipcso = 2178 ehdrlen + offsetof(struct ip, ip_sum); 2179 cmd |= E1000_TXD_CMD_IP; 2180 *txd_upper |= E1000_TXD_POPTS_IXSM << 8; 2181 } 2182 hdr_len = ehdrlen + ip_hlen; 2183 2184 if (csum_flags & CSUM_TCP) { 2185 /* 2186 * Start offset for payload checksum calculation. 2187 * End offset for payload checksum calculation. 2188 * Offset of place to put the checksum. 2189 */ 2190 TXD->upper_setup.tcp_fields.tucss = hdr_len; 2191 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2192 TXD->upper_setup.tcp_fields.tucso = 2193 hdr_len + offsetof(struct tcphdr, th_sum); 2194 cmd |= E1000_TXD_CMD_TCP; 2195 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 2196 } else if (csum_flags & CSUM_UDP) { 2197 /* 2198 * Start offset for header checksum calculation. 2199 * End offset for header checksum calculation. 2200 * Offset of place to put the checksum. 2201 */ 2202 TXD->upper_setup.tcp_fields.tucss = hdr_len; 2203 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2204 TXD->upper_setup.tcp_fields.tucso = 2205 hdr_len + offsetof(struct udphdr, uh_sum); 2206 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 2207 } 2208 2209 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */ 2210 E1000_TXD_DTYP_D; /* Data descr */ 2211 2212 /* Save the information for this csum offloading context */ 2213 sc->csum_ehlen = ehdrlen; 2214 sc->csum_iphlen = ip_hlen; 2215 sc->csum_flags = csum_flags; 2216 sc->csum_txd_upper = *txd_upper; 2217 sc->csum_txd_lower = *txd_lower; 2218 2219 TXD->tcp_seg_setup.data = htole32(0); 2220 TXD->cmd_and_length = 2221 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd); 2222 2223 if (++curr_txd == sc->num_tx_desc) 2224 curr_txd = 0; 2225 2226 KKASSERT(sc->num_tx_desc_avail > 0); 2227 sc->num_tx_desc_avail--; 2228 2229 sc->next_avail_tx_desc = curr_txd; 2230 return 1; 2231 } 2232 2233 static int 2234 emx_txcsum_pullup(struct emx_softc *sc, struct mbuf **m0) 2235 { 2236 struct mbuf *m = *m0; 2237 struct ether_header *eh; 2238 int len; 2239 2240 sc->tx_csum_try_pullup++; 2241 2242 len = ETHER_HDR_LEN + EMX_IPVHL_SIZE; 2243 2244 if (__predict_false(!M_WRITABLE(m))) { 2245 if (__predict_false(m->m_len < ETHER_HDR_LEN)) { 2246 sc->tx_csum_drop1++; 2247 m_freem(m); 2248 *m0 = NULL; 2249 return ENOBUFS; 2250 } 2251 eh = mtod(m, struct ether_header *); 2252 2253 if (eh->ether_type == htons(ETHERTYPE_VLAN)) 2254 len += EVL_ENCAPLEN; 2255 2256 if (m->m_len < len) { 2257 sc->tx_csum_drop2++; 2258 m_freem(m); 2259 *m0 = NULL; 2260 return ENOBUFS; 2261 } 2262 return 0; 2263 } 2264 2265 if (__predict_false(m->m_len < ETHER_HDR_LEN)) { 2266 sc->tx_csum_pullup1++; 2267 m = m_pullup(m, ETHER_HDR_LEN); 2268 if (m == NULL) { 2269 sc->tx_csum_pullup1_failed++; 2270 *m0 = NULL; 2271 return ENOBUFS; 2272 } 2273 *m0 = m; 2274 } 2275 eh = mtod(m, struct ether_header *); 2276 2277 if (eh->ether_type == htons(ETHERTYPE_VLAN)) 2278 len += EVL_ENCAPLEN; 2279 2280 if (m->m_len < len) { 2281 sc->tx_csum_pullup2++; 2282 m = m_pullup(m, len); 2283 if (m == NULL) { 2284 sc->tx_csum_pullup2_failed++; 2285 *m0 = NULL; 2286 return ENOBUFS; 2287 } 2288 *m0 = m; 2289 } 2290 return 0; 2291 } 2292 2293 static void 2294 emx_txeof(struct emx_softc *sc) 2295 { 2296 struct ifnet *ifp = &sc->arpcom.ac_if; 2297 struct emx_txbuf *tx_buffer; 2298 int first, num_avail; 2299 2300 if (sc->tx_dd_head == sc->tx_dd_tail) 2301 return; 2302 2303 if (sc->num_tx_desc_avail == sc->num_tx_desc) 2304 return; 2305 2306 num_avail = sc->num_tx_desc_avail; 2307 first = sc->next_tx_to_clean; 2308 2309 while (sc->tx_dd_head != sc->tx_dd_tail) { 2310 int dd_idx = sc->tx_dd[sc->tx_dd_head]; 2311 struct e1000_tx_desc *tx_desc; 2312 2313 tx_desc = &sc->tx_desc_base[dd_idx]; 2314 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) { 2315 EMX_INC_TXDD_IDX(sc->tx_dd_head); 2316 2317 if (++dd_idx == sc->num_tx_desc) 2318 dd_idx = 0; 2319 2320 while (first != dd_idx) { 2321 logif(pkt_txclean); 2322 2323 num_avail++; 2324 2325 tx_buffer = &sc->tx_buf[first]; 2326 if (tx_buffer->m_head) { 2327 ifp->if_opackets++; 2328 bus_dmamap_unload(sc->txtag, 2329 tx_buffer->map); 2330 m_freem(tx_buffer->m_head); 2331 tx_buffer->m_head = NULL; 2332 } 2333 2334 if (++first == sc->num_tx_desc) 2335 first = 0; 2336 } 2337 } else { 2338 break; 2339 } 2340 } 2341 sc->next_tx_to_clean = first; 2342 sc->num_tx_desc_avail = num_avail; 2343 2344 if (sc->tx_dd_head == sc->tx_dd_tail) { 2345 sc->tx_dd_head = 0; 2346 sc->tx_dd_tail = 0; 2347 } 2348 2349 if (!EMX_IS_OACTIVE(sc)) { 2350 ifp->if_flags &= ~IFF_OACTIVE; 2351 2352 /* All clean, turn off the timer */ 2353 if (sc->num_tx_desc_avail == sc->num_tx_desc) 2354 ifp->if_timer = 0; 2355 } 2356 } 2357 2358 static void 2359 emx_tx_collect(struct emx_softc *sc) 2360 { 2361 struct ifnet *ifp = &sc->arpcom.ac_if; 2362 struct emx_txbuf *tx_buffer; 2363 int tdh, first, num_avail, dd_idx = -1; 2364 2365 if (sc->num_tx_desc_avail == sc->num_tx_desc) 2366 return; 2367 2368 tdh = E1000_READ_REG(&sc->hw, E1000_TDH(0)); 2369 if (tdh == sc->next_tx_to_clean) 2370 return; 2371 2372 if (sc->tx_dd_head != sc->tx_dd_tail) 2373 dd_idx = sc->tx_dd[sc->tx_dd_head]; 2374 2375 num_avail = sc->num_tx_desc_avail; 2376 first = sc->next_tx_to_clean; 2377 2378 while (first != tdh) { 2379 logif(pkt_txclean); 2380 2381 num_avail++; 2382 2383 tx_buffer = &sc->tx_buf[first]; 2384 if (tx_buffer->m_head) { 2385 ifp->if_opackets++; 2386 bus_dmamap_unload(sc->txtag, 2387 tx_buffer->map); 2388 m_freem(tx_buffer->m_head); 2389 tx_buffer->m_head = NULL; 2390 } 2391 2392 if (first == dd_idx) { 2393 EMX_INC_TXDD_IDX(sc->tx_dd_head); 2394 if (sc->tx_dd_head == sc->tx_dd_tail) { 2395 sc->tx_dd_head = 0; 2396 sc->tx_dd_tail = 0; 2397 dd_idx = -1; 2398 } else { 2399 dd_idx = sc->tx_dd[sc->tx_dd_head]; 2400 } 2401 } 2402 2403 if (++first == sc->num_tx_desc) 2404 first = 0; 2405 } 2406 sc->next_tx_to_clean = first; 2407 sc->num_tx_desc_avail = num_avail; 2408 2409 if (!EMX_IS_OACTIVE(sc)) { 2410 ifp->if_flags &= ~IFF_OACTIVE; 2411 2412 /* All clean, turn off the timer */ 2413 if (sc->num_tx_desc_avail == sc->num_tx_desc) 2414 ifp->if_timer = 0; 2415 } 2416 } 2417 2418 /* 2419 * When Link is lost sometimes there is work still in the TX ring 2420 * which will result in a watchdog, rather than allow that do an 2421 * attempted cleanup and then reinit here. Note that this has been 2422 * seens mostly with fiber adapters. 2423 */ 2424 static void 2425 emx_tx_purge(struct emx_softc *sc) 2426 { 2427 struct ifnet *ifp = &sc->arpcom.ac_if; 2428 2429 if (!sc->link_active && ifp->if_timer) { 2430 emx_tx_collect(sc); 2431 if (ifp->if_timer) { 2432 if_printf(ifp, "Link lost, TX pending, reinit\n"); 2433 ifp->if_timer = 0; 2434 emx_init(sc); 2435 } 2436 } 2437 } 2438 2439 static int 2440 emx_newbuf(struct emx_softc *sc, struct emx_rxdata *rdata, int i, int init) 2441 { 2442 struct mbuf *m; 2443 bus_dma_segment_t seg; 2444 bus_dmamap_t map; 2445 struct emx_rxbuf *rx_buffer; 2446 int error, nseg; 2447 2448 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 2449 if (m == NULL) { 2450 rdata->mbuf_cluster_failed++; 2451 if (init) { 2452 if_printf(&sc->arpcom.ac_if, 2453 "Unable to allocate RX mbuf\n"); 2454 } 2455 return (ENOBUFS); 2456 } 2457 m->m_len = m->m_pkthdr.len = MCLBYTES; 2458 2459 if (sc->max_frame_size <= MCLBYTES - ETHER_ALIGN) 2460 m_adj(m, ETHER_ALIGN); 2461 2462 error = bus_dmamap_load_mbuf_segment(rdata->rxtag, 2463 rdata->rx_sparemap, m, 2464 &seg, 1, &nseg, BUS_DMA_NOWAIT); 2465 if (error) { 2466 m_freem(m); 2467 if (init) { 2468 if_printf(&sc->arpcom.ac_if, 2469 "Unable to load RX mbuf\n"); 2470 } 2471 return (error); 2472 } 2473 2474 rx_buffer = &rdata->rx_buf[i]; 2475 if (rx_buffer->m_head != NULL) 2476 bus_dmamap_unload(rdata->rxtag, rx_buffer->map); 2477 2478 map = rx_buffer->map; 2479 rx_buffer->map = rdata->rx_sparemap; 2480 rdata->rx_sparemap = map; 2481 2482 rx_buffer->m_head = m; 2483 rx_buffer->paddr = seg.ds_addr; 2484 2485 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer); 2486 return (0); 2487 } 2488 2489 static int 2490 emx_create_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata) 2491 { 2492 device_t dev = sc->dev; 2493 struct emx_rxbuf *rx_buffer; 2494 int i, error, rsize; 2495 2496 /* 2497 * Validate number of receive descriptors. It must not exceed 2498 * hardware maximum, and must be multiple of E1000_DBA_ALIGN. 2499 */ 2500 if ((emx_rxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 || 2501 emx_rxd > EMX_MAX_RXD || emx_rxd < EMX_MIN_RXD) { 2502 device_printf(dev, "Using %d RX descriptors instead of %d!\n", 2503 EMX_DEFAULT_RXD, emx_rxd); 2504 rdata->num_rx_desc = EMX_DEFAULT_RXD; 2505 } else { 2506 rdata->num_rx_desc = emx_rxd; 2507 } 2508 2509 /* 2510 * Allocate Receive Descriptor ring 2511 */ 2512 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t), 2513 EMX_DBA_ALIGN); 2514 rdata->rx_desc = bus_dmamem_coherent_any(sc->parent_dtag, 2515 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK, 2516 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap, 2517 &rdata->rx_desc_paddr); 2518 if (rdata->rx_desc == NULL) { 2519 device_printf(dev, "Unable to allocate rx_desc memory\n"); 2520 return ENOMEM; 2521 } 2522 2523 rdata->rx_buf = kmalloc(sizeof(struct emx_rxbuf) * rdata->num_rx_desc, 2524 M_DEVBUF, M_WAITOK | M_ZERO); 2525 2526 /* 2527 * Create DMA tag for rx buffers 2528 */ 2529 error = bus_dma_tag_create(sc->parent_dtag, /* parent */ 2530 1, 0, /* alignment, bounds */ 2531 BUS_SPACE_MAXADDR, /* lowaddr */ 2532 BUS_SPACE_MAXADDR, /* highaddr */ 2533 NULL, NULL, /* filter, filterarg */ 2534 MCLBYTES, /* maxsize */ 2535 1, /* nsegments */ 2536 MCLBYTES, /* maxsegsize */ 2537 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */ 2538 &rdata->rxtag); 2539 if (error) { 2540 device_printf(dev, "Unable to allocate RX DMA tag\n"); 2541 kfree(rdata->rx_buf, M_DEVBUF); 2542 rdata->rx_buf = NULL; 2543 return error; 2544 } 2545 2546 /* 2547 * Create spare DMA map for rx buffers 2548 */ 2549 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK, 2550 &rdata->rx_sparemap); 2551 if (error) { 2552 device_printf(dev, "Unable to create spare RX DMA map\n"); 2553 bus_dma_tag_destroy(rdata->rxtag); 2554 kfree(rdata->rx_buf, M_DEVBUF); 2555 rdata->rx_buf = NULL; 2556 return error; 2557 } 2558 2559 /* 2560 * Create DMA maps for rx buffers 2561 */ 2562 for (i = 0; i < rdata->num_rx_desc; i++) { 2563 rx_buffer = &rdata->rx_buf[i]; 2564 2565 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK, 2566 &rx_buffer->map); 2567 if (error) { 2568 device_printf(dev, "Unable to create RX DMA map\n"); 2569 emx_destroy_rx_ring(sc, rdata, i); 2570 return error; 2571 } 2572 } 2573 return (0); 2574 } 2575 2576 static void 2577 emx_free_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata) 2578 { 2579 int i; 2580 2581 for (i = 0; i < rdata->num_rx_desc; i++) { 2582 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i]; 2583 2584 if (rx_buffer->m_head != NULL) { 2585 bus_dmamap_unload(rdata->rxtag, rx_buffer->map); 2586 m_freem(rx_buffer->m_head); 2587 rx_buffer->m_head = NULL; 2588 } 2589 } 2590 2591 if (rdata->fmp != NULL) 2592 m_freem(rdata->fmp); 2593 rdata->fmp = NULL; 2594 rdata->lmp = NULL; 2595 } 2596 2597 static int 2598 emx_init_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata) 2599 { 2600 int i, error; 2601 2602 /* Reset descriptor ring */ 2603 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc); 2604 2605 /* Allocate new ones. */ 2606 for (i = 0; i < rdata->num_rx_desc; i++) { 2607 error = emx_newbuf(sc, rdata, i, 1); 2608 if (error) 2609 return (error); 2610 } 2611 2612 /* Setup our descriptor pointers */ 2613 rdata->next_rx_desc_to_check = 0; 2614 2615 return (0); 2616 } 2617 2618 static void 2619 emx_init_rx_unit(struct emx_softc *sc) 2620 { 2621 struct ifnet *ifp = &sc->arpcom.ac_if; 2622 uint64_t bus_addr; 2623 uint32_t rctl, itr, rfctl; 2624 int i; 2625 2626 /* 2627 * Make sure receives are disabled while setting 2628 * up the descriptor ring 2629 */ 2630 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2631 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2632 2633 /* 2634 * Set the interrupt throttling rate. Value is calculated 2635 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns) 2636 */ 2637 if (sc->int_throttle_ceil) 2638 itr = 1000000000 / 256 / sc->int_throttle_ceil; 2639 else 2640 itr = 0; 2641 emx_set_itr(sc, itr); 2642 2643 /* Use extended RX descriptor */ 2644 rfctl = E1000_RFCTL_EXTEN; 2645 2646 /* Disable accelerated ackknowledge */ 2647 if (sc->hw.mac.type == e1000_82574) 2648 rfctl |= E1000_RFCTL_ACK_DIS; 2649 2650 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl); 2651 2652 /* 2653 * Receive Checksum Offload for TCP and UDP 2654 * 2655 * Checksum offloading is also enabled if multiple receive 2656 * queue is to be supported, since we need it to figure out 2657 * packet type. 2658 */ 2659 if (ifp->if_capenable & (IFCAP_RSS | IFCAP_RXCSUM)) { 2660 uint32_t rxcsum; 2661 2662 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM); 2663 2664 /* 2665 * NOTE: 2666 * PCSD must be enabled to enable multiple 2667 * receive queues. 2668 */ 2669 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL | 2670 E1000_RXCSUM_PCSD; 2671 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum); 2672 } 2673 2674 /* 2675 * Configure multiple receive queue (RSS) 2676 */ 2677 if (ifp->if_capenable & IFCAP_RSS) { 2678 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE]; 2679 uint32_t reta; 2680 2681 KASSERT(sc->rx_ring_inuse == EMX_NRX_RING, 2682 ("invalid number of RX ring (%d)", 2683 sc->rx_ring_inuse)); 2684 2685 /* 2686 * NOTE: 2687 * When we reach here, RSS has already been disabled 2688 * in emx_stop(), so we could safely configure RSS key 2689 * and redirect table. 2690 */ 2691 2692 /* 2693 * Configure RSS key 2694 */ 2695 toeplitz_get_key(key, sizeof(key)); 2696 for (i = 0; i < EMX_NRSSRK; ++i) { 2697 uint32_t rssrk; 2698 2699 rssrk = EMX_RSSRK_VAL(key, i); 2700 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk); 2701 2702 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk); 2703 } 2704 2705 /* 2706 * Configure RSS redirect table in following fashion: 2707 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2708 */ 2709 reta = 0; 2710 for (i = 0; i < EMX_RETA_SIZE; ++i) { 2711 uint32_t q; 2712 2713 q = (i % sc->rx_ring_inuse) << EMX_RETA_RINGIDX_SHIFT; 2714 reta |= q << (8 * i); 2715 } 2716 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta); 2717 2718 for (i = 0; i < EMX_NRETA; ++i) 2719 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta); 2720 2721 /* 2722 * Enable multiple receive queues. 2723 * Enable IPv4 RSS standard hash functions. 2724 * Disable RSS interrupt. 2725 */ 2726 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 2727 E1000_MRQC_ENABLE_RSS_2Q | 2728 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2729 E1000_MRQC_RSS_FIELD_IPV4); 2730 } 2731 2732 /* 2733 * XXX TEMPORARY WORKAROUND: on some systems with 82573 2734 * long latencies are observed, like Lenovo X60. This 2735 * change eliminates the problem, but since having positive 2736 * values in RDTR is a known source of problems on other 2737 * platforms another solution is being sought. 2738 */ 2739 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) { 2740 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573); 2741 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573); 2742 } 2743 2744 for (i = 0; i < sc->rx_ring_inuse; ++i) { 2745 struct emx_rxdata *rdata = &sc->rx_data[i]; 2746 2747 /* 2748 * Setup the Base and Length of the Rx Descriptor Ring 2749 */ 2750 bus_addr = rdata->rx_desc_paddr; 2751 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i), 2752 rdata->num_rx_desc * sizeof(emx_rxdesc_t)); 2753 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i), 2754 (uint32_t)(bus_addr >> 32)); 2755 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i), 2756 (uint32_t)bus_addr); 2757 2758 /* 2759 * Setup the HW Rx Head and Tail Descriptor Pointers 2760 */ 2761 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0); 2762 E1000_WRITE_REG(&sc->hw, E1000_RDT(i), 2763 sc->rx_data[i].num_rx_desc - 1); 2764 } 2765 2766 /* Setup the Receive Control Register */ 2767 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 2768 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 2769 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC | 2770 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 2771 2772 /* Make sure VLAN Filters are off */ 2773 rctl &= ~E1000_RCTL_VFE; 2774 2775 /* Don't store bad paket */ 2776 rctl &= ~E1000_RCTL_SBP; 2777 2778 /* MCLBYTES */ 2779 rctl |= E1000_RCTL_SZ_2048; 2780 2781 if (ifp->if_mtu > ETHERMTU) 2782 rctl |= E1000_RCTL_LPE; 2783 else 2784 rctl &= ~E1000_RCTL_LPE; 2785 2786 /* Enable Receives */ 2787 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl); 2788 } 2789 2790 static void 2791 emx_destroy_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata, int ndesc) 2792 { 2793 struct emx_rxbuf *rx_buffer; 2794 int i; 2795 2796 /* Free Receive Descriptor ring */ 2797 if (rdata->rx_desc) { 2798 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap); 2799 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc, 2800 rdata->rx_desc_dmap); 2801 bus_dma_tag_destroy(rdata->rx_desc_dtag); 2802 2803 rdata->rx_desc = NULL; 2804 } 2805 2806 if (rdata->rx_buf == NULL) 2807 return; 2808 2809 for (i = 0; i < ndesc; i++) { 2810 rx_buffer = &rdata->rx_buf[i]; 2811 2812 KKASSERT(rx_buffer->m_head == NULL); 2813 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map); 2814 } 2815 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap); 2816 bus_dma_tag_destroy(rdata->rxtag); 2817 2818 kfree(rdata->rx_buf, M_DEVBUF); 2819 rdata->rx_buf = NULL; 2820 } 2821 2822 static void 2823 emx_rxeof(struct emx_softc *sc, int ring_idx, int count) 2824 { 2825 struct emx_rxdata *rdata = &sc->rx_data[ring_idx]; 2826 struct ifnet *ifp = &sc->arpcom.ac_if; 2827 uint32_t staterr; 2828 emx_rxdesc_t *current_desc; 2829 struct mbuf *mp; 2830 int i; 2831 struct mbuf_chain chain[MAXCPU]; 2832 2833 i = rdata->next_rx_desc_to_check; 2834 current_desc = &rdata->rx_desc[i]; 2835 staterr = le32toh(current_desc->rxd_staterr); 2836 2837 if (!(staterr & E1000_RXD_STAT_DD)) 2838 return; 2839 2840 ether_input_chain_init(chain); 2841 2842 while ((staterr & E1000_RXD_STAT_DD) && count != 0) { 2843 struct pktinfo *pi = NULL, pi0; 2844 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i]; 2845 struct mbuf *m = NULL; 2846 int eop, len; 2847 2848 logif(pkt_receive); 2849 2850 mp = rx_buf->m_head; 2851 2852 /* 2853 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT 2854 * needs to access the last received byte in the mbuf. 2855 */ 2856 bus_dmamap_sync(rdata->rxtag, rx_buf->map, 2857 BUS_DMASYNC_POSTREAD); 2858 2859 len = le16toh(current_desc->rxd_length); 2860 if (staterr & E1000_RXD_STAT_EOP) { 2861 count--; 2862 eop = 1; 2863 } else { 2864 eop = 0; 2865 } 2866 2867 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) { 2868 uint16_t vlan = 0; 2869 uint32_t mrq, rss_hash; 2870 2871 /* 2872 * Save several necessary information, 2873 * before emx_newbuf() destroy it. 2874 */ 2875 if ((staterr & E1000_RXD_STAT_VP) && eop) 2876 vlan = le16toh(current_desc->rxd_vlan); 2877 2878 mrq = le32toh(current_desc->rxd_mrq); 2879 rss_hash = le32toh(current_desc->rxd_rss); 2880 2881 EMX_RSS_DPRINTF(sc, 10, 2882 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n", 2883 ring_idx, mrq, rss_hash); 2884 2885 if (emx_newbuf(sc, rdata, i, 0) != 0) { 2886 ifp->if_iqdrops++; 2887 goto discard; 2888 } 2889 2890 /* Assign correct length to the current fragment */ 2891 mp->m_len = len; 2892 2893 if (rdata->fmp == NULL) { 2894 mp->m_pkthdr.len = len; 2895 rdata->fmp = mp; /* Store the first mbuf */ 2896 rdata->lmp = mp; 2897 } else { 2898 /* 2899 * Chain mbuf's together 2900 */ 2901 rdata->lmp->m_next = mp; 2902 rdata->lmp = rdata->lmp->m_next; 2903 rdata->fmp->m_pkthdr.len += len; 2904 } 2905 2906 if (eop) { 2907 rdata->fmp->m_pkthdr.rcvif = ifp; 2908 ifp->if_ipackets++; 2909 2910 if (ifp->if_capenable & IFCAP_RXCSUM) 2911 emx_rxcsum(staterr, rdata->fmp); 2912 2913 if (staterr & E1000_RXD_STAT_VP) { 2914 rdata->fmp->m_pkthdr.ether_vlantag = 2915 vlan; 2916 rdata->fmp->m_flags |= M_VLANTAG; 2917 } 2918 m = rdata->fmp; 2919 rdata->fmp = NULL; 2920 rdata->lmp = NULL; 2921 2922 if (ifp->if_capenable & IFCAP_RSS) { 2923 pi = emx_rssinfo(m, &pi0, mrq, 2924 rss_hash, staterr); 2925 } 2926 #ifdef EMX_RSS_DEBUG 2927 rdata->rx_pkts++; 2928 #endif 2929 } 2930 } else { 2931 ifp->if_ierrors++; 2932 discard: 2933 emx_setup_rxdesc(current_desc, rx_buf); 2934 if (rdata->fmp != NULL) { 2935 m_freem(rdata->fmp); 2936 rdata->fmp = NULL; 2937 rdata->lmp = NULL; 2938 } 2939 m = NULL; 2940 } 2941 2942 if (m != NULL) 2943 ether_input_chain(ifp, m, pi, chain); 2944 2945 /* Advance our pointers to the next descriptor. */ 2946 if (++i == rdata->num_rx_desc) 2947 i = 0; 2948 2949 current_desc = &rdata->rx_desc[i]; 2950 staterr = le32toh(current_desc->rxd_staterr); 2951 } 2952 rdata->next_rx_desc_to_check = i; 2953 2954 ether_input_dispatch(chain); 2955 2956 /* Advance the E1000's Receive Queue "Tail Pointer". */ 2957 if (--i < 0) 2958 i = rdata->num_rx_desc - 1; 2959 E1000_WRITE_REG(&sc->hw, E1000_RDT(ring_idx), i); 2960 } 2961 2962 static void 2963 emx_enable_intr(struct emx_softc *sc) 2964 { 2965 uint32_t ims_mask = IMS_ENABLE_MASK; 2966 2967 lwkt_serialize_handler_enable(&sc->main_serialize); 2968 2969 #if 0 2970 if (sc->hw.mac.type == e1000_82574) { 2971 E1000_WRITE_REG(hw, EMX_EIAC, EM_MSIX_MASK); 2972 ims_mask |= EM_MSIX_MASK; 2973 } 2974 #endif 2975 E1000_WRITE_REG(&sc->hw, E1000_IMS, ims_mask); 2976 } 2977 2978 static void 2979 emx_disable_intr(struct emx_softc *sc) 2980 { 2981 if (sc->hw.mac.type == e1000_82574) 2982 E1000_WRITE_REG(&sc->hw, EMX_EIAC, 0); 2983 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff); 2984 2985 lwkt_serialize_handler_disable(&sc->main_serialize); 2986 } 2987 2988 /* 2989 * Bit of a misnomer, what this really means is 2990 * to enable OS management of the system... aka 2991 * to disable special hardware management features 2992 */ 2993 static void 2994 emx_get_mgmt(struct emx_softc *sc) 2995 { 2996 /* A shared code workaround */ 2997 if (sc->has_manage) { 2998 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H); 2999 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3000 3001 /* disable hardware interception of ARP */ 3002 manc &= ~(E1000_MANC_ARP_EN); 3003 3004 /* enable receiving management packets to the host */ 3005 manc |= E1000_MANC_EN_MNG2HOST; 3006 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3007 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3008 manc2h |= E1000_MNG2HOST_PORT_623; 3009 manc2h |= E1000_MNG2HOST_PORT_664; 3010 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h); 3011 3012 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3013 } 3014 } 3015 3016 /* 3017 * Give control back to hardware management 3018 * controller if there is one. 3019 */ 3020 static void 3021 emx_rel_mgmt(struct emx_softc *sc) 3022 { 3023 if (sc->has_manage) { 3024 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3025 3026 /* re-enable hardware interception of ARP */ 3027 manc |= E1000_MANC_ARP_EN; 3028 manc &= ~E1000_MANC_EN_MNG2HOST; 3029 3030 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3031 } 3032 } 3033 3034 /* 3035 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3036 * For ASF and Pass Through versions of f/w this means that 3037 * the driver is loaded. For AMT version (only with 82573) 3038 * of the f/w this means that the network i/f is open. 3039 */ 3040 static void 3041 emx_get_hw_control(struct emx_softc *sc) 3042 { 3043 /* Let firmware know the driver has taken over */ 3044 if (sc->hw.mac.type == e1000_82573) { 3045 uint32_t swsm; 3046 3047 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3048 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3049 swsm | E1000_SWSM_DRV_LOAD); 3050 } else { 3051 uint32_t ctrl_ext; 3052 3053 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3054 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3055 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3056 } 3057 sc->control_hw = 1; 3058 } 3059 3060 /* 3061 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3062 * For ASF and Pass Through versions of f/w this means that the 3063 * driver is no longer loaded. For AMT version (only with 82573) 3064 * of the f/w this means that the network i/f is closed. 3065 */ 3066 static void 3067 emx_rel_hw_control(struct emx_softc *sc) 3068 { 3069 if (!sc->control_hw) 3070 return; 3071 sc->control_hw = 0; 3072 3073 /* Let firmware taken over control of h/w */ 3074 if (sc->hw.mac.type == e1000_82573) { 3075 uint32_t swsm; 3076 3077 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3078 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3079 swsm & ~E1000_SWSM_DRV_LOAD); 3080 } else { 3081 uint32_t ctrl_ext; 3082 3083 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3084 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3085 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3086 } 3087 } 3088 3089 static int 3090 emx_is_valid_eaddr(const uint8_t *addr) 3091 { 3092 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 }; 3093 3094 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN)) 3095 return (FALSE); 3096 3097 return (TRUE); 3098 } 3099 3100 /* 3101 * Enable PCI Wake On Lan capability 3102 */ 3103 void 3104 emx_enable_wol(device_t dev) 3105 { 3106 uint16_t cap, status; 3107 uint8_t id; 3108 3109 /* First find the capabilities pointer*/ 3110 cap = pci_read_config(dev, PCIR_CAP_PTR, 2); 3111 3112 /* Read the PM Capabilities */ 3113 id = pci_read_config(dev, cap, 1); 3114 if (id != PCIY_PMG) /* Something wrong */ 3115 return; 3116 3117 /* 3118 * OK, we have the power capabilities, 3119 * so now get the status register 3120 */ 3121 cap += PCIR_POWER_STATUS; 3122 status = pci_read_config(dev, cap, 2); 3123 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3124 pci_write_config(dev, cap, status, 2); 3125 } 3126 3127 static void 3128 emx_update_stats(struct emx_softc *sc) 3129 { 3130 struct ifnet *ifp = &sc->arpcom.ac_if; 3131 3132 if (sc->hw.phy.media_type == e1000_media_type_copper || 3133 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3134 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS); 3135 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC); 3136 } 3137 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS); 3138 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC); 3139 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC); 3140 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL); 3141 3142 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC); 3143 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL); 3144 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC); 3145 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC); 3146 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC); 3147 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC); 3148 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC); 3149 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC); 3150 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC); 3151 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC); 3152 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64); 3153 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127); 3154 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255); 3155 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511); 3156 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023); 3157 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522); 3158 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC); 3159 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC); 3160 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC); 3161 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC); 3162 3163 /* For the 64-bit byte counters the low dword must be read first. */ 3164 /* Both registers clear on the read of the high dword */ 3165 3166 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH); 3167 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH); 3168 3169 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC); 3170 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC); 3171 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC); 3172 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC); 3173 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC); 3174 3175 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH); 3176 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH); 3177 3178 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR); 3179 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT); 3180 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64); 3181 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127); 3182 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255); 3183 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511); 3184 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023); 3185 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522); 3186 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC); 3187 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC); 3188 3189 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC); 3190 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC); 3191 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS); 3192 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR); 3193 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC); 3194 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC); 3195 3196 ifp->if_collisions = sc->stats.colc; 3197 3198 /* Rx Errors */ 3199 ifp->if_ierrors = sc->dropped_pkts + sc->stats.rxerrc + 3200 sc->stats.crcerrs + sc->stats.algnerrc + 3201 sc->stats.ruc + sc->stats.roc + 3202 sc->stats.mpc + sc->stats.cexterr; 3203 3204 /* Tx Errors */ 3205 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol + 3206 sc->watchdog_events; 3207 } 3208 3209 static void 3210 emx_print_debug_info(struct emx_softc *sc) 3211 { 3212 device_t dev = sc->dev; 3213 uint8_t *hw_addr = sc->hw.hw_addr; 3214 3215 device_printf(dev, "Adapter hardware address = %p \n", hw_addr); 3216 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n", 3217 E1000_READ_REG(&sc->hw, E1000_CTRL), 3218 E1000_READ_REG(&sc->hw, E1000_RCTL)); 3219 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n", 3220 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\ 3221 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) ); 3222 device_printf(dev, "Flow control watermarks high = %d low = %d\n", 3223 sc->hw.fc.high_water, sc->hw.fc.low_water); 3224 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n", 3225 E1000_READ_REG(&sc->hw, E1000_TIDV), 3226 E1000_READ_REG(&sc->hw, E1000_TADV)); 3227 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n", 3228 E1000_READ_REG(&sc->hw, E1000_RDTR), 3229 E1000_READ_REG(&sc->hw, E1000_RADV)); 3230 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 3231 E1000_READ_REG(&sc->hw, E1000_TDH(0)), 3232 E1000_READ_REG(&sc->hw, E1000_TDT(0))); 3233 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 3234 E1000_READ_REG(&sc->hw, E1000_RDH(0)), 3235 E1000_READ_REG(&sc->hw, E1000_RDT(0))); 3236 device_printf(dev, "Num Tx descriptors avail = %d\n", 3237 sc->num_tx_desc_avail); 3238 device_printf(dev, "Tx Descriptors not avail1 = %ld\n", 3239 sc->no_tx_desc_avail1); 3240 device_printf(dev, "Tx Descriptors not avail2 = %ld\n", 3241 sc->no_tx_desc_avail2); 3242 device_printf(dev, "Std mbuf failed = %ld\n", 3243 sc->mbuf_alloc_failed); 3244 device_printf(dev, "Std mbuf cluster failed = %ld\n", 3245 sc->rx_data[0].mbuf_cluster_failed); 3246 device_printf(dev, "Driver dropped packets = %ld\n", 3247 sc->dropped_pkts); 3248 device_printf(dev, "Driver tx dma failure in encap = %ld\n", 3249 sc->no_tx_dma_setup); 3250 3251 device_printf(dev, "TXCSUM try pullup = %lu\n", 3252 sc->tx_csum_try_pullup); 3253 device_printf(dev, "TXCSUM m_pullup(eh) called = %lu\n", 3254 sc->tx_csum_pullup1); 3255 device_printf(dev, "TXCSUM m_pullup(eh) failed = %lu\n", 3256 sc->tx_csum_pullup1_failed); 3257 device_printf(dev, "TXCSUM m_pullup(eh+ip) called = %lu\n", 3258 sc->tx_csum_pullup2); 3259 device_printf(dev, "TXCSUM m_pullup(eh+ip) failed = %lu\n", 3260 sc->tx_csum_pullup2_failed); 3261 device_printf(dev, "TXCSUM non-writable(eh) droped = %lu\n", 3262 sc->tx_csum_drop1); 3263 device_printf(dev, "TXCSUM non-writable(eh+ip) droped = %lu\n", 3264 sc->tx_csum_drop2); 3265 } 3266 3267 static void 3268 emx_print_hw_stats(struct emx_softc *sc) 3269 { 3270 device_t dev = sc->dev; 3271 3272 device_printf(dev, "Excessive collisions = %lld\n", 3273 (long long)sc->stats.ecol); 3274 #if (DEBUG_HW > 0) /* Dont output these errors normally */ 3275 device_printf(dev, "Symbol errors = %lld\n", 3276 (long long)sc->stats.symerrs); 3277 #endif 3278 device_printf(dev, "Sequence errors = %lld\n", 3279 (long long)sc->stats.sec); 3280 device_printf(dev, "Defer count = %lld\n", 3281 (long long)sc->stats.dc); 3282 device_printf(dev, "Missed Packets = %lld\n", 3283 (long long)sc->stats.mpc); 3284 device_printf(dev, "Receive No Buffers = %lld\n", 3285 (long long)sc->stats.rnbc); 3286 /* RLEC is inaccurate on some hardware, calculate our own. */ 3287 device_printf(dev, "Receive Length Errors = %lld\n", 3288 ((long long)sc->stats.roc + (long long)sc->stats.ruc)); 3289 device_printf(dev, "Receive errors = %lld\n", 3290 (long long)sc->stats.rxerrc); 3291 device_printf(dev, "Crc errors = %lld\n", 3292 (long long)sc->stats.crcerrs); 3293 device_printf(dev, "Alignment errors = %lld\n", 3294 (long long)sc->stats.algnerrc); 3295 device_printf(dev, "Collision/Carrier extension errors = %lld\n", 3296 (long long)sc->stats.cexterr); 3297 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns); 3298 device_printf(dev, "watchdog timeouts = %ld\n", 3299 sc->watchdog_events); 3300 device_printf(dev, "XON Rcvd = %lld\n", 3301 (long long)sc->stats.xonrxc); 3302 device_printf(dev, "XON Xmtd = %lld\n", 3303 (long long)sc->stats.xontxc); 3304 device_printf(dev, "XOFF Rcvd = %lld\n", 3305 (long long)sc->stats.xoffrxc); 3306 device_printf(dev, "XOFF Xmtd = %lld\n", 3307 (long long)sc->stats.xofftxc); 3308 device_printf(dev, "Good Packets Rcvd = %lld\n", 3309 (long long)sc->stats.gprc); 3310 device_printf(dev, "Good Packets Xmtd = %lld\n", 3311 (long long)sc->stats.gptc); 3312 } 3313 3314 static void 3315 emx_print_nvm_info(struct emx_softc *sc) 3316 { 3317 uint16_t eeprom_data; 3318 int i, j, row = 0; 3319 3320 /* Its a bit crude, but it gets the job done */ 3321 kprintf("\nInterface EEPROM Dump:\n"); 3322 kprintf("Offset\n0x0000 "); 3323 for (i = 0, j = 0; i < 32; i++, j++) { 3324 if (j == 8) { /* Make the offset block */ 3325 j = 0; ++row; 3326 kprintf("\n0x00%x0 ",row); 3327 } 3328 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data); 3329 kprintf("%04x ", eeprom_data); 3330 } 3331 kprintf("\n"); 3332 } 3333 3334 static int 3335 emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 3336 { 3337 struct emx_softc *sc; 3338 struct ifnet *ifp; 3339 int error, result; 3340 3341 result = -1; 3342 error = sysctl_handle_int(oidp, &result, 0, req); 3343 if (error || !req->newptr) 3344 return (error); 3345 3346 sc = (struct emx_softc *)arg1; 3347 ifp = &sc->arpcom.ac_if; 3348 3349 ifnet_serialize_all(ifp); 3350 3351 if (result == 1) 3352 emx_print_debug_info(sc); 3353 3354 /* 3355 * This value will cause a hex dump of the 3356 * first 32 16-bit words of the EEPROM to 3357 * the screen. 3358 */ 3359 if (result == 2) 3360 emx_print_nvm_info(sc); 3361 3362 ifnet_deserialize_all(ifp); 3363 3364 return (error); 3365 } 3366 3367 static int 3368 emx_sysctl_stats(SYSCTL_HANDLER_ARGS) 3369 { 3370 int error, result; 3371 3372 result = -1; 3373 error = sysctl_handle_int(oidp, &result, 0, req); 3374 if (error || !req->newptr) 3375 return (error); 3376 3377 if (result == 1) { 3378 struct emx_softc *sc = (struct emx_softc *)arg1; 3379 struct ifnet *ifp = &sc->arpcom.ac_if; 3380 3381 ifnet_serialize_all(ifp); 3382 emx_print_hw_stats(sc); 3383 ifnet_deserialize_all(ifp); 3384 } 3385 return (error); 3386 } 3387 3388 static void 3389 emx_add_sysctl(struct emx_softc *sc) 3390 { 3391 #ifdef EMX_RSS_DEBUG 3392 char rx_pkt[32]; 3393 int i; 3394 #endif 3395 3396 sysctl_ctx_init(&sc->sysctl_ctx); 3397 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 3398 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 3399 device_get_nameunit(sc->dev), 3400 CTLFLAG_RD, 0, ""); 3401 if (sc->sysctl_tree == NULL) { 3402 device_printf(sc->dev, "can't add sysctl node\n"); 3403 return; 3404 } 3405 3406 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3407 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 3408 emx_sysctl_debug_info, "I", "Debug Information"); 3409 3410 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3411 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 3412 emx_sysctl_stats, "I", "Statistics"); 3413 3414 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3415 OID_AUTO, "rxd", CTLFLAG_RD, 3416 &sc->rx_data[0].num_rx_desc, 0, NULL); 3417 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3418 OID_AUTO, "txd", CTLFLAG_RD, &sc->num_tx_desc, 0, NULL); 3419 3420 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3421 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW, 3422 sc, 0, emx_sysctl_int_throttle, "I", 3423 "interrupt throttling rate"); 3424 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3425 OID_AUTO, "int_tx_nsegs", CTLTYPE_INT|CTLFLAG_RW, 3426 sc, 0, emx_sysctl_int_tx_nsegs, "I", 3427 "# segments per TX interrupt"); 3428 3429 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3430 OID_AUTO, "rx_ring_inuse", CTLFLAG_RD, 3431 &sc->rx_ring_inuse, 0, "RX ring in use"); 3432 3433 #ifdef EMX_RSS_DEBUG 3434 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 3435 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 3436 0, "RSS debug level"); 3437 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3438 ksnprintf(rx_pkt, sizeof(rx_pkt), "rx%d_pkt", i); 3439 SYSCTL_ADD_UINT(&sc->sysctl_ctx, 3440 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, 3441 rx_pkt, CTLFLAG_RW, 3442 &sc->rx_data[i].rx_pkts, 0, "RXed packets"); 3443 } 3444 #endif 3445 } 3446 3447 static int 3448 emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS) 3449 { 3450 struct emx_softc *sc = (void *)arg1; 3451 struct ifnet *ifp = &sc->arpcom.ac_if; 3452 int error, throttle; 3453 3454 throttle = sc->int_throttle_ceil; 3455 error = sysctl_handle_int(oidp, &throttle, 0, req); 3456 if (error || req->newptr == NULL) 3457 return error; 3458 if (throttle < 0 || throttle > 1000000000 / 256) 3459 return EINVAL; 3460 3461 if (throttle) { 3462 /* 3463 * Set the interrupt throttling rate in 256ns increments, 3464 * recalculate sysctl value assignment to get exact frequency. 3465 */ 3466 throttle = 1000000000 / 256 / throttle; 3467 3468 /* Upper 16bits of ITR is reserved and should be zero */ 3469 if (throttle & 0xffff0000) 3470 return EINVAL; 3471 } 3472 3473 ifnet_serialize_all(ifp); 3474 3475 if (throttle) 3476 sc->int_throttle_ceil = 1000000000 / 256 / throttle; 3477 else 3478 sc->int_throttle_ceil = 0; 3479 3480 if (ifp->if_flags & IFF_RUNNING) 3481 emx_set_itr(sc, throttle); 3482 3483 ifnet_deserialize_all(ifp); 3484 3485 if (bootverbose) { 3486 if_printf(ifp, "Interrupt moderation set to %d/sec\n", 3487 sc->int_throttle_ceil); 3488 } 3489 return 0; 3490 } 3491 3492 static int 3493 emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS) 3494 { 3495 struct emx_softc *sc = (void *)arg1; 3496 struct ifnet *ifp = &sc->arpcom.ac_if; 3497 int error, segs; 3498 3499 segs = sc->tx_int_nsegs; 3500 error = sysctl_handle_int(oidp, &segs, 0, req); 3501 if (error || req->newptr == NULL) 3502 return error; 3503 if (segs <= 0) 3504 return EINVAL; 3505 3506 ifnet_serialize_all(ifp); 3507 3508 /* 3509 * Don't allow int_tx_nsegs to become: 3510 * o Less the oact_tx_desc 3511 * o Too large that no TX desc will cause TX interrupt to 3512 * be generated (OACTIVE will never recover) 3513 * o Too small that will cause tx_dd[] overflow 3514 */ 3515 if (segs < sc->oact_tx_desc || 3516 segs >= sc->num_tx_desc - sc->oact_tx_desc || 3517 segs < sc->num_tx_desc / EMX_TXDD_SAFE) { 3518 error = EINVAL; 3519 } else { 3520 error = 0; 3521 sc->tx_int_nsegs = segs; 3522 } 3523 3524 ifnet_deserialize_all(ifp); 3525 3526 return error; 3527 } 3528 3529 static int 3530 emx_dma_alloc(struct emx_softc *sc) 3531 { 3532 int error, i; 3533 3534 /* 3535 * Create top level busdma tag 3536 */ 3537 error = bus_dma_tag_create(NULL, 1, 0, 3538 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 3539 NULL, NULL, 3540 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 3541 0, &sc->parent_dtag); 3542 if (error) { 3543 device_printf(sc->dev, "could not create top level DMA tag\n"); 3544 return error; 3545 } 3546 3547 /* 3548 * Allocate transmit descriptors ring and buffers 3549 */ 3550 error = emx_create_tx_ring(sc); 3551 if (error) { 3552 device_printf(sc->dev, "Could not setup transmit structures\n"); 3553 return error; 3554 } 3555 3556 /* 3557 * Allocate receive descriptors ring and buffers 3558 */ 3559 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3560 error = emx_create_rx_ring(sc, &sc->rx_data[i]); 3561 if (error) { 3562 device_printf(sc->dev, 3563 "Could not setup receive structures\n"); 3564 return error; 3565 } 3566 } 3567 return 0; 3568 } 3569 3570 static void 3571 emx_dma_free(struct emx_softc *sc) 3572 { 3573 int i; 3574 3575 emx_destroy_tx_ring(sc, sc->num_tx_desc); 3576 3577 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3578 emx_destroy_rx_ring(sc, &sc->rx_data[i], 3579 sc->rx_data[i].num_rx_desc); 3580 } 3581 3582 /* Free top level busdma tag */ 3583 if (sc->parent_dtag != NULL) 3584 bus_dma_tag_destroy(sc->parent_dtag); 3585 } 3586 3587 static void 3588 emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz) 3589 { 3590 struct emx_softc *sc = ifp->if_softc; 3591 3592 switch (slz) { 3593 case IFNET_SERIALIZE_ALL: 3594 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 0); 3595 break; 3596 3597 case IFNET_SERIALIZE_MAIN: 3598 lwkt_serialize_enter(&sc->main_serialize); 3599 break; 3600 3601 case IFNET_SERIALIZE_TX: 3602 lwkt_serialize_enter(&sc->tx_serialize); 3603 break; 3604 3605 case IFNET_SERIALIZE_RX(0): 3606 lwkt_serialize_enter(&sc->rx_data[0].rx_serialize); 3607 break; 3608 3609 case IFNET_SERIALIZE_RX(1): 3610 lwkt_serialize_enter(&sc->rx_data[1].rx_serialize); 3611 break; 3612 3613 default: 3614 panic("%s unsupported serialize type\n", ifp->if_xname); 3615 } 3616 } 3617 3618 static void 3619 emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz) 3620 { 3621 struct emx_softc *sc = ifp->if_softc; 3622 3623 switch (slz) { 3624 case IFNET_SERIALIZE_ALL: 3625 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 0); 3626 break; 3627 3628 case IFNET_SERIALIZE_MAIN: 3629 lwkt_serialize_exit(&sc->main_serialize); 3630 break; 3631 3632 case IFNET_SERIALIZE_TX: 3633 lwkt_serialize_exit(&sc->tx_serialize); 3634 break; 3635 3636 case IFNET_SERIALIZE_RX(0): 3637 lwkt_serialize_exit(&sc->rx_data[0].rx_serialize); 3638 break; 3639 3640 case IFNET_SERIALIZE_RX(1): 3641 lwkt_serialize_exit(&sc->rx_data[1].rx_serialize); 3642 break; 3643 3644 default: 3645 panic("%s unsupported serialize type\n", ifp->if_xname); 3646 } 3647 } 3648 3649 static int 3650 emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz) 3651 { 3652 struct emx_softc *sc = ifp->if_softc; 3653 3654 switch (slz) { 3655 case IFNET_SERIALIZE_ALL: 3656 return lwkt_serialize_array_try(sc->serializes, 3657 EMX_NSERIALIZE, 0); 3658 3659 case IFNET_SERIALIZE_MAIN: 3660 return lwkt_serialize_try(&sc->main_serialize); 3661 3662 case IFNET_SERIALIZE_TX: 3663 return lwkt_serialize_try(&sc->tx_serialize); 3664 3665 case IFNET_SERIALIZE_RX(0): 3666 return lwkt_serialize_try(&sc->rx_data[0].rx_serialize); 3667 3668 case IFNET_SERIALIZE_RX(1): 3669 return lwkt_serialize_try(&sc->rx_data[1].rx_serialize); 3670 3671 default: 3672 panic("%s unsupported serialize type\n", ifp->if_xname); 3673 } 3674 } 3675 3676 static void 3677 emx_serialize_skipmain(struct emx_softc *sc) 3678 { 3679 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1); 3680 } 3681 3682 static void 3683 emx_deserialize_skipmain(struct emx_softc *sc) 3684 { 3685 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1); 3686 } 3687 3688 #ifdef INVARIANTS 3689 3690 static void 3691 emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz, 3692 boolean_t serialized) 3693 { 3694 struct emx_softc *sc = ifp->if_softc; 3695 int i; 3696 3697 switch (slz) { 3698 case IFNET_SERIALIZE_ALL: 3699 if (serialized) { 3700 for (i = 0; i < EMX_NSERIALIZE; ++i) 3701 ASSERT_SERIALIZED(sc->serializes[i]); 3702 } else { 3703 for (i = 0; i < EMX_NSERIALIZE; ++i) 3704 ASSERT_NOT_SERIALIZED(sc->serializes[i]); 3705 } 3706 break; 3707 3708 case IFNET_SERIALIZE_MAIN: 3709 if (serialized) 3710 ASSERT_SERIALIZED(&sc->main_serialize); 3711 else 3712 ASSERT_NOT_SERIALIZED(&sc->main_serialize); 3713 break; 3714 3715 case IFNET_SERIALIZE_TX: 3716 if (serialized) 3717 ASSERT_SERIALIZED(&sc->tx_serialize); 3718 else 3719 ASSERT_NOT_SERIALIZED(&sc->tx_serialize); 3720 break; 3721 3722 case IFNET_SERIALIZE_RX(0): 3723 if (serialized) 3724 ASSERT_SERIALIZED(&sc->rx_data[0].rx_serialize); 3725 else 3726 ASSERT_NOT_SERIALIZED(&sc->rx_data[0].rx_serialize); 3727 break; 3728 3729 case IFNET_SERIALIZE_RX(1): 3730 if (serialized) 3731 ASSERT_SERIALIZED(&sc->rx_data[1].rx_serialize); 3732 else 3733 ASSERT_NOT_SERIALIZED(&sc->rx_data[1].rx_serialize); 3734 break; 3735 3736 default: 3737 panic("%s unsupported serialize type\n", ifp->if_xname); 3738 } 3739 } 3740 3741 #endif /* INVARIANTS */ 3742 3743 #ifdef IFPOLL_ENABLE 3744 3745 static void 3746 emx_qpoll_status(struct ifnet *ifp, int pollhz __unused) 3747 { 3748 struct emx_softc *sc = ifp->if_softc; 3749 uint32_t reg_icr; 3750 3751 ASSERT_SERIALIZED(&sc->main_serialize); 3752 3753 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 3754 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 3755 emx_serialize_skipmain(sc); 3756 3757 callout_stop(&sc->timer); 3758 sc->hw.mac.get_link_status = 1; 3759 emx_update_link_status(sc); 3760 callout_reset(&sc->timer, hz, emx_timer, sc); 3761 3762 emx_deserialize_skipmain(sc); 3763 } 3764 } 3765 3766 static void 3767 emx_qpoll_tx(struct ifnet *ifp, void *arg __unused, int cycle __unused) 3768 { 3769 struct emx_softc *sc = ifp->if_softc; 3770 3771 ASSERT_SERIALIZED(&sc->tx_serialize); 3772 3773 emx_txeof(sc); 3774 if (!ifq_is_empty(&ifp->if_snd)) 3775 if_devstart(ifp); 3776 } 3777 3778 static void 3779 emx_qpoll_rx(struct ifnet *ifp, void *arg, int cycle) 3780 { 3781 struct emx_softc *sc = ifp->if_softc; 3782 struct emx_rxdata *rdata = arg; 3783 3784 ASSERT_SERIALIZED(&rdata->rx_serialize); 3785 3786 emx_rxeof(sc, rdata - sc->rx_data, cycle); 3787 } 3788 3789 static void 3790 emx_qpoll(struct ifnet *ifp, struct ifpoll_info *info) 3791 { 3792 struct emx_softc *sc = ifp->if_softc; 3793 3794 ASSERT_IFNET_SERIALIZED_ALL(ifp); 3795 3796 if (info) { 3797 int i; 3798 3799 info->ifpi_status.status_func = emx_qpoll_status; 3800 info->ifpi_status.serializer = &sc->main_serialize; 3801 3802 info->ifpi_tx[0].poll_func = emx_qpoll_tx; 3803 info->ifpi_tx[0].arg = NULL; 3804 info->ifpi_tx[0].serializer = &sc->tx_serialize; 3805 3806 for (i = 0; i < sc->rx_ring_cnt; ++i) { 3807 info->ifpi_rx[i].poll_func = emx_qpoll_rx; 3808 info->ifpi_rx[i].arg = &sc->rx_data[i]; 3809 info->ifpi_rx[i].serializer = 3810 &sc->rx_data[i].rx_serialize; 3811 } 3812 3813 if (ifp->if_flags & IFF_RUNNING) 3814 emx_disable_intr(sc); 3815 } else if (ifp->if_flags & IFF_RUNNING) { 3816 emx_enable_intr(sc); 3817 } 3818 } 3819 3820 #endif /* IFPOLL_ENABLE */ 3821 3822 static void 3823 emx_set_itr(struct emx_softc *sc, uint32_t itr) 3824 { 3825 E1000_WRITE_REG(&sc->hw, E1000_ITR, itr); 3826 if (sc->hw.mac.type == e1000_82574) { 3827 int i; 3828 3829 /* 3830 * When using MSIX interrupts we need to 3831 * throttle using the EITR register 3832 */ 3833 for (i = 0; i < 4; ++i) 3834 E1000_WRITE_REG(&sc->hw, E1000_EITR_82574(i), itr); 3835 } 3836 } 3837