1 /* 2 * Copyright (c) 2001-2008, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _IF_EMX_H_ 33 #define _IF_EMX_H_ 34 35 /* Tunables */ 36 37 /* 38 * EMX_TXD: Maximum number of Transmit Descriptors 39 * Valid Range: 256-4096 for others 40 * Default Value: 512 41 * This value is the number of transmit descriptors allocated by the driver. 42 * Increasing this value allows the driver to queue more transmits. Each 43 * descriptor is 16 bytes. 44 * Since TDLEN should be multiple of 128bytes, the number of transmit 45 * desscriptors should meet the following condition. 46 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 47 */ 48 #define EMX_MIN_TXD 256 49 #define EMX_MAX_TXD 4096 50 #define EMX_DEFAULT_TXD 512 51 52 /* 53 * EMX_RXD - Maximum number of receive Descriptors 54 * Valid Range: 256-4096 for others 55 * Default Value: 512 56 * This value is the number of receive descriptors allocated by the driver. 57 * Increasing this value allows the driver to buffer more incoming packets. 58 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 59 * descriptor. The maximum MTU size is 16110. 60 * Since TDLEN should be multiple of 128bytes, the number of transmit 61 * desscriptors should meet the following condition. 62 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 63 */ 64 #define EMX_MIN_RXD 256 65 #define EMX_MAX_RXD 4096 66 #define EMX_DEFAULT_RXD 512 67 68 /* 69 * Receive Interrupt Delay Timer (Packet Timer) 70 * 71 * NOTE: 72 * RDTR and RADV are deprecated; use ITR instead. They are only used to 73 * workaround hardware bug on certain 82573 based NICs. 74 */ 75 #define EMX_RDTR_82573 32 76 77 /* 78 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 79 * 80 * NOTE: 81 * RDTR and RADV are deprecated; use ITR instead. They are only used to 82 * workaround hardware bug on certain 82573 based NICs. 83 */ 84 #define EMX_RADV_82573 64 85 86 /* 87 * This parameter controls the duration of transmit watchdog timer. 88 */ 89 #define EMX_TX_TIMEOUT 5 90 91 /* One for TX csum offloading desc, the other 2 are reserved */ 92 #define EMX_TX_RESERVED 3 93 94 /* Large enough for 64K TSO segment */ 95 #define EMX_TX_SPARE 33 96 97 #define EMX_TX_OACTIVE_MAX 64 98 99 /* Interrupt throttle rate */ 100 #define EMX_DEFAULT_ITR 6000 101 102 /* 103 * This parameter controls whether or not autonegotation is enabled. 104 * 0 - Disable autonegotiation 105 * 1 - Enable autonegotiation 106 */ 107 #define EMX_DO_AUTO_NEG 1 108 109 /* Tunables -- End */ 110 111 #define EMX_AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | \ 112 ADVERTISE_10_FULL | \ 113 ADVERTISE_100_HALF | \ 114 ADVERTISE_100_FULL | \ 115 ADVERTISE_1000_FULL) 116 117 #define EMX_AUTO_ALL_MODES 0 118 119 /* PHY master/slave setting */ 120 #define EMX_MASTER_SLAVE e1000_ms_hw_default 121 122 /* 123 * Micellaneous constants 124 */ 125 #define EMX_VENDOR_ID 0x8086 126 127 #define EMX_BAR_MEM PCIR_BAR(0) 128 129 #define EMX_JUMBO_PBA 0x00000028 130 #define EMX_DEFAULT_PBA 0x00000030 131 #define EMX_SMARTSPEED_DOWNSHIFT 3 132 #define EMX_SMARTSPEED_MAX 15 133 #define EMX_MAX_INTR 10 134 135 #define EMX_MCAST_ADDR_MAX 128 136 #define EMX_FC_PAUSE_TIME 1000 137 #define EMX_EEPROM_APME 0x400; 138 139 /* 140 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 141 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 142 * also optimize cache line size effect. H/W supports up to cache line size 128. 143 */ 144 #define EMX_DBA_ALIGN 128 145 146 /* 147 * Speed mode bit in TARC0/TARC1. 148 * 82571EB/82572EI only, used to improve small packet transmit performance. 149 */ 150 #define EMX_TARC_SPEED_MODE (1 << 21) 151 152 #define EMX_MAX_SCATTER 64 153 #define EMX_TSO_SIZE (IP_MAXPACKET + \ 154 sizeof(struct ether_vlan_header)) 155 #define EMX_MAX_SEGSIZE PAGE_SIZE 156 #define EMX_MSIX_MASK 0x01F00000 /* For 82574 use */ 157 158 #define EMX_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 159 160 /* 161 * 82574 has a nonstandard address for EIAC 162 * and since its only used in MSIX, and in 163 * the em driver only 82574 uses MSIX we can 164 * solve it just using this define. 165 */ 166 #define EMX_EIAC 0x000DC 167 168 #define EMX_NRSSRK 10 169 #define EMX_RSSRK_SIZE 4 170 #define EMX_RSSRK_VAL(key, i) (key[(i) * EMX_RSSRK_SIZE] | \ 171 key[(i) * EMX_RSSRK_SIZE + 1] << 8 | \ 172 key[(i) * EMX_RSSRK_SIZE + 2] << 16 | \ 173 key[(i) * EMX_RSSRK_SIZE + 3] << 24) 174 175 #define EMX_NRETA 32 176 #define EMX_RETA_SIZE 4 177 #define EMX_RETA_RINGIDX_SHIFT 7 178 179 #define EMX_NRX_RING 2 180 #define EMX_NSERIALIZE 4 181 182 typedef union e1000_rx_desc_extended emx_rxdesc_t; 183 184 #define rxd_bufaddr read.buffer_addr /* 64bits */ 185 #define rxd_length wb.upper.length /* 16bits */ 186 #define rxd_vlan wb.upper.vlan /* 16bits */ 187 #define rxd_staterr wb.upper.status_error /* 32bits */ 188 #define rxd_mrq wb.lower.mrq /* 32bits */ 189 #define rxd_rss wb.lower.hi_dword.rss /* 32bits */ 190 191 #define EMX_RXDMRQ_RSSTYPE_MASK 0xf 192 #define EMX_RXDMRQ_NO_HASH 0 193 #define EMX_RXDMRQ_IPV4_TCP 1 194 #define EMX_RXDMRQ_IPV4 2 195 #define EMX_RXDMRQ_IPV6_TCP 3 196 #define EMX_RXDMRQ_IPV6 5 197 198 struct emx_softc; 199 200 struct emx_rxdata { 201 struct lwkt_serialize rx_serialize; 202 struct emx_softc *sc; 203 int idx; 204 205 /* 206 * Receive definitions 207 * 208 * we have an array of num_rx_desc rx_desc (handled by the 209 * controller), and paired with an array of rx_buffers 210 * (at rx_buffer_area). 211 * The next pair to check on receive is at offset next_rx_desc_to_check 212 */ 213 emx_rxdesc_t *rx_desc; 214 uint32_t next_rx_desc_to_check; 215 int num_rx_desc; 216 struct emx_rxbuf *rx_buf; 217 bus_dma_tag_t rxtag; 218 bus_dmamap_t rx_sparemap; 219 220 /* 221 * First/last mbuf pointers, for 222 * collecting multisegment RX packets. 223 */ 224 struct mbuf *fmp; 225 struct mbuf *lmp; 226 227 /* RX statistics */ 228 unsigned long rx_pkts; 229 230 bus_dma_tag_t rx_desc_dtag; 231 bus_dmamap_t rx_desc_dmap; 232 bus_addr_t rx_desc_paddr; 233 } __cachealign; 234 235 struct emx_txdata { 236 struct lwkt_serialize tx_serialize; 237 struct emx_softc *sc; 238 int idx; 239 240 /* 241 * Transmit definitions 242 * 243 * We have an array of num_tx_desc descriptors (handled 244 * by the controller) paired with an array of tx_buffers 245 * (at tx_buffer_area). 246 * The index of the next available descriptor is next_avail_tx_desc. 247 * The number of remaining tx_desc is num_tx_desc_avail. 248 */ 249 struct e1000_tx_desc *tx_desc_base; 250 struct emx_txbuf *tx_buf; 251 uint32_t next_avail_tx_desc; 252 uint32_t next_tx_to_clean; 253 int num_tx_desc_avail; 254 int num_tx_desc; 255 bus_dma_tag_t txtag; /* dma tag for tx */ 256 int spare_tx_desc; 257 int oact_tx_desc; 258 259 /* Saved csum offloading context information */ 260 int csum_flags; 261 int csum_lhlen; 262 int csum_iphlen; 263 264 int csum_thlen; /* TSO */ 265 int csum_mss; /* TSO */ 266 int csum_pktlen; /* TSO */ 267 268 uint32_t csum_txd_upper; 269 uint32_t csum_txd_lower; 270 271 int tx_wreg_nsegs; 272 273 /* 274 * Variables used to reduce TX interrupt rate and 275 * number of device's TX ring write requests. 276 * 277 * tx_nsegs: 278 * Number of TX descriptors setup so far. 279 * 280 * tx_int_nsegs: 281 * Once tx_nsegs > tx_int_nsegs, RS bit will be set 282 * in the last TX descriptor of the packet, and 283 * tx_nsegs will be reset to 0. So TX interrupt and 284 * TX ring write request should be generated roughly 285 * every tx_int_nsegs TX descriptors. 286 * 287 * tx_dd[]: 288 * Index of the TX descriptors which have RS bit set, 289 * i.e. DD bit will be set on this TX descriptor after 290 * the data of the TX descriptor are transfered to 291 * hardware's internal packet buffer. Only the TX 292 * descriptors listed in tx_dd[] will be checked upon 293 * TX interrupt. This array is used as circular ring. 294 * 295 * tx_dd_tail, tx_dd_head: 296 * Tail and head index of valid elements in tx_dd[]. 297 * tx_dd_tail == tx_dd_head means there is no valid 298 * elements in tx_dd[]. tx_dd_tail points to the position 299 * which is one beyond the last valid element in tx_dd[]. 300 * tx_dd_head points to the first valid element in 301 * tx_dd[]. 302 */ 303 int tx_int_nsegs; 304 int tx_nsegs; 305 int tx_dd_tail; 306 int tx_dd_head; 307 #define EMX_TXDD_MAX 64 308 #define EMX_TXDD_SAFE 48 /* 48 <= val < EMX_TXDD_MAX */ 309 int tx_dd[EMX_TXDD_MAX]; 310 311 /* TX statistics */ 312 unsigned long tso_segments; 313 unsigned long tso_ctx_reused; 314 315 bus_dma_tag_t tx_desc_dtag; 316 bus_dmamap_t tx_desc_dmap; 317 bus_addr_t tx_desc_paddr; 318 } __cachealign; 319 320 struct emx_softc { 321 struct arpcom arpcom; 322 struct e1000_hw hw; 323 int flags; 324 #define EMX_FLAG_SHARED_INTR 0x0001 325 #define EMX_FLAG_TSO_PULLEX 0x0002 326 #define EMX_FLAG_HAS_MGMT 0x0004 327 #define EMX_FLAG_HAS_AMT 0x0008 328 #define EMX_FLAG_HW_CTRL 0x0010 329 330 /* DragonFly operating-system-specific structures. */ 331 struct e1000_osdep osdep; 332 device_t dev; 333 334 bus_dma_tag_t parent_dtag; 335 336 struct resource *memory; 337 int memory_rid; 338 339 struct resource *intr_res; 340 void *intr_tag; 341 int intr_rid; 342 int intr_type; 343 344 struct ifmedia media; 345 struct callout timer; 346 int if_flags; 347 int max_frame_size; 348 int min_frame_size; 349 350 /* WOL register value */ 351 int wol; 352 353 /* Multicast array memory */ 354 uint8_t *mta; 355 356 /* Info about the board itself */ 357 uint8_t link_active; 358 uint16_t link_speed; 359 uint16_t link_duplex; 360 uint32_t smartspeed; 361 int int_throttle_ceil; 362 363 int rx_npoll_off; 364 int tx_npoll_off; 365 366 struct lwkt_serialize main_serialize; 367 struct lwkt_serialize *serializes[EMX_NSERIALIZE]; 368 369 struct emx_txdata tx_data; 370 371 int rss_debug; 372 int rx_ring_cnt; 373 struct emx_rxdata rx_data[EMX_NRX_RING]; 374 375 /* Misc stats maintained by the driver */ 376 unsigned long rx_overruns; 377 378 /* sysctl tree glue */ 379 struct sysctl_ctx_list sysctl_ctx; 380 struct sysctl_oid *sysctl_tree; 381 382 struct e1000_hw_stats stats; 383 }; 384 385 struct emx_txbuf { 386 struct mbuf *m_head; 387 bus_dmamap_t map; 388 }; 389 390 struct emx_rxbuf { 391 struct mbuf *m_head; 392 bus_dmamap_t map; 393 bus_addr_t paddr; 394 }; 395 396 #define EMX_IS_OACTIVE(tdata) \ 397 ((tdata)->num_tx_desc_avail <= (tdata)->oact_tx_desc) 398 399 #define EMX_INC_TXDD_IDX(idx) \ 400 do { \ 401 if (++(idx) == EMX_TXDD_MAX) \ 402 (idx) = 0; \ 403 } while (0) 404 405 #endif /* !_IF_EMX_H_ */ 406