1 /* 2 * Copyright (c) 2001-2008, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _IF_EMX_H_ 33 #define _IF_EMX_H_ 34 35 /* Tunables */ 36 37 /* 38 * EMX_TXD: Maximum number of Transmit Descriptors 39 * Valid Range: 256-4096 for others 40 * Default Value: 512 41 * This value is the number of transmit descriptors allocated by the driver. 42 * Increasing this value allows the driver to queue more transmits. Each 43 * descriptor is 16 bytes. 44 * Since TDLEN should be multiple of 128bytes, the number of transmit 45 * desscriptors should meet the following condition. 46 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 47 */ 48 #define EMX_MIN_TXD 256 49 #define EMX_MAX_TXD 4096 50 #define EMX_DEFAULT_TXD 512 51 52 /* 53 * EMX_RXD - Maximum number of receive Descriptors 54 * Valid Range: 256-4096 for others 55 * Default Value: 512 56 * This value is the number of receive descriptors allocated by the driver. 57 * Increasing this value allows the driver to buffer more incoming packets. 58 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 59 * descriptor. The maximum MTU size is 16110. 60 * Since TDLEN should be multiple of 128bytes, the number of transmit 61 * desscriptors should meet the following condition. 62 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 63 */ 64 #define EMX_MIN_RXD 256 65 #define EMX_MAX_RXD 4096 66 #define EMX_DEFAULT_RXD 512 67 68 /* 69 * Receive Interrupt Delay Timer (Packet Timer) 70 * 71 * NOTE: 72 * RDTR and RADV are deprecated; use ITR instead. They are only used to 73 * workaround hardware bug on certain 82573 based NICs. 74 */ 75 #define EMX_RDTR_82573 32 76 77 /* 78 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 79 * 80 * NOTE: 81 * RDTR and RADV are deprecated; use ITR instead. They are only used to 82 * workaround hardware bug on certain 82573 based NICs. 83 */ 84 #define EMX_RADV_82573 64 85 86 /* 87 * This parameter controls the duration of transmit watchdog timer. 88 */ 89 #define EMX_TX_TIMEOUT 5 90 91 /* One for TX csum offloading desc, the other 2 are reserved */ 92 #define EMX_TX_RESERVED 3 93 94 /* Large enough for 16K jumbo frame */ 95 #define EMX_TX_SPARE 8 96 97 #define EMX_TX_OACTIVE_MAX 64 98 99 /* Interrupt throttle rate */ 100 #define EMX_DEFAULT_ITR 10000 101 102 /* 103 * This parameter controls whether or not autonegotation is enabled. 104 * 0 - Disable autonegotiation 105 * 1 - Enable autonegotiation 106 */ 107 #define EMX_DO_AUTO_NEG 1 108 109 /* Tunables -- End */ 110 111 #define EMX_AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | \ 112 ADVERTISE_10_FULL | \ 113 ADVERTISE_100_HALF | \ 114 ADVERTISE_100_FULL | \ 115 ADVERTISE_1000_FULL) 116 117 #define EMX_AUTO_ALL_MODES 0 118 119 /* PHY master/slave setting */ 120 #define EMX_MASTER_SLAVE e1000_ms_hw_default 121 122 /* 123 * Micellaneous constants 124 */ 125 #define EMX_VENDOR_ID 0x8086 126 127 #define EMX_BAR_MEM PCIR_BAR(0) 128 129 #define EMX_JUMBO_PBA 0x00000028 130 #define EMX_DEFAULT_PBA 0x00000030 131 #define EMX_SMARTSPEED_DOWNSHIFT 3 132 #define EMX_SMARTSPEED_MAX 15 133 #define EMX_MAX_INTR 10 134 135 #define EMX_MCAST_ADDR_MAX 128 136 #define EMX_FC_PAUSE_TIME 1000 137 #define EMX_EEPROM_APME 0x400; 138 139 /* 140 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 141 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 142 * also optimize cache line size effect. H/W supports up to cache line size 128. 143 */ 144 #define EMX_DBA_ALIGN 128 145 146 /* 147 * Speed mode bit in TARC0/TARC1. 148 * 82571EB/82572EI only, used to improve small packet transmit performance. 149 */ 150 #define EMX_TARC_SPEED_MODE (1 << 21) 151 152 #define EMX_MAX_SCATTER 64 153 #define EMX_TSO_SIZE (65535 + \ 154 sizeof(struct ether_vlan_header)) 155 #define EMX_MAX_SEGSIZE 4096 156 #define EMX_MSIX_MASK 0x01F00000 /* For 82574 use */ 157 158 #define EMX_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 159 #define EMX_IPVHL_SIZE 1 /* sizeof(ip.ip_vhl) */ 160 #define EMX_TXCSUM_MINHL (ETHER_HDR_LEN + EVL_ENCAPLEN + \ 161 EMX_IPVHL_SIZE) 162 163 /* 164 * 82574 has a nonstandard address for EIAC 165 * and since its only used in MSIX, and in 166 * the em driver only 82574 uses MSIX we can 167 * solve it just using this define. 168 */ 169 #define EMX_EIAC 0x000DC 170 171 #define EMX_NRSSRK 10 172 #define EMX_RSSRK_SIZE 4 173 #define EMX_RSSRK_VAL(key, i) (key[(i) * EMX_RSSRK_SIZE] | \ 174 key[(i) * EMX_RSSRK_SIZE + 1] << 8 | \ 175 key[(i) * EMX_RSSRK_SIZE + 2] << 16 | \ 176 key[(i) * EMX_RSSRK_SIZE + 3] << 24) 177 178 #define EMX_NRETA 32 179 #define EMX_RETA_SIZE 4 180 #define EMX_RETA_RINGIDX_SHIFT 7 181 182 #define EMX_NRX_RING 2 183 #define EMX_NSERIALIZE 4 184 185 typedef union e1000_rx_desc_extended emx_rxdesc_t; 186 187 #define rxd_bufaddr read.buffer_addr /* 64bits */ 188 #define rxd_length wb.upper.length /* 16bits */ 189 #define rxd_vlan wb.upper.vlan /* 16bits */ 190 #define rxd_staterr wb.upper.status_error /* 32bits */ 191 #define rxd_mrq wb.lower.mrq /* 32bits */ 192 #define rxd_rss wb.lower.hi_dword.rss /* 32bits */ 193 194 #define EMX_RXDMRQ_RSSTYPE_MASK 0xf 195 #define EMX_RXDMRQ_NO_HASH 0 196 #define EMX_RXDMRQ_IPV4_TCP 1 197 #define EMX_RXDMRQ_IPV4 2 198 #define EMX_RXDMRQ_IPV6_TCP 3 199 #define EMX_RXDMRQ_IPV6 5 200 201 struct emx_rxdata { 202 struct lwkt_serialize rx_serialize; 203 204 /* 205 * Receive definitions 206 * 207 * we have an array of num_rx_desc rx_desc (handled by the 208 * controller), and paired with an array of rx_buffers 209 * (at rx_buffer_area). 210 * The next pair to check on receive is at offset next_rx_desc_to_check 211 */ 212 emx_rxdesc_t *rx_desc; 213 uint32_t next_rx_desc_to_check; 214 int num_rx_desc; 215 struct emx_rxbuf *rx_buf; 216 bus_dma_tag_t rxtag; 217 bus_dmamap_t rx_sparemap; 218 219 /* 220 * First/last mbuf pointers, for 221 * collecting multisegment RX packets. 222 */ 223 struct mbuf *fmp; 224 struct mbuf *lmp; 225 226 /* RX statistics */ 227 unsigned long rx_pkts; 228 unsigned long mbuf_cluster_failed; 229 230 bus_dma_tag_t rx_desc_dtag; 231 bus_dmamap_t rx_desc_dmap; 232 bus_addr_t rx_desc_paddr; 233 } __cachealign; 234 235 struct emx_softc { 236 struct arpcom arpcom; 237 struct e1000_hw hw; 238 239 /* DragonFly operating-system-specific structures. */ 240 struct e1000_osdep osdep; 241 device_t dev; 242 243 bus_dma_tag_t parent_dtag; 244 245 bus_dma_tag_t tx_desc_dtag; 246 bus_dmamap_t tx_desc_dmap; 247 bus_addr_t tx_desc_paddr; 248 249 struct resource *memory; 250 int memory_rid; 251 252 struct resource *intr_res; 253 void *intr_tag; 254 int intr_rid; 255 256 struct ifmedia media; 257 struct callout timer; 258 int if_flags; 259 int max_frame_size; 260 int min_frame_size; 261 262 /* Management and WOL features */ 263 int wol; 264 int has_manage; 265 int has_amt; 266 int control_hw; 267 268 /* Multicast array memory */ 269 uint8_t *mta; 270 271 /* Info about the board itself */ 272 uint8_t link_active; 273 uint16_t link_speed; 274 uint16_t link_duplex; 275 uint32_t smartspeed; 276 int int_throttle_ceil; 277 278 struct lwkt_serialize main_serialize; 279 struct lwkt_serialize tx_serialize; 280 struct lwkt_serialize *serializes[EMX_NSERIALIZE]; 281 282 /* 283 * Transmit definitions 284 * 285 * We have an array of num_tx_desc descriptors (handled 286 * by the controller) paired with an array of tx_buffers 287 * (at tx_buffer_area). 288 * The index of the next available descriptor is next_avail_tx_desc. 289 * The number of remaining tx_desc is num_tx_desc_avail. 290 */ 291 struct e1000_tx_desc *tx_desc_base; 292 struct emx_txbuf *tx_buf; 293 uint32_t next_avail_tx_desc; 294 uint32_t next_tx_to_clean; 295 int num_tx_desc_avail; 296 int num_tx_desc; 297 bus_dma_tag_t txtag; /* dma tag for tx */ 298 int spare_tx_desc; 299 int oact_tx_desc; 300 301 /* Saved csum offloading context information */ 302 int csum_flags; 303 int csum_ehlen; 304 int csum_iphlen; 305 uint32_t csum_txd_upper; 306 uint32_t csum_txd_lower; 307 308 /* 309 * Variables used to reduce TX interrupt rate and 310 * number of device's TX ring write requests. 311 * 312 * tx_nsegs: 313 * Number of TX descriptors setup so far. 314 * 315 * tx_int_nsegs: 316 * Once tx_nsegs > tx_int_nsegs, RS bit will be set 317 * in the last TX descriptor of the packet, and 318 * tx_nsegs will be reset to 0. So TX interrupt and 319 * TX ring write request should be generated roughly 320 * every tx_int_nsegs TX descriptors. 321 * 322 * tx_dd[]: 323 * Index of the TX descriptors which have RS bit set, 324 * i.e. DD bit will be set on this TX descriptor after 325 * the data of the TX descriptor are transfered to 326 * hardware's internal packet buffer. Only the TX 327 * descriptors listed in tx_dd[] will be checked upon 328 * TX interrupt. This array is used as circular ring. 329 * 330 * tx_dd_tail, tx_dd_head: 331 * Tail and head index of valid elements in tx_dd[]. 332 * tx_dd_tail == tx_dd_head means there is no valid 333 * elements in tx_dd[]. tx_dd_tail points to the position 334 * which is one beyond the last valid element in tx_dd[]. 335 * tx_dd_head points to the first valid element in 336 * tx_dd[]. 337 */ 338 int tx_int_nsegs; 339 int tx_nsegs; 340 int tx_dd_tail; 341 int tx_dd_head; 342 #define EMX_TXDD_MAX 64 343 #define EMX_TXDD_SAFE 48 /* 48 <= val < EMX_TXDD_MAX */ 344 int tx_dd[EMX_TXDD_MAX]; 345 346 int rx_ring_inuse; 347 struct emx_rxdata rx_data[EMX_NRX_RING]; 348 349 /* Misc stats maintained by the driver */ 350 unsigned long dropped_pkts; 351 unsigned long mbuf_alloc_failed; 352 unsigned long no_tx_desc_avail1; 353 unsigned long no_tx_desc_avail2; 354 unsigned long no_tx_map_avail; 355 unsigned long no_tx_dma_setup; 356 unsigned long watchdog_events; 357 unsigned long rx_overruns; 358 unsigned long rx_irq; 359 unsigned long tx_irq; 360 unsigned long link_irq; 361 unsigned long tx_csum_try_pullup; 362 unsigned long tx_csum_pullup1; 363 unsigned long tx_csum_pullup1_failed; 364 unsigned long tx_csum_pullup2; 365 unsigned long tx_csum_pullup2_failed; 366 unsigned long tx_csum_drop1; 367 unsigned long tx_csum_drop2; 368 369 /* sysctl tree glue */ 370 struct sysctl_ctx_list sysctl_ctx; 371 struct sysctl_oid *sysctl_tree; 372 373 int rx_ring_cnt; 374 int rss_debug; 375 376 struct e1000_hw_stats stats; 377 }; 378 379 struct emx_txbuf { 380 struct mbuf *m_head; 381 bus_dmamap_t map; 382 }; 383 384 struct emx_rxbuf { 385 struct mbuf *m_head; 386 bus_dmamap_t map; 387 bus_addr_t paddr; 388 }; 389 390 #define EMX_IS_OACTIVE(sc) ((sc)->num_tx_desc_avail <= (sc)->oact_tx_desc) 391 392 #define EMX_INC_TXDD_IDX(idx) \ 393 do { \ 394 if (++(idx) == EMX_TXDD_MAX) \ 395 (idx) = 0; \ 396 } while (0) 397 398 #endif /* !_IF_EMX_H_ */ 399