1 /* 2 * Copyright (c) 2001-2008, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _IF_EMX_H_ 33 #define _IF_EMX_H_ 34 35 /* Tunables */ 36 37 /* 38 * EMX_TXD: Maximum number of Transmit Descriptors 39 * Valid Range: 256-4096 for others 40 * Default Value: 512 41 * This value is the number of transmit descriptors allocated by the driver. 42 * Increasing this value allows the driver to queue more transmits. Each 43 * descriptor is 16 bytes. 44 * Since TDLEN should be multiple of 128bytes, the number of transmit 45 * desscriptors should meet the following condition. 46 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 47 */ 48 #define EMX_MIN_TXD 256 49 #define EMX_MAX_TXD 4096 50 #define EMX_DEFAULT_TXD 512 51 52 /* 53 * EMX_RXD - Maximum number of receive Descriptors 54 * Valid Range: 256-4096 for others 55 * Default Value: 512 56 * This value is the number of receive descriptors allocated by the driver. 57 * Increasing this value allows the driver to buffer more incoming packets. 58 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 59 * descriptor. The maximum MTU size is 16110. 60 * Since TDLEN should be multiple of 128bytes, the number of transmit 61 * desscriptors should meet the following condition. 62 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 63 */ 64 #define EMX_MIN_RXD 256 65 #define EMX_MAX_RXD 4096 66 #define EMX_DEFAULT_RXD 512 67 68 /* 69 * Receive Interrupt Delay Timer (Packet Timer) 70 * 71 * NOTE: 72 * RDTR and RADV are deprecated; use ITR instead. They are only used to 73 * workaround hardware bug on certain 82573 based NICs. 74 */ 75 #define EMX_RDTR_82573 32 76 77 /* 78 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 79 * 80 * NOTE: 81 * RDTR and RADV are deprecated; use ITR instead. They are only used to 82 * workaround hardware bug on certain 82573 based NICs. 83 */ 84 #define EMX_RADV_82573 64 85 86 /* 87 * This parameter controls the duration of transmit watchdog timer. 88 */ 89 #define EMX_TX_TIMEOUT 5 90 91 /* One for TX csum offloading desc, the other 2 are reserved */ 92 #define EMX_TX_RESERVED 3 93 94 /* Large enough for 64K TSO segment */ 95 #define EMX_TX_SPARE 33 96 97 #define EMX_TX_OACTIVE_MAX 64 98 99 /* Interrupt throttle rate */ 100 #define EMX_DEFAULT_ITR 6000 101 102 /* 103 * This parameter controls whether or not autonegotation is enabled. 104 * 0 - Disable autonegotiation 105 * 1 - Enable autonegotiation 106 */ 107 #define EMX_DO_AUTO_NEG 1 108 109 /* Tunables -- End */ 110 111 #define EMX_AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | \ 112 ADVERTISE_10_FULL | \ 113 ADVERTISE_100_HALF | \ 114 ADVERTISE_100_FULL | \ 115 ADVERTISE_1000_FULL) 116 117 #define EMX_AUTO_ALL_MODES 0 118 119 /* PHY master/slave setting */ 120 #define EMX_MASTER_SLAVE e1000_ms_hw_default 121 122 /* 123 * Micellaneous constants 124 */ 125 #define EMX_VENDOR_ID 0x8086 126 127 #define EMX_BAR_MEM PCIR_BAR(0) 128 129 #define EMX_JUMBO_PBA 0x00000028 130 #define EMX_DEFAULT_PBA 0x00000030 131 #define EMX_SMARTSPEED_DOWNSHIFT 3 132 #define EMX_SMARTSPEED_MAX 15 133 #define EMX_MAX_INTR 10 134 135 #define EMX_MCAST_ADDR_MAX 128 136 #define EMX_FC_PAUSE_TIME 1000 137 #define EMX_EEPROM_APME 0x400; 138 139 /* 140 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 141 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 142 * also optimize cache line size effect. H/W supports up to cache line size 128. 143 */ 144 #define EMX_DBA_ALIGN 128 145 146 /* 147 * Speed mode bit in TARC0. 148 * 82571EB/82572EI only, used to improve small packet transmit performance. 149 */ 150 #define EMX_TARC_SPEED_MODE (1 << 21) 151 152 /* 153 * Multiple TX queues arbitration count mask in TARC0/TARC1. 154 */ 155 #define EMX_TARC_COUNT_MASK 0x7f 156 157 #define EMX_MAX_SCATTER 64 158 #define EMX_TSO_SIZE (IP_MAXPACKET + \ 159 sizeof(struct ether_vlan_header)) 160 #define EMX_MAX_SEGSIZE PAGE_SIZE 161 #define EMX_MSIX_MASK 0x01F00000 /* For 82574 use */ 162 163 #define EMX_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 164 165 /* 166 * 82574 has a nonstandard address for EIAC 167 * and since its only used in MSIX, and in 168 * the em driver only 82574 uses MSIX we can 169 * solve it just using this define. 170 */ 171 #define EMX_EIAC 0x000DC 172 173 #define EMX_NRSSRK 10 174 #define EMX_RSSRK_SIZE 4 175 #define EMX_RSSRK_VAL(key, i) (key[(i) * EMX_RSSRK_SIZE] | \ 176 key[(i) * EMX_RSSRK_SIZE + 1] << 8 | \ 177 key[(i) * EMX_RSSRK_SIZE + 2] << 16 | \ 178 key[(i) * EMX_RSSRK_SIZE + 3] << 24) 179 180 #define EMX_NRETA 32 181 #define EMX_RETA_SIZE 4 182 #define EMX_RETA_RINGIDX_SHIFT 7 183 184 #define EMX_NRX_RING 2 185 #define EMX_NTX_RING 2 186 #define EMX_NSERIALIZE 5 187 188 typedef union e1000_rx_desc_extended emx_rxdesc_t; 189 190 #define rxd_bufaddr read.buffer_addr /* 64bits */ 191 #define rxd_length wb.upper.length /* 16bits */ 192 #define rxd_vlan wb.upper.vlan /* 16bits */ 193 #define rxd_staterr wb.upper.status_error /* 32bits */ 194 #define rxd_mrq wb.lower.mrq /* 32bits */ 195 #define rxd_rss wb.lower.hi_dword.rss /* 32bits */ 196 197 #define EMX_RXDMRQ_RSSTYPE_MASK 0xf 198 #define EMX_RXDMRQ_NO_HASH 0 199 #define EMX_RXDMRQ_IPV4_TCP 1 200 #define EMX_RXDMRQ_IPV4 2 201 #define EMX_RXDMRQ_IPV6_TCP 3 202 #define EMX_RXDMRQ_IPV6 5 203 204 struct emx_softc; 205 206 struct emx_rxdata { 207 struct lwkt_serialize rx_serialize; 208 struct emx_softc *sc; 209 int idx; 210 211 /* 212 * Receive definitions 213 * 214 * we have an array of num_rx_desc rx_desc (handled by the 215 * controller), and paired with an array of rx_buffers 216 * (at rx_buffer_area). 217 * The next pair to check on receive is at offset next_rx_desc_to_check 218 */ 219 emx_rxdesc_t *rx_desc; 220 uint32_t next_rx_desc_to_check; 221 int num_rx_desc; 222 struct emx_rxbuf *rx_buf; 223 bus_dma_tag_t rxtag; 224 bus_dmamap_t rx_sparemap; 225 226 /* 227 * First/last mbuf pointers, for 228 * collecting multisegment RX packets. 229 */ 230 struct mbuf *fmp; 231 struct mbuf *lmp; 232 233 /* RX statistics */ 234 unsigned long rx_pkts; 235 236 bus_dma_tag_t rx_desc_dtag; 237 bus_dmamap_t rx_desc_dmap; 238 bus_addr_t rx_desc_paddr; 239 } __cachealign; 240 241 struct emx_txdata { 242 struct lwkt_serialize tx_serialize; 243 struct emx_softc *sc; 244 struct ifaltq_subque *ifsq; 245 int idx; 246 uint32_t tx_flags; 247 #define EMX_TXFLAG_TSO_PULLEX 0x1 248 #define EMX_TXFLAG_ENABLED 0x2 249 #define EMX_TXFLAG_FORCECTX 0x4 250 251 /* 252 * Transmit definitions 253 * 254 * We have an array of num_tx_desc descriptors (handled 255 * by the controller) paired with an array of tx_buffers 256 * (at tx_buffer_area). 257 * The index of the next available descriptor is next_avail_tx_desc. 258 * The number of remaining tx_desc is num_tx_desc_avail. 259 */ 260 struct e1000_tx_desc *tx_desc_base; 261 struct emx_txbuf *tx_buf; 262 uint32_t next_avail_tx_desc; 263 uint32_t next_tx_to_clean; 264 int num_tx_desc_avail; 265 int num_tx_desc; 266 bus_dma_tag_t txtag; /* dma tag for tx */ 267 int spare_tx_desc; 268 int oact_tx_desc; 269 270 /* Saved csum offloading context information */ 271 int csum_flags; 272 int csum_lhlen; 273 int csum_iphlen; 274 275 int csum_thlen; /* TSO */ 276 int csum_mss; /* TSO */ 277 int csum_pktlen; /* TSO */ 278 279 uint32_t csum_txd_upper; 280 uint32_t csum_txd_lower; 281 282 int tx_wreg_nsegs; 283 284 /* 285 * Variables used to reduce TX interrupt rate and 286 * number of device's TX ring write requests. 287 * 288 * tx_nsegs: 289 * Number of TX descriptors setup so far. 290 * 291 * tx_int_nsegs: 292 * Once tx_nsegs > tx_int_nsegs, RS bit will be set 293 * in the last TX descriptor of the packet, and 294 * tx_nsegs will be reset to 0. So TX interrupt and 295 * TX ring write request should be generated roughly 296 * every tx_int_nsegs TX descriptors. 297 * 298 * tx_dd[]: 299 * Index of the TX descriptors which have RS bit set, 300 * i.e. DD bit will be set on this TX descriptor after 301 * the data of the TX descriptor are transfered to 302 * hardware's internal packet buffer. Only the TX 303 * descriptors listed in tx_dd[] will be checked upon 304 * TX interrupt. This array is used as circular ring. 305 * 306 * tx_dd_tail, tx_dd_head: 307 * Tail and head index of valid elements in tx_dd[]. 308 * tx_dd_tail == tx_dd_head means there is no valid 309 * elements in tx_dd[]. tx_dd_tail points to the position 310 * which is one beyond the last valid element in tx_dd[]. 311 * tx_dd_head points to the first valid element in 312 * tx_dd[]. 313 */ 314 int tx_intr_nsegs; 315 int tx_nsegs; 316 int tx_dd_tail; 317 int tx_dd_head; 318 #define EMX_TXDD_MAX 64 319 #define EMX_TXDD_SAFE 48 /* 48 <= val < EMX_TXDD_MAX */ 320 int tx_dd[EMX_TXDD_MAX]; 321 322 struct ifsubq_watchdog tx_watchdog; 323 324 /* TX statistics */ 325 unsigned long tx_pkts; 326 unsigned long tso_segments; 327 unsigned long tso_ctx_reused; 328 329 bus_dma_tag_t tx_desc_dtag; 330 bus_dmamap_t tx_desc_dmap; 331 bus_addr_t tx_desc_paddr; 332 } __cachealign; 333 334 struct emx_softc { 335 struct arpcom arpcom; 336 struct e1000_hw hw; 337 int flags; 338 #define EMX_FLAG_SHARED_INTR 0x0001 339 #define EMX_FLAG_HAS_MGMT 0x0004 340 #define EMX_FLAG_HAS_AMT 0x0008 341 #define EMX_FLAG_HW_CTRL 0x0010 342 343 /* DragonFly operating-system-specific structures. */ 344 struct e1000_osdep osdep; 345 device_t dev; 346 347 bus_dma_tag_t parent_dtag; 348 349 struct resource *memory; 350 int memory_rid; 351 352 struct resource *intr_res; 353 void *intr_tag; 354 int intr_rid; 355 int intr_type; 356 357 struct ifmedia media; 358 struct callout timer; 359 int if_flags; 360 int max_frame_size; 361 int min_frame_size; 362 363 /* WOL register value */ 364 int wol; 365 366 /* Multicast array memory */ 367 uint8_t *mta; 368 369 /* Info about the board itself */ 370 uint8_t link_active; 371 uint16_t link_speed; 372 uint16_t link_duplex; 373 uint32_t smartspeed; 374 int int_throttle_ceil; 375 376 int rx_npoll_off; 377 int tx_npoll_off; 378 379 struct lwkt_serialize main_serialize; 380 struct lwkt_serialize *serializes[EMX_NSERIALIZE]; 381 382 int tx_ring_cnt; 383 int tx_ring_inuse; 384 struct emx_txdata tx_data[EMX_NTX_RING]; 385 386 int rss_debug; 387 int rx_ring_cnt; 388 struct emx_rxdata rx_data[EMX_NRX_RING]; 389 390 /* Misc stats maintained by the driver */ 391 unsigned long rx_overruns; 392 393 /* sysctl tree glue */ 394 struct sysctl_ctx_list sysctl_ctx; 395 struct sysctl_oid *sysctl_tree; 396 397 struct e1000_hw_stats stats; 398 }; 399 400 struct emx_txbuf { 401 struct mbuf *m_head; 402 bus_dmamap_t map; 403 }; 404 405 struct emx_rxbuf { 406 struct mbuf *m_head; 407 bus_dmamap_t map; 408 bus_addr_t paddr; 409 }; 410 411 #define EMX_IS_OACTIVE(tdata) \ 412 ((tdata)->num_tx_desc_avail <= (tdata)->oact_tx_desc) 413 414 #define EMX_INC_TXDD_IDX(idx) \ 415 do { \ 416 if (++(idx) == EMX_TXDD_MAX) \ 417 (idx) = 0; \ 418 } while (0) 419 420 #endif /* !_IF_EMX_H_ */ 421