1 /* 2 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Sepherosa Ziehau <sepherosa@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of The DragonFly Project nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific, prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 #include <sys/param.h> 36 #include <sys/bitops.h> 37 #include <sys/endian.h> 38 #include <sys/kernel.h> 39 #include <sys/bus.h> 40 #include <sys/interrupt.h> 41 #include <sys/malloc.h> 42 #include <sys/proc.h> 43 #include <sys/rman.h> 44 #include <sys/serialize.h> 45 #include <sys/socket.h> 46 #include <sys/sockio.h> 47 #include <sys/sysctl.h> 48 49 #include <net/ethernet.h> 50 #include <net/if.h> 51 #include <net/bpf.h> 52 #include <net/if_arp.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/ifq_var.h> 56 #include <net/vlan/if_vlan_var.h> 57 58 #include <dev/netif/mii_layer/miivar.h> 59 60 #include <bus/pci/pcireg.h> 61 #include <bus/pci/pcivar.h> 62 #include <bus/pci/pcidevs.h> 63 64 #include <dev/netif/et/if_etreg.h> 65 #include <dev/netif/et/if_etvar.h> 66 67 #include "miibus_if.h" 68 69 static int et_probe(device_t); 70 static int et_attach(device_t); 71 static int et_detach(device_t); 72 static int et_shutdown(device_t); 73 74 static int et_miibus_readreg(device_t, int, int); 75 static int et_miibus_writereg(device_t, int, int, int); 76 static void et_miibus_statchg(device_t); 77 78 static void et_init(void *); 79 static int et_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 80 static void et_start(struct ifnet *, struct ifaltq_subque *); 81 static void et_watchdog(struct ifnet *); 82 static int et_ifmedia_upd(struct ifnet *); 83 static void et_ifmedia_sts(struct ifnet *, struct ifmediareq *); 84 85 static int et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS); 86 static int et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS); 87 88 static void et_intr(void *); 89 static void et_enable_intrs(struct et_softc *, uint32_t); 90 static void et_disable_intrs(struct et_softc *); 91 static void et_rxeof(struct et_softc *); 92 static void et_txeof(struct et_softc *, int); 93 94 static int et_dma_alloc(device_t); 95 static void et_dma_free(device_t); 96 static void et_dma_mem_destroy(bus_dma_tag_t, void *, bus_dmamap_t); 97 static int et_dma_mbuf_create(device_t); 98 static void et_dma_mbuf_destroy(device_t, int, const int[]); 99 static int et_jumbo_mem_alloc(device_t); 100 static void et_jumbo_mem_free(device_t); 101 static int et_init_tx_ring(struct et_softc *); 102 static int et_init_rx_ring(struct et_softc *); 103 static void et_free_tx_ring(struct et_softc *); 104 static void et_free_rx_ring(struct et_softc *); 105 static int et_encap(struct et_softc *, struct mbuf **); 106 static struct et_jslot * 107 et_jalloc(struct et_jumbo_data *); 108 static void et_jfree(void *); 109 static void et_jref(void *); 110 static int et_newbuf(struct et_rxbuf_data *, int, int, int); 111 static int et_newbuf_cluster(struct et_rxbuf_data *, int, int); 112 static int et_newbuf_hdr(struct et_rxbuf_data *, int, int); 113 static int et_newbuf_jumbo(struct et_rxbuf_data *, int, int); 114 115 static void et_stop(struct et_softc *); 116 static int et_chip_init(struct et_softc *); 117 static void et_chip_attach(struct et_softc *); 118 static void et_init_mac(struct et_softc *); 119 static void et_init_rxmac(struct et_softc *); 120 static void et_init_txmac(struct et_softc *); 121 static int et_init_rxdma(struct et_softc *); 122 static int et_init_txdma(struct et_softc *); 123 static int et_start_rxdma(struct et_softc *); 124 static int et_start_txdma(struct et_softc *); 125 static int et_stop_rxdma(struct et_softc *); 126 static int et_stop_txdma(struct et_softc *); 127 static int et_enable_txrx(struct et_softc *, int); 128 static void et_reset(struct et_softc *); 129 static int et_bus_config(device_t); 130 static void et_get_eaddr(device_t, uint8_t[]); 131 static void et_setmulti(struct et_softc *); 132 static void et_tick(void *); 133 static void et_setmedia(struct et_softc *); 134 static void et_setup_rxdesc(struct et_rxbuf_data *, int, bus_addr_t); 135 136 static const struct et_dev { 137 uint16_t vid; 138 uint16_t did; 139 const char *desc; 140 } et_devices[] = { 141 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310, 142 "Agere ET1310 Gigabit Ethernet" }, 143 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310_FAST, 144 "Agere ET1310 Fast Ethernet" }, 145 { 0, 0, NULL } 146 }; 147 148 static device_method_t et_methods[] = { 149 DEVMETHOD(device_probe, et_probe), 150 DEVMETHOD(device_attach, et_attach), 151 DEVMETHOD(device_detach, et_detach), 152 DEVMETHOD(device_shutdown, et_shutdown), 153 #if 0 154 DEVMETHOD(device_suspend, et_suspend), 155 DEVMETHOD(device_resume, et_resume), 156 #endif 157 158 DEVMETHOD(bus_print_child, bus_generic_print_child), 159 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 160 161 DEVMETHOD(miibus_readreg, et_miibus_readreg), 162 DEVMETHOD(miibus_writereg, et_miibus_writereg), 163 DEVMETHOD(miibus_statchg, et_miibus_statchg), 164 165 DEVMETHOD_END 166 }; 167 168 static driver_t et_driver = { 169 "et", 170 et_methods, 171 sizeof(struct et_softc) 172 }; 173 174 static devclass_t et_devclass; 175 176 DECLARE_DUMMY_MODULE(if_et); 177 MODULE_DEPEND(if_et, miibus, 1, 1, 1); 178 DRIVER_MODULE(if_et, pci, et_driver, et_devclass, NULL, NULL); 179 DRIVER_MODULE(miibus, et, miibus_driver, miibus_devclass, NULL, NULL); 180 181 static int et_rx_intr_npkts = 129; 182 static int et_rx_intr_delay = 25; /* x4 usec */ 183 static int et_tx_intr_nsegs = 256; 184 static uint32_t et_timer = 1000 * 1000 * 1000; /* nanosec */ 185 186 static int et_msi_enable = 1; 187 188 TUNABLE_INT("hw.et.timer", &et_timer); 189 TUNABLE_INT("hw.et.rx_intr_npkts", &et_rx_intr_npkts); 190 TUNABLE_INT("hw.et.rx_intr_delay", &et_rx_intr_delay); 191 TUNABLE_INT("hw.et.tx_intr_nsegs", &et_tx_intr_nsegs); 192 TUNABLE_INT("hw.et.msi.enable", &et_msi_enable); 193 194 struct et_bsize { 195 int bufsize; 196 int jumbo; 197 et_newbuf_t newbuf; 198 }; 199 200 static const struct et_bsize et_bufsize_std[ET_RX_NRING] = { 201 { .bufsize = ET_RXDMA_CTRL_RING0_128, .jumbo = 0, 202 .newbuf = et_newbuf_hdr }, 203 { .bufsize = ET_RXDMA_CTRL_RING1_2048, .jumbo = 0, 204 .newbuf = et_newbuf_cluster }, 205 }; 206 207 static const struct et_bsize et_bufsize_jumbo[ET_RX_NRING] = { 208 { .bufsize = ET_RXDMA_CTRL_RING0_128, .jumbo = 0, 209 .newbuf = et_newbuf_hdr }, 210 { .bufsize = ET_RXDMA_CTRL_RING1_16384, .jumbo = 1, 211 .newbuf = et_newbuf_jumbo }, 212 }; 213 214 static int 215 et_probe(device_t dev) 216 { 217 const struct et_dev *d; 218 uint16_t did, vid; 219 220 vid = pci_get_vendor(dev); 221 did = pci_get_device(dev); 222 223 for (d = et_devices; d->desc != NULL; ++d) { 224 if (vid == d->vid && did == d->did) { 225 device_set_desc(dev, d->desc); 226 return 0; 227 } 228 } 229 return ENXIO; 230 } 231 232 static int 233 et_attach(device_t dev) 234 { 235 struct et_softc *sc = device_get_softc(dev); 236 struct ifnet *ifp = &sc->arpcom.ac_if; 237 uint8_t eaddr[ETHER_ADDR_LEN]; 238 int error; 239 u_int irq_flags; 240 241 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 242 callout_init(&sc->sc_tick); 243 244 /* 245 * Initialize tunables 246 */ 247 sc->sc_rx_intr_npkts = et_rx_intr_npkts; 248 sc->sc_rx_intr_delay = et_rx_intr_delay; 249 sc->sc_tx_intr_nsegs = et_tx_intr_nsegs; 250 sc->sc_timer = et_timer; 251 252 #ifndef BURN_BRIDGES 253 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 254 uint32_t irq, mem; 255 256 irq = pci_read_config(dev, PCIR_INTLINE, 4); 257 mem = pci_read_config(dev, ET_PCIR_BAR, 4); 258 259 device_printf(dev, "chip is in D%d power mode " 260 "-- setting to D0\n", pci_get_powerstate(dev)); 261 262 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 263 264 pci_write_config(dev, PCIR_INTLINE, irq, 4); 265 pci_write_config(dev, ET_PCIR_BAR, mem, 4); 266 } 267 #endif /* !BURN_BRIDGE */ 268 269 /* Enable bus mastering */ 270 pci_enable_busmaster(dev); 271 272 /* 273 * Allocate IO memory 274 */ 275 sc->sc_mem_rid = ET_PCIR_BAR; 276 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 277 &sc->sc_mem_rid, RF_ACTIVE); 278 if (sc->sc_mem_res == NULL) { 279 device_printf(dev, "can't allocate IO memory\n"); 280 return ENXIO; 281 } 282 sc->sc_mem_bt = rman_get_bustag(sc->sc_mem_res); 283 sc->sc_mem_bh = rman_get_bushandle(sc->sc_mem_res); 284 285 /* 286 * Allocate IRQ 287 */ 288 sc->sc_irq_type = pci_alloc_1intr(dev, et_msi_enable, 289 &sc->sc_irq_rid, &irq_flags); 290 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 291 &sc->sc_irq_rid, irq_flags); 292 if (sc->sc_irq_res == NULL) { 293 device_printf(dev, "can't allocate irq\n"); 294 error = ENXIO; 295 goto fail; 296 } 297 298 /* 299 * Create sysctl tree 300 */ 301 sysctl_ctx_init(&sc->sc_sysctl_ctx); 302 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx, 303 SYSCTL_STATIC_CHILDREN(_hw), 304 OID_AUTO, 305 device_get_nameunit(dev), 306 CTLFLAG_RD, 0, ""); 307 if (sc->sc_sysctl_tree == NULL) { 308 device_printf(dev, "can't add sysctl node\n"); 309 error = ENXIO; 310 goto fail; 311 } 312 313 SYSCTL_ADD_PROC(&sc->sc_sysctl_ctx, 314 SYSCTL_CHILDREN(sc->sc_sysctl_tree), 315 OID_AUTO, "rx_intr_npkts", CTLTYPE_INT | CTLFLAG_RW, 316 sc, 0, et_sysctl_rx_intr_npkts, "I", 317 "RX IM, # packets per RX interrupt"); 318 SYSCTL_ADD_PROC(&sc->sc_sysctl_ctx, 319 SYSCTL_CHILDREN(sc->sc_sysctl_tree), 320 OID_AUTO, "rx_intr_delay", CTLTYPE_INT | CTLFLAG_RW, 321 sc, 0, et_sysctl_rx_intr_delay, "I", 322 "RX IM, RX interrupt delay (x10 usec)"); 323 SYSCTL_ADD_INT(&sc->sc_sysctl_ctx, 324 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO, 325 "tx_intr_nsegs", CTLFLAG_RW, &sc->sc_tx_intr_nsegs, 0, 326 "TX IM, # segments per TX interrupt"); 327 SYSCTL_ADD_UINT(&sc->sc_sysctl_ctx, 328 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO, 329 "timer", CTLFLAG_RW, &sc->sc_timer, 0, 330 "TX timer"); 331 332 error = et_bus_config(dev); 333 if (error) 334 goto fail; 335 336 et_get_eaddr(dev, eaddr); 337 338 CSR_WRITE_4(sc, ET_PM, 339 ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE); 340 341 et_reset(sc); 342 343 et_disable_intrs(sc); 344 345 error = et_dma_alloc(dev); 346 if (error) 347 goto fail; 348 349 ifp->if_softc = sc; 350 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 351 ifp->if_init = et_init; 352 ifp->if_ioctl = et_ioctl; 353 ifp->if_start = et_start; 354 ifp->if_watchdog = et_watchdog; 355 ifp->if_mtu = ETHERMTU; 356 ifp->if_capabilities = IFCAP_VLAN_MTU; 357 ifp->if_capenable = ifp->if_capabilities; 358 ifq_set_maxlen(&ifp->if_snd, ET_TX_NDESC); 359 ifq_set_ready(&ifp->if_snd); 360 361 et_chip_attach(sc); 362 363 error = mii_phy_probe(dev, &sc->sc_miibus, 364 et_ifmedia_upd, et_ifmedia_sts); 365 if (error) { 366 device_printf(dev, "can't probe any PHY\n"); 367 goto fail; 368 } 369 370 ether_ifattach(ifp, eaddr, NULL); 371 372 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->sc_irq_res)); 373 374 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, et_intr, sc, 375 &sc->sc_irq_handle, ifp->if_serializer); 376 if (error) { 377 ether_ifdetach(ifp); 378 device_printf(dev, "can't setup intr\n"); 379 goto fail; 380 } 381 382 return 0; 383 fail: 384 et_detach(dev); 385 return error; 386 } 387 388 static int 389 et_detach(device_t dev) 390 { 391 struct et_softc *sc = device_get_softc(dev); 392 393 if (device_is_attached(dev)) { 394 struct ifnet *ifp = &sc->arpcom.ac_if; 395 396 lwkt_serialize_enter(ifp->if_serializer); 397 et_stop(sc); 398 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_handle); 399 lwkt_serialize_exit(ifp->if_serializer); 400 401 ether_ifdetach(ifp); 402 } 403 404 if (sc->sc_sysctl_tree != NULL) 405 sysctl_ctx_free(&sc->sc_sysctl_ctx); 406 407 if (sc->sc_miibus != NULL) 408 device_delete_child(dev, sc->sc_miibus); 409 bus_generic_detach(dev); 410 411 if (sc->sc_irq_res != NULL) { 412 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid, 413 sc->sc_irq_res); 414 } 415 if (sc->sc_irq_type == PCI_INTR_TYPE_MSI) 416 pci_release_msi(dev); 417 418 if (sc->sc_mem_res != NULL) { 419 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid, 420 sc->sc_mem_res); 421 } 422 423 et_dma_free(dev); 424 425 return 0; 426 } 427 428 static int 429 et_shutdown(device_t dev) 430 { 431 struct et_softc *sc = device_get_softc(dev); 432 struct ifnet *ifp = &sc->arpcom.ac_if; 433 434 lwkt_serialize_enter(ifp->if_serializer); 435 et_stop(sc); 436 lwkt_serialize_exit(ifp->if_serializer); 437 return 0; 438 } 439 440 static int 441 et_miibus_readreg(device_t dev, int phy, int reg) 442 { 443 struct et_softc *sc = device_get_softc(dev); 444 uint32_t val; 445 int i, ret; 446 447 /* Stop any pending operations */ 448 CSR_WRITE_4(sc, ET_MII_CMD, 0); 449 450 val = __SHIFTIN(phy, ET_MII_ADDR_PHY) | 451 __SHIFTIN(reg, ET_MII_ADDR_REG); 452 CSR_WRITE_4(sc, ET_MII_ADDR, val); 453 454 /* Start reading */ 455 CSR_WRITE_4(sc, ET_MII_CMD, ET_MII_CMD_READ); 456 457 #define NRETRY 50 458 459 for (i = 0; i < NRETRY; ++i) { 460 val = CSR_READ_4(sc, ET_MII_IND); 461 if ((val & (ET_MII_IND_BUSY | ET_MII_IND_INVALID)) == 0) 462 break; 463 DELAY(50); 464 } 465 if (i == NRETRY) { 466 if_printf(&sc->arpcom.ac_if, 467 "read phy %d, reg %d timed out\n", phy, reg); 468 ret = 0; 469 goto back; 470 } 471 472 #undef NRETRY 473 474 val = CSR_READ_4(sc, ET_MII_STAT); 475 ret = __SHIFTOUT(val, ET_MII_STAT_VALUE); 476 477 back: 478 /* Make sure that the current operation is stopped */ 479 CSR_WRITE_4(sc, ET_MII_CMD, 0); 480 return ret; 481 } 482 483 static int 484 et_miibus_writereg(device_t dev, int phy, int reg, int val0) 485 { 486 struct et_softc *sc = device_get_softc(dev); 487 uint32_t val; 488 int i; 489 490 /* Stop any pending operations */ 491 CSR_WRITE_4(sc, ET_MII_CMD, 0); 492 493 val = __SHIFTIN(phy, ET_MII_ADDR_PHY) | 494 __SHIFTIN(reg, ET_MII_ADDR_REG); 495 CSR_WRITE_4(sc, ET_MII_ADDR, val); 496 497 /* Start writing */ 498 CSR_WRITE_4(sc, ET_MII_CTRL, __SHIFTIN(val0, ET_MII_CTRL_VALUE)); 499 500 #define NRETRY 100 501 502 for (i = 0; i < NRETRY; ++i) { 503 val = CSR_READ_4(sc, ET_MII_IND); 504 if ((val & ET_MII_IND_BUSY) == 0) 505 break; 506 DELAY(50); 507 } 508 if (i == NRETRY) { 509 if_printf(&sc->arpcom.ac_if, 510 "write phy %d, reg %d timed out\n", phy, reg); 511 et_miibus_readreg(dev, phy, reg); 512 } 513 514 #undef NRETRY 515 516 /* Make sure that the current operation is stopped */ 517 CSR_WRITE_4(sc, ET_MII_CMD, 0); 518 return 0; 519 } 520 521 static void 522 et_miibus_statchg(device_t dev) 523 { 524 et_setmedia(device_get_softc(dev)); 525 } 526 527 static int 528 et_ifmedia_upd(struct ifnet *ifp) 529 { 530 struct et_softc *sc = ifp->if_softc; 531 struct mii_data *mii = device_get_softc(sc->sc_miibus); 532 533 if (mii->mii_instance != 0) { 534 struct mii_softc *miisc; 535 536 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 537 mii_phy_reset(miisc); 538 } 539 mii_mediachg(mii); 540 541 return 0; 542 } 543 544 static void 545 et_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 546 { 547 struct et_softc *sc = ifp->if_softc; 548 struct mii_data *mii = device_get_softc(sc->sc_miibus); 549 550 mii_pollstat(mii); 551 ifmr->ifm_active = mii->mii_media_active; 552 ifmr->ifm_status = mii->mii_media_status; 553 } 554 555 static void 556 et_stop(struct et_softc *sc) 557 { 558 struct ifnet *ifp = &sc->arpcom.ac_if; 559 560 ASSERT_SERIALIZED(ifp->if_serializer); 561 562 callout_stop(&sc->sc_tick); 563 564 et_stop_rxdma(sc); 565 et_stop_txdma(sc); 566 567 et_disable_intrs(sc); 568 569 et_free_tx_ring(sc); 570 et_free_rx_ring(sc); 571 572 et_reset(sc); 573 574 sc->sc_tx = 0; 575 sc->sc_tx_intr = 0; 576 sc->sc_flags &= ~ET_FLAG_TXRX_ENABLED; 577 578 ifp->if_timer = 0; 579 ifp->if_flags &= ~IFF_RUNNING; 580 ifq_clr_oactive(&ifp->if_snd); 581 } 582 583 static int 584 et_bus_config(device_t dev) 585 { 586 uint32_t val, max_plsz; 587 uint16_t ack_latency, replay_timer; 588 589 /* 590 * Test whether EEPROM is valid 591 * NOTE: Read twice to get the correct value 592 */ 593 pci_read_config(dev, ET_PCIR_EEPROM_STATUS, 1); 594 val = pci_read_config(dev, ET_PCIR_EEPROM_STATUS, 1); 595 if (val & ET_PCIM_EEPROM_STATUS_ERROR) { 596 device_printf(dev, "EEPROM status error 0x%02x\n", val); 597 return ENXIO; 598 } 599 600 /* TODO: LED */ 601 602 /* 603 * Configure ACK latency and replay timer according to 604 * max playload size 605 */ 606 val = pci_read_config(dev, ET_PCIR_DEVICE_CAPS, 4); 607 max_plsz = val & ET_PCIM_DEVICE_CAPS_MAX_PLSZ; 608 609 switch (max_plsz) { 610 case ET_PCIV_DEVICE_CAPS_PLSZ_128: 611 ack_latency = ET_PCIV_ACK_LATENCY_128; 612 replay_timer = ET_PCIV_REPLAY_TIMER_128; 613 break; 614 615 case ET_PCIV_DEVICE_CAPS_PLSZ_256: 616 ack_latency = ET_PCIV_ACK_LATENCY_256; 617 replay_timer = ET_PCIV_REPLAY_TIMER_256; 618 break; 619 620 default: 621 ack_latency = pci_read_config(dev, ET_PCIR_ACK_LATENCY, 2); 622 replay_timer = pci_read_config(dev, ET_PCIR_REPLAY_TIMER, 2); 623 device_printf(dev, "ack latency %u, replay timer %u\n", 624 ack_latency, replay_timer); 625 break; 626 } 627 if (ack_latency != 0) { 628 pci_write_config(dev, ET_PCIR_ACK_LATENCY, ack_latency, 2); 629 pci_write_config(dev, ET_PCIR_REPLAY_TIMER, replay_timer, 2); 630 } 631 632 /* 633 * Set L0s and L1 latency timer to 2us 634 */ 635 val = ET_PCIV_L0S_LATENCY(2) | ET_PCIV_L1_LATENCY(2); 636 pci_write_config(dev, ET_PCIR_L0S_L1_LATENCY, val, 1); 637 638 /* 639 * Set max read request size to 2048 bytes 640 */ 641 val = pci_read_config(dev, ET_PCIR_DEVICE_CTRL, 2); 642 val &= ~ET_PCIM_DEVICE_CTRL_MAX_RRSZ; 643 val |= ET_PCIV_DEVICE_CTRL_RRSZ_2K; 644 pci_write_config(dev, ET_PCIR_DEVICE_CTRL, val, 2); 645 646 return 0; 647 } 648 649 static void 650 et_get_eaddr(device_t dev, uint8_t eaddr[]) 651 { 652 uint32_t val; 653 int i; 654 655 val = pci_read_config(dev, ET_PCIR_MAC_ADDR0, 4); 656 for (i = 0; i < 4; ++i) 657 eaddr[i] = (val >> (8 * i)) & 0xff; 658 659 val = pci_read_config(dev, ET_PCIR_MAC_ADDR1, 2); 660 for (; i < ETHER_ADDR_LEN; ++i) 661 eaddr[i] = (val >> (8 * (i - 4))) & 0xff; 662 } 663 664 static void 665 et_reset(struct et_softc *sc) 666 { 667 CSR_WRITE_4(sc, ET_MAC_CFG1, 668 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 669 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 670 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 671 672 CSR_WRITE_4(sc, ET_SWRST, 673 ET_SWRST_TXDMA | ET_SWRST_RXDMA | 674 ET_SWRST_TXMAC | ET_SWRST_RXMAC | 675 ET_SWRST_MAC | ET_SWRST_MAC_STAT | ET_SWRST_MMC); 676 677 CSR_WRITE_4(sc, ET_MAC_CFG1, 678 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 679 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC); 680 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 681 } 682 683 static void 684 et_disable_intrs(struct et_softc *sc) 685 { 686 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 687 } 688 689 static void 690 et_enable_intrs(struct et_softc *sc, uint32_t intrs) 691 { 692 CSR_WRITE_4(sc, ET_INTR_MASK, ~intrs); 693 } 694 695 static int 696 et_dma_alloc(device_t dev) 697 { 698 struct et_softc *sc = device_get_softc(dev); 699 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 700 struct et_txstatus_data *txsd = &sc->sc_tx_status; 701 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 702 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 703 int i, error; 704 705 /* 706 * Create top level DMA tag 707 */ 708 error = bus_dma_tag_create(NULL, 1, 0, 709 BUS_SPACE_MAXADDR, 710 BUS_SPACE_MAXADDR, 711 NULL, NULL, 712 BUS_SPACE_MAXSIZE_32BIT, 713 0, 714 BUS_SPACE_MAXSIZE_32BIT, 715 0, &sc->sc_dtag); 716 if (error) { 717 device_printf(dev, "can't create DMA tag\n"); 718 return error; 719 } 720 721 /* 722 * Create TX ring DMA stuffs 723 */ 724 tx_ring->tr_desc = bus_dmamem_coherent_any(sc->sc_dtag, 725 ET_ALIGN, ET_TX_RING_SIZE, 726 BUS_DMA_WAITOK | BUS_DMA_ZERO, 727 &tx_ring->tr_dtag, &tx_ring->tr_dmap, 728 &tx_ring->tr_paddr); 729 if (tx_ring->tr_desc == NULL) { 730 device_printf(dev, "can't create TX ring DMA stuffs\n"); 731 return ENOMEM; 732 } 733 734 /* 735 * Create TX status DMA stuffs 736 */ 737 txsd->txsd_status = bus_dmamem_coherent_any(sc->sc_dtag, 738 ET_ALIGN, sizeof(uint32_t), 739 BUS_DMA_WAITOK | BUS_DMA_ZERO, 740 &txsd->txsd_dtag, &txsd->txsd_dmap, 741 &txsd->txsd_paddr); 742 if (txsd->txsd_status == NULL) { 743 device_printf(dev, "can't create TX status DMA stuffs\n"); 744 return ENOMEM; 745 } 746 747 /* 748 * Create DMA stuffs for RX rings 749 */ 750 for (i = 0; i < ET_RX_NRING; ++i) { 751 static const uint32_t rx_ring_posreg[ET_RX_NRING] = 752 { ET_RX_RING0_POS, ET_RX_RING1_POS }; 753 754 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[i]; 755 756 rx_ring->rr_desc = bus_dmamem_coherent_any(sc->sc_dtag, 757 ET_ALIGN, ET_RX_RING_SIZE, 758 BUS_DMA_WAITOK | BUS_DMA_ZERO, 759 &rx_ring->rr_dtag, &rx_ring->rr_dmap, 760 &rx_ring->rr_paddr); 761 if (rx_ring->rr_desc == NULL) { 762 device_printf(dev, "can't create DMA stuffs for " 763 "the %d RX ring\n", i); 764 return ENOMEM; 765 } 766 rx_ring->rr_posreg = rx_ring_posreg[i]; 767 } 768 769 /* 770 * Create RX stat ring DMA stuffs 771 */ 772 rxst_ring->rsr_stat = bus_dmamem_coherent_any(sc->sc_dtag, 773 ET_ALIGN, ET_RXSTAT_RING_SIZE, 774 BUS_DMA_WAITOK | BUS_DMA_ZERO, 775 &rxst_ring->rsr_dtag, &rxst_ring->rsr_dmap, 776 &rxst_ring->rsr_paddr); 777 if (rxst_ring->rsr_stat == NULL) { 778 device_printf(dev, "can't create RX stat ring DMA stuffs\n"); 779 return ENOMEM; 780 } 781 782 /* 783 * Create RX status DMA stuffs 784 */ 785 rxsd->rxsd_status = bus_dmamem_coherent_any(sc->sc_dtag, 786 ET_ALIGN, sizeof(struct et_rxstatus), 787 BUS_DMA_WAITOK | BUS_DMA_ZERO, 788 &rxsd->rxsd_dtag, &rxsd->rxsd_dmap, 789 &rxsd->rxsd_paddr); 790 if (rxsd->rxsd_status == NULL) { 791 device_printf(dev, "can't create RX status DMA stuffs\n"); 792 return ENOMEM; 793 } 794 795 /* 796 * Create mbuf DMA stuffs 797 */ 798 error = et_dma_mbuf_create(dev); 799 if (error) 800 return error; 801 802 /* 803 * Create jumbo buffer DMA stuffs 804 * NOTE: Allow it to fail 805 */ 806 if (et_jumbo_mem_alloc(dev) == 0) 807 sc->sc_flags |= ET_FLAG_JUMBO; 808 809 return 0; 810 } 811 812 static void 813 et_dma_free(device_t dev) 814 { 815 struct et_softc *sc = device_get_softc(dev); 816 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 817 struct et_txstatus_data *txsd = &sc->sc_tx_status; 818 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 819 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 820 int i, rx_done[ET_RX_NRING]; 821 822 /* 823 * Destroy TX ring DMA stuffs 824 */ 825 et_dma_mem_destroy(tx_ring->tr_dtag, tx_ring->tr_desc, 826 tx_ring->tr_dmap); 827 828 /* 829 * Destroy TX status DMA stuffs 830 */ 831 et_dma_mem_destroy(txsd->txsd_dtag, txsd->txsd_status, 832 txsd->txsd_dmap); 833 834 /* 835 * Destroy DMA stuffs for RX rings 836 */ 837 for (i = 0; i < ET_RX_NRING; ++i) { 838 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[i]; 839 840 et_dma_mem_destroy(rx_ring->rr_dtag, rx_ring->rr_desc, 841 rx_ring->rr_dmap); 842 } 843 844 /* 845 * Destroy RX stat ring DMA stuffs 846 */ 847 et_dma_mem_destroy(rxst_ring->rsr_dtag, rxst_ring->rsr_stat, 848 rxst_ring->rsr_dmap); 849 850 /* 851 * Destroy RX status DMA stuffs 852 */ 853 et_dma_mem_destroy(rxsd->rxsd_dtag, rxsd->rxsd_status, 854 rxsd->rxsd_dmap); 855 856 /* 857 * Destroy mbuf DMA stuffs 858 */ 859 for (i = 0; i < ET_RX_NRING; ++i) 860 rx_done[i] = ET_RX_NDESC; 861 et_dma_mbuf_destroy(dev, ET_TX_NDESC, rx_done); 862 863 /* 864 * Destroy jumbo buffer DMA stuffs 865 */ 866 if (sc->sc_flags & ET_FLAG_JUMBO) 867 et_jumbo_mem_free(dev); 868 869 /* 870 * Destroy top level DMA tag 871 */ 872 if (sc->sc_dtag != NULL) 873 bus_dma_tag_destroy(sc->sc_dtag); 874 } 875 876 static int 877 et_dma_mbuf_create(device_t dev) 878 { 879 struct et_softc *sc = device_get_softc(dev); 880 struct et_txbuf_data *tbd = &sc->sc_tx_data; 881 int i, error, rx_done[ET_RX_NRING]; 882 883 /* 884 * Create RX mbuf DMA tag 885 */ 886 error = bus_dma_tag_create(sc->sc_dtag, 1, 0, 887 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 888 NULL, NULL, 889 MCLBYTES, 1, MCLBYTES, 890 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK, 891 &sc->sc_rxbuf_dtag); 892 if (error) { 893 device_printf(dev, "can't create RX mbuf DMA tag\n"); 894 return error; 895 } 896 897 /* 898 * Create spare DMA map for RX mbufs 899 */ 900 error = bus_dmamap_create(sc->sc_rxbuf_dtag, BUS_DMA_WAITOK, 901 &sc->sc_rxbuf_tmp_dmap); 902 if (error) { 903 device_printf(dev, "can't create spare mbuf DMA map\n"); 904 bus_dma_tag_destroy(sc->sc_rxbuf_dtag); 905 sc->sc_rxbuf_dtag = NULL; 906 return error; 907 } 908 909 /* 910 * Create DMA maps for RX mbufs 911 */ 912 bzero(rx_done, sizeof(rx_done)); 913 for (i = 0; i < ET_RX_NRING; ++i) { 914 struct et_rxbuf_data *rbd = &sc->sc_rx_data[i]; 915 int j; 916 917 for (j = 0; j < ET_RX_NDESC; ++j) { 918 error = bus_dmamap_create(sc->sc_rxbuf_dtag, 919 BUS_DMA_WAITOK, 920 &rbd->rbd_buf[j].rb_dmap); 921 if (error) { 922 device_printf(dev, "can't create %d RX mbuf " 923 "for %d RX ring\n", j, i); 924 rx_done[i] = j; 925 et_dma_mbuf_destroy(dev, 0, rx_done); 926 return error; 927 } 928 } 929 rx_done[i] = ET_RX_NDESC; 930 931 rbd->rbd_softc = sc; 932 rbd->rbd_ring = &sc->sc_rx_ring[i]; 933 } 934 935 /* 936 * Create TX mbuf DMA tag 937 */ 938 error = bus_dma_tag_create(sc->sc_dtag, 1, 0, 939 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 940 NULL, NULL, 941 ET_JUMBO_FRAMELEN, ET_NSEG_MAX, MCLBYTES, 942 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | 943 BUS_DMA_ONEBPAGE, 944 &sc->sc_txbuf_dtag); 945 if (error) { 946 device_printf(dev, "can't create TX mbuf DMA tag\n"); 947 return error; 948 } 949 950 /* 951 * Create DMA maps for TX mbufs 952 */ 953 for (i = 0; i < ET_TX_NDESC; ++i) { 954 error = bus_dmamap_create(sc->sc_txbuf_dtag, 955 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 956 &tbd->tbd_buf[i].tb_dmap); 957 if (error) { 958 device_printf(dev, "can't create %d TX mbuf " 959 "DMA map\n", i); 960 et_dma_mbuf_destroy(dev, i, rx_done); 961 return error; 962 } 963 } 964 965 return 0; 966 } 967 968 static void 969 et_dma_mbuf_destroy(device_t dev, int tx_done, const int rx_done[]) 970 { 971 struct et_softc *sc = device_get_softc(dev); 972 struct et_txbuf_data *tbd = &sc->sc_tx_data; 973 int i; 974 975 /* 976 * Destroy DMA tag and maps for RX mbufs 977 */ 978 if (sc->sc_rxbuf_dtag) { 979 for (i = 0; i < ET_RX_NRING; ++i) { 980 struct et_rxbuf_data *rbd = &sc->sc_rx_data[i]; 981 int j; 982 983 for (j = 0; j < rx_done[i]; ++j) { 984 struct et_rxbuf *rb = &rbd->rbd_buf[j]; 985 986 KASSERT(rb->rb_mbuf == NULL, 987 ("RX mbuf in %d RX ring is " 988 "not freed yet", i)); 989 bus_dmamap_destroy(sc->sc_rxbuf_dtag, 990 rb->rb_dmap); 991 } 992 } 993 bus_dmamap_destroy(sc->sc_rxbuf_dtag, sc->sc_rxbuf_tmp_dmap); 994 bus_dma_tag_destroy(sc->sc_rxbuf_dtag); 995 sc->sc_rxbuf_dtag = NULL; 996 } 997 998 /* 999 * Destroy DMA tag and maps for TX mbufs 1000 */ 1001 if (sc->sc_txbuf_dtag) { 1002 for (i = 0; i < tx_done; ++i) { 1003 struct et_txbuf *tb = &tbd->tbd_buf[i]; 1004 1005 KASSERT(tb->tb_mbuf == NULL, 1006 ("TX mbuf is not freed yet")); 1007 bus_dmamap_destroy(sc->sc_txbuf_dtag, tb->tb_dmap); 1008 } 1009 bus_dma_tag_destroy(sc->sc_txbuf_dtag); 1010 sc->sc_txbuf_dtag = NULL; 1011 } 1012 } 1013 1014 static void 1015 et_dma_mem_destroy(bus_dma_tag_t dtag, void *addr, bus_dmamap_t dmap) 1016 { 1017 if (dtag != NULL) { 1018 bus_dmamap_unload(dtag, dmap); 1019 bus_dmamem_free(dtag, addr, dmap); 1020 bus_dma_tag_destroy(dtag); 1021 } 1022 } 1023 1024 static void 1025 et_chip_attach(struct et_softc *sc) 1026 { 1027 uint32_t val; 1028 1029 /* 1030 * Perform minimal initialization 1031 */ 1032 1033 /* Disable loopback */ 1034 CSR_WRITE_4(sc, ET_LOOPBACK, 0); 1035 1036 /* Reset MAC */ 1037 CSR_WRITE_4(sc, ET_MAC_CFG1, 1038 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 1039 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 1040 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 1041 1042 /* 1043 * Setup half duplex mode 1044 */ 1045 val = __SHIFTIN(10, ET_MAC_HDX_ALT_BEB_TRUNC) | 1046 __SHIFTIN(15, ET_MAC_HDX_REXMIT_MAX) | 1047 __SHIFTIN(55, ET_MAC_HDX_COLLWIN) | 1048 ET_MAC_HDX_EXC_DEFER; 1049 CSR_WRITE_4(sc, ET_MAC_HDX, val); 1050 1051 /* Clear MAC control */ 1052 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 1053 1054 /* Reset MII */ 1055 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 1056 1057 /* Bring MAC out of reset state */ 1058 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 1059 1060 /* Enable memory controllers */ 1061 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 1062 } 1063 1064 static void 1065 et_intr(void *xsc) 1066 { 1067 struct et_softc *sc = xsc; 1068 struct ifnet *ifp = &sc->arpcom.ac_if; 1069 uint32_t intrs; 1070 1071 ASSERT_SERIALIZED(ifp->if_serializer); 1072 1073 if ((ifp->if_flags & IFF_RUNNING) == 0) 1074 return; 1075 1076 et_disable_intrs(sc); 1077 1078 intrs = CSR_READ_4(sc, ET_INTR_STATUS); 1079 intrs &= ET_INTRS; 1080 if (intrs == 0) /* Not interested */ 1081 goto back; 1082 1083 if (intrs & ET_INTR_RXEOF) 1084 et_rxeof(sc); 1085 if (intrs & (ET_INTR_TXEOF | ET_INTR_TIMER)) 1086 et_txeof(sc, 1); 1087 if (intrs & ET_INTR_TIMER) 1088 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 1089 back: 1090 et_enable_intrs(sc, ET_INTRS); 1091 } 1092 1093 static void 1094 et_init(void *xsc) 1095 { 1096 struct et_softc *sc = xsc; 1097 struct ifnet *ifp = &sc->arpcom.ac_if; 1098 const struct et_bsize *arr; 1099 int error, i; 1100 1101 ASSERT_SERIALIZED(ifp->if_serializer); 1102 1103 et_stop(sc); 1104 1105 arr = ET_FRAMELEN(ifp->if_mtu) < MCLBYTES ? 1106 et_bufsize_std : et_bufsize_jumbo; 1107 for (i = 0; i < ET_RX_NRING; ++i) { 1108 sc->sc_rx_data[i].rbd_bufsize = arr[i].bufsize; 1109 sc->sc_rx_data[i].rbd_newbuf = arr[i].newbuf; 1110 sc->sc_rx_data[i].rbd_jumbo = arr[i].jumbo; 1111 } 1112 1113 error = et_init_tx_ring(sc); 1114 if (error) 1115 goto back; 1116 1117 error = et_init_rx_ring(sc); 1118 if (error) 1119 goto back; 1120 1121 error = et_chip_init(sc); 1122 if (error) 1123 goto back; 1124 1125 error = et_enable_txrx(sc, 1); 1126 if (error) 1127 goto back; 1128 1129 et_enable_intrs(sc, ET_INTRS); 1130 1131 callout_reset(&sc->sc_tick, hz, et_tick, sc); 1132 1133 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 1134 1135 ifp->if_flags |= IFF_RUNNING; 1136 ifq_clr_oactive(&ifp->if_snd); 1137 back: 1138 if (error) 1139 et_stop(sc); 1140 } 1141 1142 static int 1143 et_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr) 1144 { 1145 struct et_softc *sc = ifp->if_softc; 1146 struct mii_data *mii = device_get_softc(sc->sc_miibus); 1147 struct ifreq *ifr = (struct ifreq *)data; 1148 int error = 0, max_framelen; 1149 1150 ASSERT_SERIALIZED(ifp->if_serializer); 1151 1152 switch (cmd) { 1153 case SIOCSIFFLAGS: 1154 if (ifp->if_flags & IFF_UP) { 1155 if (ifp->if_flags & IFF_RUNNING) { 1156 if ((ifp->if_flags ^ sc->sc_if_flags) & 1157 (IFF_ALLMULTI | IFF_PROMISC)) 1158 et_setmulti(sc); 1159 } else { 1160 et_init(sc); 1161 } 1162 } else { 1163 if (ifp->if_flags & IFF_RUNNING) 1164 et_stop(sc); 1165 } 1166 sc->sc_if_flags = ifp->if_flags; 1167 break; 1168 1169 case SIOCSIFMEDIA: 1170 case SIOCGIFMEDIA: 1171 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1172 break; 1173 1174 case SIOCADDMULTI: 1175 case SIOCDELMULTI: 1176 if (ifp->if_flags & IFF_RUNNING) 1177 et_setmulti(sc); 1178 break; 1179 1180 case SIOCSIFMTU: 1181 if (sc->sc_flags & ET_FLAG_JUMBO) 1182 max_framelen = ET_JUMBO_FRAMELEN; 1183 else 1184 max_framelen = MCLBYTES - 1; 1185 1186 if (ET_FRAMELEN(ifr->ifr_mtu) > max_framelen) { 1187 error = EOPNOTSUPP; 1188 break; 1189 } 1190 1191 ifp->if_mtu = ifr->ifr_mtu; 1192 if (ifp->if_flags & IFF_RUNNING) 1193 et_init(sc); 1194 break; 1195 1196 default: 1197 error = ether_ioctl(ifp, cmd, data); 1198 break; 1199 } 1200 return error; 1201 } 1202 1203 static void 1204 et_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 1205 { 1206 struct et_softc *sc = ifp->if_softc; 1207 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1208 int trans, oactive; 1209 1210 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 1211 ASSERT_SERIALIZED(ifp->if_serializer); 1212 1213 if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) { 1214 ifq_purge(&ifp->if_snd); 1215 return; 1216 } 1217 1218 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd)) 1219 return; 1220 1221 oactive = 0; 1222 trans = 0; 1223 for (;;) { 1224 struct mbuf *m; 1225 int error; 1226 1227 if ((tbd->tbd_used + ET_NSEG_SPARE) > ET_TX_NDESC) { 1228 if (oactive) { 1229 ifq_set_oactive(&ifp->if_snd); 1230 break; 1231 } 1232 1233 et_txeof(sc, 0); 1234 oactive = 1; 1235 continue; 1236 } 1237 1238 m = ifq_dequeue(&ifp->if_snd); 1239 if (m == NULL) 1240 break; 1241 1242 error = et_encap(sc, &m); 1243 if (error) { 1244 IFNET_STAT_INC(ifp, oerrors, 1); 1245 KKASSERT(m == NULL); 1246 1247 if (error == EFBIG) { 1248 /* 1249 * Excessive fragmented packets 1250 */ 1251 if (oactive) { 1252 ifq_set_oactive(&ifp->if_snd); 1253 break; 1254 } 1255 et_txeof(sc, 0); 1256 oactive = 1; 1257 } 1258 continue; 1259 } else { 1260 oactive = 0; 1261 } 1262 trans = 1; 1263 1264 BPF_MTAP(ifp, m); 1265 } 1266 1267 if (trans) 1268 ifp->if_timer = 5; 1269 } 1270 1271 static void 1272 et_watchdog(struct ifnet *ifp) 1273 { 1274 ASSERT_SERIALIZED(ifp->if_serializer); 1275 1276 if_printf(ifp, "watchdog timed out\n"); 1277 1278 ifp->if_init(ifp->if_softc); 1279 if_devstart(ifp); 1280 } 1281 1282 static int 1283 et_stop_rxdma(struct et_softc *sc) 1284 { 1285 CSR_WRITE_4(sc, ET_RXDMA_CTRL, 1286 ET_RXDMA_CTRL_HALT | ET_RXDMA_CTRL_RING1_ENABLE); 1287 1288 DELAY(5); 1289 if ((CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) == 0) { 1290 if_printf(&sc->arpcom.ac_if, "can't stop RX DMA engine\n"); 1291 return ETIMEDOUT; 1292 } 1293 return 0; 1294 } 1295 1296 static int 1297 et_stop_txdma(struct et_softc *sc) 1298 { 1299 CSR_WRITE_4(sc, ET_TXDMA_CTRL, 1300 ET_TXDMA_CTRL_HALT | ET_TXDMA_CTRL_SINGLE_EPKT); 1301 return 0; 1302 } 1303 1304 static void 1305 et_free_tx_ring(struct et_softc *sc) 1306 { 1307 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1308 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1309 int i; 1310 1311 for (i = 0; i < ET_TX_NDESC; ++i) { 1312 struct et_txbuf *tb = &tbd->tbd_buf[i]; 1313 1314 if (tb->tb_mbuf != NULL) { 1315 bus_dmamap_unload(sc->sc_txbuf_dtag, tb->tb_dmap); 1316 m_freem(tb->tb_mbuf); 1317 tb->tb_mbuf = NULL; 1318 } 1319 } 1320 bzero(tx_ring->tr_desc, ET_TX_RING_SIZE); 1321 } 1322 1323 static void 1324 et_free_rx_ring(struct et_softc *sc) 1325 { 1326 int n; 1327 1328 for (n = 0; n < ET_RX_NRING; ++n) { 1329 struct et_rxbuf_data *rbd = &sc->sc_rx_data[n]; 1330 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[n]; 1331 int i; 1332 1333 for (i = 0; i < ET_RX_NDESC; ++i) { 1334 struct et_rxbuf *rb = &rbd->rbd_buf[i]; 1335 1336 if (rb->rb_mbuf != NULL) { 1337 if (!rbd->rbd_jumbo) { 1338 bus_dmamap_unload(sc->sc_rxbuf_dtag, 1339 rb->rb_dmap); 1340 } 1341 m_freem(rb->rb_mbuf); 1342 rb->rb_mbuf = NULL; 1343 } 1344 } 1345 bzero(rx_ring->rr_desc, ET_RX_RING_SIZE); 1346 } 1347 } 1348 1349 static void 1350 et_setmulti(struct et_softc *sc) 1351 { 1352 struct ifnet *ifp = &sc->arpcom.ac_if; 1353 uint32_t hash[4] = { 0, 0, 0, 0 }; 1354 uint32_t rxmac_ctrl, pktfilt; 1355 struct ifmultiaddr *ifma; 1356 int i, count; 1357 1358 pktfilt = CSR_READ_4(sc, ET_PKTFILT); 1359 rxmac_ctrl = CSR_READ_4(sc, ET_RXMAC_CTRL); 1360 1361 pktfilt &= ~(ET_PKTFILT_BCAST | ET_PKTFILT_MCAST | ET_PKTFILT_UCAST); 1362 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 1363 rxmac_ctrl |= ET_RXMAC_CTRL_NO_PKTFILT; 1364 goto back; 1365 } 1366 1367 count = 0; 1368 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1369 uint32_t *hp, h; 1370 1371 if (ifma->ifma_addr->sa_family != AF_LINK) 1372 continue; 1373 1374 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 1375 ifma->ifma_addr), ETHER_ADDR_LEN); 1376 h = (h & 0x3f800000) >> 23; 1377 1378 hp = &hash[0]; 1379 if (h >= 32 && h < 64) { 1380 h -= 32; 1381 hp = &hash[1]; 1382 } else if (h >= 64 && h < 96) { 1383 h -= 64; 1384 hp = &hash[2]; 1385 } else if (h >= 96) { 1386 h -= 96; 1387 hp = &hash[3]; 1388 } 1389 *hp |= (1 << h); 1390 1391 ++count; 1392 } 1393 1394 for (i = 0; i < 4; ++i) 1395 CSR_WRITE_4(sc, ET_MULTI_HASH + (i * 4), hash[i]); 1396 1397 if (count > 0) 1398 pktfilt |= ET_PKTFILT_MCAST; 1399 rxmac_ctrl &= ~ET_RXMAC_CTRL_NO_PKTFILT; 1400 back: 1401 CSR_WRITE_4(sc, ET_PKTFILT, pktfilt); 1402 CSR_WRITE_4(sc, ET_RXMAC_CTRL, rxmac_ctrl); 1403 } 1404 1405 static int 1406 et_chip_init(struct et_softc *sc) 1407 { 1408 struct ifnet *ifp = &sc->arpcom.ac_if; 1409 uint32_t rxq_end; 1410 int error, frame_len, rxmem_size; 1411 1412 /* 1413 * Split 16Kbytes internal memory between TX and RX 1414 * according to frame length. 1415 */ 1416 frame_len = ET_FRAMELEN(ifp->if_mtu); 1417 if (frame_len < 2048) { 1418 rxmem_size = ET_MEM_RXSIZE_DEFAULT; 1419 } else if (frame_len <= ET_RXMAC_CUT_THRU_FRMLEN) { 1420 rxmem_size = ET_MEM_SIZE / 2; 1421 } else { 1422 rxmem_size = ET_MEM_SIZE - 1423 roundup(frame_len + ET_MEM_TXSIZE_EX, ET_MEM_UNIT); 1424 } 1425 rxq_end = ET_QUEUE_ADDR(rxmem_size); 1426 1427 CSR_WRITE_4(sc, ET_RXQUEUE_START, ET_QUEUE_ADDR_START); 1428 CSR_WRITE_4(sc, ET_RXQUEUE_END, rxq_end); 1429 CSR_WRITE_4(sc, ET_TXQUEUE_START, rxq_end + 1); 1430 CSR_WRITE_4(sc, ET_TXQUEUE_END, ET_QUEUE_ADDR_END); 1431 1432 /* No loopback */ 1433 CSR_WRITE_4(sc, ET_LOOPBACK, 0); 1434 1435 /* Clear MSI configure */ 1436 CSR_WRITE_4(sc, ET_MSI_CFG, 0); 1437 1438 /* Disable timer */ 1439 CSR_WRITE_4(sc, ET_TIMER, 0); 1440 1441 /* Initialize MAC */ 1442 et_init_mac(sc); 1443 1444 /* Enable memory controllers */ 1445 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 1446 1447 /* Initialize RX MAC */ 1448 et_init_rxmac(sc); 1449 1450 /* Initialize TX MAC */ 1451 et_init_txmac(sc); 1452 1453 /* Initialize RX DMA engine */ 1454 error = et_init_rxdma(sc); 1455 if (error) 1456 return error; 1457 1458 /* Initialize TX DMA engine */ 1459 error = et_init_txdma(sc); 1460 if (error) 1461 return error; 1462 1463 return 0; 1464 } 1465 1466 static int 1467 et_init_tx_ring(struct et_softc *sc) 1468 { 1469 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1470 struct et_txstatus_data *txsd = &sc->sc_tx_status; 1471 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1472 1473 bzero(tx_ring->tr_desc, ET_TX_RING_SIZE); 1474 1475 tbd->tbd_start_index = 0; 1476 tbd->tbd_start_wrap = 0; 1477 tbd->tbd_used = 0; 1478 1479 bzero(txsd->txsd_status, sizeof(uint32_t)); 1480 1481 return 0; 1482 } 1483 1484 static int 1485 et_init_rx_ring(struct et_softc *sc) 1486 { 1487 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 1488 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 1489 int n; 1490 1491 for (n = 0; n < ET_RX_NRING; ++n) { 1492 struct et_rxbuf_data *rbd = &sc->sc_rx_data[n]; 1493 int i, error; 1494 1495 for (i = 0; i < ET_RX_NDESC; ++i) { 1496 error = rbd->rbd_newbuf(rbd, i, 1); 1497 if (error) { 1498 if_printf(&sc->arpcom.ac_if, "%d ring %d buf, " 1499 "newbuf failed: %d\n", n, i, error); 1500 return error; 1501 } 1502 } 1503 } 1504 1505 bzero(rxsd->rxsd_status, sizeof(struct et_rxstatus)); 1506 bzero(rxst_ring->rsr_stat, ET_RXSTAT_RING_SIZE); 1507 1508 return 0; 1509 } 1510 1511 static int 1512 et_init_rxdma(struct et_softc *sc) 1513 { 1514 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 1515 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 1516 struct et_rxdesc_ring *rx_ring; 1517 int error; 1518 1519 error = et_stop_rxdma(sc); 1520 if (error) { 1521 if_printf(&sc->arpcom.ac_if, "can't init RX DMA engine\n"); 1522 return error; 1523 } 1524 1525 /* 1526 * Install RX status 1527 */ 1528 CSR_WRITE_4(sc, ET_RX_STATUS_HI, ET_ADDR_HI(rxsd->rxsd_paddr)); 1529 CSR_WRITE_4(sc, ET_RX_STATUS_LO, ET_ADDR_LO(rxsd->rxsd_paddr)); 1530 1531 /* 1532 * Install RX stat ring 1533 */ 1534 CSR_WRITE_4(sc, ET_RXSTAT_HI, ET_ADDR_HI(rxst_ring->rsr_paddr)); 1535 CSR_WRITE_4(sc, ET_RXSTAT_LO, ET_ADDR_LO(rxst_ring->rsr_paddr)); 1536 CSR_WRITE_4(sc, ET_RXSTAT_CNT, ET_RX_NSTAT - 1); 1537 CSR_WRITE_4(sc, ET_RXSTAT_POS, 0); 1538 CSR_WRITE_4(sc, ET_RXSTAT_MINCNT, ((ET_RX_NSTAT * 15) / 100) - 1); 1539 1540 /* Match ET_RXSTAT_POS */ 1541 rxst_ring->rsr_index = 0; 1542 rxst_ring->rsr_wrap = 0; 1543 1544 /* 1545 * Install the 2nd RX descriptor ring 1546 */ 1547 rx_ring = &sc->sc_rx_ring[1]; 1548 CSR_WRITE_4(sc, ET_RX_RING1_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1549 CSR_WRITE_4(sc, ET_RX_RING1_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1550 CSR_WRITE_4(sc, ET_RX_RING1_CNT, ET_RX_NDESC - 1); 1551 CSR_WRITE_4(sc, ET_RX_RING1_POS, ET_RX_RING1_POS_WRAP); 1552 CSR_WRITE_4(sc, ET_RX_RING1_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1553 1554 /* Match ET_RX_RING1_POS */ 1555 rx_ring->rr_index = 0; 1556 rx_ring->rr_wrap = 1; 1557 1558 /* 1559 * Install the 1st RX descriptor ring 1560 */ 1561 rx_ring = &sc->sc_rx_ring[0]; 1562 CSR_WRITE_4(sc, ET_RX_RING0_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1563 CSR_WRITE_4(sc, ET_RX_RING0_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1564 CSR_WRITE_4(sc, ET_RX_RING0_CNT, ET_RX_NDESC - 1); 1565 CSR_WRITE_4(sc, ET_RX_RING0_POS, ET_RX_RING0_POS_WRAP); 1566 CSR_WRITE_4(sc, ET_RX_RING0_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1567 1568 /* Match ET_RX_RING0_POS */ 1569 rx_ring->rr_index = 0; 1570 rx_ring->rr_wrap = 1; 1571 1572 /* 1573 * RX intr moderation 1574 */ 1575 CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, sc->sc_rx_intr_npkts); 1576 CSR_WRITE_4(sc, ET_RX_INTR_DELAY, sc->sc_rx_intr_delay); 1577 1578 return 0; 1579 } 1580 1581 static int 1582 et_init_txdma(struct et_softc *sc) 1583 { 1584 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1585 struct et_txstatus_data *txsd = &sc->sc_tx_status; 1586 int error; 1587 1588 error = et_stop_txdma(sc); 1589 if (error) { 1590 if_printf(&sc->arpcom.ac_if, "can't init TX DMA engine\n"); 1591 return error; 1592 } 1593 1594 /* 1595 * Install TX descriptor ring 1596 */ 1597 CSR_WRITE_4(sc, ET_TX_RING_HI, ET_ADDR_HI(tx_ring->tr_paddr)); 1598 CSR_WRITE_4(sc, ET_TX_RING_LO, ET_ADDR_LO(tx_ring->tr_paddr)); 1599 CSR_WRITE_4(sc, ET_TX_RING_CNT, ET_TX_NDESC - 1); 1600 1601 /* 1602 * Install TX status 1603 */ 1604 CSR_WRITE_4(sc, ET_TX_STATUS_HI, ET_ADDR_HI(txsd->txsd_paddr)); 1605 CSR_WRITE_4(sc, ET_TX_STATUS_LO, ET_ADDR_LO(txsd->txsd_paddr)); 1606 1607 CSR_WRITE_4(sc, ET_TX_READY_POS, 0); 1608 1609 /* Match ET_TX_READY_POS */ 1610 tx_ring->tr_ready_index = 0; 1611 tx_ring->tr_ready_wrap = 0; 1612 1613 return 0; 1614 } 1615 1616 static void 1617 et_init_mac(struct et_softc *sc) 1618 { 1619 struct ifnet *ifp = &sc->arpcom.ac_if; 1620 const uint8_t *eaddr = IF_LLADDR(ifp); 1621 uint32_t val; 1622 1623 /* Reset MAC */ 1624 CSR_WRITE_4(sc, ET_MAC_CFG1, 1625 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 1626 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 1627 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 1628 1629 /* 1630 * Setup inter packet gap 1631 */ 1632 val = __SHIFTIN(56, ET_IPG_NONB2B_1) | 1633 __SHIFTIN(88, ET_IPG_NONB2B_2) | 1634 __SHIFTIN(80, ET_IPG_MINIFG) | 1635 __SHIFTIN(96, ET_IPG_B2B); 1636 CSR_WRITE_4(sc, ET_IPG, val); 1637 1638 /* 1639 * Setup half duplex mode 1640 */ 1641 val = __SHIFTIN(10, ET_MAC_HDX_ALT_BEB_TRUNC) | 1642 __SHIFTIN(15, ET_MAC_HDX_REXMIT_MAX) | 1643 __SHIFTIN(55, ET_MAC_HDX_COLLWIN) | 1644 ET_MAC_HDX_EXC_DEFER; 1645 CSR_WRITE_4(sc, ET_MAC_HDX, val); 1646 1647 /* Clear MAC control */ 1648 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 1649 1650 /* Reset MII */ 1651 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 1652 1653 /* 1654 * Set MAC address 1655 */ 1656 val = eaddr[2] | (eaddr[3] << 8) | (eaddr[4] << 16) | (eaddr[5] << 24); 1657 CSR_WRITE_4(sc, ET_MAC_ADDR1, val); 1658 val = (eaddr[0] << 16) | (eaddr[1] << 24); 1659 CSR_WRITE_4(sc, ET_MAC_ADDR2, val); 1660 1661 /* Set max frame length */ 1662 CSR_WRITE_4(sc, ET_MAX_FRMLEN, ET_FRAMELEN(ifp->if_mtu)); 1663 1664 /* Bring MAC out of reset state */ 1665 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 1666 } 1667 1668 static void 1669 et_init_rxmac(struct et_softc *sc) 1670 { 1671 struct ifnet *ifp = &sc->arpcom.ac_if; 1672 const uint8_t *eaddr = IF_LLADDR(ifp); 1673 uint32_t val; 1674 int i; 1675 1676 /* Disable RX MAC and WOL */ 1677 CSR_WRITE_4(sc, ET_RXMAC_CTRL, ET_RXMAC_CTRL_WOL_DISABLE); 1678 1679 /* 1680 * Clear all WOL related registers 1681 */ 1682 for (i = 0; i < 3; ++i) 1683 CSR_WRITE_4(sc, ET_WOL_CRC + (i * 4), 0); 1684 for (i = 0; i < 20; ++i) 1685 CSR_WRITE_4(sc, ET_WOL_MASK + (i * 4), 0); 1686 1687 /* 1688 * Set WOL source address. XXX is this necessary? 1689 */ 1690 val = (eaddr[2] << 24) | (eaddr[3] << 16) | (eaddr[4] << 8) | eaddr[5]; 1691 CSR_WRITE_4(sc, ET_WOL_SA_LO, val); 1692 val = (eaddr[0] << 8) | eaddr[1]; 1693 CSR_WRITE_4(sc, ET_WOL_SA_HI, val); 1694 1695 /* Clear packet filters */ 1696 CSR_WRITE_4(sc, ET_PKTFILT, 0); 1697 1698 /* No ucast filtering */ 1699 CSR_WRITE_4(sc, ET_UCAST_FILTADDR1, 0); 1700 CSR_WRITE_4(sc, ET_UCAST_FILTADDR2, 0); 1701 CSR_WRITE_4(sc, ET_UCAST_FILTADDR3, 0); 1702 1703 if (ET_FRAMELEN(ifp->if_mtu) > ET_RXMAC_CUT_THRU_FRMLEN) { 1704 /* 1705 * In order to transmit jumbo packets greater than 1706 * ET_RXMAC_CUT_THRU_FRMLEN bytes, the FIFO between 1707 * RX MAC and RX DMA needs to be reduced in size to 1708 * (ET_MEM_SIZE - ET_MEM_TXSIZE_EX - framelen). In 1709 * order to implement this, we must use "cut through" 1710 * mode in the RX MAC, which chops packets down into 1711 * segments. In this case we selected 256 bytes, 1712 * since this is the size of the PCI-Express TLP's 1713 * that the ET1310 uses. 1714 */ 1715 val = __SHIFTIN(ET_RXMAC_SEGSZ(256), ET_RXMAC_MC_SEGSZ_MAX) | 1716 ET_RXMAC_MC_SEGSZ_ENABLE; 1717 } else { 1718 val = 0; 1719 } 1720 CSR_WRITE_4(sc, ET_RXMAC_MC_SEGSZ, val); 1721 1722 CSR_WRITE_4(sc, ET_RXMAC_MC_WATERMARK, 0); 1723 1724 /* Initialize RX MAC management register */ 1725 CSR_WRITE_4(sc, ET_RXMAC_MGT, 0); 1726 1727 CSR_WRITE_4(sc, ET_RXMAC_SPACE_AVL, 0); 1728 1729 CSR_WRITE_4(sc, ET_RXMAC_MGT, 1730 ET_RXMAC_MGT_PASS_ECRC | 1731 ET_RXMAC_MGT_PASS_ELEN | 1732 ET_RXMAC_MGT_PASS_ETRUNC | 1733 ET_RXMAC_MGT_CHECK_PKT); 1734 1735 /* 1736 * Configure runt filtering (may not work on certain chip generation) 1737 */ 1738 val = __SHIFTIN(ETHER_MIN_LEN, ET_PKTFILT_MINLEN) | ET_PKTFILT_FRAG; 1739 CSR_WRITE_4(sc, ET_PKTFILT, val); 1740 1741 /* Enable RX MAC but leave WOL disabled */ 1742 CSR_WRITE_4(sc, ET_RXMAC_CTRL, 1743 ET_RXMAC_CTRL_WOL_DISABLE | ET_RXMAC_CTRL_ENABLE); 1744 1745 /* 1746 * Setup multicast hash and allmulti/promisc mode 1747 */ 1748 et_setmulti(sc); 1749 } 1750 1751 static void 1752 et_init_txmac(struct et_softc *sc) 1753 { 1754 /* Disable TX MAC and FC(?) */ 1755 CSR_WRITE_4(sc, ET_TXMAC_CTRL, ET_TXMAC_CTRL_FC_DISABLE); 1756 1757 /* No flow control yet */ 1758 CSR_WRITE_4(sc, ET_TXMAC_FLOWCTRL, 0); 1759 1760 /* Enable TX MAC but leave FC(?) diabled */ 1761 CSR_WRITE_4(sc, ET_TXMAC_CTRL, 1762 ET_TXMAC_CTRL_ENABLE | ET_TXMAC_CTRL_FC_DISABLE); 1763 } 1764 1765 static int 1766 et_start_rxdma(struct et_softc *sc) 1767 { 1768 uint32_t val = 0; 1769 1770 val |= __SHIFTIN(sc->sc_rx_data[0].rbd_bufsize, 1771 ET_RXDMA_CTRL_RING0_SIZE) | 1772 ET_RXDMA_CTRL_RING0_ENABLE; 1773 val |= __SHIFTIN(sc->sc_rx_data[1].rbd_bufsize, 1774 ET_RXDMA_CTRL_RING1_SIZE) | 1775 ET_RXDMA_CTRL_RING1_ENABLE; 1776 1777 CSR_WRITE_4(sc, ET_RXDMA_CTRL, val); 1778 1779 DELAY(5); 1780 1781 if (CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) { 1782 if_printf(&sc->arpcom.ac_if, "can't start RX DMA engine\n"); 1783 return ETIMEDOUT; 1784 } 1785 return 0; 1786 } 1787 1788 static int 1789 et_start_txdma(struct et_softc *sc) 1790 { 1791 CSR_WRITE_4(sc, ET_TXDMA_CTRL, ET_TXDMA_CTRL_SINGLE_EPKT); 1792 return 0; 1793 } 1794 1795 static int 1796 et_enable_txrx(struct et_softc *sc, int media_upd) 1797 { 1798 struct ifnet *ifp = &sc->arpcom.ac_if; 1799 uint32_t val; 1800 int i, error; 1801 1802 val = CSR_READ_4(sc, ET_MAC_CFG1); 1803 val |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN; 1804 val &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW | 1805 ET_MAC_CFG1_LOOPBACK); 1806 CSR_WRITE_4(sc, ET_MAC_CFG1, val); 1807 1808 if (media_upd) 1809 et_ifmedia_upd(ifp); 1810 else 1811 et_setmedia(sc); 1812 1813 #define NRETRY 100 1814 1815 for (i = 0; i < NRETRY; ++i) { 1816 val = CSR_READ_4(sc, ET_MAC_CFG1); 1817 if ((val & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) == 1818 (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) 1819 break; 1820 1821 DELAY(10); 1822 } 1823 if (i == NRETRY) { 1824 if_printf(ifp, "can't enable RX/TX\n"); 1825 return 0; 1826 } 1827 sc->sc_flags |= ET_FLAG_TXRX_ENABLED; 1828 1829 #undef NRETRY 1830 1831 /* 1832 * Start TX/RX DMA engine 1833 */ 1834 error = et_start_rxdma(sc); 1835 if (error) 1836 return error; 1837 1838 error = et_start_txdma(sc); 1839 if (error) 1840 return error; 1841 1842 return 0; 1843 } 1844 1845 static void 1846 et_rxeof(struct et_softc *sc) 1847 { 1848 struct ifnet *ifp = &sc->arpcom.ac_if; 1849 struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 1850 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 1851 uint32_t rxs_stat_ring; 1852 int rxst_wrap, rxst_index; 1853 1854 if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) 1855 return; 1856 1857 rxs_stat_ring = rxsd->rxsd_status->rxs_stat_ring; 1858 rxst_wrap = (rxs_stat_ring & ET_RXS_STATRING_WRAP) ? 1 : 0; 1859 rxst_index = __SHIFTOUT(rxs_stat_ring, ET_RXS_STATRING_INDEX); 1860 1861 while (rxst_index != rxst_ring->rsr_index || 1862 rxst_wrap != rxst_ring->rsr_wrap) { 1863 struct et_rxbuf_data *rbd; 1864 struct et_rxdesc_ring *rx_ring; 1865 struct et_rxstat *st; 1866 struct mbuf *m; 1867 int buflen, buf_idx, ring_idx; 1868 uint32_t rxstat_pos, rxring_pos; 1869 1870 KKASSERT(rxst_ring->rsr_index < ET_RX_NSTAT); 1871 st = &rxst_ring->rsr_stat[rxst_ring->rsr_index]; 1872 1873 buflen = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_LEN); 1874 buf_idx = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_BUFIDX); 1875 ring_idx = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_RINGIDX); 1876 1877 if (++rxst_ring->rsr_index == ET_RX_NSTAT) { 1878 rxst_ring->rsr_index = 0; 1879 rxst_ring->rsr_wrap ^= 1; 1880 } 1881 rxstat_pos = __SHIFTIN(rxst_ring->rsr_index, 1882 ET_RXSTAT_POS_INDEX); 1883 if (rxst_ring->rsr_wrap) 1884 rxstat_pos |= ET_RXSTAT_POS_WRAP; 1885 CSR_WRITE_4(sc, ET_RXSTAT_POS, rxstat_pos); 1886 1887 if (ring_idx >= ET_RX_NRING) { 1888 IFNET_STAT_INC(ifp, ierrors, 1); 1889 if_printf(ifp, "invalid ring index %d\n", ring_idx); 1890 continue; 1891 } 1892 if (buf_idx >= ET_RX_NDESC) { 1893 IFNET_STAT_INC(ifp, ierrors, 1); 1894 if_printf(ifp, "invalid buf index %d\n", buf_idx); 1895 continue; 1896 } 1897 1898 rbd = &sc->sc_rx_data[ring_idx]; 1899 m = rbd->rbd_buf[buf_idx].rb_mbuf; 1900 1901 if (rbd->rbd_newbuf(rbd, buf_idx, 0) == 0) { 1902 if (buflen < ETHER_CRC_LEN) { 1903 m_freem(m); 1904 IFNET_STAT_INC(ifp, ierrors, 1); 1905 } else { 1906 m->m_pkthdr.len = m->m_len = buflen; 1907 m->m_pkthdr.rcvif = ifp; 1908 1909 m_adj(m, -ETHER_CRC_LEN); 1910 1911 IFNET_STAT_INC(ifp, ipackets, 1); 1912 ifp->if_input(ifp, m); 1913 } 1914 } else { 1915 IFNET_STAT_INC(ifp, ierrors, 1); 1916 } 1917 m = NULL; /* Catch invalid reference */ 1918 1919 rx_ring = &sc->sc_rx_ring[ring_idx]; 1920 1921 if (buf_idx != rx_ring->rr_index) { 1922 if_printf(ifp, "WARNING!! ring %d, " 1923 "buf_idx %d, rr_idx %d\n", 1924 ring_idx, buf_idx, rx_ring->rr_index); 1925 } 1926 1927 KKASSERT(rx_ring->rr_index < ET_RX_NDESC); 1928 if (++rx_ring->rr_index == ET_RX_NDESC) { 1929 rx_ring->rr_index = 0; 1930 rx_ring->rr_wrap ^= 1; 1931 } 1932 rxring_pos = __SHIFTIN(rx_ring->rr_index, ET_RX_RING_POS_INDEX); 1933 if (rx_ring->rr_wrap) 1934 rxring_pos |= ET_RX_RING_POS_WRAP; 1935 CSR_WRITE_4(sc, rx_ring->rr_posreg, rxring_pos); 1936 } 1937 } 1938 1939 static int 1940 et_encap(struct et_softc *sc, struct mbuf **m0) 1941 { 1942 bus_dma_segment_t segs[ET_NSEG_MAX]; 1943 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 1944 struct et_txbuf_data *tbd = &sc->sc_tx_data; 1945 struct et_txdesc *td; 1946 bus_dmamap_t map; 1947 int error, maxsegs, nsegs, first_idx, last_idx, i; 1948 uint32_t tx_ready_pos, last_td_ctrl2; 1949 1950 maxsegs = ET_TX_NDESC - tbd->tbd_used; 1951 if (maxsegs > ET_NSEG_MAX) 1952 maxsegs = ET_NSEG_MAX; 1953 KASSERT(maxsegs >= ET_NSEG_SPARE, 1954 ("not enough spare TX desc (%d)", maxsegs)); 1955 1956 KKASSERT(tx_ring->tr_ready_index < ET_TX_NDESC); 1957 first_idx = tx_ring->tr_ready_index; 1958 map = tbd->tbd_buf[first_idx].tb_dmap; 1959 1960 error = bus_dmamap_load_mbuf_defrag(sc->sc_txbuf_dtag, map, m0, 1961 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 1962 if (error) 1963 goto back; 1964 bus_dmamap_sync(sc->sc_txbuf_dtag, map, BUS_DMASYNC_PREWRITE); 1965 1966 last_td_ctrl2 = ET_TDCTRL2_LAST_FRAG; 1967 sc->sc_tx += nsegs; 1968 if (sc->sc_tx / sc->sc_tx_intr_nsegs != sc->sc_tx_intr) { 1969 sc->sc_tx_intr = sc->sc_tx / sc->sc_tx_intr_nsegs; 1970 last_td_ctrl2 |= ET_TDCTRL2_INTR; 1971 } 1972 1973 last_idx = -1; 1974 for (i = 0; i < nsegs; ++i) { 1975 int idx; 1976 1977 idx = (first_idx + i) % ET_TX_NDESC; 1978 td = &tx_ring->tr_desc[idx]; 1979 td->td_addr_hi = ET_ADDR_HI(segs[i].ds_addr); 1980 td->td_addr_lo = ET_ADDR_LO(segs[i].ds_addr); 1981 td->td_ctrl1 = __SHIFTIN(segs[i].ds_len, ET_TDCTRL1_LEN); 1982 1983 if (i == nsegs - 1) { /* Last frag */ 1984 td->td_ctrl2 = last_td_ctrl2; 1985 last_idx = idx; 1986 } 1987 1988 KKASSERT(tx_ring->tr_ready_index < ET_TX_NDESC); 1989 if (++tx_ring->tr_ready_index == ET_TX_NDESC) { 1990 tx_ring->tr_ready_index = 0; 1991 tx_ring->tr_ready_wrap ^= 1; 1992 } 1993 } 1994 td = &tx_ring->tr_desc[first_idx]; 1995 td->td_ctrl2 |= ET_TDCTRL2_FIRST_FRAG; /* First frag */ 1996 1997 KKASSERT(last_idx >= 0); 1998 tbd->tbd_buf[first_idx].tb_dmap = tbd->tbd_buf[last_idx].tb_dmap; 1999 tbd->tbd_buf[last_idx].tb_dmap = map; 2000 tbd->tbd_buf[last_idx].tb_mbuf = *m0; 2001 2002 tbd->tbd_used += nsegs; 2003 KKASSERT(tbd->tbd_used <= ET_TX_NDESC); 2004 2005 tx_ready_pos = __SHIFTIN(tx_ring->tr_ready_index, 2006 ET_TX_READY_POS_INDEX); 2007 if (tx_ring->tr_ready_wrap) 2008 tx_ready_pos |= ET_TX_READY_POS_WRAP; 2009 CSR_WRITE_4(sc, ET_TX_READY_POS, tx_ready_pos); 2010 2011 error = 0; 2012 back: 2013 if (error) { 2014 m_freem(*m0); 2015 *m0 = NULL; 2016 } 2017 return error; 2018 } 2019 2020 static void 2021 et_txeof(struct et_softc *sc, int start) 2022 { 2023 struct ifnet *ifp = &sc->arpcom.ac_if; 2024 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 2025 struct et_txbuf_data *tbd = &sc->sc_tx_data; 2026 uint32_t tx_done; 2027 int end, wrap; 2028 2029 if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) 2030 return; 2031 2032 if (tbd->tbd_used == 0) 2033 return; 2034 2035 tx_done = CSR_READ_4(sc, ET_TX_DONE_POS); 2036 end = __SHIFTOUT(tx_done, ET_TX_DONE_POS_INDEX); 2037 wrap = (tx_done & ET_TX_DONE_POS_WRAP) ? 1 : 0; 2038 2039 while (tbd->tbd_start_index != end || tbd->tbd_start_wrap != wrap) { 2040 struct et_txbuf *tb; 2041 2042 KKASSERT(tbd->tbd_start_index < ET_TX_NDESC); 2043 tb = &tbd->tbd_buf[tbd->tbd_start_index]; 2044 2045 bzero(&tx_ring->tr_desc[tbd->tbd_start_index], 2046 sizeof(struct et_txdesc)); 2047 2048 if (tb->tb_mbuf != NULL) { 2049 bus_dmamap_unload(sc->sc_txbuf_dtag, tb->tb_dmap); 2050 m_freem(tb->tb_mbuf); 2051 tb->tb_mbuf = NULL; 2052 IFNET_STAT_INC(ifp, opackets, 1); 2053 } 2054 2055 if (++tbd->tbd_start_index == ET_TX_NDESC) { 2056 tbd->tbd_start_index = 0; 2057 tbd->tbd_start_wrap ^= 1; 2058 } 2059 2060 KKASSERT(tbd->tbd_used > 0); 2061 tbd->tbd_used--; 2062 } 2063 2064 if (tbd->tbd_used == 0) 2065 ifp->if_timer = 0; 2066 if (tbd->tbd_used + ET_NSEG_SPARE <= ET_TX_NDESC) 2067 ifq_clr_oactive(&ifp->if_snd); 2068 2069 if (start) 2070 if_devstart(ifp); 2071 } 2072 2073 static void 2074 et_tick(void *xsc) 2075 { 2076 struct et_softc *sc = xsc; 2077 struct ifnet *ifp = &sc->arpcom.ac_if; 2078 struct mii_data *mii = device_get_softc(sc->sc_miibus); 2079 2080 lwkt_serialize_enter(ifp->if_serializer); 2081 2082 mii_tick(mii); 2083 if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0 && 2084 (mii->mii_media_status & IFM_ACTIVE) && 2085 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2086 if_printf(ifp, "Link up, enable TX/RX\n"); 2087 if (et_enable_txrx(sc, 0) == 0) 2088 if_devstart(ifp); 2089 } 2090 callout_reset(&sc->sc_tick, hz, et_tick, sc); 2091 2092 lwkt_serialize_exit(ifp->if_serializer); 2093 } 2094 2095 static int 2096 et_newbuf_cluster(struct et_rxbuf_data *rbd, int buf_idx, int init) 2097 { 2098 return et_newbuf(rbd, buf_idx, init, MCLBYTES); 2099 } 2100 2101 static int 2102 et_newbuf_hdr(struct et_rxbuf_data *rbd, int buf_idx, int init) 2103 { 2104 return et_newbuf(rbd, buf_idx, init, MHLEN); 2105 } 2106 2107 static int 2108 et_newbuf(struct et_rxbuf_data *rbd, int buf_idx, int init, int len0) 2109 { 2110 struct et_softc *sc = rbd->rbd_softc; 2111 struct et_rxbuf *rb; 2112 struct mbuf *m; 2113 bus_dma_segment_t seg; 2114 bus_dmamap_t dmap; 2115 int error, len, nseg; 2116 2117 KASSERT(!rbd->rbd_jumbo, ("calling %s with jumbo ring", __func__)); 2118 2119 KKASSERT(buf_idx < ET_RX_NDESC); 2120 rb = &rbd->rbd_buf[buf_idx]; 2121 2122 m = m_getl(len0, init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR, &len); 2123 if (m == NULL) { 2124 error = ENOBUFS; 2125 2126 if (init) { 2127 if_printf(&sc->arpcom.ac_if, 2128 "m_getl failed, size %d\n", len0); 2129 return error; 2130 } else { 2131 goto back; 2132 } 2133 } 2134 m->m_len = m->m_pkthdr.len = len; 2135 2136 /* 2137 * Try load RX mbuf into temporary DMA tag 2138 */ 2139 error = bus_dmamap_load_mbuf_segment(sc->sc_rxbuf_dtag, 2140 sc->sc_rxbuf_tmp_dmap, m, &seg, 1, &nseg, 2141 BUS_DMA_NOWAIT); 2142 if (error) { 2143 m_freem(m); 2144 if (init) { 2145 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n"); 2146 return error; 2147 } else { 2148 goto back; 2149 } 2150 } 2151 2152 if (!init) { 2153 bus_dmamap_sync(sc->sc_rxbuf_dtag, rb->rb_dmap, 2154 BUS_DMASYNC_POSTREAD); 2155 bus_dmamap_unload(sc->sc_rxbuf_dtag, rb->rb_dmap); 2156 } 2157 rb->rb_mbuf = m; 2158 rb->rb_paddr = seg.ds_addr; 2159 2160 /* 2161 * Swap RX buf's DMA map with the loaded temporary one 2162 */ 2163 dmap = rb->rb_dmap; 2164 rb->rb_dmap = sc->sc_rxbuf_tmp_dmap; 2165 sc->sc_rxbuf_tmp_dmap = dmap; 2166 2167 error = 0; 2168 back: 2169 et_setup_rxdesc(rbd, buf_idx, rb->rb_paddr); 2170 return error; 2171 } 2172 2173 static int 2174 et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS) 2175 { 2176 struct et_softc *sc = arg1; 2177 struct ifnet *ifp = &sc->arpcom.ac_if; 2178 int error = 0, v; 2179 2180 lwkt_serialize_enter(ifp->if_serializer); 2181 2182 v = sc->sc_rx_intr_npkts; 2183 error = sysctl_handle_int(oidp, &v, 0, req); 2184 if (error || req->newptr == NULL) 2185 goto back; 2186 if (v <= 0) { 2187 error = EINVAL; 2188 goto back; 2189 } 2190 2191 if (sc->sc_rx_intr_npkts != v) { 2192 if (ifp->if_flags & IFF_RUNNING) 2193 CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, v); 2194 sc->sc_rx_intr_npkts = v; 2195 } 2196 back: 2197 lwkt_serialize_exit(ifp->if_serializer); 2198 return error; 2199 } 2200 2201 static int 2202 et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS) 2203 { 2204 struct et_softc *sc = arg1; 2205 struct ifnet *ifp = &sc->arpcom.ac_if; 2206 int error = 0, v; 2207 2208 lwkt_serialize_enter(ifp->if_serializer); 2209 2210 v = sc->sc_rx_intr_delay; 2211 error = sysctl_handle_int(oidp, &v, 0, req); 2212 if (error || req->newptr == NULL) 2213 goto back; 2214 if (v <= 0) { 2215 error = EINVAL; 2216 goto back; 2217 } 2218 2219 if (sc->sc_rx_intr_delay != v) { 2220 if (ifp->if_flags & IFF_RUNNING) 2221 CSR_WRITE_4(sc, ET_RX_INTR_DELAY, v); 2222 sc->sc_rx_intr_delay = v; 2223 } 2224 back: 2225 lwkt_serialize_exit(ifp->if_serializer); 2226 return error; 2227 } 2228 2229 static void 2230 et_setmedia(struct et_softc *sc) 2231 { 2232 struct mii_data *mii = device_get_softc(sc->sc_miibus); 2233 uint32_t cfg2, ctrl; 2234 2235 cfg2 = CSR_READ_4(sc, ET_MAC_CFG2); 2236 cfg2 &= ~(ET_MAC_CFG2_MODE_MII | ET_MAC_CFG2_MODE_GMII | 2237 ET_MAC_CFG2_FDX | ET_MAC_CFG2_BIGFRM); 2238 cfg2 |= ET_MAC_CFG2_LENCHK | ET_MAC_CFG2_CRC | ET_MAC_CFG2_PADCRC | 2239 __SHIFTIN(7, ET_MAC_CFG2_PREAMBLE_LEN); 2240 2241 ctrl = CSR_READ_4(sc, ET_MAC_CTRL); 2242 ctrl &= ~(ET_MAC_CTRL_GHDX | ET_MAC_CTRL_MODE_MII); 2243 2244 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 2245 cfg2 |= ET_MAC_CFG2_MODE_GMII; 2246 } else { 2247 cfg2 |= ET_MAC_CFG2_MODE_MII; 2248 ctrl |= ET_MAC_CTRL_MODE_MII; 2249 } 2250 2251 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 2252 cfg2 |= ET_MAC_CFG2_FDX; 2253 else 2254 ctrl |= ET_MAC_CTRL_GHDX; 2255 2256 CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl); 2257 CSR_WRITE_4(sc, ET_MAC_CFG2, cfg2); 2258 } 2259 2260 static int 2261 et_jumbo_mem_alloc(device_t dev) 2262 { 2263 struct et_softc *sc = device_get_softc(dev); 2264 struct et_jumbo_data *jd = &sc->sc_jumbo_data; 2265 bus_addr_t paddr; 2266 uint8_t *buf; 2267 int i; 2268 2269 jd->jd_buf = bus_dmamem_coherent_any(sc->sc_dtag, 2270 ET_JUMBO_ALIGN, ET_JUMBO_MEM_SIZE, BUS_DMA_WAITOK, 2271 &jd->jd_dtag, &jd->jd_dmap, &paddr); 2272 if (jd->jd_buf == NULL) { 2273 device_printf(dev, "can't create jumbo DMA stuffs\n"); 2274 return ENOMEM; 2275 } 2276 2277 jd->jd_slots = kmalloc(sizeof(*jd->jd_slots) * ET_JSLOTS, M_DEVBUF, 2278 M_WAITOK | M_ZERO); 2279 lwkt_serialize_init(&jd->jd_serializer); 2280 SLIST_INIT(&jd->jd_free_slots); 2281 2282 buf = jd->jd_buf; 2283 for (i = 0; i < ET_JSLOTS; ++i) { 2284 struct et_jslot *jslot = &jd->jd_slots[i]; 2285 2286 jslot->jslot_data = jd; 2287 jslot->jslot_buf = buf; 2288 jslot->jslot_paddr = paddr; 2289 jslot->jslot_inuse = 0; 2290 jslot->jslot_index = i; 2291 SLIST_INSERT_HEAD(&jd->jd_free_slots, jslot, jslot_link); 2292 2293 buf += ET_JLEN; 2294 paddr += ET_JLEN; 2295 } 2296 return 0; 2297 } 2298 2299 static void 2300 et_jumbo_mem_free(device_t dev) 2301 { 2302 struct et_softc *sc = device_get_softc(dev); 2303 struct et_jumbo_data *jd = &sc->sc_jumbo_data; 2304 2305 KKASSERT(sc->sc_flags & ET_FLAG_JUMBO); 2306 2307 kfree(jd->jd_slots, M_DEVBUF); 2308 et_dma_mem_destroy(jd->jd_dtag, jd->jd_buf, jd->jd_dmap); 2309 } 2310 2311 static struct et_jslot * 2312 et_jalloc(struct et_jumbo_data *jd) 2313 { 2314 struct et_jslot *jslot; 2315 2316 lwkt_serialize_enter(&jd->jd_serializer); 2317 2318 jslot = SLIST_FIRST(&jd->jd_free_slots); 2319 if (jslot) { 2320 SLIST_REMOVE_HEAD(&jd->jd_free_slots, jslot_link); 2321 jslot->jslot_inuse = 1; 2322 } 2323 2324 lwkt_serialize_exit(&jd->jd_serializer); 2325 return jslot; 2326 } 2327 2328 static void 2329 et_jfree(void *xjslot) 2330 { 2331 struct et_jslot *jslot = xjslot; 2332 struct et_jumbo_data *jd = jslot->jslot_data; 2333 2334 if (&jd->jd_slots[jslot->jslot_index] != jslot) { 2335 panic("%s wrong jslot!?", __func__); 2336 } else if (jslot->jslot_inuse == 0) { 2337 panic("%s jslot already freed", __func__); 2338 } else { 2339 lwkt_serialize_enter(&jd->jd_serializer); 2340 2341 atomic_subtract_int(&jslot->jslot_inuse, 1); 2342 if (jslot->jslot_inuse == 0) { 2343 SLIST_INSERT_HEAD(&jd->jd_free_slots, jslot, 2344 jslot_link); 2345 } 2346 2347 lwkt_serialize_exit(&jd->jd_serializer); 2348 } 2349 } 2350 2351 static void 2352 et_jref(void *xjslot) 2353 { 2354 struct et_jslot *jslot = xjslot; 2355 struct et_jumbo_data *jd = jslot->jslot_data; 2356 2357 if (&jd->jd_slots[jslot->jslot_index] != jslot) 2358 panic("%s wrong jslot!?", __func__); 2359 else if (jslot->jslot_inuse == 0) 2360 panic("%s jslot already freed", __func__); 2361 else 2362 atomic_add_int(&jslot->jslot_inuse, 1); 2363 } 2364 2365 static int 2366 et_newbuf_jumbo(struct et_rxbuf_data *rbd, int buf_idx, int init) 2367 { 2368 struct et_softc *sc = rbd->rbd_softc; 2369 struct et_rxbuf *rb; 2370 struct mbuf *m; 2371 struct et_jslot *jslot; 2372 int error; 2373 2374 KASSERT(rbd->rbd_jumbo, ("calling %s with non-jumbo ring", __func__)); 2375 2376 KKASSERT(buf_idx < ET_RX_NDESC); 2377 rb = &rbd->rbd_buf[buf_idx]; 2378 2379 error = ENOBUFS; 2380 2381 MGETHDR(m, init ? MB_WAIT : MB_DONTWAIT, MT_DATA); 2382 if (m == NULL) { 2383 if (init) { 2384 if_printf(&sc->arpcom.ac_if, "MGETHDR failed\n"); 2385 return error; 2386 } else { 2387 goto back; 2388 } 2389 } 2390 2391 jslot = et_jalloc(&sc->sc_jumbo_data); 2392 if (jslot == NULL) { 2393 m_freem(m); 2394 2395 if (init) { 2396 if_printf(&sc->arpcom.ac_if, 2397 "jslot allocation failed\n"); 2398 return error; 2399 } else { 2400 goto back; 2401 } 2402 } 2403 2404 m->m_ext.ext_arg = jslot; 2405 m->m_ext.ext_buf = jslot->jslot_buf; 2406 m->m_ext.ext_free = et_jfree; 2407 m->m_ext.ext_ref = et_jref; 2408 m->m_ext.ext_size = ET_JUMBO_FRAMELEN; 2409 m->m_flags |= M_EXT; 2410 m->m_data = m->m_ext.ext_buf; 2411 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2412 2413 rb->rb_mbuf = m; 2414 rb->rb_paddr = jslot->jslot_paddr; 2415 2416 error = 0; 2417 back: 2418 et_setup_rxdesc(rbd, buf_idx, rb->rb_paddr); 2419 return error; 2420 } 2421 2422 static void 2423 et_setup_rxdesc(struct et_rxbuf_data *rbd, int buf_idx, bus_addr_t paddr) 2424 { 2425 struct et_rxdesc_ring *rx_ring = rbd->rbd_ring; 2426 struct et_rxdesc *desc; 2427 2428 KKASSERT(buf_idx < ET_RX_NDESC); 2429 desc = &rx_ring->rr_desc[buf_idx]; 2430 2431 desc->rd_addr_hi = ET_ADDR_HI(paddr); 2432 desc->rd_addr_lo = ET_ADDR_LO(paddr); 2433 desc->rd_ctrl = __SHIFTIN(buf_idx, ET_RDCTRL_BUFIDX); 2434 } 2435