1 /* 2 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Sepherosa Ziehau <sepherosa@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of The DragonFly Project nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific, prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * $DragonFly: src/sys/dev/netif/et/if_etreg.h,v 1.4 2008/10/18 11:36:37 sephe Exp $ 35 */ 36 37 #ifndef _IF_ETREG_H 38 #define _IF_ETREG_H 39 40 #define ET_MEM_TXSIZE_EX 182 41 #define ET_MEM_RXSIZE_MIN 608 42 #define ET_MEM_RXSIZE_DEFAULT 11216 43 #define ET_MEM_SIZE 16384 44 #define ET_MEM_UNIT 16 45 46 /* 47 * PCI registers 48 * 49 * ET_PCIV_ACK_LATENCY_{128,256} are from 50 * PCI EXPRESS BASE SPECIFICATION, REV. 1.0a, Table 3-5 51 * 52 * ET_PCIV_REPLAY_TIMER_{128,256} are from 53 * PCI EXPRESS BASE SPECIFICATION, REV. 1.0a, Table 3-4 54 */ 55 #define ET_PCIR_BAR PCIR_BAR(0) 56 57 #define ET_PCIR_DEVICE_CAPS 0x4c 58 #define ET_PCIM_DEVICE_CAPS_MAX_PLSZ 0x7 /* Max playload size */ 59 #define ET_PCIV_DEVICE_CAPS_PLSZ_128 0x0 60 #define ET_PCIV_DEVICE_CAPS_PLSZ_256 0x1 61 62 #define ET_PCIR_DEVICE_CTRL 0x50 63 #define ET_PCIM_DEVICE_CTRL_MAX_RRSZ 0x7000 /* Max read request size */ 64 #define ET_PCIV_DEVICE_CTRL_RRSZ_2K 0x4000 65 66 #define ET_PCIR_MAC_ADDR0 0xa4 67 #define ET_PCIR_MAC_ADDR1 0xa8 68 69 #define ET_PCIR_EEPROM_STATUS 0xb2 /* XXX undocumented */ 70 #define ET_PCIM_EEPROM_STATUS_ERROR 0x4c 71 72 #define ET_PCIR_ACK_LATENCY 0xc0 73 #define ET_PCIV_ACK_LATENCY_128 237 74 #define ET_PCIV_ACK_LATENCY_256 416 75 76 #define ET_PCIR_REPLAY_TIMER 0xc2 77 #define ET_REPLAY_TIMER_RX_L0S_ADJ 250 /* XXX infered from default */ 78 #define ET_PCIV_REPLAY_TIMER_128 (711 + ET_REPLAY_TIMER_RX_L0S_ADJ) 79 #define ET_PCIV_REPLAY_TIMER_256 (1248 + ET_REPLAY_TIMER_RX_L0S_ADJ) 80 81 #define ET_PCIR_L0S_L1_LATENCY 0xcf 82 #define ET_PCIM_L0S_LATENCY __BITS(2, 0) 83 #define ET_PCIM_L1_LATENCY __BITS(5, 3) 84 #define ET_PCIV_L0S_LATENCY(l) __SHIFTIN((l) - 1, ET_PCIM_L0S_LATENCY) 85 #define ET_PCIV_L1_LATENCY(l) __SHIFTIN((l) - 1, ET_PCIM_L1_LATENCY) 86 87 /* 88 * CSR 89 */ 90 #define ET_TXQUEUE_START 0x0000 91 #define ET_TXQUEUE_END 0x0004 92 #define ET_RXQUEUE_START 0x0008 93 #define ET_RXQUEUE_END 0x000c 94 #define ET_QUEUE_ADDR(addr) (((addr) / ET_MEM_UNIT) - 1) 95 #define ET_QUEUE_ADDR_START 0 96 #define ET_QUEUE_ADDR_END ET_QUEUE_ADDR(ET_MEM_SIZE) 97 98 #define ET_PM 0x0010 99 #define ET_PM_SYSCLK_GATE __BIT(3) 100 #define ET_PM_TXCLK_GATE __BIT(4) 101 #define ET_PM_RXCLK_GATE __BIT(5) 102 103 #define ET_INTR_STATUS 0x0018 104 #define ET_INTR_MASK 0x001c 105 106 #define ET_SWRST 0x0028 107 #define ET_SWRST_TXDMA __BIT(0) 108 #define ET_SWRST_RXDMA __BIT(1) 109 #define ET_SWRST_TXMAC __BIT(2) 110 #define ET_SWRST_RXMAC __BIT(3) 111 #define ET_SWRST_MAC __BIT(4) 112 #define ET_SWRST_MAC_STAT __BIT(5) 113 #define ET_SWRST_MMC __BIT(6) 114 #define ET_SWRST_SELFCLR_DISABLE __BIT(31) 115 116 #define ET_MSI_CFG 0x0030 117 118 #define ET_LOOPBACK 0x0034 119 120 #define ET_TIMER 0x0038 121 122 #define ET_TXDMA_CTRL 0x1000 123 #define ET_TXDMA_CTRL_HALT __BIT(0) 124 #define ET_TXDMA_CTRL_CACHE_THR __BITS(7, 4) 125 #define ET_TXDMA_CTRL_SINGLE_EPKT __BIT(8) /* ??? */ 126 127 #define ET_TX_RING_HI 0x1004 128 #define ET_TX_RING_LO 0x1008 129 #define ET_TX_RING_CNT 0x100c 130 131 #define ET_TX_STATUS_HI 0x101c 132 #define ET_TX_STATUS_LO 0x1020 133 134 #define ET_TX_READY_POS 0x1024 135 #define ET_TX_READY_POS_INDEX __BITS(9, 0) 136 #define ET_TX_READY_POS_WRAP __BIT(10) 137 138 #define ET_TX_DONE_POS 0x1060 139 #define ET_TX_DONE_POS_INDEX __BITS(9, 0) 140 #define ET_TX_DONE_POS_WRAP __BIT(10) 141 142 #define ET_RXDMA_CTRL 0x2000 143 #define ET_RXDMA_CTRL_HALT __BIT(0) 144 #define ET_RXDMA_CTRL_RING0_SIZE __BITS(9, 8) 145 #define ET_RXDMA_CTRL_RING0_128 0 /* 127 */ 146 #define ET_RXDMA_CTRL_RING0_256 1 /* 255 */ 147 #define ET_RXDMA_CTRL_RING0_512 2 /* 511 */ 148 #define ET_RXDMA_CTRL_RING0_1024 3 /* 1023 */ 149 #define ET_RXDMA_CTRL_RING0_ENABLE __BIT(10) 150 #define ET_RXDMA_CTRL_RING1_SIZE __BITS(12, 11) 151 #define ET_RXDMA_CTRL_RING1_2048 0 /* 2047 */ 152 #define ET_RXDMA_CTRL_RING1_4096 1 /* 4095 */ 153 #define ET_RXDMA_CTRL_RING1_8192 2 /* 8191 */ 154 #define ET_RXDMA_CTRL_RING1_16384 3 /* 16383 (9022?) */ 155 #define ET_RXDMA_CTRL_RING1_ENABLE __BIT(13) 156 #define ET_RXDMA_CTRL_HALTED __BIT(17) 157 158 #define ET_RX_STATUS_LO 0x2004 159 #define ET_RX_STATUS_HI 0x2008 160 161 #define ET_RX_INTR_NPKTS 0x200c 162 #define ET_RX_INTR_DELAY 0x2010 163 164 #define ET_RXSTAT_LO 0x2020 165 #define ET_RXSTAT_HI 0x2024 166 #define ET_RXSTAT_CNT 0x2028 167 168 #define ET_RXSTAT_POS 0x2030 169 #define ET_RXSTAT_POS_INDEX __BITS(11, 0) 170 #define ET_RXSTAT_POS_WRAP __BIT(12) 171 172 #define ET_RXSTAT_MINCNT 0x2038 173 174 #define ET_RX_RING0_LO 0x203c 175 #define ET_RX_RING0_HI 0x2040 176 #define ET_RX_RING0_CNT 0x2044 177 178 #define ET_RX_RING0_POS 0x204c 179 #define ET_RX_RING0_POS_INDEX __BITS(9, 0) 180 #define ET_RX_RING0_POS_WRAP __BIT(10) 181 182 #define ET_RX_RING0_MINCNT 0x2054 183 184 #define ET_RX_RING1_LO 0x2058 185 #define ET_RX_RING1_HI 0x205c 186 #define ET_RX_RING1_CNT 0x2060 187 188 #define ET_RX_RING1_POS 0x2068 189 #define ET_RX_RING1_POS_INDEX __BITS(9, 0) 190 #define ET_RX_RING1_POS_WRAP __BIT(10) 191 192 #define ET_RX_RING1_MINCNT 0x2070 193 194 #define ET_TXMAC_CTRL 0x3000 195 #define ET_TXMAC_CTRL_ENABLE __BIT(0) 196 #define ET_TXMAC_CTRL_FC_DISABLE __BIT(3) 197 198 #define ET_TXMAC_FLOWCTRL 0x3010 199 200 #define ET_RXMAC_CTRL 0x4000 201 #define ET_RXMAC_CTRL_ENABLE __BIT(0) 202 #define ET_RXMAC_CTRL_NO_PKTFILT __BIT(2) 203 #define ET_RXMAC_CTRL_WOL_DISABLE __BIT(3) 204 205 #define ET_WOL_CRC 0x4004 206 #define ET_WOL_SA_LO 0x4010 207 #define ET_WOL_SA_HI 0x4014 208 #define ET_WOL_MASK 0x4018 209 210 #define ET_UCAST_FILTADDR1 0x4068 211 #define ET_UCAST_FILTADDR2 0x406c 212 #define ET_UCAST_FILTADDR3 0x4070 213 214 #define ET_MULTI_HASH 0x4074 215 216 #define ET_PKTFILT 0x4084 217 #define ET_PKTFILT_BCAST __BIT(0) 218 #define ET_PKTFILT_MCAST __BIT(1) 219 #define ET_PKTFILT_UCAST __BIT(2) 220 #define ET_PKTFILT_FRAG __BIT(3) 221 #define ET_PKTFILT_MINLEN __BITS(22, 16) 222 223 #define ET_RXMAC_MC_SEGSZ 0x4088 224 #define ET_RXMAC_MC_SEGSZ_ENABLE __BIT(0) 225 #define ET_RXMAC_MC_SEGSZ_FC __BIT(1) 226 #define ET_RXMAC_MC_SEGSZ_MAX __BITS(9, 2) 227 #define ET_RXMAC_SEGSZ(segsz) ((segsz) / ET_MEM_UNIT) 228 #define ET_RXMAC_CUT_THRU_FRMLEN 6122 229 230 #define ET_RXMAC_MC_WATERMARK 0x408c 231 #define ET_RXMAC_SPACE_AVL 0x4094 232 233 #define ET_RXMAC_MGT 0x4098 234 #define ET_RXMAC_MGT_PASS_ECRC __BIT(4) 235 #define ET_RXMAC_MGT_PASS_ELEN __BIT(5) 236 #define ET_RXMAC_MGT_PASS_ETRUNC __BIT(16) 237 #define ET_RXMAC_MGT_CHECK_PKT __BIT(17) 238 239 #define ET_MAC_CFG1 0x5000 240 #define ET_MAC_CFG1_TXEN __BIT(0) 241 #define ET_MAC_CFG1_SYNC_TXEN __BIT(1) 242 #define ET_MAC_CFG1_RXEN __BIT(2) 243 #define ET_MAC_CFG1_SYNC_RXEN __BIT(3) 244 #define ET_MAC_CFG1_TXFLOW __BIT(4) 245 #define ET_MAC_CFG1_RXFLOW __BIT(5) 246 #define ET_MAC_CFG1_LOOPBACK __BIT(8) 247 #define ET_MAC_CFG1_RST_TXFUNC __BIT(16) 248 #define ET_MAC_CFG1_RST_RXFUNC __BIT(17) 249 #define ET_MAC_CFG1_RST_TXMC __BIT(18) 250 #define ET_MAC_CFG1_RST_RXMC __BIT(19) 251 #define ET_MAC_CFG1_SIM_RST __BIT(30) 252 #define ET_MAC_CFG1_SOFT_RST __BIT(31) 253 254 #define ET_MAC_CFG2 0x5004 255 #define ET_MAC_CFG2_FDX __BIT(0) 256 #define ET_MAC_CFG2_CRC __BIT(1) 257 #define ET_MAC_CFG2_PADCRC __BIT(2) 258 #define ET_MAC_CFG2_LENCHK __BIT(4) 259 #define ET_MAC_CFG2_BIGFRM __BIT(5) 260 #define ET_MAC_CFG2_MODE_MII __BIT(8) 261 #define ET_MAC_CFG2_MODE_GMII __BIT(9) 262 #define ET_MAC_CFG2_PREAMBLE_LEN __BITS(15, 12) 263 264 #define ET_IPG 0x5008 265 #define ET_IPG_B2B __BITS(6, 0) 266 #define ET_IPG_MINIFG __BITS(15, 8) 267 #define ET_IPG_NONB2B_2 __BITS(22, 16) 268 #define ET_IPG_NONB2B_1 __BITS(30, 24) 269 270 #define ET_MAC_HDX 0x500c 271 #define ET_MAC_HDX_COLLWIN __BITS(9, 0) 272 #define ET_MAC_HDX_REXMIT_MAX __BITS(15, 12) 273 #define ET_MAC_HDX_EXC_DEFER __BIT(16) 274 #define ET_MAC_HDX_NOBACKOFF __BIT(17) 275 #define ET_MAC_HDX_BP_NOBACKOFF __BIT(18) 276 #define ET_MAC_HDX_ALT_BEB __BIT(19) 277 #define ET_MAC_HDX_ALT_BEB_TRUNC __BITS(23, 20) 278 279 #define ET_MAX_FRMLEN 0x5010 280 281 #define ET_MII_CFG 0x5020 282 #define ET_MII_CFG_CLKRST __BITS(2, 0) 283 #define ET_MII_CFG_PREAMBLE_SUP __BIT(4) 284 #define ET_MII_CFG_SCAN_AUTOINC __BIT(5) 285 #define ET_MII_CFG_RST __BIT(31) 286 287 #define ET_MII_CMD 0x5024 288 #define ET_MII_CMD_READ __BIT(0) 289 290 #define ET_MII_ADDR 0x5028 291 #define ET_MII_ADDR_REG __BITS(4, 0) 292 #define ET_MII_ADDR_PHY __BITS(12, 8) 293 294 #define ET_MII_CTRL 0x502c 295 #define ET_MII_CTRL_VALUE __BITS(15, 0) 296 297 #define ET_MII_STAT 0x5030 298 #define ET_MII_STAT_VALUE __BITS(15, 0) 299 300 #define ET_MII_IND 0x5034 301 #define ET_MII_IND_BUSY __BIT(0) 302 #define ET_MII_IND_INVALID __BIT(2) 303 304 #define ET_MAC_CTRL 0x5038 305 #define ET_MAC_CTRL_MODE_MII __BIT(24) 306 #define ET_MAC_CTRL_LHDX __BIT(25) 307 #define ET_MAC_CTRL_GHDX __BIT(26) 308 309 #define ET_MAC_ADDR1 0x5040 310 #define ET_MAC_ADDR2 0x5044 311 312 #define ET_MMC_CTRL 0x7000 313 #define ET_MMC_CTRL_ENABLE __BIT(0) 314 #define ET_MMC_CTRL_ARB_DISABLE __BIT(1) 315 #define ET_MMC_CTRL_RXMAC_DISABLE __BIT(2) 316 #define ET_MMC_CTRL_TXMAC_DISABLE __BIT(3) 317 #define ET_MMC_CTRL_TXDMA_DISABLE __BIT(4) 318 #define ET_MMC_CTRL_RXDMA_DISABLE __BIT(5) 319 #define ET_MMC_CTRL_FORCE_CE __BIT(6) 320 321 /* 322 * Interrupts 323 */ 324 #define ET_INTR_TXEOF __BIT(3) 325 #define ET_INTR_TXDMA_ERROR __BIT(4) 326 #define ET_INTR_RXEOF __BIT(5) 327 #define ET_INTR_RXRING0_LOW __BIT(6) 328 #define ET_INTR_RXRING1_LOW __BIT(7) 329 #define ET_INTR_RXSTAT_LOW __BIT(8) 330 #define ET_INTR_RXDMA_ERROR __BIT(9) 331 #define ET_INTR_TIMER __BIT(14) 332 #define ET_INTR_WOL __BIT(15) 333 #define ET_INTR_PHY __BIT(16) 334 #define ET_INTR_TXMAC __BIT(17) 335 #define ET_INTR_RXMAC __BIT(18) 336 #define ET_INTR_MAC_STATS __BIT(19) 337 #define ET_INTR_SLAVE_TO __BIT(20) 338 339 #define ET_INTRS (ET_INTR_TXEOF | \ 340 ET_INTR_RXEOF | \ 341 ET_INTR_TIMER) 342 343 /* 344 * RX ring position uses same layout 345 */ 346 #define ET_RX_RING_POS_INDEX __BITS(9, 0) 347 #define ET_RX_RING_POS_WRAP __BIT(10) 348 349 #endif /* !_IF_ETREG_H */ 350