1 /* 2 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Sepherosa Ziehau <sepherosa@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of The DragonFly Project nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific, prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 #ifndef _IF_ETVAR_H 36 #define _IF_ETVAR_H 37 38 #define ET_ALIGN 0x1000 /* XXX safest guess */ 39 #define ET_NSEG_MAX 32 /* XXX no limit actually */ 40 #define ET_NSEG_SPARE 8 41 42 #define ET_TX_NDESC 512 43 #define ET_RX_NDESC 512 44 #define ET_RX_NRING 2 45 #define ET_RX_NSTAT (ET_RX_NRING * ET_RX_NDESC) 46 47 #define ET_TX_RING_SIZE (ET_TX_NDESC * sizeof(struct et_txdesc)) 48 #define ET_RX_RING_SIZE (ET_RX_NDESC * sizeof(struct et_rxdesc)) 49 #define ET_RXSTAT_RING_SIZE (ET_RX_NSTAT * sizeof(struct et_rxstat)) 50 51 #define ET_JUMBO_ALIGN 8 52 #define ET_JUMBO_FRAMELEN (ET_MEM_SIZE - ET_MEM_RXSIZE_MIN - \ 53 ET_MEM_TXSIZE_EX) 54 #define ET_JUMBO_MTU (ET_JUMBO_FRAMELEN - ETHER_HDR_LEN - \ 55 EVL_ENCAPLEN - ETHER_CRC_LEN) 56 57 #define ET_FRAMELEN(mtu) (ETHER_HDR_LEN + EVL_ENCAPLEN + (mtu) + \ 58 ETHER_CRC_LEN) 59 60 #define ET_JSLOTS (ET_RX_NDESC + 128) 61 #define ET_JLEN roundup2(ET_JUMBO_FRAMELEN, ET_JUMBO_ALIGN) 62 #define ET_JUMBO_MEM_SIZE (ET_JSLOTS * ET_JLEN) 63 64 #define CSR_WRITE_4(sc, reg, val) \ 65 bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) 66 #define CSR_READ_4(sc, reg) \ 67 bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg)) 68 69 #define ET_ADDR_HI(addr) ((uint64_t) (addr) >> 32) 70 #define ET_ADDR_LO(addr) ((uint64_t) (addr) & 0xffffffff) 71 72 struct et_txdesc { 73 uint32_t td_addr_hi; 74 uint32_t td_addr_lo; 75 uint32_t td_ctrl1; /* ET_TDCTRL1_ */ 76 uint32_t td_ctrl2; /* ET_TDCTRL2_ */ 77 } __packed; 78 79 #define ET_TDCTRL1_LEN __BITS(15, 0) 80 81 #define ET_TDCTRL2_LAST_FRAG __BIT(0) 82 #define ET_TDCTRL2_FIRST_FRAG __BIT(1) 83 #define ET_TDCTRL2_INTR __BIT(2) 84 85 struct et_rxdesc { 86 uint32_t rd_addr_lo; 87 uint32_t rd_addr_hi; 88 uint32_t rd_ctrl; /* ET_RDCTRL_ */ 89 } __packed; 90 91 #define ET_RDCTRL_BUFIDX __BITS(9, 0) 92 93 struct et_rxstat { 94 uint32_t rxst_info1; 95 uint32_t rxst_info2; /* ET_RXST_INFO2_ */ 96 } __packed; 97 98 #define ET_RXST_INFO2_LEN __BITS(15, 0) 99 #define ET_RXST_INFO2_BUFIDX __BITS(25, 16) 100 #define ET_RXST_INFO2_RINGIDX __BITS(27, 26) 101 102 struct et_rxstatus { 103 uint32_t rxs_ring; 104 uint32_t rxs_stat_ring; /* ET_RXS_STATRING_ */ 105 } __packed; 106 107 #define ET_RXS_STATRING_INDEX __BITS(27, 16) 108 #define ET_RXS_STATRING_WRAP __BIT(28) 109 110 struct et_txbuf { 111 struct mbuf *tb_mbuf; 112 bus_dmamap_t tb_dmap; 113 }; 114 115 struct et_rxbuf { 116 struct mbuf *rb_mbuf; 117 bus_dmamap_t rb_dmap; 118 bus_addr_t rb_paddr; 119 }; 120 121 struct et_txstatus_data { 122 uint32_t *txsd_status; 123 bus_addr_t txsd_paddr; 124 bus_dma_tag_t txsd_dtag; 125 bus_dmamap_t txsd_dmap; 126 }; 127 128 struct et_rxstatus_data { 129 struct et_rxstatus *rxsd_status; 130 bus_addr_t rxsd_paddr; 131 bus_dma_tag_t rxsd_dtag; 132 bus_dmamap_t rxsd_dmap; 133 }; 134 135 struct et_rxstat_ring { 136 struct et_rxstat *rsr_stat; 137 bus_addr_t rsr_paddr; 138 bus_dma_tag_t rsr_dtag; 139 bus_dmamap_t rsr_dmap; 140 141 int rsr_index; 142 int rsr_wrap; 143 }; 144 145 struct et_txdesc_ring { 146 struct et_txdesc *tr_desc; 147 bus_addr_t tr_paddr; 148 bus_dma_tag_t tr_dtag; 149 bus_dmamap_t tr_dmap; 150 151 int tr_ready_index; 152 int tr_ready_wrap; 153 }; 154 155 struct et_rxdesc_ring { 156 struct et_rxdesc *rr_desc; 157 bus_addr_t rr_paddr; 158 bus_dma_tag_t rr_dtag; 159 bus_dmamap_t rr_dmap; 160 161 uint32_t rr_posreg; 162 int rr_index; 163 int rr_wrap; 164 }; 165 166 struct et_txbuf_data { 167 struct et_txbuf tbd_buf[ET_TX_NDESC]; 168 169 int tbd_start_index; 170 int tbd_start_wrap; 171 int tbd_used; 172 }; 173 174 struct et_softc; 175 struct et_rxbuf_data; 176 typedef int (*et_newbuf_t)(struct et_rxbuf_data *, int, int); 177 178 struct et_rxbuf_data { 179 struct et_rxbuf rbd_buf[ET_RX_NDESC]; 180 181 struct et_softc *rbd_softc; 182 struct et_rxdesc_ring *rbd_ring; 183 184 int rbd_jumbo; 185 int rbd_bufsize; 186 et_newbuf_t rbd_newbuf; 187 }; 188 189 struct et_jslot; 190 191 struct et_jumbo_data { 192 bus_dma_tag_t jd_dtag; 193 bus_dmamap_t jd_dmap; 194 void *jd_buf; 195 196 struct lwkt_serialize jd_serializer; 197 struct et_jslot *jd_slots; 198 SLIST_HEAD(, et_jslot) jd_free_slots; 199 }; 200 201 struct et_jslot { 202 struct et_jumbo_data *jslot_data; 203 void *jslot_buf; 204 bus_addr_t jslot_paddr; 205 int jslot_inuse; 206 int jslot_index; 207 SLIST_ENTRY(et_jslot) jslot_link; 208 }; 209 210 struct et_softc { 211 struct arpcom arpcom; 212 int sc_if_flags; 213 uint32_t sc_flags; /* ET_FLAG_ */ 214 215 int sc_mem_rid; 216 struct resource *sc_mem_res; 217 bus_space_tag_t sc_mem_bt; 218 bus_space_handle_t sc_mem_bh; 219 220 int sc_irq_type; 221 int sc_irq_rid; 222 struct resource *sc_irq_res; 223 void *sc_irq_handle; 224 225 device_t sc_miibus; 226 struct callout sc_tick; 227 228 bus_dma_tag_t sc_dtag; 229 230 struct et_rxdesc_ring sc_rx_ring[ET_RX_NRING]; 231 struct et_rxstat_ring sc_rxstat_ring; 232 struct et_rxstatus_data sc_rx_status; 233 234 struct et_txdesc_ring sc_tx_ring; 235 struct et_txstatus_data sc_tx_status; 236 237 bus_dma_tag_t sc_rxbuf_dtag; 238 bus_dmamap_t sc_rxbuf_tmp_dmap; 239 struct et_rxbuf_data sc_rx_data[ET_RX_NRING]; 240 241 bus_dma_tag_t sc_txbuf_dtag; 242 struct et_txbuf_data sc_tx_data; 243 244 struct et_jumbo_data sc_jumbo_data; 245 246 uint32_t sc_tx; 247 uint32_t sc_tx_intr; 248 249 /* 250 * Sysctl variables 251 */ 252 int sc_rx_intr_npkts; 253 int sc_rx_intr_delay; 254 int sc_tx_intr_nsegs; 255 uint32_t sc_timer; 256 }; 257 258 #define ET_FLAG_TXRX_ENABLED 0x1 259 #define ET_FLAG_JUMBO 0x2 260 261 #endif /* !_IF_ETVAR_H */ 262