1 /* 2 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Sepherosa Ziehau <sepherosa@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of The DragonFly Project nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific, prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * $DragonFly: src/sys/dev/netif/et/if_etvar.h,v 1.4 2007/10/23 14:28:42 sephe Exp $ 35 */ 36 37 #ifndef _IF_ETVAR_H 38 #define _IF_ETVAR_H 39 40 #define ET_ALIGN 0x1000 41 #define ET_NSEG_MAX 32 /* XXX no limit actually */ 42 #define ET_NSEG_SPARE 8 43 44 #define ET_TX_NDESC 512 45 #define ET_RX_NDESC 512 46 #define ET_RX_NRING 2 47 #define ET_RX_NSTAT (ET_RX_NRING * ET_RX_NDESC) 48 49 #define ET_TX_RING_SIZE (ET_TX_NDESC * sizeof(struct et_txdesc)) 50 #define ET_RX_RING_SIZE (ET_RX_NDESC * sizeof(struct et_rxdesc)) 51 #define ET_RXSTAT_RING_SIZE (ET_RX_NSTAT * sizeof(struct et_rxstat)) 52 53 #define ET_JUMBO_FRAMELEN (ET_MEM_SIZE - ET_MEM_RXSIZE_MIN - \ 54 ET_MEM_TXSIZE_EX) 55 #define ET_JUMBO_MTU (ET_JUMBO_FRAMELEN - ETHER_HDR_LEN - \ 56 EVL_ENCAPLEN - ETHER_CRC_LEN) 57 58 #define ET_FRAMELEN(mtu) (ETHER_HDR_LEN + EVL_ENCAPLEN + (mtu) + \ 59 ETHER_CRC_LEN) 60 61 #define ET_JSLOTS (ET_RX_NDESC + 128) 62 #define ET_JLEN (ET_JUMBO_FRAMELEN + ETHER_ALIGN) 63 #define ET_JUMBO_MEM_SIZE (ET_JSLOTS * ET_JLEN) 64 65 #define CSR_WRITE_4(sc, reg, val) \ 66 bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) 67 #define CSR_READ_4(sc, reg) \ 68 bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg)) 69 70 #define ET_ADDR_HI(addr) ((uint64_t) (addr) >> 32) 71 #define ET_ADDR_LO(addr) ((uint64_t) (addr) & 0xffffffff) 72 73 struct et_txdesc { 74 uint32_t td_addr_hi; 75 uint32_t td_addr_lo; 76 uint32_t td_ctrl1; /* ET_TDCTRL1_ */ 77 uint32_t td_ctrl2; /* ET_TDCTRL2_ */ 78 } __packed; 79 80 #define ET_TDCTRL1_LEN __BITS(15, 0) 81 82 #define ET_TDCTRL2_LAST_FRAG __BIT(0) 83 #define ET_TDCTRL2_FIRST_FRAG __BIT(1) 84 #define ET_TDCTRL2_INTR __BIT(2) 85 86 struct et_rxdesc { 87 uint32_t rd_addr_lo; 88 uint32_t rd_addr_hi; 89 uint32_t rd_ctrl; /* ET_RDCTRL_ */ 90 } __packed; 91 92 #define ET_RDCTRL_BUFIDX __BITS(9, 0) 93 94 struct et_rxstat { 95 uint32_t rxst_info1; 96 uint32_t rxst_info2; /* ET_RXST_INFO2_ */ 97 } __packed; 98 99 #define ET_RXST_INFO2_LEN __BITS(15, 0) 100 #define ET_RXST_INFO2_BUFIDX __BITS(25, 16) 101 #define ET_RXST_INFO2_RINGIDX __BITS(27, 26) 102 103 struct et_rxstatus { 104 uint32_t rxs_ring; 105 uint32_t rxs_stat_ring; /* ET_RXS_STATRING_ */ 106 } __packed; 107 108 #define ET_RXS_STATRING_INDEX __BITS(27, 16) 109 #define ET_RXS_STATRING_WRAP __BIT(28) 110 111 struct et_dmamap_ctx { 112 int nsegs; 113 bus_dma_segment_t *segs; 114 }; 115 116 struct et_txbuf { 117 struct mbuf *tb_mbuf; 118 bus_dmamap_t tb_dmap; 119 }; 120 121 struct et_rxbuf { 122 struct mbuf *rb_mbuf; 123 bus_dmamap_t rb_dmap; 124 bus_addr_t rb_paddr; 125 }; 126 127 struct et_txstatus_data { 128 uint32_t *txsd_status; 129 bus_addr_t txsd_paddr; 130 bus_dma_tag_t txsd_dtag; 131 bus_dmamap_t txsd_dmap; 132 }; 133 134 struct et_rxstatus_data { 135 struct et_rxstatus *rxsd_status; 136 bus_addr_t rxsd_paddr; 137 bus_dma_tag_t rxsd_dtag; 138 bus_dmamap_t rxsd_dmap; 139 }; 140 141 struct et_rxstat_ring { 142 struct et_rxstat *rsr_stat; 143 bus_addr_t rsr_paddr; 144 bus_dma_tag_t rsr_dtag; 145 bus_dmamap_t rsr_dmap; 146 147 int rsr_index; 148 int rsr_wrap; 149 }; 150 151 struct et_txdesc_ring { 152 struct et_txdesc *tr_desc; 153 bus_addr_t tr_paddr; 154 bus_dma_tag_t tr_dtag; 155 bus_dmamap_t tr_dmap; 156 157 int tr_ready_index; 158 int tr_ready_wrap; 159 }; 160 161 struct et_rxdesc_ring { 162 struct et_rxdesc *rr_desc; 163 bus_addr_t rr_paddr; 164 bus_dma_tag_t rr_dtag; 165 bus_dmamap_t rr_dmap; 166 167 uint32_t rr_posreg; 168 int rr_index; 169 int rr_wrap; 170 }; 171 172 struct et_txbuf_data { 173 struct et_txbuf tbd_buf[ET_TX_NDESC]; 174 175 int tbd_start_index; 176 int tbd_start_wrap; 177 int tbd_used; 178 }; 179 180 struct et_softc; 181 struct et_rxbuf_data; 182 typedef int (*et_newbuf_t)(struct et_rxbuf_data *, int, int); 183 184 struct et_rxbuf_data { 185 struct et_rxbuf rbd_buf[ET_RX_NDESC]; 186 187 struct et_softc *rbd_softc; 188 struct et_rxdesc_ring *rbd_ring; 189 190 int rbd_jumbo; 191 int rbd_bufsize; 192 et_newbuf_t rbd_newbuf; 193 }; 194 195 struct et_jslot; 196 197 struct et_jumbo_data { 198 bus_dma_tag_t jd_dtag; 199 bus_dmamap_t jd_dmap; 200 void *jd_buf; 201 202 struct lwkt_serialize jd_serializer; 203 struct et_jslot *jd_slots; 204 SLIST_HEAD(, et_jslot) jd_free_slots; 205 }; 206 207 struct et_jslot { 208 struct et_jumbo_data *jslot_data; 209 void *jslot_buf; 210 bus_addr_t jslot_paddr; 211 int jslot_inuse; 212 int jslot_index; 213 SLIST_ENTRY(et_jslot) jslot_link; 214 }; 215 216 struct et_softc { 217 struct arpcom arpcom; 218 int sc_if_flags; 219 uint32_t sc_flags; /* ET_FLAG_ */ 220 221 int sc_mem_rid; 222 struct resource *sc_mem_res; 223 bus_space_tag_t sc_mem_bt; 224 bus_space_handle_t sc_mem_bh; 225 226 int sc_irq_rid; 227 struct resource *sc_irq_res; 228 void *sc_irq_handle; 229 230 device_t sc_miibus; 231 struct callout sc_tick; 232 233 bus_dma_tag_t sc_dtag; 234 235 struct et_rxdesc_ring sc_rx_ring[ET_RX_NRING]; 236 struct et_rxstat_ring sc_rxstat_ring; 237 struct et_rxstatus_data sc_rx_status; 238 239 struct et_txdesc_ring sc_tx_ring; 240 struct et_txstatus_data sc_tx_status; 241 242 bus_dma_tag_t sc_mbuf_dtag; 243 bus_dmamap_t sc_mbuf_tmp_dmap; 244 struct et_rxbuf_data sc_rx_data[ET_RX_NRING]; 245 struct et_txbuf_data sc_tx_data; 246 247 struct et_jumbo_data sc_jumbo_data; 248 249 uint32_t sc_tx; 250 uint32_t sc_tx_intr; 251 252 struct sysctl_ctx_list sc_sysctl_ctx; 253 struct sysctl_oid *sc_sysctl_tree; 254 255 /* 256 * Sysctl variables 257 */ 258 int sc_rx_intr_npkts; 259 int sc_rx_intr_delay; 260 int sc_tx_intr_nsegs; 261 uint32_t sc_timer; 262 }; 263 264 #define ET_FLAG_TXRX_ENABLED 0x1 265 #define ET_FLAG_JUMBO 0x2 266 267 #endif /* !_IF_ETVAR_H */ 268