1 /* 2 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Sepherosa Ziehau <sepherosa@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of The DragonFly Project nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific, prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * $DragonFly: src/sys/dev/netif/et/if_etvar.h,v 1.3 2007/10/20 05:22:57 sephe Exp $ 35 */ 36 37 #ifndef _IF_ETVAR_H 38 #define _IF_ETVAR_H 39 40 #define ET_ALIGN 0x1000 41 #define ET_NSEG_MAX 32 /* XXX no limit actually */ 42 #define ET_NSEG_SPARE 5 43 44 #define ET_TX_NDESC 512 45 #define ET_RX_NDESC 512 46 #define ET_RX_NRING 2 47 #define ET_RX_NSTAT (ET_RX_NRING * ET_RX_NDESC) 48 49 #define ET_TX_RING_SIZE (ET_TX_NDESC * sizeof(struct et_txdesc)) 50 #define ET_RX_RING_SIZE (ET_RX_NDESC * sizeof(struct et_rxdesc)) 51 #define ET_RXSTAT_RING_SIZE (ET_RX_NSTAT * sizeof(struct et_rxstat)) 52 53 #define ET_FRAMELEN(mtu) (ETHER_HDR_LEN + EVL_ENCAPLEN + (mtu) + \ 54 ETHER_CRC_LEN) 55 56 #define CSR_WRITE_4(sc, reg, val) \ 57 bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) 58 #define CSR_READ_4(sc, reg) \ 59 bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg)) 60 61 #define ET_ADDR_HI(addr) ((uint64_t) (addr) >> 32) 62 #define ET_ADDR_LO(addr) ((uint64_t) (addr) & 0xffffffff) 63 64 struct et_txdesc { 65 uint32_t td_addr_hi; 66 uint32_t td_addr_lo; 67 uint32_t td_ctrl1; /* ET_TDCTRL1_ */ 68 uint32_t td_ctrl2; /* ET_TDCTRL2_ */ 69 } __packed; 70 71 #define ET_TDCTRL1_LEN __BITS(15, 0) 72 73 #define ET_TDCTRL2_LAST_FRAG __BIT(0) 74 #define ET_TDCTRL2_FIRST_FRAG __BIT(1) 75 #define ET_TDCTRL2_INTR __BIT(2) 76 77 struct et_rxdesc { 78 uint32_t rd_addr_lo; 79 uint32_t rd_addr_hi; 80 uint32_t rd_ctrl; /* ET_RDCTRL_ */ 81 } __packed; 82 83 #define ET_RDCTRL_BUFIDX __BITS(9, 0) 84 85 struct et_rxstat { 86 uint32_t rxst_info1; 87 uint32_t rxst_info2; /* ET_RXST_INFO2_ */ 88 } __packed; 89 90 #define ET_RXST_INFO2_LEN __BITS(15, 0) 91 #define ET_RXST_INFO2_BUFIDX __BITS(25, 16) 92 #define ET_RXST_INFO2_RINGIDX __BITS(27, 26) 93 94 struct et_rxstatus { 95 uint32_t rxs_ring; 96 uint32_t rxs_stat_ring; /* ET_RXS_STATRING_ */ 97 } __packed; 98 99 #define ET_RXS_STATRING_INDEX __BITS(27, 16) 100 #define ET_RXS_STATRING_WRAP __BIT(28) 101 102 struct et_dmamap_ctx { 103 int nsegs; 104 bus_dma_segment_t *segs; 105 }; 106 107 struct et_txbuf { 108 struct mbuf *tb_mbuf; 109 bus_dmamap_t tb_dmap; 110 }; 111 112 struct et_rxbuf { 113 struct mbuf *rb_mbuf; 114 bus_dmamap_t rb_dmap; 115 bus_addr_t rb_paddr; 116 }; 117 118 struct et_txstatus_data { 119 uint32_t *txsd_status; 120 bus_addr_t txsd_paddr; 121 bus_dma_tag_t txsd_dtag; 122 bus_dmamap_t txsd_dmap; 123 }; 124 125 struct et_rxstatus_data { 126 struct et_rxstatus *rxsd_status; 127 bus_addr_t rxsd_paddr; 128 bus_dma_tag_t rxsd_dtag; 129 bus_dmamap_t rxsd_dmap; 130 }; 131 132 struct et_rxstat_ring { 133 struct et_rxstat *rsr_stat; 134 bus_addr_t rsr_paddr; 135 bus_dma_tag_t rsr_dtag; 136 bus_dmamap_t rsr_dmap; 137 138 int rsr_index; 139 int rsr_wrap; 140 }; 141 142 struct et_txdesc_ring { 143 struct et_txdesc *tr_desc; 144 bus_addr_t tr_paddr; 145 bus_dma_tag_t tr_dtag; 146 bus_dmamap_t tr_dmap; 147 148 int tr_ready_index; 149 int tr_ready_wrap; 150 }; 151 152 struct et_rxdesc_ring { 153 struct et_rxdesc *rr_desc; 154 bus_addr_t rr_paddr; 155 bus_dma_tag_t rr_dtag; 156 bus_dmamap_t rr_dmap; 157 158 uint32_t rr_posreg; 159 int rr_index; 160 int rr_wrap; 161 }; 162 163 struct et_txbuf_data { 164 struct et_txbuf tbd_buf[ET_TX_NDESC]; 165 166 int tbd_start_index; 167 int tbd_start_wrap; 168 int tbd_used; 169 }; 170 171 struct et_softc; 172 struct et_rxbuf_data; 173 typedef int (*et_newbuf_t)(struct et_rxbuf_data *, int, int); 174 175 struct et_rxbuf_data { 176 struct et_rxbuf rbd_buf[ET_RX_NDESC]; 177 178 struct et_softc *rbd_softc; 179 struct et_rxdesc_ring *rbd_ring; 180 181 int rbd_bufsize; 182 et_newbuf_t rbd_newbuf; 183 }; 184 185 struct et_softc { 186 struct arpcom arpcom; 187 int sc_if_flags; 188 int sc_txrx_enabled; 189 190 int sc_mem_rid; 191 struct resource *sc_mem_res; 192 bus_space_tag_t sc_mem_bt; 193 bus_space_handle_t sc_mem_bh; 194 195 int sc_irq_rid; 196 struct resource *sc_irq_res; 197 void *sc_irq_handle; 198 199 device_t sc_miibus; 200 struct callout sc_tick; 201 202 bus_dma_tag_t sc_dtag; 203 204 struct et_rxdesc_ring sc_rx_ring[ET_RX_NRING]; 205 struct et_rxstat_ring sc_rxstat_ring; 206 struct et_rxstatus_data sc_rx_status; 207 208 struct et_txdesc_ring sc_tx_ring; 209 struct et_txstatus_data sc_tx_status; 210 211 bus_dma_tag_t sc_mbuf_dtag; 212 bus_dmamap_t sc_mbuf_tmp_dmap; 213 struct et_rxbuf_data sc_rx_data[ET_RX_NRING]; 214 struct et_txbuf_data sc_tx_data; 215 216 uint32_t sc_tx; 217 uint32_t sc_tx_intr; 218 219 struct sysctl_ctx_list sc_sysctl_ctx; 220 struct sysctl_oid *sc_sysctl_tree; 221 222 /* 223 * Sysctl variables 224 */ 225 int sc_rx_intr_npkts; 226 int sc_rx_intr_delay; 227 int sc_tx_intr_nsegs; 228 uint32_t sc_timer; 229 }; 230 231 #endif /* !_IF_ETVAR_H */ 232