1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.110.2.30 2003/06/12 16:47:05 mux Exp $ 29 * $DragonFly: src/sys/dev/netif/fxp/if_fxp.c,v 1.18 2004/12/24 10:50:06 asmodai Exp $ 30 */ 31 32 /* 33 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/mbuf.h> 39 #include <sys/malloc.h> 40 /* #include <sys/mutex.h> */ 41 #include <sys/kernel.h> 42 #include <sys/socket.h> 43 #include <sys/sysctl.h> 44 45 #include <net/if.h> 46 #include <net/if_dl.h> 47 #include <net/if_media.h> 48 49 #ifdef NS 50 #include <netns/ns.h> 51 #include <netns/ns_if.h> 52 #endif 53 54 #include <net/bpf.h> 55 #include <sys/sockio.h> 56 #include <sys/bus.h> 57 #include <machine/bus.h> 58 #include <sys/rman.h> 59 #include <machine/resource.h> 60 61 #include <net/ethernet.h> 62 #include <net/if_arp.h> 63 64 #include <vm/vm.h> /* for vtophys */ 65 #include <vm/pmap.h> /* for vtophys */ 66 #include <machine/clock.h> /* for DELAY */ 67 68 #include <net/if_types.h> 69 #include <net/vlan/if_vlan_var.h> 70 71 #include <bus/pci/pcivar.h> 72 #include <bus/pci/pcireg.h> /* for PCIM_CMD_xxx */ 73 74 #include "../mii_layer/mii.h" 75 #include "../mii_layer/miivar.h" 76 77 #include "if_fxpreg.h" 78 #include "if_fxpvar.h" 79 #include "rcvbundl.h" 80 81 #include "miibus_if.h" 82 83 /* 84 * NOTE! On the Alpha, we have an alignment constraint. The 85 * card DMAs the packet immediately following the RFA. However, 86 * the first thing in the packet is a 14-byte Ethernet header. 87 * This means that the packet is misaligned. To compensate, 88 * we actually offset the RFA 2 bytes into the cluster. This 89 * alignes the packet after the Ethernet header at a 32-bit 90 * boundary. HOWEVER! This means that the RFA is misaligned! 91 */ 92 #define RFA_ALIGNMENT_FUDGE 2 93 94 /* 95 * Set initial transmit threshold at 64 (512 bytes). This is 96 * increased by 64 (512 bytes) at a time, to maximum of 192 97 * (1536 bytes), if an underrun occurs. 98 */ 99 static int tx_threshold = 64; 100 101 /* 102 * The configuration byte map has several undefined fields which 103 * must be one or must be zero. Set up a template for these bits 104 * only, (assuming a 82557 chip) leaving the actual configuration 105 * to fxp_init. 106 * 107 * See struct fxp_cb_config for the bit definitions. 108 */ 109 static u_char fxp_cb_config_template[] = { 110 0x0, 0x0, /* cb_status */ 111 0x0, 0x0, /* cb_command */ 112 0x0, 0x0, 0x0, 0x0, /* link_addr */ 113 0x0, /* 0 */ 114 0x0, /* 1 */ 115 0x0, /* 2 */ 116 0x0, /* 3 */ 117 0x0, /* 4 */ 118 0x0, /* 5 */ 119 0x32, /* 6 */ 120 0x0, /* 7 */ 121 0x0, /* 8 */ 122 0x0, /* 9 */ 123 0x6, /* 10 */ 124 0x0, /* 11 */ 125 0x0, /* 12 */ 126 0x0, /* 13 */ 127 0xf2, /* 14 */ 128 0x48, /* 15 */ 129 0x0, /* 16 */ 130 0x40, /* 17 */ 131 0xf0, /* 18 */ 132 0x0, /* 19 */ 133 0x3f, /* 20 */ 134 0x5 /* 21 */ 135 }; 136 137 struct fxp_ident { 138 u_int16_t devid; 139 int16_t revid; /* -1 matches anything */ 140 char *name; 141 }; 142 143 /* 144 * Claim various Intel PCI device identifiers for this driver. The 145 * sub-vendor and sub-device field are extensively used to identify 146 * particular variants, but we don't currently differentiate between 147 * them. 148 */ 149 static struct fxp_ident fxp_ident_table[] = { 150 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 151 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 152 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 153 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 154 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 155 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 156 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 157 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 158 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 159 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 160 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 161 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 162 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 163 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 164 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 165 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 166 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 167 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 168 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 169 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 170 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 171 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 172 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 173 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 174 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 175 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 176 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 177 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 178 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 179 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 180 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 181 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 182 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 183 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 184 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 185 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 186 { 0, -1, NULL }, 187 }; 188 189 static int fxp_probe(device_t dev); 190 static int fxp_attach(device_t dev); 191 static int fxp_detach(device_t dev); 192 static int fxp_shutdown(device_t dev); 193 static int fxp_suspend(device_t dev); 194 static int fxp_resume(device_t dev); 195 196 static void fxp_intr(void *xsc); 197 static void fxp_intr_body(struct fxp_softc *sc, 198 u_int8_t statack, int count); 199 200 static void fxp_init(void *xsc); 201 static void fxp_tick(void *xsc); 202 static void fxp_powerstate_d0(device_t dev); 203 static void fxp_start(struct ifnet *ifp); 204 static void fxp_stop(struct fxp_softc *sc); 205 static void fxp_release(struct fxp_softc *sc); 206 static int fxp_ioctl(struct ifnet *ifp, u_long command, 207 caddr_t data, struct ucred *); 208 static void fxp_watchdog(struct ifnet *ifp); 209 static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm); 210 static int fxp_mc_addrs(struct fxp_softc *sc); 211 static void fxp_mc_setup(struct fxp_softc *sc); 212 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 213 int autosize); 214 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 215 u_int16_t data); 216 static void fxp_autosize_eeprom(struct fxp_softc *sc); 217 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 218 int offset, int words); 219 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 220 int offset, int words); 221 static int fxp_ifmedia_upd(struct ifnet *ifp); 222 static void fxp_ifmedia_sts(struct ifnet *ifp, 223 struct ifmediareq *ifmr); 224 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 225 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 226 struct ifmediareq *ifmr); 227 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 228 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 229 int value); 230 static void fxp_load_ucode(struct fxp_softc *sc); 231 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 232 int low, int high); 233 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 234 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 235 static __inline void fxp_lwcopy(volatile u_int32_t *src, 236 volatile u_int32_t *dst); 237 static __inline void fxp_scb_wait(struct fxp_softc *sc); 238 static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 239 static __inline void fxp_dma_wait(volatile u_int16_t *status, 240 struct fxp_softc *sc); 241 242 static device_method_t fxp_methods[] = { 243 /* Device interface */ 244 DEVMETHOD(device_probe, fxp_probe), 245 DEVMETHOD(device_attach, fxp_attach), 246 DEVMETHOD(device_detach, fxp_detach), 247 DEVMETHOD(device_shutdown, fxp_shutdown), 248 DEVMETHOD(device_suspend, fxp_suspend), 249 DEVMETHOD(device_resume, fxp_resume), 250 251 /* MII interface */ 252 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 253 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 254 255 { 0, 0 } 256 }; 257 258 static driver_t fxp_driver = { 259 "fxp", 260 fxp_methods, 261 sizeof(struct fxp_softc), 262 }; 263 264 static devclass_t fxp_devclass; 265 266 DECLARE_DUMMY_MODULE(if_fxp); 267 MODULE_DEPEND(if_fxp, miibus, 1, 1, 1); 268 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 269 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 270 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 271 272 static int fxp_rnr; 273 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 274 275 /* 276 * Inline function to copy a 16-bit aligned 32-bit quantity. 277 */ 278 static __inline void 279 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst) 280 { 281 #ifdef __i386__ 282 *dst = *src; 283 #else 284 volatile u_int16_t *a = (volatile u_int16_t *)src; 285 volatile u_int16_t *b = (volatile u_int16_t *)dst; 286 287 b[0] = a[0]; 288 b[1] = a[1]; 289 #endif 290 } 291 292 /* 293 * Wait for the previous command to be accepted (but not necessarily 294 * completed). 295 */ 296 static __inline void 297 fxp_scb_wait(struct fxp_softc *sc) 298 { 299 int i = 10000; 300 301 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 302 DELAY(2); 303 if (i == 0) 304 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 305 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 306 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 307 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 308 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 309 } 310 311 static __inline void 312 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 313 { 314 315 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 316 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 317 fxp_scb_wait(sc); 318 } 319 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 320 } 321 322 static __inline void 323 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc) 324 { 325 int i = 10000; 326 327 while (!(*status & FXP_CB_STATUS_C) && --i) 328 DELAY(2); 329 if (i == 0) 330 device_printf(sc->dev, "DMA timeout\n"); 331 } 332 333 /* 334 * Return identification string if this is device is ours. 335 */ 336 static int 337 fxp_probe(device_t dev) 338 { 339 u_int16_t devid; 340 u_int8_t revid; 341 struct fxp_ident *ident; 342 343 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 344 devid = pci_get_device(dev); 345 revid = pci_get_revid(dev); 346 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 347 if (ident->devid == devid && 348 (ident->revid == revid || ident->revid == -1)) { 349 device_set_desc(dev, ident->name); 350 return (0); 351 } 352 } 353 } 354 return (ENXIO); 355 } 356 357 static void 358 fxp_powerstate_d0(device_t dev) 359 { 360 #if defined(__DragonFly__) || __FreeBSD_version >= 430002 361 u_int32_t iobase, membase, irq; 362 363 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 364 /* Save important PCI config data. */ 365 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 366 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 367 irq = pci_read_config(dev, PCIR_INTLINE, 4); 368 369 /* Reset the power state. */ 370 device_printf(dev, "chip is in D%d power mode " 371 "-- setting to D0\n", pci_get_powerstate(dev)); 372 373 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 374 375 /* Restore PCI config data. */ 376 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 377 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 378 pci_write_config(dev, PCIR_INTLINE, irq, 4); 379 } 380 #endif 381 } 382 383 static int 384 fxp_attach(device_t dev) 385 { 386 int error = 0; 387 struct fxp_softc *sc = device_get_softc(dev); 388 struct ifnet *ifp; 389 u_int32_t val; 390 u_int16_t data; 391 int i, rid, m1, m2, prefer_iomap; 392 int s; 393 394 bzero(sc, sizeof(*sc)); 395 sc->dev = dev; 396 callout_init(&sc->fxp_stat_timer); 397 sysctl_ctx_init(&sc->sysctl_ctx); 398 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 399 400 s = splimp(); 401 402 /* 403 * Enable bus mastering. Enable memory space too, in case 404 * BIOS/Prom forgot about it. 405 */ 406 val = pci_read_config(dev, PCIR_COMMAND, 2); 407 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 408 pci_write_config(dev, PCIR_COMMAND, val, 2); 409 val = pci_read_config(dev, PCIR_COMMAND, 2); 410 411 fxp_powerstate_d0(dev); 412 413 /* 414 * Figure out which we should try first - memory mapping or i/o mapping? 415 * We default to memory mapping. Then we accept an override from the 416 * command line. Then we check to see which one is enabled. 417 */ 418 m1 = PCIM_CMD_MEMEN; 419 m2 = PCIM_CMD_PORTEN; 420 prefer_iomap = 0; 421 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 422 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 423 m1 = PCIM_CMD_PORTEN; 424 m2 = PCIM_CMD_MEMEN; 425 } 426 427 if (val & m1) { 428 sc->rtp = 429 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 430 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 431 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 432 0, ~0, 1, RF_ACTIVE); 433 } 434 if (sc->mem == NULL && (val & m2)) { 435 sc->rtp = 436 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 437 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 438 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 439 0, ~0, 1, RF_ACTIVE); 440 } 441 442 if (!sc->mem) { 443 device_printf(dev, "could not map device registers\n"); 444 error = ENXIO; 445 goto fail; 446 } 447 if (bootverbose) { 448 device_printf(dev, "using %s space register mapping\n", 449 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 450 } 451 452 sc->sc_st = rman_get_bustag(sc->mem); 453 sc->sc_sh = rman_get_bushandle(sc->mem); 454 455 /* 456 * Allocate our interrupt. 457 */ 458 rid = 0; 459 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 460 RF_SHAREABLE | RF_ACTIVE); 461 if (sc->irq == NULL) { 462 device_printf(dev, "could not map interrupt\n"); 463 error = ENXIO; 464 goto fail; 465 } 466 467 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, 468 fxp_intr, sc, &sc->ih); 469 if (error) { 470 device_printf(dev, "could not setup irq\n"); 471 goto fail; 472 } 473 474 /* 475 * Reset to a stable state. 476 */ 477 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 478 DELAY(10); 479 480 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 481 M_DEVBUF, M_WAITOK | M_ZERO); 482 483 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, 484 M_WAITOK | M_ZERO); 485 486 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_WAITOK); 487 488 /* 489 * Pre-allocate our receive buffers. 490 */ 491 for (i = 0; i < FXP_NRFABUFS; i++) { 492 if (fxp_add_rfabuf(sc, NULL) != 0) { 493 goto failmem; 494 } 495 } 496 497 /* 498 * Find out how large of an SEEPROM we have. 499 */ 500 fxp_autosize_eeprom(sc); 501 502 /* 503 * Determine whether we must use the 503 serial interface. 504 */ 505 fxp_read_eeprom(sc, &data, 6, 1); 506 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 507 (data & FXP_PHY_SERIAL_ONLY)) 508 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 509 510 /* 511 * Create the sysctl tree 512 */ 513 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 514 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 515 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 516 if (sc->sysctl_tree == NULL) 517 goto fail; 518 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 519 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 520 &sc->tunable_int_delay, 0, &sysctl_hw_fxp_int_delay, "I", 521 "FXP driver receive interrupt microcode bundling delay"); 522 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 523 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 524 &sc->tunable_bundle_max, 0, &sysctl_hw_fxp_bundle_max, "I", 525 "FXP driver receive interrupt microcode bundle size limit"); 526 527 /* 528 * Pull in device tunables. 529 */ 530 sc->tunable_int_delay = TUNABLE_INT_DELAY; 531 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 532 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 533 "int_delay", &sc->tunable_int_delay); 534 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 535 "bundle_max", &sc->tunable_bundle_max); 536 537 /* 538 * Find out the chip revision; lump all 82557 revs together. 539 */ 540 fxp_read_eeprom(sc, &data, 5, 1); 541 if ((data >> 8) == 1) 542 sc->revision = FXP_REV_82557; 543 else 544 sc->revision = pci_get_revid(dev); 545 546 /* 547 * Enable workarounds for certain chip revision deficiencies. 548 * 549 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 550 * some systems based a normal 82559 design, have a defect where 551 * the chip can cause a PCI protocol violation if it receives 552 * a CU_RESUME command when it is entering the IDLE state. The 553 * workaround is to disable Dynamic Standby Mode, so the chip never 554 * deasserts CLKRUN#, and always remains in an active state. 555 * 556 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 557 */ 558 i = pci_get_device(dev); 559 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 560 sc->revision >= FXP_REV_82559_A0) { 561 fxp_read_eeprom(sc, &data, 10, 1); 562 if (data & 0x02) { /* STB enable */ 563 u_int16_t cksum; 564 int i; 565 566 device_printf(dev, 567 "Disabling dynamic standby mode in EEPROM\n"); 568 data &= ~0x02; 569 fxp_write_eeprom(sc, &data, 10, 1); 570 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 571 cksum = 0; 572 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 573 fxp_read_eeprom(sc, &data, i, 1); 574 cksum += data; 575 } 576 i = (1 << sc->eeprom_size) - 1; 577 cksum = 0xBABA - cksum; 578 fxp_read_eeprom(sc, &data, i, 1); 579 fxp_write_eeprom(sc, &cksum, i, 1); 580 device_printf(dev, 581 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 582 i, data, cksum); 583 #if 1 584 /* 585 * If the user elects to continue, try the software 586 * workaround, as it is better than nothing. 587 */ 588 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 589 #endif 590 } 591 } 592 593 /* 594 * If we are not a 82557 chip, we can enable extended features. 595 */ 596 if (sc->revision != FXP_REV_82557) { 597 /* 598 * If MWI is enabled in the PCI configuration, and there 599 * is a valid cacheline size (8 or 16 dwords), then tell 600 * the board to turn on MWI. 601 */ 602 if (val & PCIM_CMD_MWRICEN && 603 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 604 sc->flags |= FXP_FLAG_MWI_ENABLE; 605 606 /* turn on the extended TxCB feature */ 607 sc->flags |= FXP_FLAG_EXT_TXCB; 608 609 /* enable reception of long frames for VLAN */ 610 sc->flags |= FXP_FLAG_LONG_PKT_EN; 611 } 612 613 /* 614 * Read MAC address. 615 */ 616 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3); 617 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) 618 device_printf(dev, "10Mbps"); 619 if (bootverbose) { 620 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 621 pci_get_vendor(dev), pci_get_device(dev), 622 pci_get_subvendor(dev), pci_get_subdevice(dev), 623 pci_get_revid(dev)); 624 fxp_read_eeprom(sc, &data, 10, 1); 625 device_printf(dev, "Dynamic Standby mode is %s\n", 626 data & 0x02 ? "enabled" : "disabled"); 627 } 628 629 /* 630 * If this is only a 10Mbps device, then there is no MII, and 631 * the PHY will use a serial interface instead. 632 * 633 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 634 * doesn't have a programming interface of any sort. The 635 * media is sensed automatically based on how the link partner 636 * is configured. This is, in essence, manual configuration. 637 */ 638 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 639 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 640 fxp_serial_ifmedia_sts); 641 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 642 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 643 } else { 644 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 645 fxp_ifmedia_sts)) { 646 device_printf(dev, "MII without any PHY!\n"); 647 error = ENXIO; 648 goto fail; 649 } 650 } 651 652 ifp = &sc->arpcom.ac_if; 653 if_initname(ifp, "fxp", device_get_unit(dev)); 654 ifp->if_baudrate = 100000000; 655 ifp->if_init = fxp_init; 656 ifp->if_softc = sc; 657 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 658 ifp->if_ioctl = fxp_ioctl; 659 ifp->if_start = fxp_start; 660 ifp->if_watchdog = fxp_watchdog; 661 662 /* 663 * Attach the interface. 664 */ 665 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 666 667 /* 668 * Tell the upper layer(s) we support long frames. 669 */ 670 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 671 672 /* 673 * Let the system queue as many packets as we have available 674 * TX descriptors. 675 */ 676 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 677 678 splx(s); 679 return (0); 680 681 failmem: 682 device_printf(dev, "Failed to malloc memory\n"); 683 error = ENOMEM; 684 fail: 685 splx(s); 686 fxp_release(sc); 687 return (error); 688 } 689 690 /* 691 * release all resources 692 */ 693 static void 694 fxp_release(struct fxp_softc *sc) 695 { 696 697 bus_generic_detach(sc->dev); 698 if (sc->miibus) 699 device_delete_child(sc->dev, sc->miibus); 700 701 if (sc->cbl_base) 702 free(sc->cbl_base, M_DEVBUF); 703 if (sc->fxp_stats) 704 free(sc->fxp_stats, M_DEVBUF); 705 if (sc->mcsp) 706 free(sc->mcsp, M_DEVBUF); 707 if (sc->rfa_headm) 708 m_freem(sc->rfa_headm); 709 710 if (sc->ih) 711 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 712 if (sc->irq) 713 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 714 if (sc->mem) 715 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 716 717 sysctl_ctx_free(&sc->sysctl_ctx); 718 719 mtx_destroy(&sc->sc_mtx); 720 } 721 722 /* 723 * Detach interface. 724 */ 725 static int 726 fxp_detach(device_t dev) 727 { 728 struct fxp_softc *sc = device_get_softc(dev); 729 int s; 730 731 /* disable interrupts */ 732 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 733 734 s = splimp(); 735 736 /* 737 * Stop DMA and drop transmit queue. 738 */ 739 fxp_stop(sc); 740 741 /* 742 * Close down routes etc. 743 */ 744 ether_ifdetach(&sc->arpcom.ac_if); 745 746 /* 747 * Free all media structures. 748 */ 749 ifmedia_removeall(&sc->sc_media); 750 751 splx(s); 752 753 /* Release our allocated resources. */ 754 fxp_release(sc); 755 756 return (0); 757 } 758 759 /* 760 * Device shutdown routine. Called at system shutdown after sync. The 761 * main purpose of this routine is to shut off receiver DMA so that 762 * kernel memory doesn't get clobbered during warmboot. 763 */ 764 static int 765 fxp_shutdown(device_t dev) 766 { 767 /* 768 * Make sure that DMA is disabled prior to reboot. Not doing 769 * do could allow DMA to corrupt kernel memory during the 770 * reboot before the driver initializes. 771 */ 772 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 773 return (0); 774 } 775 776 /* 777 * Device suspend routine. Stop the interface and save some PCI 778 * settings in case the BIOS doesn't restore them properly on 779 * resume. 780 */ 781 static int 782 fxp_suspend(device_t dev) 783 { 784 struct fxp_softc *sc = device_get_softc(dev); 785 int i, s; 786 787 s = splimp(); 788 789 fxp_stop(sc); 790 791 for (i = 0; i < 5; i++) 792 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 793 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 794 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 795 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 796 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 797 798 sc->suspended = 1; 799 800 splx(s); 801 return (0); 802 } 803 804 /* 805 * Device resume routine. Restore some PCI settings in case the BIOS 806 * doesn't, re-enable busmastering, and restart the interface if 807 * appropriate. 808 */ 809 static int 810 fxp_resume(device_t dev) 811 { 812 struct fxp_softc *sc = device_get_softc(dev); 813 struct ifnet *ifp = &sc->sc_if; 814 u_int16_t pci_command; 815 int i, s; 816 817 s = splimp(); 818 819 fxp_powerstate_d0(dev); 820 821 /* better way to do this? */ 822 for (i = 0; i < 5; i++) 823 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 824 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 825 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 826 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 827 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 828 829 /* reenable busmastering */ 830 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 831 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 832 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 833 834 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 835 DELAY(10); 836 837 /* reinitialize interface if necessary */ 838 if (ifp->if_flags & IFF_UP) 839 fxp_init(sc); 840 841 sc->suspended = 0; 842 843 splx(s); 844 return (0); 845 } 846 847 static void 848 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 849 { 850 u_int16_t reg; 851 int x; 852 853 /* 854 * Shift in data. 855 */ 856 for (x = 1 << (length - 1); x; x >>= 1) { 857 if (data & x) 858 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 859 else 860 reg = FXP_EEPROM_EECS; 861 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 862 DELAY(1); 863 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 864 DELAY(1); 865 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 866 DELAY(1); 867 } 868 } 869 870 /* 871 * Read from the serial EEPROM. Basically, you manually shift in 872 * the read opcode (one bit at a time) and then shift in the address, 873 * and then you shift out the data (all of this one bit at a time). 874 * The word size is 16 bits, so you have to provide the address for 875 * every 16 bits of data. 876 */ 877 static u_int16_t 878 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 879 { 880 u_int16_t reg, data; 881 int x; 882 883 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 884 /* 885 * Shift in read opcode. 886 */ 887 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 888 /* 889 * Shift in address. 890 */ 891 data = 0; 892 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 893 if (offset & x) 894 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 895 else 896 reg = FXP_EEPROM_EECS; 897 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 898 DELAY(1); 899 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 900 DELAY(1); 901 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 902 DELAY(1); 903 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 904 data++; 905 if (autosize && reg == 0) { 906 sc->eeprom_size = data; 907 break; 908 } 909 } 910 /* 911 * Shift out data. 912 */ 913 data = 0; 914 reg = FXP_EEPROM_EECS; 915 for (x = 1 << 15; x; x >>= 1) { 916 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 917 DELAY(1); 918 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 919 data |= x; 920 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 921 DELAY(1); 922 } 923 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 924 DELAY(1); 925 926 return (data); 927 } 928 929 static void 930 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 931 { 932 int i; 933 934 /* 935 * Erase/write enable. 936 */ 937 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 938 fxp_eeprom_shiftin(sc, 0x4, 3); 939 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 940 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 941 DELAY(1); 942 /* 943 * Shift in write opcode, address, data. 944 */ 945 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 946 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 947 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 948 fxp_eeprom_shiftin(sc, data, 16); 949 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 950 DELAY(1); 951 /* 952 * Wait for EEPROM to finish up. 953 */ 954 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 955 DELAY(1); 956 for (i = 0; i < 1000; i++) { 957 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 958 break; 959 DELAY(50); 960 } 961 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 962 DELAY(1); 963 /* 964 * Erase/write disable. 965 */ 966 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 967 fxp_eeprom_shiftin(sc, 0x4, 3); 968 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 969 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 970 DELAY(1); 971 } 972 973 /* 974 * From NetBSD: 975 * 976 * Figure out EEPROM size. 977 * 978 * 559's can have either 64-word or 256-word EEPROMs, the 558 979 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 980 * talks about the existance of 16 to 256 word EEPROMs. 981 * 982 * The only known sizes are 64 and 256, where the 256 version is used 983 * by CardBus cards to store CIS information. 984 * 985 * The address is shifted in msb-to-lsb, and after the last 986 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 987 * after which follows the actual data. We try to detect this zero, by 988 * probing the data-out bit in the EEPROM control register just after 989 * having shifted in a bit. If the bit is zero, we assume we've 990 * shifted enough address bits. The data-out should be tri-state, 991 * before this, which should translate to a logical one. 992 */ 993 static void 994 fxp_autosize_eeprom(struct fxp_softc *sc) 995 { 996 997 /* guess maximum size of 256 words */ 998 sc->eeprom_size = 8; 999 1000 /* autosize */ 1001 (void) fxp_eeprom_getword(sc, 0, 1); 1002 } 1003 1004 static void 1005 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1006 { 1007 int i; 1008 1009 for (i = 0; i < words; i++) 1010 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1011 } 1012 1013 static void 1014 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1015 { 1016 int i; 1017 1018 for (i = 0; i < words; i++) 1019 fxp_eeprom_putword(sc, offset + i, data[i]); 1020 } 1021 1022 /* 1023 * Start packet transmission on the interface. 1024 */ 1025 static void 1026 fxp_start(struct ifnet *ifp) 1027 { 1028 struct fxp_softc *sc = ifp->if_softc; 1029 struct fxp_cb_tx *txp; 1030 1031 /* 1032 * See if we need to suspend xmit until the multicast filter 1033 * has been reprogrammed (which can only be done at the head 1034 * of the command chain). 1035 */ 1036 if (sc->need_mcsetup) { 1037 return; 1038 } 1039 1040 txp = NULL; 1041 1042 /* 1043 * We're finished if there is nothing more to add to the list or if 1044 * we're all filled up with buffers to transmit. 1045 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1046 * a NOP command when needed. 1047 */ 1048 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 1049 struct mbuf *m, *mb_head; 1050 int segment; 1051 1052 /* 1053 * Grab a packet to transmit. 1054 */ 1055 IF_DEQUEUE(&ifp->if_snd, mb_head); 1056 1057 /* 1058 * Get pointer to next available tx desc. 1059 */ 1060 txp = sc->cbl_last->next; 1061 1062 /* 1063 * Go through each of the mbufs in the chain and initialize 1064 * the transmit buffer descriptors with the physical address 1065 * and size of the mbuf. 1066 */ 1067 tbdinit: 1068 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 1069 if (m->m_len != 0) { 1070 if (segment == FXP_NTXSEG) 1071 break; 1072 txp->tbd[segment].tb_addr = 1073 vtophys(mtod(m, vm_offset_t)); 1074 txp->tbd[segment].tb_size = m->m_len; 1075 segment++; 1076 } 1077 } 1078 if (m != NULL) { 1079 struct mbuf *mn; 1080 1081 /* 1082 * We ran out of segments. We have to recopy this 1083 * mbuf chain first. Bail out if we can't get the 1084 * new buffers. 1085 */ 1086 MGETHDR(mn, MB_DONTWAIT, MT_DATA); 1087 if (mn == NULL) { 1088 m_freem(mb_head); 1089 break; 1090 } 1091 if (mb_head->m_pkthdr.len > MHLEN) { 1092 MCLGET(mn, MB_DONTWAIT); 1093 if ((mn->m_flags & M_EXT) == 0) { 1094 m_freem(mn); 1095 m_freem(mb_head); 1096 break; 1097 } 1098 } 1099 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1100 mtod(mn, caddr_t)); 1101 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1102 m_freem(mb_head); 1103 mb_head = mn; 1104 goto tbdinit; 1105 } 1106 1107 txp->tbd_number = segment; 1108 txp->mb_head = mb_head; 1109 txp->cb_status = 0; 1110 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1111 txp->cb_command = 1112 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1113 FXP_CB_COMMAND_S; 1114 } else { 1115 txp->cb_command = 1116 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1117 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1118 /* 1119 * Set a 5 second timer just in case we don't hear 1120 * from the card again. 1121 */ 1122 ifp->if_timer = 5; 1123 } 1124 txp->tx_threshold = tx_threshold; 1125 1126 /* 1127 * Advance the end of list forward. 1128 */ 1129 1130 #ifdef __alpha__ 1131 /* 1132 * On platforms which can't access memory in 16-bit 1133 * granularities, we must prevent the card from DMA'ing 1134 * up the status while we update the command field. 1135 * This could cause us to overwrite the completion status. 1136 */ 1137 atomic_clear_short(&sc->cbl_last->cb_command, 1138 FXP_CB_COMMAND_S); 1139 #else 1140 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1141 #endif /*__alpha__*/ 1142 sc->cbl_last = txp; 1143 1144 /* 1145 * Advance the beginning of the list forward if there are 1146 * no other packets queued (when nothing is queued, cbl_first 1147 * sits on the last TxCB that was sent out). 1148 */ 1149 if (sc->tx_queued == 0) 1150 sc->cbl_first = txp; 1151 1152 sc->tx_queued++; 1153 1154 /* 1155 * Pass packet to bpf if there is a listener. 1156 */ 1157 if (ifp->if_bpf) 1158 bpf_mtap(ifp, mb_head); 1159 } 1160 1161 /* 1162 * We're finished. If we added to the list, issue a RESUME to get DMA 1163 * going again if suspended. 1164 */ 1165 if (txp != NULL) { 1166 fxp_scb_wait(sc); 1167 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1168 } 1169 } 1170 1171 #ifdef DEVICE_POLLING 1172 static poll_handler_t fxp_poll; 1173 1174 static void 1175 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1176 { 1177 struct fxp_softc *sc = ifp->if_softc; 1178 u_int8_t statack; 1179 1180 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1181 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1182 return; 1183 } 1184 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1185 FXP_SCB_STATACK_FR; 1186 if (cmd == POLL_AND_CHECK_STATUS) { 1187 u_int8_t tmp; 1188 1189 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1190 if (tmp == 0xff || tmp == 0) 1191 return; /* nothing to do */ 1192 tmp &= ~statack; 1193 /* ack what we can */ 1194 if (tmp != 0) 1195 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1196 statack |= tmp; 1197 } 1198 fxp_intr_body(sc, statack, count); 1199 } 1200 #endif /* DEVICE_POLLING */ 1201 1202 /* 1203 * Process interface interrupts. 1204 */ 1205 static void 1206 fxp_intr(void *xsc) 1207 { 1208 struct fxp_softc *sc = xsc; 1209 u_int8_t statack; 1210 1211 #ifdef DEVICE_POLLING 1212 struct ifnet *ifp = &sc->sc_if; 1213 1214 if (ifp->if_flags & IFF_POLLING) 1215 return; 1216 if (ether_poll_register(fxp_poll, ifp)) { 1217 /* disable interrupts */ 1218 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1219 fxp_poll(ifp, 0, 1); 1220 return; 1221 } 1222 #endif 1223 1224 if (sc->suspended) { 1225 return; 1226 } 1227 1228 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1229 /* 1230 * It should not be possible to have all bits set; the 1231 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1232 * all bits are set, this may indicate that the card has 1233 * been physically ejected, so ignore it. 1234 */ 1235 if (statack == 0xff) 1236 return; 1237 1238 /* 1239 * First ACK all the interrupts in this pass. 1240 */ 1241 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1242 fxp_intr_body(sc, statack, -1); 1243 } 1244 } 1245 1246 static void 1247 fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count) 1248 { 1249 struct ifnet *ifp = &sc->sc_if; 1250 struct mbuf *m; 1251 struct fxp_rfa *rfa; 1252 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1253 1254 if (rnr) 1255 fxp_rnr++; 1256 #ifdef DEVICE_POLLING 1257 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1258 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1259 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1260 rnr = 1; 1261 } 1262 #endif 1263 1264 /* 1265 * Free any finished transmit mbuf chains. 1266 * 1267 * Handle the CNA event likt a CXTNO event. It used to 1268 * be that this event (control unit not ready) was not 1269 * encountered, but it is now with the SMPng modifications. 1270 * The exact sequence of events that occur when the interface 1271 * is brought up are different now, and if this event 1272 * goes unhandled, the configuration/rxfilter setup sequence 1273 * can stall for several seconds. The result is that no 1274 * packets go out onto the wire for about 5 to 10 seconds 1275 * after the interface is ifconfig'ed for the first time. 1276 */ 1277 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1278 struct fxp_cb_tx *txp; 1279 1280 for (txp = sc->cbl_first; sc->tx_queued && 1281 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1282 txp = txp->next) { 1283 if ((m = txp->mb_head) != NULL) { 1284 txp->mb_head = NULL; 1285 sc->tx_queued--; 1286 m_freem(m); 1287 } else { 1288 sc->tx_queued--; 1289 } 1290 } 1291 sc->cbl_first = txp; 1292 ifp->if_timer = 0; 1293 if (sc->tx_queued == 0) { 1294 if (sc->need_mcsetup) 1295 fxp_mc_setup(sc); 1296 } 1297 /* 1298 * Try to start more packets transmitting. 1299 */ 1300 if (ifp->if_snd.ifq_head != NULL) 1301 fxp_start(ifp); 1302 } 1303 1304 /* 1305 * Just return if nothing happened on the receive side. 1306 */ 1307 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1308 return; 1309 1310 /* 1311 * Process receiver interrupts. If a no-resource (RNR) 1312 * condition exists, get whatever packets we can and 1313 * re-start the receiver. 1314 * 1315 * When using polling, we do not process the list to completion, 1316 * so when we get an RNR interrupt we must defer the restart 1317 * until we hit the last buffer with the C bit set. 1318 * If we run out of cycles and rfa_headm has the C bit set, 1319 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1320 * that the info will be used in the subsequent polling cycle. 1321 */ 1322 for (;;) { 1323 m = sc->rfa_headm; 1324 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1325 RFA_ALIGNMENT_FUDGE); 1326 1327 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1328 if (count >= 0 && count-- == 0) { 1329 if (rnr) { 1330 /* Defer RNR processing until the next time. */ 1331 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1332 rnr = 0; 1333 } 1334 break; 1335 } 1336 #endif /* DEVICE_POLLING */ 1337 1338 if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0) 1339 break; 1340 1341 /* 1342 * Remove first packet from the chain. 1343 */ 1344 sc->rfa_headm = m->m_next; 1345 m->m_next = NULL; 1346 1347 /* 1348 * Add a new buffer to the receive chain. 1349 * If this fails, the old buffer is recycled 1350 * instead. 1351 */ 1352 if (fxp_add_rfabuf(sc, m) == 0) { 1353 int total_len; 1354 1355 /* 1356 * Fetch packet length (the top 2 bits of 1357 * actual_size are flags set by the controller 1358 * upon completion), and drop the packet in case 1359 * of bogus length or CRC errors. 1360 */ 1361 total_len = rfa->actual_size & 0x3fff; 1362 if (total_len < sizeof(struct ether_header) || 1363 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1364 sizeof(struct fxp_rfa) || 1365 rfa->rfa_status & FXP_RFA_STATUS_CRC) { 1366 m_freem(m); 1367 continue; 1368 } 1369 m->m_pkthdr.len = m->m_len = total_len; 1370 (*ifp->if_input)(ifp, m); 1371 } 1372 } 1373 if (rnr) { 1374 fxp_scb_wait(sc); 1375 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1376 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1377 RFA_ALIGNMENT_FUDGE); 1378 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1379 } 1380 } 1381 1382 /* 1383 * Update packet in/out/collision statistics. The i82557 doesn't 1384 * allow you to access these counters without doing a fairly 1385 * expensive DMA to get _all_ of the statistics it maintains, so 1386 * we do this operation here only once per second. The statistics 1387 * counters in the kernel are updated from the previous dump-stats 1388 * DMA and then a new dump-stats DMA is started. The on-chip 1389 * counters are zeroed when the DMA completes. If we can't start 1390 * the DMA immediately, we don't wait - we just prepare to read 1391 * them again next time. 1392 */ 1393 static void 1394 fxp_tick(void *xsc) 1395 { 1396 struct fxp_softc *sc = xsc; 1397 struct ifnet *ifp = &sc->sc_if; 1398 struct fxp_stats *sp = sc->fxp_stats; 1399 struct fxp_cb_tx *txp; 1400 struct mbuf *m; 1401 int s; 1402 1403 ifp->if_opackets += sp->tx_good; 1404 ifp->if_collisions += sp->tx_total_collisions; 1405 if (sp->rx_good) { 1406 ifp->if_ipackets += sp->rx_good; 1407 sc->rx_idle_secs = 0; 1408 } else { 1409 /* 1410 * Receiver's been idle for another second. 1411 */ 1412 sc->rx_idle_secs++; 1413 } 1414 ifp->if_ierrors += 1415 sp->rx_crc_errors + 1416 sp->rx_alignment_errors + 1417 sp->rx_rnr_errors + 1418 sp->rx_overrun_errors; 1419 /* 1420 * If any transmit underruns occured, bump up the transmit 1421 * threshold by another 512 bytes (64 * 8). 1422 */ 1423 if (sp->tx_underruns) { 1424 ifp->if_oerrors += sp->tx_underruns; 1425 if (tx_threshold < 192) 1426 tx_threshold += 64; 1427 } 1428 s = splimp(); 1429 /* 1430 * Release any xmit buffers that have completed DMA. This isn't 1431 * strictly necessary to do here, but it's advantagous for mbufs 1432 * with external storage to be released in a timely manner rather 1433 * than being defered for a potentially long time. This limits 1434 * the delay to a maximum of one second. 1435 */ 1436 for (txp = sc->cbl_first; sc->tx_queued && 1437 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1438 txp = txp->next) { 1439 if ((m = txp->mb_head) != NULL) { 1440 txp->mb_head = NULL; 1441 sc->tx_queued--; 1442 m_freem(m); 1443 } else { 1444 sc->tx_queued--; 1445 } 1446 } 1447 sc->cbl_first = txp; 1448 /* 1449 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1450 * then assume the receiver has locked up and attempt to clear 1451 * the condition by reprogramming the multicast filter. This is 1452 * a work-around for a bug in the 82557 where the receiver locks 1453 * up if it gets certain types of garbage in the syncronization 1454 * bits prior to the packet header. This bug is supposed to only 1455 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1456 * mode as well (perhaps due to a 10/100 speed transition). 1457 */ 1458 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1459 sc->rx_idle_secs = 0; 1460 fxp_mc_setup(sc); 1461 } 1462 /* 1463 * If there is no pending command, start another stats 1464 * dump. Otherwise punt for now. 1465 */ 1466 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1467 /* 1468 * Start another stats dump. 1469 */ 1470 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1471 } else { 1472 /* 1473 * A previous command is still waiting to be accepted. 1474 * Just zero our copy of the stats and wait for the 1475 * next timer event to update them. 1476 */ 1477 sp->tx_good = 0; 1478 sp->tx_underruns = 0; 1479 sp->tx_total_collisions = 0; 1480 1481 sp->rx_good = 0; 1482 sp->rx_crc_errors = 0; 1483 sp->rx_alignment_errors = 0; 1484 sp->rx_rnr_errors = 0; 1485 sp->rx_overrun_errors = 0; 1486 } 1487 if (sc->miibus != NULL) 1488 mii_tick(device_get_softc(sc->miibus)); 1489 splx(s); 1490 /* 1491 * Schedule another timeout one second from now. 1492 */ 1493 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc); 1494 } 1495 1496 /* 1497 * Stop the interface. Cancels the statistics updater and resets 1498 * the interface. 1499 */ 1500 static void 1501 fxp_stop(struct fxp_softc *sc) 1502 { 1503 struct ifnet *ifp = &sc->sc_if; 1504 struct fxp_cb_tx *txp; 1505 int i; 1506 1507 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1508 ifp->if_timer = 0; 1509 1510 #ifdef DEVICE_POLLING 1511 ether_poll_deregister(ifp); 1512 #endif 1513 /* 1514 * Cancel stats updater. 1515 */ 1516 callout_stop(&sc->fxp_stat_timer); 1517 1518 /* 1519 * Issue software reset, which also unloads the microcode. 1520 */ 1521 sc->flags &= ~FXP_FLAG_UCODE; 1522 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1523 DELAY(50); 1524 1525 /* 1526 * Release any xmit buffers. 1527 */ 1528 txp = sc->cbl_base; 1529 if (txp != NULL) { 1530 for (i = 0; i < FXP_NTXCB; i++) { 1531 if (txp[i].mb_head != NULL) { 1532 m_freem(txp[i].mb_head); 1533 txp[i].mb_head = NULL; 1534 } 1535 } 1536 } 1537 sc->tx_queued = 0; 1538 1539 /* 1540 * Free all the receive buffers then reallocate/reinitialize 1541 */ 1542 if (sc->rfa_headm != NULL) 1543 m_freem(sc->rfa_headm); 1544 sc->rfa_headm = NULL; 1545 sc->rfa_tailm = NULL; 1546 for (i = 0; i < FXP_NRFABUFS; i++) { 1547 if (fxp_add_rfabuf(sc, NULL) != 0) { 1548 /* 1549 * This "can't happen" - we're at splimp() 1550 * and we just freed all the buffers we need 1551 * above. 1552 */ 1553 panic("fxp_stop: no buffers!"); 1554 } 1555 } 1556 } 1557 1558 /* 1559 * Watchdog/transmission transmit timeout handler. Called when a 1560 * transmission is started on the interface, but no interrupt is 1561 * received before the timeout. This usually indicates that the 1562 * card has wedged for some reason. 1563 */ 1564 static void 1565 fxp_watchdog(struct ifnet *ifp) 1566 { 1567 struct fxp_softc *sc = ifp->if_softc; 1568 1569 device_printf(sc->dev, "device timeout\n"); 1570 ifp->if_oerrors++; 1571 1572 fxp_init(sc); 1573 } 1574 1575 static void 1576 fxp_init(void *xsc) 1577 { 1578 struct fxp_softc *sc = xsc; 1579 struct ifnet *ifp = &sc->sc_if; 1580 struct fxp_cb_config *cbp; 1581 struct fxp_cb_ias *cb_ias; 1582 struct fxp_cb_tx *txp; 1583 struct fxp_cb_mcs *mcsp; 1584 int i, prm, s; 1585 1586 s = splimp(); 1587 /* 1588 * Cancel any pending I/O 1589 */ 1590 fxp_stop(sc); 1591 1592 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1593 1594 /* 1595 * Initialize base of CBL and RFA memory. Loading with zero 1596 * sets it up for regular linear addressing. 1597 */ 1598 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1599 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1600 1601 fxp_scb_wait(sc); 1602 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1603 1604 /* 1605 * Initialize base of dump-stats buffer. 1606 */ 1607 fxp_scb_wait(sc); 1608 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1609 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1610 1611 /* 1612 * Attempt to load microcode if requested. 1613 */ 1614 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1615 fxp_load_ucode(sc); 1616 1617 /* 1618 * Initialize the multicast address list. 1619 */ 1620 if (fxp_mc_addrs(sc)) { 1621 mcsp = sc->mcsp; 1622 mcsp->cb_status = 0; 1623 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL; 1624 mcsp->link_addr = -1; 1625 /* 1626 * Start the multicast setup command. 1627 */ 1628 fxp_scb_wait(sc); 1629 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 1630 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1631 /* ...and wait for it to complete. */ 1632 fxp_dma_wait(&mcsp->cb_status, sc); 1633 } 1634 1635 /* 1636 * We temporarily use memory that contains the TxCB list to 1637 * construct the config CB. The TxCB list memory is rebuilt 1638 * later. 1639 */ 1640 cbp = (struct fxp_cb_config *) sc->cbl_base; 1641 1642 /* 1643 * This bcopy is kind of disgusting, but there are a bunch of must be 1644 * zero and must be one bits in this structure and this is the easiest 1645 * way to initialize them all to proper values. 1646 */ 1647 bcopy(fxp_cb_config_template, 1648 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1649 sizeof(fxp_cb_config_template)); 1650 1651 cbp->cb_status = 0; 1652 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1653 cbp->link_addr = -1; /* (no) next command */ 1654 cbp->byte_count = 22; /* (22) bytes to config */ 1655 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1656 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1657 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1658 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1659 cbp->type_enable = 0; /* actually reserved */ 1660 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1661 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1662 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1663 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1664 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1665 cbp->late_scb = 0; /* (don't) defer SCB update */ 1666 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 1667 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1668 cbp->ci_int = 1; /* interrupt on CU idle */ 1669 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 1670 cbp->ext_stats_dis = 1; /* disable extended counters */ 1671 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1672 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 1673 cbp->disc_short_rx = !prm; /* discard short packets */ 1674 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 1675 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1676 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1677 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 1678 cbp->csma_dis = 0; /* (don't) disable link */ 1679 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1680 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1681 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1682 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1683 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 1684 cbp->nsai = 1; /* (don't) disable source addr insert */ 1685 cbp->preamble_length = 2; /* (7 byte) preamble */ 1686 cbp->loopback = 0; /* (don't) loopback */ 1687 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1688 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1689 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1690 cbp->promiscuous = prm; /* promiscuous mode */ 1691 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1692 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1693 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1694 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1695 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 1696 1697 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1698 cbp->padding = 1; /* (do) pad short tx packets */ 1699 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1700 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 1701 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1702 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1703 /* must set wake_en in PMCSR also */ 1704 cbp->force_fdx = 0; /* (don't) force full duplex */ 1705 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1706 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1707 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 1708 1709 if (sc->revision == FXP_REV_82557) { 1710 /* 1711 * The 82557 has no hardware flow control, the values 1712 * below are the defaults for the chip. 1713 */ 1714 cbp->fc_delay_lsb = 0; 1715 cbp->fc_delay_msb = 0x40; 1716 cbp->pri_fc_thresh = 3; 1717 cbp->tx_fc_dis = 0; 1718 cbp->rx_fc_restop = 0; 1719 cbp->rx_fc_restart = 0; 1720 cbp->fc_filter = 0; 1721 cbp->pri_fc_loc = 1; 1722 } else { 1723 cbp->fc_delay_lsb = 0x1f; 1724 cbp->fc_delay_msb = 0x01; 1725 cbp->pri_fc_thresh = 3; 1726 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1727 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1728 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1729 cbp->fc_filter = !prm; /* drop FC frames to host */ 1730 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1731 } 1732 1733 /* 1734 * Start the config command/DMA. 1735 */ 1736 fxp_scb_wait(sc); 1737 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1738 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1739 /* ...and wait for it to complete. */ 1740 fxp_dma_wait(&cbp->cb_status, sc); 1741 1742 /* 1743 * Now initialize the station address. Temporarily use the TxCB 1744 * memory area like we did above for the config CB. 1745 */ 1746 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1747 cb_ias->cb_status = 0; 1748 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1749 cb_ias->link_addr = -1; 1750 bcopy(sc->arpcom.ac_enaddr, 1751 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1752 sizeof(sc->arpcom.ac_enaddr)); 1753 1754 /* 1755 * Start the IAS (Individual Address Setup) command/DMA. 1756 */ 1757 fxp_scb_wait(sc); 1758 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1759 /* ...and wait for it to complete. */ 1760 fxp_dma_wait(&cb_ias->cb_status, sc); 1761 1762 /* 1763 * Initialize transmit control block (TxCB) list. 1764 */ 1765 1766 txp = sc->cbl_base; 1767 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1768 for (i = 0; i < FXP_NTXCB; i++) { 1769 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1770 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1771 txp[i].link_addr = 1772 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1773 if (sc->flags & FXP_FLAG_EXT_TXCB) 1774 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]); 1775 else 1776 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1777 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1778 } 1779 /* 1780 * Set the suspend flag on the first TxCB and start the control 1781 * unit. It will execute the NOP and then suspend. 1782 */ 1783 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1784 sc->cbl_first = sc->cbl_last = txp; 1785 sc->tx_queued = 1; 1786 1787 fxp_scb_wait(sc); 1788 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1789 1790 /* 1791 * Initialize receiver buffer area - RFA. 1792 */ 1793 fxp_scb_wait(sc); 1794 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1795 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1796 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1797 1798 /* 1799 * Set current media. 1800 */ 1801 if (sc->miibus != NULL) 1802 mii_mediachg(device_get_softc(sc->miibus)); 1803 1804 ifp->if_flags |= IFF_RUNNING; 1805 ifp->if_flags &= ~IFF_OACTIVE; 1806 1807 /* 1808 * Enable interrupts. 1809 */ 1810 #ifdef DEVICE_POLLING 1811 /* 1812 * ... but only do that if we are not polling. And because (presumably) 1813 * the default is interrupts on, we need to disable them explicitly! 1814 */ 1815 if ( ifp->if_flags & IFF_POLLING ) 1816 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1817 else 1818 #endif /* DEVICE_POLLING */ 1819 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1820 splx(s); 1821 1822 /* 1823 * Start stats updater. 1824 */ 1825 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc); 1826 } 1827 1828 static int 1829 fxp_serial_ifmedia_upd(struct ifnet *ifp) 1830 { 1831 1832 return (0); 1833 } 1834 1835 static void 1836 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1837 { 1838 1839 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 1840 } 1841 1842 /* 1843 * Change media according to request. 1844 */ 1845 static int 1846 fxp_ifmedia_upd(struct ifnet *ifp) 1847 { 1848 struct fxp_softc *sc = ifp->if_softc; 1849 struct mii_data *mii; 1850 1851 mii = device_get_softc(sc->miibus); 1852 mii_mediachg(mii); 1853 return (0); 1854 } 1855 1856 /* 1857 * Notify the world which media we're using. 1858 */ 1859 static void 1860 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1861 { 1862 struct fxp_softc *sc = ifp->if_softc; 1863 struct mii_data *mii; 1864 1865 mii = device_get_softc(sc->miibus); 1866 mii_pollstat(mii); 1867 ifmr->ifm_active = mii->mii_media_active; 1868 ifmr->ifm_status = mii->mii_media_status; 1869 1870 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 1871 sc->cu_resume_bug = 1; 1872 else 1873 sc->cu_resume_bug = 0; 1874 } 1875 1876 /* 1877 * Add a buffer to the end of the RFA buffer list. 1878 * Return 0 if successful, 1 for failure. A failure results in 1879 * adding the 'oldm' (if non-NULL) on to the end of the list - 1880 * tossing out its old contents and recycling it. 1881 * The RFA struct is stuck at the beginning of mbuf cluster and the 1882 * data pointer is fixed up to point just past it. 1883 */ 1884 static int 1885 fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm) 1886 { 1887 u_int32_t v; 1888 struct mbuf *m; 1889 struct fxp_rfa *rfa, *p_rfa; 1890 1891 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1892 if (m == NULL) { /* try to recycle the old mbuf instead */ 1893 if (oldm == NULL) 1894 return 1; 1895 m = oldm; 1896 m->m_data = m->m_ext.ext_buf; 1897 } 1898 1899 /* 1900 * Move the data pointer up so that the incoming data packet 1901 * will be 32-bit aligned. 1902 */ 1903 m->m_data += RFA_ALIGNMENT_FUDGE; 1904 1905 /* 1906 * Get a pointer to the base of the mbuf cluster and move 1907 * data start past it. 1908 */ 1909 rfa = mtod(m, struct fxp_rfa *); 1910 m->m_data += sizeof(struct fxp_rfa); 1911 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); 1912 1913 /* 1914 * Initialize the rest of the RFA. Note that since the RFA 1915 * is misaligned, we cannot store values directly. Instead, 1916 * we use an optimized, inline copy. 1917 */ 1918 1919 rfa->rfa_status = 0; 1920 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1921 rfa->actual_size = 0; 1922 1923 v = -1; 1924 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 1925 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 1926 1927 /* 1928 * If there are other buffers already on the list, attach this 1929 * one to the end by fixing up the tail to point to this one. 1930 */ 1931 if (sc->rfa_headm != NULL) { 1932 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 1933 RFA_ALIGNMENT_FUDGE); 1934 sc->rfa_tailm->m_next = m; 1935 v = vtophys(rfa); 1936 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 1937 p_rfa->rfa_control = 0; 1938 } else { 1939 sc->rfa_headm = m; 1940 } 1941 sc->rfa_tailm = m; 1942 1943 return (m == oldm); 1944 } 1945 1946 static volatile int 1947 fxp_miibus_readreg(device_t dev, int phy, int reg) 1948 { 1949 struct fxp_softc *sc = device_get_softc(dev); 1950 int count = 10000; 1951 int value; 1952 1953 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1954 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1955 1956 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1957 && count--) 1958 DELAY(10); 1959 1960 if (count <= 0) 1961 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 1962 1963 return (value & 0xffff); 1964 } 1965 1966 static void 1967 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 1968 { 1969 struct fxp_softc *sc = device_get_softc(dev); 1970 int count = 10000; 1971 1972 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1973 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1974 (value & 0xffff)); 1975 1976 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1977 count--) 1978 DELAY(10); 1979 1980 if (count <= 0) 1981 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 1982 } 1983 1984 static int 1985 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1986 { 1987 struct fxp_softc *sc = ifp->if_softc; 1988 struct ifreq *ifr = (struct ifreq *)data; 1989 struct mii_data *mii; 1990 int s, error = 0; 1991 1992 s = splimp(); 1993 1994 switch (command) { 1995 case SIOCSIFADDR: 1996 case SIOCGIFADDR: 1997 case SIOCSIFMTU: 1998 error = ether_ioctl(ifp, command, data); 1999 break; 2000 2001 case SIOCSIFFLAGS: 2002 if (ifp->if_flags & IFF_ALLMULTI) 2003 sc->flags |= FXP_FLAG_ALL_MCAST; 2004 else 2005 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2006 2007 /* 2008 * If interface is marked up and not running, then start it. 2009 * If it is marked down and running, stop it. 2010 * XXX If it's up then re-initialize it. This is so flags 2011 * such as IFF_PROMISC are handled. 2012 */ 2013 if (ifp->if_flags & IFF_UP) { 2014 fxp_init(sc); 2015 } else { 2016 if (ifp->if_flags & IFF_RUNNING) 2017 fxp_stop(sc); 2018 } 2019 break; 2020 2021 case SIOCADDMULTI: 2022 case SIOCDELMULTI: 2023 if (ifp->if_flags & IFF_ALLMULTI) 2024 sc->flags |= FXP_FLAG_ALL_MCAST; 2025 else 2026 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2027 /* 2028 * Multicast list has changed; set the hardware filter 2029 * accordingly. 2030 */ 2031 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2032 fxp_mc_setup(sc); 2033 /* 2034 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2035 * again rather than else {}. 2036 */ 2037 if (sc->flags & FXP_FLAG_ALL_MCAST) 2038 fxp_init(sc); 2039 error = 0; 2040 break; 2041 2042 case SIOCSIFMEDIA: 2043 case SIOCGIFMEDIA: 2044 if (sc->miibus != NULL) { 2045 mii = device_get_softc(sc->miibus); 2046 error = ifmedia_ioctl(ifp, ifr, 2047 &mii->mii_media, command); 2048 } else { 2049 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2050 } 2051 break; 2052 2053 default: 2054 error = EINVAL; 2055 } 2056 splx(s); 2057 return (error); 2058 } 2059 2060 /* 2061 * Fill in the multicast address list and return number of entries. 2062 */ 2063 static int 2064 fxp_mc_addrs(struct fxp_softc *sc) 2065 { 2066 struct fxp_cb_mcs *mcsp = sc->mcsp; 2067 struct ifnet *ifp = &sc->sc_if; 2068 struct ifmultiaddr *ifma; 2069 int nmcasts; 2070 2071 nmcasts = 0; 2072 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2073 #if defined(__DragonFly__) || __FreeBSD_version < 500000 2074 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2075 #else 2076 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2077 #endif 2078 if (ifma->ifma_addr->sa_family != AF_LINK) 2079 continue; 2080 if (nmcasts >= MAXMCADDR) { 2081 sc->flags |= FXP_FLAG_ALL_MCAST; 2082 nmcasts = 0; 2083 break; 2084 } 2085 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2086 (void *)(uintptr_t)(volatile void *) 2087 &sc->mcsp->mc_addr[nmcasts][0], 6); 2088 nmcasts++; 2089 } 2090 } 2091 mcsp->mc_cnt = nmcasts * 6; 2092 return (nmcasts); 2093 } 2094 2095 /* 2096 * Program the multicast filter. 2097 * 2098 * We have an artificial restriction that the multicast setup command 2099 * must be the first command in the chain, so we take steps to ensure 2100 * this. By requiring this, it allows us to keep up the performance of 2101 * the pre-initialized command ring (esp. link pointers) by not actually 2102 * inserting the mcsetup command in the ring - i.e. its link pointer 2103 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2104 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2105 * lead into the regular TxCB ring when it completes. 2106 * 2107 * This function must be called at splimp. 2108 */ 2109 static void 2110 fxp_mc_setup(struct fxp_softc *sc) 2111 { 2112 struct fxp_cb_mcs *mcsp = sc->mcsp; 2113 struct ifnet *ifp = &sc->sc_if; 2114 int count; 2115 2116 /* 2117 * If there are queued commands, we must wait until they are all 2118 * completed. If we are already waiting, then add a NOP command 2119 * with interrupt option so that we're notified when all commands 2120 * have been completed - fxp_start() ensures that no additional 2121 * TX commands will be added when need_mcsetup is true. 2122 */ 2123 if (sc->tx_queued) { 2124 struct fxp_cb_tx *txp; 2125 2126 /* 2127 * need_mcsetup will be true if we are already waiting for the 2128 * NOP command to be completed (see below). In this case, bail. 2129 */ 2130 if (sc->need_mcsetup) 2131 return; 2132 sc->need_mcsetup = 1; 2133 2134 /* 2135 * Add a NOP command with interrupt so that we are notified 2136 * when all TX commands have been processed. 2137 */ 2138 txp = sc->cbl_last->next; 2139 txp->mb_head = NULL; 2140 txp->cb_status = 0; 2141 txp->cb_command = FXP_CB_COMMAND_NOP | 2142 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2143 /* 2144 * Advance the end of list forward. 2145 */ 2146 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 2147 sc->cbl_last = txp; 2148 sc->tx_queued++; 2149 /* 2150 * Issue a resume in case the CU has just suspended. 2151 */ 2152 fxp_scb_wait(sc); 2153 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2154 /* 2155 * Set a 5 second timer just in case we don't hear from the 2156 * card again. 2157 */ 2158 ifp->if_timer = 5; 2159 2160 return; 2161 } 2162 sc->need_mcsetup = 0; 2163 2164 /* 2165 * Initialize multicast setup descriptor. 2166 */ 2167 mcsp->next = sc->cbl_base; 2168 mcsp->mb_head = NULL; 2169 mcsp->cb_status = 0; 2170 mcsp->cb_command = FXP_CB_COMMAND_MCAS | 2171 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2172 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 2173 (void) fxp_mc_addrs(sc); 2174 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 2175 sc->tx_queued = 1; 2176 2177 /* 2178 * Wait until command unit is not active. This should never 2179 * be the case when nothing is queued, but make sure anyway. 2180 */ 2181 count = 100; 2182 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2183 FXP_SCB_CUS_ACTIVE && --count) 2184 DELAY(10); 2185 if (count == 0) { 2186 device_printf(sc->dev, "command queue timeout\n"); 2187 return; 2188 } 2189 2190 /* 2191 * Start the multicast setup command. 2192 */ 2193 fxp_scb_wait(sc); 2194 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 2195 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2196 2197 ifp->if_timer = 2; 2198 return; 2199 } 2200 2201 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2202 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2203 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2204 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2205 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2206 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2207 2208 #define UCODE(x) x, sizeof(x) 2209 2210 struct ucode { 2211 u_int32_t revision; 2212 u_int32_t *ucode; 2213 int length; 2214 u_short int_delay_offset; 2215 u_short bundle_max_offset; 2216 } ucode_table[] = { 2217 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2218 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2219 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2220 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2221 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2222 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2223 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2224 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2225 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2226 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2227 { 0, NULL, 0, 0, 0 } 2228 }; 2229 2230 static void 2231 fxp_load_ucode(struct fxp_softc *sc) 2232 { 2233 struct ucode *uc; 2234 struct fxp_cb_ucode *cbp; 2235 2236 for (uc = ucode_table; uc->ucode != NULL; uc++) 2237 if (sc->revision == uc->revision) 2238 break; 2239 if (uc->ucode == NULL) 2240 return; 2241 cbp = (struct fxp_cb_ucode *)sc->cbl_base; 2242 cbp->cb_status = 0; 2243 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL; 2244 cbp->link_addr = -1; /* (no) next command */ 2245 memcpy(cbp->ucode, uc->ucode, uc->length); 2246 if (uc->int_delay_offset) 2247 *(u_short *)&cbp->ucode[uc->int_delay_offset] = 2248 sc->tunable_int_delay + sc->tunable_int_delay / 2; 2249 if (uc->bundle_max_offset) 2250 *(u_short *)&cbp->ucode[uc->bundle_max_offset] = 2251 sc->tunable_bundle_max; 2252 /* 2253 * Download the ucode to the chip. 2254 */ 2255 fxp_scb_wait(sc); 2256 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 2257 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2258 /* ...and wait for it to complete. */ 2259 fxp_dma_wait(&cbp->cb_status, sc); 2260 device_printf(sc->dev, 2261 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2262 sc->tunable_int_delay, 2263 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2264 sc->flags |= FXP_FLAG_UCODE; 2265 } 2266 2267 static int 2268 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2269 { 2270 int error, value; 2271 2272 value = *(int *)arg1; 2273 error = sysctl_handle_int(oidp, &value, 0, req); 2274 if (error || !req->newptr) 2275 return (error); 2276 if (value < low || value > high) 2277 return (EINVAL); 2278 *(int *)arg1 = value; 2279 return (0); 2280 } 2281 2282 /* 2283 * Interrupt delay is expressed in microseconds, a multiplier is used 2284 * to convert this to the appropriate clock ticks before using. 2285 */ 2286 static int 2287 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2288 { 2289 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2290 } 2291 2292 static int 2293 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2294 { 2295 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2296 } 2297