1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.110.2.30 2003/06/12 16:47:05 mux Exp $ 29 */ 30 31 /* 32 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 33 */ 34 35 #include "opt_ifpoll.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/mbuf.h> 40 #include <sys/malloc.h> 41 #include <sys/kernel.h> 42 #include <sys/interrupt.h> 43 #include <sys/socket.h> 44 #include <sys/sysctl.h> 45 #include <sys/thread2.h> 46 47 #include <net/if.h> 48 #include <net/ifq_var.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 52 #include <net/bpf.h> 53 #include <sys/sockio.h> 54 #include <sys/bus.h> 55 #include <sys/rman.h> 56 57 #include <net/ethernet.h> 58 #include <net/if_arp.h> 59 #include <net/if_poll.h> 60 61 #include <vm/vm.h> /* for vtophys */ 62 #include <vm/pmap.h> /* for vtophys */ 63 64 #include <net/if_types.h> 65 #include <net/vlan/if_vlan_var.h> 66 67 #include <bus/pci/pcivar.h> 68 #include <bus/pci/pcireg.h> /* for PCIM_CMD_xxx */ 69 70 #include "../mii_layer/mii.h" 71 #include "../mii_layer/miivar.h" 72 73 #include "if_fxpreg.h" 74 #include "if_fxpvar.h" 75 #include "rcvbundl.h" 76 77 #include "miibus_if.h" 78 79 /* 80 * NOTE! On the Alpha, we have an alignment constraint. The 81 * card DMAs the packet immediately following the RFA. However, 82 * the first thing in the packet is a 14-byte Ethernet header. 83 * This means that the packet is misaligned. To compensate, 84 * we actually offset the RFA 2 bytes into the cluster. This 85 * alignes the packet after the Ethernet header at a 32-bit 86 * boundary. HOWEVER! This means that the RFA is misaligned! 87 */ 88 #define RFA_ALIGNMENT_FUDGE 2 89 90 /* 91 * Set initial transmit threshold at 64 (512 bytes). This is 92 * increased by 64 (512 bytes) at a time, to maximum of 192 93 * (1536 bytes), if an underrun occurs. 94 */ 95 static int tx_threshold = 64; 96 97 /* 98 * The configuration byte map has several undefined fields which 99 * must be one or must be zero. Set up a template for these bits 100 * only, (assuming a 82557 chip) leaving the actual configuration 101 * to fxp_init. 102 * 103 * See struct fxp_cb_config for the bit definitions. 104 */ 105 static u_char fxp_cb_config_template[] = { 106 0x0, 0x0, /* cb_status */ 107 0x0, 0x0, /* cb_command */ 108 0x0, 0x0, 0x0, 0x0, /* link_addr */ 109 0x0, /* 0 */ 110 0x0, /* 1 */ 111 0x0, /* 2 */ 112 0x0, /* 3 */ 113 0x0, /* 4 */ 114 0x0, /* 5 */ 115 0x32, /* 6 */ 116 0x0, /* 7 */ 117 0x0, /* 8 */ 118 0x0, /* 9 */ 119 0x6, /* 10 */ 120 0x0, /* 11 */ 121 0x0, /* 12 */ 122 0x0, /* 13 */ 123 0xf2, /* 14 */ 124 0x48, /* 15 */ 125 0x0, /* 16 */ 126 0x40, /* 17 */ 127 0xf0, /* 18 */ 128 0x0, /* 19 */ 129 0x3f, /* 20 */ 130 0x5 /* 21 */ 131 }; 132 133 struct fxp_ident { 134 u_int16_t devid; 135 int16_t revid; /* -1 matches anything */ 136 char *name; 137 }; 138 139 /* 140 * Claim various Intel PCI device identifiers for this driver. The 141 * sub-vendor and sub-device field are extensively used to identify 142 * particular variants, but we don't currently differentiate between 143 * them. 144 */ 145 static struct fxp_ident fxp_ident_table[] = { 146 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 147 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 148 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 149 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 150 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 151 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 152 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 153 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 154 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 155 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 156 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 157 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 158 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 159 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 160 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 161 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 162 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 163 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 164 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 165 { 0x1064, -1, "Intel 82562ET/EZ/GT/GZ (ICH6/ICH6R) Pro/100 VE Ethernet" }, 166 { 0x1065, -1, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" }, 167 { 0x1068, -1, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" }, 168 { 0x1069, -1, "Intel 82562EM/EX/GX Pro/100 Ethernet" }, 169 { 0x1091, -1, "Intel 82562GX Pro/100 Ethernet" }, 170 { 0x1092, -1, "Intel Pro/100 VE Network Connection" }, 171 { 0x1093, -1, "Intel Pro/100 VM Network Connection" }, 172 { 0x1094, -1, "Intel Pro/100 946GZ (ICH7) Network Connection" }, 173 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 174 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 175 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 176 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 177 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 178 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 179 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 180 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 181 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 182 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 183 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 184 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 185 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 186 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 187 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 188 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 189 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 190 { 0x27dc, -1, "Intel 82801GB (ICH7) 10/100 Ethernet" }, 191 { 0, -1, NULL }, 192 }; 193 194 static int fxp_probe(device_t dev); 195 static int fxp_attach(device_t dev); 196 static int fxp_detach(device_t dev); 197 static int fxp_shutdown(device_t dev); 198 static int fxp_suspend(device_t dev); 199 static int fxp_resume(device_t dev); 200 201 static void fxp_intr(void *xsc); 202 static void fxp_intr_body(struct fxp_softc *sc, 203 u_int8_t statack, int count); 204 205 static void fxp_init(void *xsc); 206 static void fxp_tick(void *xsc); 207 static void fxp_powerstate_d0(device_t dev); 208 static void fxp_start(struct ifnet *ifp, struct ifaltq_subque *); 209 static void fxp_stop(struct fxp_softc *sc); 210 static void fxp_release(device_t dev); 211 static int fxp_ioctl(struct ifnet *ifp, u_long command, 212 caddr_t data, struct ucred *); 213 static void fxp_watchdog(struct ifnet *ifp); 214 static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm); 215 static int fxp_mc_addrs(struct fxp_softc *sc); 216 static void fxp_mc_setup(struct fxp_softc *sc); 217 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 218 int autosize); 219 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 220 u_int16_t data); 221 static void fxp_autosize_eeprom(struct fxp_softc *sc); 222 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 223 int offset, int words); 224 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 225 int offset, int words); 226 static int fxp_ifmedia_upd(struct ifnet *ifp); 227 static void fxp_ifmedia_sts(struct ifnet *ifp, 228 struct ifmediareq *ifmr); 229 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 230 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 231 struct ifmediareq *ifmr); 232 static int fxp_miibus_readreg(device_t dev, int phy, int reg); 233 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 234 int value); 235 static void fxp_load_ucode(struct fxp_softc *sc); 236 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 237 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 238 #ifdef IFPOLL_ENABLE 239 static void fxp_npoll(struct ifnet *, struct ifpoll_info *); 240 static void fxp_npoll_compat(struct ifnet *, void *, int); 241 #endif 242 243 static void fxp_lwcopy(volatile u_int32_t *src, 244 volatile u_int32_t *dst); 245 static void fxp_scb_wait(struct fxp_softc *sc); 246 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 247 static void fxp_dma_wait(volatile u_int16_t *status, 248 struct fxp_softc *sc); 249 250 static device_method_t fxp_methods[] = { 251 /* Device interface */ 252 DEVMETHOD(device_probe, fxp_probe), 253 DEVMETHOD(device_attach, fxp_attach), 254 DEVMETHOD(device_detach, fxp_detach), 255 DEVMETHOD(device_shutdown, fxp_shutdown), 256 DEVMETHOD(device_suspend, fxp_suspend), 257 DEVMETHOD(device_resume, fxp_resume), 258 259 /* MII interface */ 260 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 261 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 262 263 DEVMETHOD_END 264 }; 265 266 static driver_t fxp_driver = { 267 "fxp", 268 fxp_methods, 269 sizeof(struct fxp_softc), 270 }; 271 272 static devclass_t fxp_devclass; 273 274 DECLARE_DUMMY_MODULE(if_fxp); 275 MODULE_DEPEND(if_fxp, miibus, 1, 1, 1); 276 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, NULL, NULL); 277 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, NULL, NULL); 278 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, NULL, NULL); 279 280 static int fxp_rnr; 281 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 282 283 /* 284 * Copy a 16-bit aligned 32-bit quantity. 285 */ 286 static void 287 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst) 288 { 289 #ifdef __i386__ 290 *dst = *src; 291 #else 292 volatile u_int16_t *a = (volatile u_int16_t *)src; 293 volatile u_int16_t *b = (volatile u_int16_t *)dst; 294 295 b[0] = a[0]; 296 b[1] = a[1]; 297 #endif 298 } 299 300 /* 301 * Wait for the previous command to be accepted (but not necessarily 302 * completed). 303 */ 304 static void 305 fxp_scb_wait(struct fxp_softc *sc) 306 { 307 int i = 10000; 308 309 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 310 DELAY(2); 311 if (i == 0) { 312 if_printf(&sc->arpcom.ac_if, 313 "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 314 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 315 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 316 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 317 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 318 } 319 } 320 321 static void 322 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 323 { 324 325 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 326 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 327 fxp_scb_wait(sc); 328 } 329 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 330 } 331 332 static void 333 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc) 334 { 335 int i = 10000; 336 337 while (!(*status & FXP_CB_STATUS_C) && --i) 338 DELAY(2); 339 if (i == 0) 340 if_printf(&sc->arpcom.ac_if, "DMA timeout\n"); 341 } 342 343 /* 344 * Return identification string if this is device is ours. 345 */ 346 static int 347 fxp_probe(device_t dev) 348 { 349 u_int16_t devid; 350 u_int8_t revid; 351 struct fxp_ident *ident; 352 353 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 354 devid = pci_get_device(dev); 355 revid = pci_get_revid(dev); 356 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 357 if (ident->devid == devid && 358 (ident->revid == revid || ident->revid == -1)) { 359 device_set_desc(dev, ident->name); 360 return (0); 361 } 362 } 363 } 364 return (ENXIO); 365 } 366 367 static void 368 fxp_powerstate_d0(device_t dev) 369 { 370 u_int32_t iobase, membase, irq; 371 372 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 373 /* Save important PCI config data. */ 374 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 375 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 376 irq = pci_read_config(dev, PCIR_INTLINE, 4); 377 378 /* Reset the power state. */ 379 device_printf(dev, "chip is in D%d power mode " 380 "-- setting to D0\n", pci_get_powerstate(dev)); 381 382 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 383 384 /* Restore PCI config data. */ 385 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 386 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 387 pci_write_config(dev, PCIR_INTLINE, irq, 4); 388 } 389 } 390 391 static int 392 fxp_attach(device_t dev) 393 { 394 int error = 0; 395 struct fxp_softc *sc = device_get_softc(dev); 396 struct ifnet *ifp; 397 u_int32_t val; 398 u_int16_t data; 399 int i, rid, m1, m2, prefer_iomap; 400 401 callout_init(&sc->fxp_stat_timer); 402 sysctl_ctx_init(&sc->sysctl_ctx); 403 404 /* 405 * Enable bus mastering. Enable memory space too, in case 406 * BIOS/Prom forgot about it. 407 */ 408 pci_enable_busmaster(dev); 409 pci_enable_io(dev, SYS_RES_MEMORY); 410 val = pci_read_config(dev, PCIR_COMMAND, 2); 411 412 fxp_powerstate_d0(dev); 413 414 /* 415 * Figure out which we should try first - memory mapping or i/o mapping? 416 * We default to memory mapping. Then we accept an override from the 417 * command line. Then we check to see which one is enabled. 418 */ 419 m1 = PCIM_CMD_MEMEN; 420 m2 = PCIM_CMD_PORTEN; 421 prefer_iomap = 0; 422 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 423 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 424 m1 = PCIM_CMD_PORTEN; 425 m2 = PCIM_CMD_MEMEN; 426 } 427 428 if (val & m1) { 429 sc->rtp = 430 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 431 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 432 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 433 RF_ACTIVE); 434 } 435 if (sc->mem == NULL && (val & m2)) { 436 sc->rtp = 437 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 438 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 439 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 440 RF_ACTIVE); 441 } 442 443 if (!sc->mem) { 444 device_printf(dev, "could not map device registers\n"); 445 error = ENXIO; 446 goto fail; 447 } 448 if (bootverbose) { 449 device_printf(dev, "using %s space register mapping\n", 450 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 451 } 452 453 sc->sc_st = rman_get_bustag(sc->mem); 454 sc->sc_sh = rman_get_bushandle(sc->mem); 455 456 /* 457 * Allocate our interrupt. 458 */ 459 rid = 0; 460 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 461 RF_SHAREABLE | RF_ACTIVE); 462 if (sc->irq == NULL) { 463 device_printf(dev, "could not map interrupt\n"); 464 error = ENXIO; 465 goto fail; 466 } 467 468 /* 469 * Reset to a stable state. 470 */ 471 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 472 DELAY(10); 473 474 sc->cbl_base = kmalloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 475 M_DEVBUF, M_WAITOK | M_ZERO); 476 477 sc->fxp_stats = kmalloc(sizeof(struct fxp_stats), M_DEVBUF, 478 M_WAITOK | M_ZERO); 479 480 sc->mcsp = kmalloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_WAITOK); 481 482 /* 483 * Pre-allocate our receive buffers. 484 */ 485 for (i = 0; i < FXP_NRFABUFS; i++) { 486 if (fxp_add_rfabuf(sc, NULL) != 0) { 487 goto failmem; 488 } 489 } 490 491 /* 492 * Find out how large of an SEEPROM we have. 493 */ 494 fxp_autosize_eeprom(sc); 495 496 /* 497 * Determine whether we must use the 503 serial interface. 498 */ 499 fxp_read_eeprom(sc, &data, 6, 1); 500 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 501 (data & FXP_PHY_SERIAL_ONLY)) 502 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 503 504 /* 505 * Create the sysctl tree 506 */ 507 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 508 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 509 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 510 if (sc->sysctl_tree == NULL) 511 goto fail; 512 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 513 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 514 &sc->tunable_int_delay, 0, &sysctl_hw_fxp_int_delay, "I", 515 "FXP driver receive interrupt microcode bundling delay"); 516 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 517 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 518 &sc->tunable_bundle_max, 0, &sysctl_hw_fxp_bundle_max, "I", 519 "FXP driver receive interrupt microcode bundle size limit"); 520 521 /* 522 * Pull in device tunables. 523 */ 524 sc->tunable_int_delay = TUNABLE_INT_DELAY; 525 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 526 resource_int_value(device_get_name(dev), device_get_unit(dev), 527 "int_delay", &sc->tunable_int_delay); 528 resource_int_value(device_get_name(dev), device_get_unit(dev), 529 "bundle_max", &sc->tunable_bundle_max); 530 531 /* 532 * Find out the chip revision; lump all 82557 revs together. 533 */ 534 fxp_read_eeprom(sc, &data, 5, 1); 535 if ((data >> 8) == 1) 536 sc->revision = FXP_REV_82557; 537 else 538 sc->revision = pci_get_revid(dev); 539 540 /* 541 * Enable workarounds for certain chip revision deficiencies. 542 * 543 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 544 * some systems based a normal 82559 design, have a defect where 545 * the chip can cause a PCI protocol violation if it receives 546 * a CU_RESUME command when it is entering the IDLE state. The 547 * workaround is to disable Dynamic Standby Mode, so the chip never 548 * deasserts CLKRUN#, and always remains in an active state. 549 * 550 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 551 */ 552 i = pci_get_device(dev); 553 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 554 sc->revision >= FXP_REV_82559_A0) { 555 fxp_read_eeprom(sc, &data, 10, 1); 556 if (data & 0x02) { /* STB enable */ 557 u_int16_t cksum; 558 int i; 559 560 device_printf(dev, 561 "Disabling dynamic standby mode in EEPROM\n"); 562 data &= ~0x02; 563 fxp_write_eeprom(sc, &data, 10, 1); 564 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 565 cksum = 0; 566 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 567 fxp_read_eeprom(sc, &data, i, 1); 568 cksum += data; 569 } 570 i = (1 << sc->eeprom_size) - 1; 571 cksum = 0xBABA - cksum; 572 fxp_read_eeprom(sc, &data, i, 1); 573 fxp_write_eeprom(sc, &cksum, i, 1); 574 device_printf(dev, 575 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 576 i, data, cksum); 577 #if 1 578 /* 579 * If the user elects to continue, try the software 580 * workaround, as it is better than nothing. 581 */ 582 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 583 #endif 584 } 585 } 586 587 /* 588 * If we are not a 82557 chip, we can enable extended features. 589 */ 590 if (sc->revision != FXP_REV_82557) { 591 /* 592 * If MWI is enabled in the PCI configuration, and there 593 * is a valid cacheline size (8 or 16 dwords), then tell 594 * the board to turn on MWI. 595 */ 596 if (val & PCIM_CMD_MWRICEN && 597 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 598 sc->flags |= FXP_FLAG_MWI_ENABLE; 599 600 /* turn on the extended TxCB feature */ 601 sc->flags |= FXP_FLAG_EXT_TXCB; 602 603 /* enable reception of long frames for VLAN */ 604 sc->flags |= FXP_FLAG_LONG_PKT_EN; 605 } 606 607 /* 608 * Read MAC address. 609 */ 610 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3); 611 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) 612 device_printf(dev, "10Mbps\n"); 613 if (bootverbose) { 614 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 615 pci_get_vendor(dev), pci_get_device(dev), 616 pci_get_subvendor(dev), pci_get_subdevice(dev), 617 pci_get_revid(dev)); 618 fxp_read_eeprom(sc, &data, 10, 1); 619 device_printf(dev, "Dynamic Standby mode is %s\n", 620 data & 0x02 ? "enabled" : "disabled"); 621 } 622 623 /* 624 * If this is only a 10Mbps device, then there is no MII, and 625 * the PHY will use a serial interface instead. 626 * 627 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 628 * doesn't have a programming interface of any sort. The 629 * media is sensed automatically based on how the link partner 630 * is configured. This is, in essence, manual configuration. 631 */ 632 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 633 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 634 fxp_serial_ifmedia_sts); 635 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 636 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 637 } else { 638 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 639 fxp_ifmedia_sts)) { 640 device_printf(dev, "MII without any PHY!\n"); 641 error = ENXIO; 642 goto fail; 643 } 644 } 645 646 ifp = &sc->arpcom.ac_if; 647 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 648 ifp->if_baudrate = 100000000; 649 ifp->if_init = fxp_init; 650 ifp->if_softc = sc; 651 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 652 ifp->if_ioctl = fxp_ioctl; 653 ifp->if_start = fxp_start; 654 #ifdef IFPOLL_ENABLE 655 ifp->if_npoll = fxp_npoll; 656 #endif 657 ifp->if_watchdog = fxp_watchdog; 658 659 /* 660 * Attach the interface. 661 */ 662 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL); 663 664 #ifdef IFPOLL_ENABLE 665 ifpoll_compat_setup(&sc->fxp_npoll, 666 &sc->sysctl_ctx, sc->sysctl_tree, device_get_unit(dev), 667 ifp->if_serializer); 668 #endif 669 670 /* 671 * Tell the upper layer(s) we support long frames. 672 */ 673 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 674 675 /* 676 * Let the system queue as many packets as we have available 677 * TX descriptors. 678 */ 679 ifq_set_maxlen(&ifp->if_snd, FXP_USABLE_TXCB); 680 ifq_set_ready(&ifp->if_snd); 681 682 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->irq)); 683 684 error = bus_setup_intr(dev, sc->irq, INTR_MPSAFE, 685 fxp_intr, sc, &sc->ih, 686 ifp->if_serializer); 687 if (error) { 688 ether_ifdetach(ifp); 689 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) 690 ifmedia_removeall(&sc->sc_media); 691 device_printf(dev, "could not setup irq\n"); 692 goto fail; 693 } 694 695 return (0); 696 697 failmem: 698 device_printf(dev, "Failed to malloc memory\n"); 699 error = ENOMEM; 700 fail: 701 fxp_release(dev); 702 return (error); 703 } 704 705 /* 706 * release all resources 707 */ 708 static void 709 fxp_release(device_t dev) 710 { 711 struct fxp_softc *sc = device_get_softc(dev); 712 713 if (sc->miibus) 714 device_delete_child(dev, sc->miibus); 715 bus_generic_detach(dev); 716 717 if (sc->cbl_base) 718 kfree(sc->cbl_base, M_DEVBUF); 719 if (sc->fxp_stats) 720 kfree(sc->fxp_stats, M_DEVBUF); 721 if (sc->mcsp) 722 kfree(sc->mcsp, M_DEVBUF); 723 if (sc->rfa_headm) 724 m_freem(sc->rfa_headm); 725 726 if (sc->irq) 727 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 728 if (sc->mem) 729 bus_release_resource(dev, sc->rtp, sc->rgd, sc->mem); 730 731 sysctl_ctx_free(&sc->sysctl_ctx); 732 } 733 734 /* 735 * Detach interface. 736 */ 737 static int 738 fxp_detach(device_t dev) 739 { 740 struct fxp_softc *sc = device_get_softc(dev); 741 742 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 743 744 /* 745 * Stop DMA and drop transmit queue. 746 */ 747 fxp_stop(sc); 748 749 /* 750 * Disable interrupts. 751 * 752 * NOTE: This should be done after fxp_stop(), because software 753 * resetting in fxp_stop() may leave interrupts turned on. 754 */ 755 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 756 757 /* 758 * Free all media structures. 759 */ 760 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) 761 ifmedia_removeall(&sc->sc_media); 762 763 if (sc->ih) 764 bus_teardown_intr(dev, sc->irq, sc->ih); 765 766 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 767 768 /* 769 * Close down routes etc. 770 */ 771 ether_ifdetach(&sc->arpcom.ac_if); 772 773 /* Release our allocated resources. */ 774 fxp_release(dev); 775 776 return (0); 777 } 778 779 /* 780 * Device shutdown routine. Called at system shutdown after sync. The 781 * main purpose of this routine is to shut off receiver DMA so that 782 * kernel memory doesn't get clobbered during warmboot. 783 */ 784 static int 785 fxp_shutdown(device_t dev) 786 { 787 struct fxp_softc *sc = device_get_softc(dev); 788 struct ifnet *ifp = &sc->arpcom.ac_if; 789 790 lwkt_serialize_enter(ifp->if_serializer); 791 /* 792 * Make sure that DMA is disabled prior to reboot. Not doing 793 * do could allow DMA to corrupt kernel memory during the 794 * reboot before the driver initializes. 795 */ 796 fxp_stop(sc); 797 lwkt_serialize_exit(ifp->if_serializer); 798 return (0); 799 } 800 801 /* 802 * Device suspend routine. Stop the interface and save some PCI 803 * settings in case the BIOS doesn't restore them properly on 804 * resume. 805 */ 806 static int 807 fxp_suspend(device_t dev) 808 { 809 struct fxp_softc *sc = device_get_softc(dev); 810 int i; 811 812 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 813 814 fxp_stop(sc); 815 816 for (i = 0; i < 5; i++) 817 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 818 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 819 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 820 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 821 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 822 823 sc->suspended = 1; 824 825 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 826 return (0); 827 } 828 829 /* 830 * Device resume routine. Restore some PCI settings in case the BIOS 831 * doesn't, re-enable busmastering, and restart the interface if 832 * appropriate. 833 */ 834 static int 835 fxp_resume(device_t dev) 836 { 837 struct fxp_softc *sc = device_get_softc(dev); 838 struct ifnet *ifp = &sc->arpcom.ac_if; 839 int i; 840 841 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 842 843 fxp_powerstate_d0(dev); 844 845 /* better way to do this? */ 846 for (i = 0; i < 5; i++) 847 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 848 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 849 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 850 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 851 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 852 853 /* reenable busmastering and memory space */ 854 pci_enable_busmaster(dev); 855 pci_enable_io(dev, SYS_RES_MEMORY); 856 857 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 858 DELAY(10); 859 860 /* reinitialize interface if necessary */ 861 if (ifp->if_flags & IFF_UP) 862 fxp_init(sc); 863 864 sc->suspended = 0; 865 866 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 867 return (0); 868 } 869 870 static void 871 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 872 { 873 u_int16_t reg; 874 int x; 875 876 /* 877 * Shift in data. 878 */ 879 for (x = 1 << (length - 1); x; x >>= 1) { 880 if (data & x) 881 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 882 else 883 reg = FXP_EEPROM_EECS; 884 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 885 DELAY(1); 886 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 887 DELAY(1); 888 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 889 DELAY(1); 890 } 891 } 892 893 /* 894 * Read from the serial EEPROM. Basically, you manually shift in 895 * the read opcode (one bit at a time) and then shift in the address, 896 * and then you shift out the data (all of this one bit at a time). 897 * The word size is 16 bits, so you have to provide the address for 898 * every 16 bits of data. 899 */ 900 static u_int16_t 901 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 902 { 903 u_int16_t reg, data; 904 int x; 905 906 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 907 /* 908 * Shift in read opcode. 909 */ 910 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 911 /* 912 * Shift in address. 913 */ 914 data = 0; 915 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 916 if (offset & x) 917 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 918 else 919 reg = FXP_EEPROM_EECS; 920 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 921 DELAY(1); 922 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 923 DELAY(1); 924 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 925 DELAY(1); 926 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 927 data++; 928 if (autosize && reg == 0) { 929 sc->eeprom_size = data; 930 break; 931 } 932 } 933 /* 934 * Shift out data. 935 */ 936 data = 0; 937 reg = FXP_EEPROM_EECS; 938 for (x = 1 << 15; x; x >>= 1) { 939 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 940 DELAY(1); 941 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 942 data |= x; 943 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 944 DELAY(1); 945 } 946 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 947 DELAY(1); 948 949 return (data); 950 } 951 952 static void 953 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 954 { 955 int i; 956 957 /* 958 * Erase/write enable. 959 */ 960 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 961 fxp_eeprom_shiftin(sc, 0x4, 3); 962 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 963 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 964 DELAY(1); 965 /* 966 * Shift in write opcode, address, data. 967 */ 968 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 969 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 970 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 971 fxp_eeprom_shiftin(sc, data, 16); 972 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 973 DELAY(1); 974 /* 975 * Wait for EEPROM to finish up. 976 */ 977 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 978 DELAY(1); 979 for (i = 0; i < 1000; i++) { 980 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 981 break; 982 DELAY(50); 983 } 984 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 985 DELAY(1); 986 /* 987 * Erase/write disable. 988 */ 989 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 990 fxp_eeprom_shiftin(sc, 0x4, 3); 991 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 992 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 993 DELAY(1); 994 } 995 996 /* 997 * From NetBSD: 998 * 999 * Figure out EEPROM size. 1000 * 1001 * 559's can have either 64-word or 256-word EEPROMs, the 558 1002 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 1003 * talks about the existance of 16 to 256 word EEPROMs. 1004 * 1005 * The only known sizes are 64 and 256, where the 256 version is used 1006 * by CardBus cards to store CIS information. 1007 * 1008 * The address is shifted in msb-to-lsb, and after the last 1009 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1010 * after which follows the actual data. We try to detect this zero, by 1011 * probing the data-out bit in the EEPROM control register just after 1012 * having shifted in a bit. If the bit is zero, we assume we've 1013 * shifted enough address bits. The data-out should be tri-state, 1014 * before this, which should translate to a logical one. 1015 */ 1016 static void 1017 fxp_autosize_eeprom(struct fxp_softc *sc) 1018 { 1019 1020 /* guess maximum size of 256 words */ 1021 sc->eeprom_size = 8; 1022 1023 /* autosize */ 1024 fxp_eeprom_getword(sc, 0, 1); 1025 } 1026 1027 static void 1028 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1029 { 1030 int i; 1031 1032 for (i = 0; i < words; i++) 1033 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1034 } 1035 1036 static void 1037 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1038 { 1039 int i; 1040 1041 for (i = 0; i < words; i++) 1042 fxp_eeprom_putword(sc, offset + i, data[i]); 1043 } 1044 1045 /* 1046 * Start packet transmission on the interface. 1047 */ 1048 static void 1049 fxp_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 1050 { 1051 struct fxp_softc *sc = ifp->if_softc; 1052 struct fxp_cb_tx *txp; 1053 1054 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 1055 ASSERT_SERIALIZED(ifp->if_serializer); 1056 1057 /* 1058 * See if we need to suspend xmit until the multicast filter 1059 * has been reprogrammed (which can only be done at the head 1060 * of the command chain). 1061 */ 1062 if (sc->need_mcsetup) { 1063 ifq_purge(&ifp->if_snd); 1064 return; 1065 } 1066 1067 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd)) 1068 return; 1069 1070 txp = NULL; 1071 1072 /* 1073 * We're finished if there is nothing more to add to the list or if 1074 * we're all filled up with buffers to transmit. 1075 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1076 * a NOP command when needed. 1077 */ 1078 while (!ifq_is_empty(&ifp->if_snd) && sc->tx_queued < FXP_USABLE_TXCB) { 1079 struct mbuf *m, *mb_head; 1080 int segment, ntries = 0; 1081 1082 /* 1083 * Grab a packet to transmit. 1084 */ 1085 mb_head = ifq_dequeue(&ifp->if_snd); 1086 if (mb_head == NULL) 1087 break; 1088 tbdinit: 1089 /* 1090 * Make sure that the packet fits into one TX desc 1091 */ 1092 segment = 0; 1093 for (m = mb_head; m != NULL; m = m->m_next) { 1094 if (m->m_len != 0) { 1095 ++segment; 1096 if (segment >= FXP_NTXSEG) 1097 break; 1098 } 1099 } 1100 if (segment >= FXP_NTXSEG) { 1101 struct mbuf *mn; 1102 1103 if (ntries) { 1104 /* 1105 * Packet is excessively fragmented, 1106 * and will never fit into one TX 1107 * desc. Give it up. 1108 */ 1109 m_freem(mb_head); 1110 IFNET_STAT_INC(ifp, oerrors, 1); 1111 continue; 1112 } 1113 1114 mn = m_dup(mb_head, MB_DONTWAIT); 1115 if (mn == NULL) { 1116 m_freem(mb_head); 1117 IFNET_STAT_INC(ifp, oerrors, 1); 1118 continue; 1119 } 1120 1121 m_freem(mb_head); 1122 mb_head = mn; 1123 ntries = 1; 1124 goto tbdinit; 1125 } 1126 1127 /* 1128 * Get pointer to next available tx desc. 1129 */ 1130 txp = sc->cbl_last->next; 1131 1132 /* 1133 * Go through each of the mbufs in the chain and initialize 1134 * the transmit buffer descriptors with the physical address 1135 * and size of the mbuf. 1136 */ 1137 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 1138 if (m->m_len != 0) { 1139 KKASSERT(segment < FXP_NTXSEG); 1140 1141 txp->tbd[segment].tb_addr = 1142 vtophys(mtod(m, vm_offset_t)); 1143 txp->tbd[segment].tb_size = m->m_len; 1144 segment++; 1145 } 1146 } 1147 KKASSERT(m == NULL); 1148 1149 txp->tbd_number = segment; 1150 txp->mb_head = mb_head; 1151 txp->cb_status = 0; 1152 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1153 txp->cb_command = 1154 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1155 FXP_CB_COMMAND_S; 1156 } else { 1157 txp->cb_command = 1158 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1159 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1160 } 1161 txp->tx_threshold = tx_threshold; 1162 1163 /* 1164 * Advance the end of list forward. 1165 */ 1166 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1167 sc->cbl_last = txp; 1168 1169 /* 1170 * Advance the beginning of the list forward if there are 1171 * no other packets queued (when nothing is queued, cbl_first 1172 * sits on the last TxCB that was sent out). 1173 */ 1174 if (sc->tx_queued == 0) 1175 sc->cbl_first = txp; 1176 1177 sc->tx_queued++; 1178 /* 1179 * Set a 5 second timer just in case we don't hear 1180 * from the card again. 1181 */ 1182 ifp->if_timer = 5; 1183 1184 BPF_MTAP(ifp, mb_head); 1185 } 1186 1187 if (sc->tx_queued >= FXP_USABLE_TXCB) 1188 ifq_set_oactive(&ifp->if_snd); 1189 1190 /* 1191 * We're finished. If we added to the list, issue a RESUME to get DMA 1192 * going again if suspended. 1193 */ 1194 if (txp != NULL) { 1195 fxp_scb_wait(sc); 1196 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1197 } 1198 } 1199 1200 #ifdef IFPOLL_ENABLE 1201 1202 static void 1203 fxp_npoll_compat(struct ifnet *ifp, void *arg __unused, int count) 1204 { 1205 struct fxp_softc *sc = ifp->if_softc; 1206 u_int8_t statack; 1207 1208 ASSERT_SERIALIZED(ifp->if_serializer); 1209 1210 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1211 FXP_SCB_STATACK_FR; 1212 if (sc->fxp_npoll.ifpc_stcount-- == 0) { 1213 u_int8_t tmp; 1214 1215 sc->fxp_npoll.ifpc_stcount = sc->fxp_npoll.ifpc_stfrac; 1216 1217 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1218 if (tmp == 0xff || tmp == 0) 1219 return; /* nothing to do */ 1220 tmp &= ~statack; 1221 /* ack what we can */ 1222 if (tmp != 0) 1223 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1224 statack |= tmp; 1225 } 1226 fxp_intr_body(sc, statack, count); 1227 } 1228 1229 static void 1230 fxp_npoll(struct ifnet *ifp, struct ifpoll_info *info) 1231 { 1232 struct fxp_softc *sc = ifp->if_softc; 1233 1234 ASSERT_SERIALIZED(ifp->if_serializer); 1235 1236 if (info != NULL) { 1237 int cpuid = sc->fxp_npoll.ifpc_cpuid; 1238 1239 info->ifpi_rx[cpuid].poll_func = fxp_npoll_compat; 1240 info->ifpi_rx[cpuid].arg = NULL; 1241 info->ifpi_rx[cpuid].serializer = ifp->if_serializer; 1242 1243 if (ifp->if_flags & IFF_RUNNING) { 1244 /* disable interrupts */ 1245 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 1246 FXP_SCB_INTR_DISABLE); 1247 sc->fxp_npoll.ifpc_stcount = 0; 1248 } 1249 ifq_set_cpuid(&ifp->if_snd, cpuid); 1250 } else { 1251 if (ifp->if_flags & IFF_RUNNING) { 1252 /* enable interrupts */ 1253 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1254 } 1255 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->irq)); 1256 } 1257 } 1258 1259 #endif /* IFPOLL_ENABLE */ 1260 1261 /* 1262 * Process interface interrupts. 1263 */ 1264 static void 1265 fxp_intr(void *xsc) 1266 { 1267 struct fxp_softc *sc = xsc; 1268 u_int8_t statack; 1269 1270 ASSERT_SERIALIZED(sc->arpcom.ac_if.if_serializer); 1271 1272 if (sc->suspended) { 1273 return; 1274 } 1275 1276 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1277 /* 1278 * It should not be possible to have all bits set; the 1279 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1280 * all bits are set, this may indicate that the card has 1281 * been physically ejected, so ignore it. 1282 */ 1283 if (statack == 0xff) 1284 return; 1285 1286 /* 1287 * First ACK all the interrupts in this pass. 1288 */ 1289 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1290 fxp_intr_body(sc, statack, -1); 1291 } 1292 } 1293 1294 static void 1295 fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count) 1296 { 1297 struct ifnet *ifp = &sc->arpcom.ac_if; 1298 struct mbuf *m; 1299 struct fxp_rfa *rfa; 1300 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1301 1302 if (rnr) 1303 fxp_rnr++; 1304 #ifdef IFPOLL_ENABLE 1305 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1306 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1307 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1308 rnr = 1; 1309 } 1310 #endif 1311 1312 /* 1313 * Free any finished transmit mbuf chains. 1314 * 1315 * Handle the CNA event likt a CXTNO event. It used to 1316 * be that this event (control unit not ready) was not 1317 * encountered, but it is now with the SMPng modifications. 1318 * The exact sequence of events that occur when the interface 1319 * is brought up are different now, and if this event 1320 * goes unhandled, the configuration/rxfilter setup sequence 1321 * can stall for several seconds. The result is that no 1322 * packets go out onto the wire for about 5 to 10 seconds 1323 * after the interface is ifconfig'ed for the first time. 1324 */ 1325 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1326 struct fxp_cb_tx *txp; 1327 1328 for (txp = sc->cbl_first; sc->tx_queued && 1329 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1330 txp = txp->next) { 1331 if ((m = txp->mb_head) != NULL) { 1332 txp->mb_head = NULL; 1333 sc->tx_queued--; 1334 m_freem(m); 1335 } else { 1336 sc->tx_queued--; 1337 } 1338 } 1339 sc->cbl_first = txp; 1340 1341 if (sc->tx_queued < FXP_USABLE_TXCB) 1342 ifq_clr_oactive(&ifp->if_snd); 1343 1344 if (sc->tx_queued == 0) { 1345 ifp->if_timer = 0; 1346 if (sc->need_mcsetup) 1347 fxp_mc_setup(sc); 1348 } 1349 1350 /* 1351 * Try to start more packets transmitting. 1352 */ 1353 if (!ifq_is_empty(&ifp->if_snd)) 1354 if_devstart(ifp); 1355 } 1356 1357 /* 1358 * Just return if nothing happened on the receive side. 1359 */ 1360 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1361 return; 1362 1363 /* 1364 * Process receiver interrupts. If a no-resource (RNR) 1365 * condition exists, get whatever packets we can and 1366 * re-start the receiver. 1367 * 1368 * When using polling, we do not process the list to completion, 1369 * so when we get an RNR interrupt we must defer the restart 1370 * until we hit the last buffer with the C bit set. 1371 * If we run out of cycles and rfa_headm has the C bit set, 1372 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1373 * that the info will be used in the subsequent polling cycle. 1374 */ 1375 for (;;) { 1376 m = sc->rfa_headm; 1377 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1378 RFA_ALIGNMENT_FUDGE); 1379 1380 #ifdef IFPOLL_ENABLE /* loop at most count times if count >=0 */ 1381 if (count >= 0 && count-- == 0) { 1382 if (rnr) { 1383 /* Defer RNR processing until the next time. */ 1384 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1385 rnr = 0; 1386 } 1387 break; 1388 } 1389 #endif /* IFPOLL_ENABLE */ 1390 1391 if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0) 1392 break; 1393 1394 /* 1395 * Remove first packet from the chain. 1396 */ 1397 sc->rfa_headm = m->m_next; 1398 if (sc->rfa_headm == NULL) 1399 sc->rfa_tailm = NULL; 1400 m->m_next = NULL; 1401 1402 /* 1403 * Add a new buffer to the receive chain. 1404 * If this fails, the old buffer is recycled 1405 * instead. 1406 */ 1407 if (fxp_add_rfabuf(sc, m) == 0) { 1408 int total_len; 1409 1410 /* 1411 * Fetch packet length (the top 2 bits of 1412 * actual_size are flags set by the controller 1413 * upon completion), and drop the packet in case 1414 * of bogus length or CRC errors. 1415 */ 1416 total_len = rfa->actual_size & 0x3fff; 1417 if (total_len < sizeof(struct ether_header) || 1418 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1419 sizeof(struct fxp_rfa) || 1420 (rfa->rfa_status & FXP_RFA_STATUS_CRC)) { 1421 m_freem(m); 1422 continue; 1423 } 1424 m->m_pkthdr.len = m->m_len = total_len; 1425 ifp->if_input(ifp, m, NULL, -1); 1426 } 1427 } 1428 1429 if (rnr) { 1430 fxp_scb_wait(sc); 1431 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1432 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1433 RFA_ALIGNMENT_FUDGE); 1434 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1435 } 1436 } 1437 1438 /* 1439 * Update packet in/out/collision statistics. The i82557 doesn't 1440 * allow you to access these counters without doing a fairly 1441 * expensive DMA to get _all_ of the statistics it maintains, so 1442 * we do this operation here only once per second. The statistics 1443 * counters in the kernel are updated from the previous dump-stats 1444 * DMA and then a new dump-stats DMA is started. The on-chip 1445 * counters are zeroed when the DMA completes. If we can't start 1446 * the DMA immediately, we don't wait - we just prepare to read 1447 * them again next time. 1448 */ 1449 static void 1450 fxp_tick(void *xsc) 1451 { 1452 struct fxp_softc *sc = xsc; 1453 struct ifnet *ifp = &sc->arpcom.ac_if; 1454 struct fxp_stats *sp = sc->fxp_stats; 1455 struct fxp_cb_tx *txp; 1456 struct mbuf *m; 1457 1458 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 1459 1460 IFNET_STAT_INC(ifp, opackets, sp->tx_good); 1461 IFNET_STAT_INC(ifp, collisions, sp->tx_total_collisions); 1462 if (sp->rx_good) { 1463 IFNET_STAT_INC(ifp, ipackets, sp->rx_good); 1464 sc->rx_idle_secs = 0; 1465 } else { 1466 /* 1467 * Receiver's been idle for another second. 1468 */ 1469 sc->rx_idle_secs++; 1470 } 1471 IFNET_STAT_INC(ifp, ierrors, 1472 sp->rx_crc_errors + 1473 sp->rx_alignment_errors + 1474 sp->rx_rnr_errors + 1475 sp->rx_overrun_errors); 1476 /* 1477 * If any transmit underruns occured, bump up the transmit 1478 * threshold by another 512 bytes (64 * 8). 1479 */ 1480 if (sp->tx_underruns) { 1481 IFNET_STAT_INC(ifp, oerrors, sp->tx_underruns); 1482 if (tx_threshold < 192) 1483 tx_threshold += 64; 1484 } 1485 1486 /* 1487 * Release any xmit buffers that have completed DMA. This isn't 1488 * strictly necessary to do here, but it's advantagous for mbufs 1489 * with external storage to be released in a timely manner rather 1490 * than being defered for a potentially long time. This limits 1491 * the delay to a maximum of one second. 1492 */ 1493 for (txp = sc->cbl_first; sc->tx_queued && 1494 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1495 txp = txp->next) { 1496 if ((m = txp->mb_head) != NULL) { 1497 txp->mb_head = NULL; 1498 sc->tx_queued--; 1499 m_freem(m); 1500 } else { 1501 sc->tx_queued--; 1502 } 1503 } 1504 sc->cbl_first = txp; 1505 1506 if (sc->tx_queued < FXP_USABLE_TXCB) 1507 ifq_clr_oactive(&ifp->if_snd); 1508 if (sc->tx_queued == 0) 1509 ifp->if_timer = 0; 1510 1511 /* 1512 * Try to start more packets transmitting. 1513 */ 1514 if (!ifq_is_empty(&ifp->if_snd)) 1515 if_devstart(ifp); 1516 1517 /* 1518 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1519 * then assume the receiver has locked up and attempt to clear 1520 * the condition by reprogramming the multicast filter. This is 1521 * a work-around for a bug in the 82557 where the receiver locks 1522 * up if it gets certain types of garbage in the syncronization 1523 * bits prior to the packet header. This bug is supposed to only 1524 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1525 * mode as well (perhaps due to a 10/100 speed transition). 1526 */ 1527 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1528 sc->rx_idle_secs = 0; 1529 fxp_mc_setup(sc); 1530 } 1531 /* 1532 * If there is no pending command, start another stats 1533 * dump. Otherwise punt for now. 1534 */ 1535 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1536 /* 1537 * Start another stats dump. 1538 */ 1539 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1540 } else { 1541 /* 1542 * A previous command is still waiting to be accepted. 1543 * Just zero our copy of the stats and wait for the 1544 * next timer event to update them. 1545 */ 1546 sp->tx_good = 0; 1547 sp->tx_underruns = 0; 1548 sp->tx_total_collisions = 0; 1549 1550 sp->rx_good = 0; 1551 sp->rx_crc_errors = 0; 1552 sp->rx_alignment_errors = 0; 1553 sp->rx_rnr_errors = 0; 1554 sp->rx_overrun_errors = 0; 1555 } 1556 if (sc->miibus != NULL) 1557 mii_tick(device_get_softc(sc->miibus)); 1558 /* 1559 * Schedule another timeout one second from now. 1560 */ 1561 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc); 1562 1563 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 1564 } 1565 1566 /* 1567 * Stop the interface. Cancels the statistics updater and resets 1568 * the interface. 1569 */ 1570 static void 1571 fxp_stop(struct fxp_softc *sc) 1572 { 1573 struct ifnet *ifp = &sc->arpcom.ac_if; 1574 struct fxp_cb_tx *txp; 1575 int i; 1576 1577 ASSERT_SERIALIZED(ifp->if_serializer); 1578 1579 ifp->if_flags &= ~IFF_RUNNING; 1580 ifq_clr_oactive(&ifp->if_snd); 1581 ifp->if_timer = 0; 1582 1583 /* 1584 * Cancel stats updater. 1585 */ 1586 callout_stop(&sc->fxp_stat_timer); 1587 1588 /* 1589 * Issue software reset, which also unloads the microcode. 1590 */ 1591 sc->flags &= ~FXP_FLAG_UCODE; 1592 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1593 DELAY(50); 1594 1595 /* 1596 * Release any xmit buffers. 1597 */ 1598 txp = sc->cbl_base; 1599 if (txp != NULL) { 1600 for (i = 0; i < FXP_NTXCB; i++) { 1601 if (txp[i].mb_head != NULL) { 1602 m_freem(txp[i].mb_head); 1603 txp[i].mb_head = NULL; 1604 } 1605 } 1606 } 1607 sc->tx_queued = 0; 1608 1609 /* 1610 * Free all the receive buffers then reallocate/reinitialize 1611 */ 1612 if (sc->rfa_headm != NULL) 1613 m_freem(sc->rfa_headm); 1614 sc->rfa_headm = NULL; 1615 sc->rfa_tailm = NULL; 1616 for (i = 0; i < FXP_NRFABUFS; i++) { 1617 if (fxp_add_rfabuf(sc, NULL) != 0) { 1618 /* 1619 * This "can't happen" - we're at splimp() 1620 * and we just freed all the buffers we need 1621 * above. 1622 */ 1623 panic("fxp_stop: no buffers!"); 1624 } 1625 } 1626 } 1627 1628 /* 1629 * Watchdog/transmission transmit timeout handler. Called when a 1630 * transmission is started on the interface, but no interrupt is 1631 * received before the timeout. This usually indicates that the 1632 * card has wedged for some reason. 1633 */ 1634 static void 1635 fxp_watchdog(struct ifnet *ifp) 1636 { 1637 ASSERT_SERIALIZED(ifp->if_serializer); 1638 1639 if_printf(ifp, "device timeout\n"); 1640 IFNET_STAT_INC(ifp, oerrors, 1); 1641 fxp_init(ifp->if_softc); 1642 } 1643 1644 static void 1645 fxp_init(void *xsc) 1646 { 1647 struct fxp_softc *sc = xsc; 1648 struct ifnet *ifp = &sc->arpcom.ac_if; 1649 struct fxp_cb_config *cbp; 1650 struct fxp_cb_ias *cb_ias; 1651 struct fxp_cb_tx *txp; 1652 struct fxp_cb_mcs *mcsp; 1653 int i, prm; 1654 1655 ASSERT_SERIALIZED(ifp->if_serializer); 1656 1657 /* 1658 * Cancel any pending I/O 1659 */ 1660 fxp_stop(sc); 1661 1662 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1663 1664 /* 1665 * Initialize base of CBL and RFA memory. Loading with zero 1666 * sets it up for regular linear addressing. 1667 */ 1668 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1669 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1670 1671 fxp_scb_wait(sc); 1672 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1673 1674 /* 1675 * Initialize base of dump-stats buffer. 1676 */ 1677 fxp_scb_wait(sc); 1678 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1679 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1680 1681 /* 1682 * Attempt to load microcode if requested. 1683 */ 1684 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1685 fxp_load_ucode(sc); 1686 1687 /* 1688 * Initialize the multicast address list. 1689 */ 1690 if (fxp_mc_addrs(sc)) { 1691 mcsp = sc->mcsp; 1692 mcsp->cb_status = 0; 1693 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL; 1694 mcsp->link_addr = -1; 1695 /* 1696 * Start the multicast setup command. 1697 */ 1698 fxp_scb_wait(sc); 1699 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 1700 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1701 /* ...and wait for it to complete. */ 1702 fxp_dma_wait(&mcsp->cb_status, sc); 1703 } 1704 1705 /* 1706 * We temporarily use memory that contains the TxCB list to 1707 * construct the config CB. The TxCB list memory is rebuilt 1708 * later. 1709 */ 1710 cbp = (struct fxp_cb_config *) sc->cbl_base; 1711 1712 /* 1713 * This bcopy is kind of disgusting, but there are a bunch of must be 1714 * zero and must be one bits in this structure and this is the easiest 1715 * way to initialize them all to proper values. 1716 */ 1717 bcopy(fxp_cb_config_template, 1718 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1719 sizeof(fxp_cb_config_template)); 1720 1721 cbp->cb_status = 0; 1722 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1723 cbp->link_addr = -1; /* (no) next command */ 1724 cbp->byte_count = 22; /* (22) bytes to config */ 1725 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1726 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1727 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1728 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1729 cbp->type_enable = 0; /* actually reserved */ 1730 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1731 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1732 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1733 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1734 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1735 cbp->late_scb = 0; /* (don't) defer SCB update */ 1736 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 1737 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1738 cbp->ci_int = 1; /* interrupt on CU idle */ 1739 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 1740 cbp->ext_stats_dis = 1; /* disable extended counters */ 1741 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1742 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 1743 cbp->disc_short_rx = !prm; /* discard short packets */ 1744 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 1745 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1746 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1747 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 1748 cbp->csma_dis = 0; /* (don't) disable link */ 1749 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1750 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1751 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1752 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1753 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 1754 cbp->nsai = 1; /* (don't) disable source addr insert */ 1755 cbp->preamble_length = 2; /* (7 byte) preamble */ 1756 cbp->loopback = 0; /* (don't) loopback */ 1757 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1758 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1759 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1760 cbp->promiscuous = prm; /* promiscuous mode */ 1761 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1762 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1763 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1764 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1765 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 1766 1767 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1768 cbp->padding = 1; /* (do) pad short tx packets */ 1769 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1770 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 1771 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1772 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1773 /* must set wake_en in PMCSR also */ 1774 cbp->force_fdx = 0; /* (don't) force full duplex */ 1775 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1776 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1777 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 1778 1779 if (sc->revision == FXP_REV_82557) { 1780 /* 1781 * The 82557 has no hardware flow control, the values 1782 * below are the defaults for the chip. 1783 */ 1784 cbp->fc_delay_lsb = 0; 1785 cbp->fc_delay_msb = 0x40; 1786 cbp->pri_fc_thresh = 3; 1787 cbp->tx_fc_dis = 0; 1788 cbp->rx_fc_restop = 0; 1789 cbp->rx_fc_restart = 0; 1790 cbp->fc_filter = 0; 1791 cbp->pri_fc_loc = 1; 1792 } else { 1793 cbp->fc_delay_lsb = 0x1f; 1794 cbp->fc_delay_msb = 0x01; 1795 cbp->pri_fc_thresh = 3; 1796 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1797 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1798 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1799 cbp->fc_filter = !prm; /* drop FC frames to host */ 1800 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1801 } 1802 1803 /* 1804 * Start the config command/DMA. 1805 */ 1806 fxp_scb_wait(sc); 1807 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1808 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1809 /* ...and wait for it to complete. */ 1810 fxp_dma_wait(&cbp->cb_status, sc); 1811 1812 /* 1813 * Now initialize the station address. Temporarily use the TxCB 1814 * memory area like we did above for the config CB. 1815 */ 1816 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1817 cb_ias->cb_status = 0; 1818 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1819 cb_ias->link_addr = -1; 1820 bcopy(sc->arpcom.ac_enaddr, 1821 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1822 sizeof(sc->arpcom.ac_enaddr)); 1823 1824 /* 1825 * Start the IAS (Individual Address Setup) command/DMA. 1826 */ 1827 fxp_scb_wait(sc); 1828 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1829 /* ...and wait for it to complete. */ 1830 fxp_dma_wait(&cb_ias->cb_status, sc); 1831 1832 /* 1833 * Initialize transmit control block (TxCB) list. 1834 */ 1835 1836 txp = sc->cbl_base; 1837 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1838 for (i = 0; i < FXP_NTXCB; i++) { 1839 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1840 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1841 txp[i].link_addr = 1842 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1843 if (sc->flags & FXP_FLAG_EXT_TXCB) 1844 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]); 1845 else 1846 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1847 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1848 } 1849 /* 1850 * Set the suspend flag on the first TxCB and start the control 1851 * unit. It will execute the NOP and then suspend. 1852 */ 1853 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1854 sc->cbl_first = sc->cbl_last = txp; 1855 sc->tx_queued = 1; 1856 1857 fxp_scb_wait(sc); 1858 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1859 1860 /* 1861 * Initialize receiver buffer area - RFA. 1862 */ 1863 fxp_scb_wait(sc); 1864 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1865 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1866 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1867 1868 /* 1869 * Set current media. 1870 */ 1871 if (sc->miibus != NULL) 1872 mii_mediachg(device_get_softc(sc->miibus)); 1873 1874 ifp->if_flags |= IFF_RUNNING; 1875 ifq_clr_oactive(&ifp->if_snd); 1876 1877 /* 1878 * Enable interrupts. 1879 */ 1880 #ifdef IFPOLL_ENABLE 1881 /* 1882 * ... but only do that if we are not polling. And because (presumably) 1883 * the default is interrupts on, we need to disable them explicitly! 1884 */ 1885 if (ifp->if_flags & IFF_NPOLLING) { 1886 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1887 sc->fxp_npoll.ifpc_stcount = 0; 1888 } else 1889 #endif /* IFPOLL_ENABLE */ 1890 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1891 1892 /* 1893 * Start stats updater. 1894 */ 1895 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc); 1896 } 1897 1898 static int 1899 fxp_serial_ifmedia_upd(struct ifnet *ifp) 1900 { 1901 ASSERT_SERIALIZED(ifp->if_serializer); 1902 return (0); 1903 } 1904 1905 static void 1906 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1907 { 1908 ASSERT_SERIALIZED(ifp->if_serializer); 1909 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 1910 } 1911 1912 /* 1913 * Change media according to request. 1914 */ 1915 static int 1916 fxp_ifmedia_upd(struct ifnet *ifp) 1917 { 1918 struct fxp_softc *sc = ifp->if_softc; 1919 struct mii_data *mii; 1920 1921 ASSERT_SERIALIZED(ifp->if_serializer); 1922 1923 mii = device_get_softc(sc->miibus); 1924 mii_mediachg(mii); 1925 return (0); 1926 } 1927 1928 /* 1929 * Notify the world which media we're using. 1930 */ 1931 static void 1932 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1933 { 1934 struct fxp_softc *sc = ifp->if_softc; 1935 struct mii_data *mii; 1936 1937 ASSERT_SERIALIZED(ifp->if_serializer); 1938 1939 mii = device_get_softc(sc->miibus); 1940 mii_pollstat(mii); 1941 ifmr->ifm_active = mii->mii_media_active; 1942 ifmr->ifm_status = mii->mii_media_status; 1943 1944 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 1945 sc->cu_resume_bug = 1; 1946 else 1947 sc->cu_resume_bug = 0; 1948 } 1949 1950 /* 1951 * Add a buffer to the end of the RFA buffer list. 1952 * Return 0 if successful, 1 for failure. A failure results in 1953 * adding the 'oldm' (if non-NULL) on to the end of the list - 1954 * tossing out its old contents and recycling it. 1955 * The RFA struct is stuck at the beginning of mbuf cluster and the 1956 * data pointer is fixed up to point just past it. 1957 */ 1958 static int 1959 fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm) 1960 { 1961 u_int32_t v; 1962 struct mbuf *m; 1963 struct fxp_rfa *rfa, *p_rfa; 1964 1965 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1966 if (m == NULL) { /* try to recycle the old mbuf instead */ 1967 if (oldm == NULL) 1968 return 1; 1969 m = oldm; 1970 m->m_data = m->m_ext.ext_buf; 1971 } 1972 1973 /* 1974 * Move the data pointer up so that the incoming data packet 1975 * will be 32-bit aligned. 1976 */ 1977 m->m_data += RFA_ALIGNMENT_FUDGE; 1978 1979 /* 1980 * Get a pointer to the base of the mbuf cluster and move 1981 * data start past it. 1982 */ 1983 rfa = mtod(m, struct fxp_rfa *); 1984 m->m_data += sizeof(struct fxp_rfa); 1985 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - 1986 RFA_ALIGNMENT_FUDGE); 1987 1988 /* 1989 * Initialize the rest of the RFA. Note that since the RFA 1990 * is misaligned, we cannot store values directly. Instead, 1991 * we use an optimized, inline copy. 1992 */ 1993 1994 rfa->rfa_status = 0; 1995 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1996 rfa->actual_size = 0; 1997 1998 v = -1; 1999 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 2000 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 2001 2002 /* 2003 * If there are other buffers already on the list, attach this 2004 * one to the end by fixing up the tail to point to this one. 2005 */ 2006 if (sc->rfa_headm != NULL) { 2007 p_rfa = (struct fxp_rfa *)(sc->rfa_tailm->m_ext.ext_buf + 2008 RFA_ALIGNMENT_FUDGE); 2009 sc->rfa_tailm->m_next = m; 2010 v = vtophys(rfa); 2011 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 2012 p_rfa->rfa_control = 0; 2013 } else { 2014 sc->rfa_headm = m; 2015 } 2016 sc->rfa_tailm = m; 2017 2018 return (m == oldm); 2019 } 2020 2021 static int 2022 fxp_miibus_readreg(device_t dev, int phy, int reg) 2023 { 2024 struct fxp_softc *sc = device_get_softc(dev); 2025 int count = 10000; 2026 int value; 2027 2028 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2029 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2030 2031 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 2032 && count--) 2033 DELAY(10); 2034 2035 if (count <= 0) 2036 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 2037 2038 return (value & 0xffff); 2039 } 2040 2041 static void 2042 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 2043 { 2044 struct fxp_softc *sc = device_get_softc(dev); 2045 int count = 10000; 2046 2047 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2048 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2049 (value & 0xffff)); 2050 2051 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2052 count--) 2053 DELAY(10); 2054 2055 if (count <= 0) 2056 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 2057 } 2058 2059 static int 2060 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2061 { 2062 struct fxp_softc *sc = ifp->if_softc; 2063 struct ifreq *ifr = (struct ifreq *)data; 2064 struct mii_data *mii; 2065 int error = 0; 2066 2067 ASSERT_SERIALIZED(ifp->if_serializer); 2068 2069 switch (command) { 2070 2071 case SIOCSIFFLAGS: 2072 if (ifp->if_flags & IFF_ALLMULTI) 2073 sc->flags |= FXP_FLAG_ALL_MCAST; 2074 else 2075 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2076 2077 /* 2078 * If interface is marked up and not running, then start it. 2079 * If it is marked down and running, stop it. 2080 * XXX If it's up then re-initialize it. This is so flags 2081 * such as IFF_PROMISC are handled. 2082 */ 2083 if (ifp->if_flags & IFF_UP) { 2084 fxp_init(sc); 2085 } else { 2086 if (ifp->if_flags & IFF_RUNNING) 2087 fxp_stop(sc); 2088 } 2089 break; 2090 2091 case SIOCADDMULTI: 2092 case SIOCDELMULTI: 2093 if (ifp->if_flags & IFF_ALLMULTI) 2094 sc->flags |= FXP_FLAG_ALL_MCAST; 2095 else 2096 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2097 /* 2098 * Multicast list has changed; set the hardware filter 2099 * accordingly. 2100 */ 2101 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2102 fxp_mc_setup(sc); 2103 /* 2104 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2105 * again rather than else {}. 2106 */ 2107 if (sc->flags & FXP_FLAG_ALL_MCAST) 2108 fxp_init(sc); 2109 error = 0; 2110 break; 2111 2112 case SIOCSIFMEDIA: 2113 case SIOCGIFMEDIA: 2114 if (sc->miibus != NULL) { 2115 mii = device_get_softc(sc->miibus); 2116 error = ifmedia_ioctl(ifp, ifr, 2117 &mii->mii_media, command); 2118 } else { 2119 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2120 } 2121 break; 2122 2123 default: 2124 error = ether_ioctl(ifp, command, data); 2125 break; 2126 } 2127 return (error); 2128 } 2129 2130 /* 2131 * Fill in the multicast address list and return number of entries. 2132 */ 2133 static int 2134 fxp_mc_addrs(struct fxp_softc *sc) 2135 { 2136 struct fxp_cb_mcs *mcsp = sc->mcsp; 2137 struct ifnet *ifp = &sc->arpcom.ac_if; 2138 struct ifmultiaddr *ifma; 2139 int nmcasts; 2140 2141 nmcasts = 0; 2142 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2143 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2144 if (ifma->ifma_addr->sa_family != AF_LINK) 2145 continue; 2146 if (nmcasts >= MAXMCADDR) { 2147 sc->flags |= FXP_FLAG_ALL_MCAST; 2148 nmcasts = 0; 2149 break; 2150 } 2151 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2152 (void *)(uintptr_t)(volatile void *) 2153 &sc->mcsp->mc_addr[nmcasts][0], 6); 2154 nmcasts++; 2155 } 2156 } 2157 mcsp->mc_cnt = nmcasts * 6; 2158 return (nmcasts); 2159 } 2160 2161 /* 2162 * Program the multicast filter. 2163 * 2164 * We have an artificial restriction that the multicast setup command 2165 * must be the first command in the chain, so we take steps to ensure 2166 * this. By requiring this, it allows us to keep up the performance of 2167 * the pre-initialized command ring (esp. link pointers) by not actually 2168 * inserting the mcsetup command in the ring - i.e. its link pointer 2169 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2170 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2171 * lead into the regular TxCB ring when it completes. 2172 * 2173 * This function must be called at splimp. 2174 */ 2175 static void 2176 fxp_mc_setup(struct fxp_softc *sc) 2177 { 2178 struct fxp_cb_mcs *mcsp = sc->mcsp; 2179 struct ifnet *ifp = &sc->arpcom.ac_if; 2180 int count; 2181 2182 /* 2183 * If there are queued commands, we must wait until they are all 2184 * completed. If we are already waiting, then add a NOP command 2185 * with interrupt option so that we're notified when all commands 2186 * have been completed - fxp_start() ensures that no additional 2187 * TX commands will be added when need_mcsetup is true. 2188 */ 2189 if (sc->tx_queued) { 2190 struct fxp_cb_tx *txp; 2191 2192 /* 2193 * need_mcsetup will be true if we are already waiting for the 2194 * NOP command to be completed (see below). In this case, bail. 2195 */ 2196 if (sc->need_mcsetup) 2197 return; 2198 sc->need_mcsetup = 1; 2199 2200 /* 2201 * Add a NOP command with interrupt so that we are notified 2202 * when all TX commands have been processed. 2203 */ 2204 txp = sc->cbl_last->next; 2205 txp->mb_head = NULL; 2206 txp->cb_status = 0; 2207 txp->cb_command = FXP_CB_COMMAND_NOP | 2208 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2209 /* 2210 * Advance the end of list forward. 2211 */ 2212 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 2213 sc->cbl_last = txp; 2214 sc->tx_queued++; 2215 /* 2216 * Issue a resume in case the CU has just suspended. 2217 */ 2218 fxp_scb_wait(sc); 2219 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2220 /* 2221 * Set a 5 second timer just in case we don't hear from the 2222 * card again. 2223 */ 2224 ifp->if_timer = 5; 2225 2226 return; 2227 } 2228 sc->need_mcsetup = 0; 2229 2230 /* 2231 * Initialize multicast setup descriptor. 2232 */ 2233 mcsp->next = sc->cbl_base; 2234 mcsp->mb_head = NULL; 2235 mcsp->cb_status = 0; 2236 mcsp->cb_command = FXP_CB_COMMAND_MCAS | 2237 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2238 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 2239 fxp_mc_addrs(sc); 2240 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 2241 sc->tx_queued = 1; 2242 2243 /* 2244 * Wait until command unit is not active. This should never 2245 * be the case when nothing is queued, but make sure anyway. 2246 */ 2247 count = 100; 2248 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2249 FXP_SCB_CUS_ACTIVE && --count) 2250 DELAY(10); 2251 if (count == 0) { 2252 if_printf(&sc->arpcom.ac_if, "command queue timeout\n"); 2253 return; 2254 } 2255 2256 /* 2257 * Start the multicast setup command. 2258 */ 2259 fxp_scb_wait(sc); 2260 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 2261 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2262 2263 ifp->if_timer = 2; 2264 return; 2265 } 2266 2267 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2268 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2269 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2270 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2271 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2272 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2273 2274 #define UCODE(x) x, sizeof(x) 2275 2276 struct ucode { 2277 u_int32_t revision; 2278 u_int32_t *ucode; 2279 int length; 2280 u_short int_delay_offset; 2281 u_short bundle_max_offset; 2282 } ucode_table[] = { 2283 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2284 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2285 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2286 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2287 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2288 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2289 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2290 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2291 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2292 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2293 { 0, NULL, 0, 0, 0 } 2294 }; 2295 2296 static void 2297 fxp_load_ucode(struct fxp_softc *sc) 2298 { 2299 struct ucode *uc; 2300 struct fxp_cb_ucode *cbp; 2301 2302 for (uc = ucode_table; uc->ucode != NULL; uc++) 2303 if (sc->revision == uc->revision) 2304 break; 2305 if (uc->ucode == NULL) 2306 return; 2307 cbp = (struct fxp_cb_ucode *)sc->cbl_base; 2308 cbp->cb_status = 0; 2309 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL; 2310 cbp->link_addr = -1; /* (no) next command */ 2311 memcpy(cbp->ucode, uc->ucode, uc->length); 2312 if (uc->int_delay_offset) 2313 *(u_short *)&cbp->ucode[uc->int_delay_offset] = 2314 sc->tunable_int_delay + sc->tunable_int_delay / 2; 2315 if (uc->bundle_max_offset) 2316 *(u_short *)&cbp->ucode[uc->bundle_max_offset] = 2317 sc->tunable_bundle_max; 2318 /* 2319 * Download the ucode to the chip. 2320 */ 2321 fxp_scb_wait(sc); 2322 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 2323 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2324 /* ...and wait for it to complete. */ 2325 fxp_dma_wait(&cbp->cb_status, sc); 2326 if_printf(&sc->arpcom.ac_if, 2327 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2328 sc->tunable_int_delay, 2329 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2330 sc->flags |= FXP_FLAG_UCODE; 2331 } 2332 2333 /* 2334 * Interrupt delay is expressed in microseconds, a multiplier is used 2335 * to convert this to the appropriate clock ticks before using. 2336 */ 2337 static int 2338 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2339 { 2340 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2341 } 2342 2343 static int 2344 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2345 { 2346 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2347 } 2348