1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.110.2.30 2003/06/12 16:47:05 mux Exp $ 29 * $DragonFly: src/sys/dev/netif/fxp/if_fxp.c,v 1.3 2003/08/07 21:17:02 dillon Exp $ 30 */ 31 32 /* 33 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/mbuf.h> 39 #include <sys/malloc.h> 40 /* #include <sys/mutex.h> */ 41 #include <sys/kernel.h> 42 #include <sys/socket.h> 43 #include <sys/sysctl.h> 44 45 #include <net/if.h> 46 #include <net/if_dl.h> 47 #include <net/if_media.h> 48 49 #ifdef NS 50 #include <netns/ns.h> 51 #include <netns/ns_if.h> 52 #endif 53 54 #include <net/bpf.h> 55 #include <sys/sockio.h> 56 #include <sys/bus.h> 57 #include <machine/bus.h> 58 #include <sys/rman.h> 59 #include <machine/resource.h> 60 61 #include <net/ethernet.h> 62 #include <net/if_arp.h> 63 64 #include <vm/vm.h> /* for vtophys */ 65 #include <vm/pmap.h> /* for vtophys */ 66 #include <machine/clock.h> /* for DELAY */ 67 68 #include <net/if_types.h> 69 #include <net/vlan/if_vlan_var.h> 70 71 #include <bus/pci/pcivar.h> 72 #include <bus/pci/pcireg.h> /* for PCIM_CMD_xxx */ 73 74 #include "../mii_layer/mii.h" 75 #include "../mii_layer/miivar.h" 76 77 #include "if_fxpreg.h" 78 #include "if_fxpvar.h" 79 #include "rcvbundl.h" 80 81 MODULE_DEPEND(fxp, miibus, 1, 1, 1); 82 #include "miibus_if.h" 83 84 /* 85 * NOTE! On the Alpha, we have an alignment constraint. The 86 * card DMAs the packet immediately following the RFA. However, 87 * the first thing in the packet is a 14-byte Ethernet header. 88 * This means that the packet is misaligned. To compensate, 89 * we actually offset the RFA 2 bytes into the cluster. This 90 * alignes the packet after the Ethernet header at a 32-bit 91 * boundary. HOWEVER! This means that the RFA is misaligned! 92 */ 93 #define RFA_ALIGNMENT_FUDGE 2 94 95 /* 96 * Set initial transmit threshold at 64 (512 bytes). This is 97 * increased by 64 (512 bytes) at a time, to maximum of 192 98 * (1536 bytes), if an underrun occurs. 99 */ 100 static int tx_threshold = 64; 101 102 /* 103 * The configuration byte map has several undefined fields which 104 * must be one or must be zero. Set up a template for these bits 105 * only, (assuming a 82557 chip) leaving the actual configuration 106 * to fxp_init. 107 * 108 * See struct fxp_cb_config for the bit definitions. 109 */ 110 static u_char fxp_cb_config_template[] = { 111 0x0, 0x0, /* cb_status */ 112 0x0, 0x0, /* cb_command */ 113 0x0, 0x0, 0x0, 0x0, /* link_addr */ 114 0x0, /* 0 */ 115 0x0, /* 1 */ 116 0x0, /* 2 */ 117 0x0, /* 3 */ 118 0x0, /* 4 */ 119 0x0, /* 5 */ 120 0x32, /* 6 */ 121 0x0, /* 7 */ 122 0x0, /* 8 */ 123 0x0, /* 9 */ 124 0x6, /* 10 */ 125 0x0, /* 11 */ 126 0x0, /* 12 */ 127 0x0, /* 13 */ 128 0xf2, /* 14 */ 129 0x48, /* 15 */ 130 0x0, /* 16 */ 131 0x40, /* 17 */ 132 0xf0, /* 18 */ 133 0x0, /* 19 */ 134 0x3f, /* 20 */ 135 0x5 /* 21 */ 136 }; 137 138 struct fxp_ident { 139 u_int16_t devid; 140 char *name; 141 }; 142 143 /* 144 * Claim various Intel PCI device identifiers for this driver. The 145 * sub-vendor and sub-device field are extensively used to identify 146 * particular variants, but we don't currently differentiate between 147 * them. 148 */ 149 static struct fxp_ident fxp_ident_table[] = { 150 { 0x1029, "Intel 82559 PCI/CardBus Pro/100" }, 151 { 0x1030, "Intel 82559 Pro/100 Ethernet" }, 152 { 0x1031, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 153 { 0x1032, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 154 { 0x1033, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 155 { 0x1034, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 156 { 0x1035, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 157 { 0x1036, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 158 { 0x1037, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 159 { 0x1038, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 160 { 0x1039, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 161 { 0x103A, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 162 { 0x103B, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 163 { 0x103C, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 164 { 0x103D, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 165 { 0x103E, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 166 { 0x1050, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 167 { 0x1059, "Intel 82551QM Pro/100 M Mobile Connection" }, 168 { 0x1209, "Intel 82559ER Embedded 10/100 Ethernet" }, 169 { 0x1229, "Intel 82557/8/9 EtherExpress Pro/100(B) Ethernet" }, 170 { 0x2449, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 171 { 0, NULL }, 172 }; 173 174 static int fxp_probe(device_t dev); 175 static int fxp_attach(device_t dev); 176 static int fxp_detach(device_t dev); 177 static int fxp_shutdown(device_t dev); 178 static int fxp_suspend(device_t dev); 179 static int fxp_resume(device_t dev); 180 181 static void fxp_intr(void *xsc); 182 static void fxp_intr_body(struct fxp_softc *sc, 183 u_int8_t statack, int count); 184 185 static void fxp_init(void *xsc); 186 static void fxp_tick(void *xsc); 187 static void fxp_powerstate_d0(device_t dev); 188 static void fxp_start(struct ifnet *ifp); 189 static void fxp_stop(struct fxp_softc *sc); 190 static void fxp_release(struct fxp_softc *sc); 191 static int fxp_ioctl(struct ifnet *ifp, u_long command, 192 caddr_t data); 193 static void fxp_watchdog(struct ifnet *ifp); 194 static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm); 195 static int fxp_mc_addrs(struct fxp_softc *sc); 196 static void fxp_mc_setup(struct fxp_softc *sc); 197 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 198 int autosize); 199 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 200 u_int16_t data); 201 static void fxp_autosize_eeprom(struct fxp_softc *sc); 202 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 203 int offset, int words); 204 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 205 int offset, int words); 206 static int fxp_ifmedia_upd(struct ifnet *ifp); 207 static void fxp_ifmedia_sts(struct ifnet *ifp, 208 struct ifmediareq *ifmr); 209 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 210 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 211 struct ifmediareq *ifmr); 212 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 213 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 214 int value); 215 static void fxp_load_ucode(struct fxp_softc *sc); 216 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 217 int low, int high); 218 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 219 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 220 static __inline void fxp_lwcopy(volatile u_int32_t *src, 221 volatile u_int32_t *dst); 222 static __inline void fxp_scb_wait(struct fxp_softc *sc); 223 static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 224 static __inline void fxp_dma_wait(volatile u_int16_t *status, 225 struct fxp_softc *sc); 226 227 static device_method_t fxp_methods[] = { 228 /* Device interface */ 229 DEVMETHOD(device_probe, fxp_probe), 230 DEVMETHOD(device_attach, fxp_attach), 231 DEVMETHOD(device_detach, fxp_detach), 232 DEVMETHOD(device_shutdown, fxp_shutdown), 233 DEVMETHOD(device_suspend, fxp_suspend), 234 DEVMETHOD(device_resume, fxp_resume), 235 236 /* MII interface */ 237 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 238 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 239 240 { 0, 0 } 241 }; 242 243 static driver_t fxp_driver = { 244 "fxp", 245 fxp_methods, 246 sizeof(struct fxp_softc), 247 }; 248 249 static devclass_t fxp_devclass; 250 251 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 252 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 253 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 254 255 static int fxp_rnr; 256 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 257 258 /* 259 * Inline function to copy a 16-bit aligned 32-bit quantity. 260 */ 261 static __inline void 262 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst) 263 { 264 #ifdef __i386__ 265 *dst = *src; 266 #else 267 volatile u_int16_t *a = (volatile u_int16_t *)src; 268 volatile u_int16_t *b = (volatile u_int16_t *)dst; 269 270 b[0] = a[0]; 271 b[1] = a[1]; 272 #endif 273 } 274 275 /* 276 * Wait for the previous command to be accepted (but not necessarily 277 * completed). 278 */ 279 static __inline void 280 fxp_scb_wait(struct fxp_softc *sc) 281 { 282 int i = 10000; 283 284 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 285 DELAY(2); 286 if (i == 0) 287 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 288 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 289 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 290 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 291 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 292 } 293 294 static __inline void 295 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 296 { 297 298 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 299 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 300 fxp_scb_wait(sc); 301 } 302 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 303 } 304 305 static __inline void 306 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc) 307 { 308 int i = 10000; 309 310 while (!(*status & FXP_CB_STATUS_C) && --i) 311 DELAY(2); 312 if (i == 0) 313 device_printf(sc->dev, "DMA timeout\n"); 314 } 315 316 /* 317 * Return identification string if this is device is ours. 318 */ 319 static int 320 fxp_probe(device_t dev) 321 { 322 u_int16_t devid; 323 struct fxp_ident *ident; 324 325 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 326 devid = pci_get_device(dev); 327 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 328 if (ident->devid == devid) { 329 device_set_desc(dev, ident->name); 330 return (0); 331 } 332 } 333 } 334 return (ENXIO); 335 } 336 337 static void 338 fxp_powerstate_d0(device_t dev) 339 { 340 #if __FreeBSD_version >= 430002 341 u_int32_t iobase, membase, irq; 342 343 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 344 /* Save important PCI config data. */ 345 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 346 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 347 irq = pci_read_config(dev, PCIR_INTLINE, 4); 348 349 /* Reset the power state. */ 350 device_printf(dev, "chip is in D%d power mode " 351 "-- setting to D0\n", pci_get_powerstate(dev)); 352 353 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 354 355 /* Restore PCI config data. */ 356 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 357 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 358 pci_write_config(dev, PCIR_INTLINE, irq, 4); 359 } 360 #endif 361 } 362 363 static int 364 fxp_attach(device_t dev) 365 { 366 int error = 0; 367 struct fxp_softc *sc = device_get_softc(dev); 368 struct ifnet *ifp; 369 u_int32_t val; 370 u_int16_t data; 371 int i, rid, m1, m2, prefer_iomap; 372 int s; 373 374 bzero(sc, sizeof(*sc)); 375 sc->dev = dev; 376 callout_handle_init(&sc->stat_ch); 377 sysctl_ctx_init(&sc->sysctl_ctx); 378 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 379 380 s = splimp(); 381 382 /* 383 * Enable bus mastering. Enable memory space too, in case 384 * BIOS/Prom forgot about it. 385 */ 386 val = pci_read_config(dev, PCIR_COMMAND, 2); 387 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 388 pci_write_config(dev, PCIR_COMMAND, val, 2); 389 val = pci_read_config(dev, PCIR_COMMAND, 2); 390 391 fxp_powerstate_d0(dev); 392 393 /* 394 * Figure out which we should try first - memory mapping or i/o mapping? 395 * We default to memory mapping. Then we accept an override from the 396 * command line. Then we check to see which one is enabled. 397 */ 398 m1 = PCIM_CMD_MEMEN; 399 m2 = PCIM_CMD_PORTEN; 400 prefer_iomap = 0; 401 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 402 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 403 m1 = PCIM_CMD_PORTEN; 404 m2 = PCIM_CMD_MEMEN; 405 } 406 407 if (val & m1) { 408 sc->rtp = 409 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 410 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 411 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 412 0, ~0, 1, RF_ACTIVE); 413 } 414 if (sc->mem == NULL && (val & m2)) { 415 sc->rtp = 416 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 417 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 418 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 419 0, ~0, 1, RF_ACTIVE); 420 } 421 422 if (!sc->mem) { 423 device_printf(dev, "could not map device registers\n"); 424 error = ENXIO; 425 goto fail; 426 } 427 if (bootverbose) { 428 device_printf(dev, "using %s space register mapping\n", 429 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 430 } 431 432 sc->sc_st = rman_get_bustag(sc->mem); 433 sc->sc_sh = rman_get_bushandle(sc->mem); 434 435 /* 436 * Allocate our interrupt. 437 */ 438 rid = 0; 439 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 440 RF_SHAREABLE | RF_ACTIVE); 441 if (sc->irq == NULL) { 442 device_printf(dev, "could not map interrupt\n"); 443 error = ENXIO; 444 goto fail; 445 } 446 447 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, 448 fxp_intr, sc, &sc->ih); 449 if (error) { 450 device_printf(dev, "could not setup irq\n"); 451 goto fail; 452 } 453 454 /* 455 * Reset to a stable state. 456 */ 457 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 458 DELAY(10); 459 460 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 461 M_DEVBUF, M_NOWAIT | M_ZERO); 462 if (sc->cbl_base == NULL) 463 goto failmem; 464 465 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, 466 M_NOWAIT | M_ZERO); 467 if (sc->fxp_stats == NULL) 468 goto failmem; 469 470 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT); 471 if (sc->mcsp == NULL) 472 goto failmem; 473 474 /* 475 * Pre-allocate our receive buffers. 476 */ 477 for (i = 0; i < FXP_NRFABUFS; i++) { 478 if (fxp_add_rfabuf(sc, NULL) != 0) { 479 goto failmem; 480 } 481 } 482 483 /* 484 * Find out how large of an SEEPROM we have. 485 */ 486 fxp_autosize_eeprom(sc); 487 488 /* 489 * Determine whether we must use the 503 serial interface. 490 */ 491 fxp_read_eeprom(sc, &data, 6, 1); 492 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 493 (data & FXP_PHY_SERIAL_ONLY)) 494 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 495 496 /* 497 * Create the sysctl tree 498 */ 499 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 500 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 501 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 502 if (sc->sysctl_tree == NULL) 503 goto fail; 504 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 505 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 506 &sc->tunable_int_delay, 0, &sysctl_hw_fxp_int_delay, "I", 507 "FXP driver receive interrupt microcode bundling delay"); 508 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 509 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 510 &sc->tunable_bundle_max, 0, &sysctl_hw_fxp_bundle_max, "I", 511 "FXP driver receive interrupt microcode bundle size limit"); 512 513 /* 514 * Pull in device tunables. 515 */ 516 sc->tunable_int_delay = TUNABLE_INT_DELAY; 517 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 518 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 519 "int_delay", &sc->tunable_int_delay); 520 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 521 "bundle_max", &sc->tunable_bundle_max); 522 523 /* 524 * Find out the chip revision; lump all 82557 revs together. 525 */ 526 fxp_read_eeprom(sc, &data, 5, 1); 527 if ((data >> 8) == 1) 528 sc->revision = FXP_REV_82557; 529 else 530 sc->revision = pci_get_revid(dev); 531 532 /* 533 * Enable workarounds for certain chip revision deficiencies. 534 * 535 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 536 * some systems based a normal 82559 design, have a defect where 537 * the chip can cause a PCI protocol violation if it receives 538 * a CU_RESUME command when it is entering the IDLE state. The 539 * workaround is to disable Dynamic Standby Mode, so the chip never 540 * deasserts CLKRUN#, and always remains in an active state. 541 * 542 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 543 */ 544 i = pci_get_device(dev); 545 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 546 sc->revision >= FXP_REV_82559_A0) { 547 fxp_read_eeprom(sc, &data, 10, 1); 548 if (data & 0x02) { /* STB enable */ 549 u_int16_t cksum; 550 int i; 551 552 device_printf(dev, 553 "Disabling dynamic standby mode in EEPROM\n"); 554 data &= ~0x02; 555 fxp_write_eeprom(sc, &data, 10, 1); 556 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 557 cksum = 0; 558 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 559 fxp_read_eeprom(sc, &data, i, 1); 560 cksum += data; 561 } 562 i = (1 << sc->eeprom_size) - 1; 563 cksum = 0xBABA - cksum; 564 fxp_read_eeprom(sc, &data, i, 1); 565 fxp_write_eeprom(sc, &cksum, i, 1); 566 device_printf(dev, 567 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 568 i, data, cksum); 569 #if 1 570 /* 571 * If the user elects to continue, try the software 572 * workaround, as it is better than nothing. 573 */ 574 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 575 #endif 576 } 577 } 578 579 /* 580 * If we are not a 82557 chip, we can enable extended features. 581 */ 582 if (sc->revision != FXP_REV_82557) { 583 /* 584 * If MWI is enabled in the PCI configuration, and there 585 * is a valid cacheline size (8 or 16 dwords), then tell 586 * the board to turn on MWI. 587 */ 588 if (val & PCIM_CMD_MWRICEN && 589 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 590 sc->flags |= FXP_FLAG_MWI_ENABLE; 591 592 /* turn on the extended TxCB feature */ 593 sc->flags |= FXP_FLAG_EXT_TXCB; 594 595 /* enable reception of long frames for VLAN */ 596 sc->flags |= FXP_FLAG_LONG_PKT_EN; 597 } 598 599 /* 600 * Read MAC address. 601 */ 602 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3); 603 device_printf(dev, "Ethernet address %6D%s\n", 604 sc->arpcom.ac_enaddr, ":", 605 sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : ""); 606 if (bootverbose) { 607 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 608 pci_get_vendor(dev), pci_get_device(dev), 609 pci_get_subvendor(dev), pci_get_subdevice(dev), 610 pci_get_revid(dev)); 611 fxp_read_eeprom(sc, &data, 10, 1); 612 device_printf(dev, "Dynamic Standby mode is %s\n", 613 data & 0x02 ? "enabled" : "disabled"); 614 } 615 616 /* 617 * If this is only a 10Mbps device, then there is no MII, and 618 * the PHY will use a serial interface instead. 619 * 620 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 621 * doesn't have a programming interface of any sort. The 622 * media is sensed automatically based on how the link partner 623 * is configured. This is, in essence, manual configuration. 624 */ 625 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 626 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 627 fxp_serial_ifmedia_sts); 628 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 629 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 630 } else { 631 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 632 fxp_ifmedia_sts)) { 633 device_printf(dev, "MII without any PHY!\n"); 634 error = ENXIO; 635 goto fail; 636 } 637 } 638 639 ifp = &sc->arpcom.ac_if; 640 ifp->if_unit = device_get_unit(dev); 641 ifp->if_name = "fxp"; 642 ifp->if_output = ether_output; 643 ifp->if_baudrate = 100000000; 644 ifp->if_init = fxp_init; 645 ifp->if_softc = sc; 646 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 647 ifp->if_ioctl = fxp_ioctl; 648 ifp->if_start = fxp_start; 649 ifp->if_watchdog = fxp_watchdog; 650 651 /* 652 * Attach the interface. 653 */ 654 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 655 656 /* 657 * Tell the upper layer(s) we support long frames. 658 */ 659 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 660 661 /* 662 * Let the system queue as many packets as we have available 663 * TX descriptors. 664 */ 665 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 666 667 splx(s); 668 return (0); 669 670 failmem: 671 device_printf(dev, "Failed to malloc memory\n"); 672 error = ENOMEM; 673 fail: 674 splx(s); 675 fxp_release(sc); 676 return (error); 677 } 678 679 /* 680 * release all resources 681 */ 682 static void 683 fxp_release(struct fxp_softc *sc) 684 { 685 686 bus_generic_detach(sc->dev); 687 if (sc->miibus) 688 device_delete_child(sc->dev, sc->miibus); 689 690 if (sc->cbl_base) 691 free(sc->cbl_base, M_DEVBUF); 692 if (sc->fxp_stats) 693 free(sc->fxp_stats, M_DEVBUF); 694 if (sc->mcsp) 695 free(sc->mcsp, M_DEVBUF); 696 if (sc->rfa_headm) 697 m_freem(sc->rfa_headm); 698 699 if (sc->ih) 700 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 701 if (sc->irq) 702 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 703 if (sc->mem) 704 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 705 706 sysctl_ctx_free(&sc->sysctl_ctx); 707 708 mtx_destroy(&sc->sc_mtx); 709 } 710 711 /* 712 * Detach interface. 713 */ 714 static int 715 fxp_detach(device_t dev) 716 { 717 struct fxp_softc *sc = device_get_softc(dev); 718 int s; 719 720 /* disable interrupts */ 721 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 722 723 s = splimp(); 724 725 /* 726 * Stop DMA and drop transmit queue. 727 */ 728 fxp_stop(sc); 729 730 /* 731 * Close down routes etc. 732 */ 733 ether_ifdetach(&sc->arpcom.ac_if, ETHER_BPF_SUPPORTED); 734 735 /* 736 * Free all media structures. 737 */ 738 ifmedia_removeall(&sc->sc_media); 739 740 splx(s); 741 742 /* Release our allocated resources. */ 743 fxp_release(sc); 744 745 return (0); 746 } 747 748 /* 749 * Device shutdown routine. Called at system shutdown after sync. The 750 * main purpose of this routine is to shut off receiver DMA so that 751 * kernel memory doesn't get clobbered during warmboot. 752 */ 753 static int 754 fxp_shutdown(device_t dev) 755 { 756 /* 757 * Make sure that DMA is disabled prior to reboot. Not doing 758 * do could allow DMA to corrupt kernel memory during the 759 * reboot before the driver initializes. 760 */ 761 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 762 return (0); 763 } 764 765 /* 766 * Device suspend routine. Stop the interface and save some PCI 767 * settings in case the BIOS doesn't restore them properly on 768 * resume. 769 */ 770 static int 771 fxp_suspend(device_t dev) 772 { 773 struct fxp_softc *sc = device_get_softc(dev); 774 int i, s; 775 776 s = splimp(); 777 778 fxp_stop(sc); 779 780 for (i = 0; i < 5; i++) 781 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 782 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 783 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 784 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 785 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 786 787 sc->suspended = 1; 788 789 splx(s); 790 return (0); 791 } 792 793 /* 794 * Device resume routine. Restore some PCI settings in case the BIOS 795 * doesn't, re-enable busmastering, and restart the interface if 796 * appropriate. 797 */ 798 static int 799 fxp_resume(device_t dev) 800 { 801 struct fxp_softc *sc = device_get_softc(dev); 802 struct ifnet *ifp = &sc->sc_if; 803 u_int16_t pci_command; 804 int i, s; 805 806 s = splimp(); 807 808 fxp_powerstate_d0(dev); 809 810 /* better way to do this? */ 811 for (i = 0; i < 5; i++) 812 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 813 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 814 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 815 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 816 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 817 818 /* reenable busmastering */ 819 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 820 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 821 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 822 823 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 824 DELAY(10); 825 826 /* reinitialize interface if necessary */ 827 if (ifp->if_flags & IFF_UP) 828 fxp_init(sc); 829 830 sc->suspended = 0; 831 832 splx(s); 833 return (0); 834 } 835 836 static void 837 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 838 { 839 u_int16_t reg; 840 int x; 841 842 /* 843 * Shift in data. 844 */ 845 for (x = 1 << (length - 1); x; x >>= 1) { 846 if (data & x) 847 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 848 else 849 reg = FXP_EEPROM_EECS; 850 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 851 DELAY(1); 852 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 853 DELAY(1); 854 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 855 DELAY(1); 856 } 857 } 858 859 /* 860 * Read from the serial EEPROM. Basically, you manually shift in 861 * the read opcode (one bit at a time) and then shift in the address, 862 * and then you shift out the data (all of this one bit at a time). 863 * The word size is 16 bits, so you have to provide the address for 864 * every 16 bits of data. 865 */ 866 static u_int16_t 867 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 868 { 869 u_int16_t reg, data; 870 int x; 871 872 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 873 /* 874 * Shift in read opcode. 875 */ 876 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 877 /* 878 * Shift in address. 879 */ 880 data = 0; 881 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 882 if (offset & x) 883 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 884 else 885 reg = FXP_EEPROM_EECS; 886 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 887 DELAY(1); 888 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 889 DELAY(1); 890 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 891 DELAY(1); 892 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 893 data++; 894 if (autosize && reg == 0) { 895 sc->eeprom_size = data; 896 break; 897 } 898 } 899 /* 900 * Shift out data. 901 */ 902 data = 0; 903 reg = FXP_EEPROM_EECS; 904 for (x = 1 << 15; x; x >>= 1) { 905 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 906 DELAY(1); 907 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 908 data |= x; 909 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 910 DELAY(1); 911 } 912 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 913 DELAY(1); 914 915 return (data); 916 } 917 918 static void 919 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 920 { 921 int i; 922 923 /* 924 * Erase/write enable. 925 */ 926 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 927 fxp_eeprom_shiftin(sc, 0x4, 3); 928 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 929 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 930 DELAY(1); 931 /* 932 * Shift in write opcode, address, data. 933 */ 934 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 935 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 936 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 937 fxp_eeprom_shiftin(sc, data, 16); 938 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 939 DELAY(1); 940 /* 941 * Wait for EEPROM to finish up. 942 */ 943 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 944 DELAY(1); 945 for (i = 0; i < 1000; i++) { 946 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 947 break; 948 DELAY(50); 949 } 950 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 951 DELAY(1); 952 /* 953 * Erase/write disable. 954 */ 955 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 956 fxp_eeprom_shiftin(sc, 0x4, 3); 957 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 958 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 959 DELAY(1); 960 } 961 962 /* 963 * From NetBSD: 964 * 965 * Figure out EEPROM size. 966 * 967 * 559's can have either 64-word or 256-word EEPROMs, the 558 968 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 969 * talks about the existance of 16 to 256 word EEPROMs. 970 * 971 * The only known sizes are 64 and 256, where the 256 version is used 972 * by CardBus cards to store CIS information. 973 * 974 * The address is shifted in msb-to-lsb, and after the last 975 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 976 * after which follows the actual data. We try to detect this zero, by 977 * probing the data-out bit in the EEPROM control register just after 978 * having shifted in a bit. If the bit is zero, we assume we've 979 * shifted enough address bits. The data-out should be tri-state, 980 * before this, which should translate to a logical one. 981 */ 982 static void 983 fxp_autosize_eeprom(struct fxp_softc *sc) 984 { 985 986 /* guess maximum size of 256 words */ 987 sc->eeprom_size = 8; 988 989 /* autosize */ 990 (void) fxp_eeprom_getword(sc, 0, 1); 991 } 992 993 static void 994 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 995 { 996 int i; 997 998 for (i = 0; i < words; i++) 999 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1000 } 1001 1002 static void 1003 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1004 { 1005 int i; 1006 1007 for (i = 0; i < words; i++) 1008 fxp_eeprom_putword(sc, offset + i, data[i]); 1009 } 1010 1011 /* 1012 * Start packet transmission on the interface. 1013 */ 1014 static void 1015 fxp_start(struct ifnet *ifp) 1016 { 1017 struct fxp_softc *sc = ifp->if_softc; 1018 struct fxp_cb_tx *txp; 1019 1020 /* 1021 * See if we need to suspend xmit until the multicast filter 1022 * has been reprogrammed (which can only be done at the head 1023 * of the command chain). 1024 */ 1025 if (sc->need_mcsetup) { 1026 return; 1027 } 1028 1029 txp = NULL; 1030 1031 /* 1032 * We're finished if there is nothing more to add to the list or if 1033 * we're all filled up with buffers to transmit. 1034 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1035 * a NOP command when needed. 1036 */ 1037 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 1038 struct mbuf *m, *mb_head; 1039 int segment; 1040 1041 /* 1042 * Grab a packet to transmit. 1043 */ 1044 IF_DEQUEUE(&ifp->if_snd, mb_head); 1045 1046 /* 1047 * Get pointer to next available tx desc. 1048 */ 1049 txp = sc->cbl_last->next; 1050 1051 /* 1052 * Go through each of the mbufs in the chain and initialize 1053 * the transmit buffer descriptors with the physical address 1054 * and size of the mbuf. 1055 */ 1056 tbdinit: 1057 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 1058 if (m->m_len != 0) { 1059 if (segment == FXP_NTXSEG) 1060 break; 1061 txp->tbd[segment].tb_addr = 1062 vtophys(mtod(m, vm_offset_t)); 1063 txp->tbd[segment].tb_size = m->m_len; 1064 segment++; 1065 } 1066 } 1067 if (m != NULL) { 1068 struct mbuf *mn; 1069 1070 /* 1071 * We ran out of segments. We have to recopy this 1072 * mbuf chain first. Bail out if we can't get the 1073 * new buffers. 1074 */ 1075 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1076 if (mn == NULL) { 1077 m_freem(mb_head); 1078 break; 1079 } 1080 if (mb_head->m_pkthdr.len > MHLEN) { 1081 MCLGET(mn, M_DONTWAIT); 1082 if ((mn->m_flags & M_EXT) == 0) { 1083 m_freem(mn); 1084 m_freem(mb_head); 1085 break; 1086 } 1087 } 1088 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1089 mtod(mn, caddr_t)); 1090 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1091 m_freem(mb_head); 1092 mb_head = mn; 1093 goto tbdinit; 1094 } 1095 1096 txp->tbd_number = segment; 1097 txp->mb_head = mb_head; 1098 txp->cb_status = 0; 1099 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1100 txp->cb_command = 1101 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1102 FXP_CB_COMMAND_S; 1103 } else { 1104 txp->cb_command = 1105 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1106 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1107 /* 1108 * Set a 5 second timer just in case we don't hear 1109 * from the card again. 1110 */ 1111 ifp->if_timer = 5; 1112 } 1113 txp->tx_threshold = tx_threshold; 1114 1115 /* 1116 * Advance the end of list forward. 1117 */ 1118 1119 #ifdef __alpha__ 1120 /* 1121 * On platforms which can't access memory in 16-bit 1122 * granularities, we must prevent the card from DMA'ing 1123 * up the status while we update the command field. 1124 * This could cause us to overwrite the completion status. 1125 */ 1126 atomic_clear_short(&sc->cbl_last->cb_command, 1127 FXP_CB_COMMAND_S); 1128 #else 1129 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1130 #endif /*__alpha__*/ 1131 sc->cbl_last = txp; 1132 1133 /* 1134 * Advance the beginning of the list forward if there are 1135 * no other packets queued (when nothing is queued, cbl_first 1136 * sits on the last TxCB that was sent out). 1137 */ 1138 if (sc->tx_queued == 0) 1139 sc->cbl_first = txp; 1140 1141 sc->tx_queued++; 1142 1143 /* 1144 * Pass packet to bpf if there is a listener. 1145 */ 1146 if (ifp->if_bpf) 1147 bpf_mtap(ifp, mb_head); 1148 } 1149 1150 /* 1151 * We're finished. If we added to the list, issue a RESUME to get DMA 1152 * going again if suspended. 1153 */ 1154 if (txp != NULL) { 1155 fxp_scb_wait(sc); 1156 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1157 } 1158 } 1159 1160 #ifdef DEVICE_POLLING 1161 static poll_handler_t fxp_poll; 1162 1163 static void 1164 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1165 { 1166 struct fxp_softc *sc = ifp->if_softc; 1167 u_int8_t statack; 1168 1169 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1170 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1171 return; 1172 } 1173 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1174 FXP_SCB_STATACK_FR; 1175 if (cmd == POLL_AND_CHECK_STATUS) { 1176 u_int8_t tmp; 1177 1178 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1179 if (tmp == 0xff || tmp == 0) 1180 return; /* nothing to do */ 1181 tmp &= ~statack; 1182 /* ack what we can */ 1183 if (tmp != 0) 1184 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1185 statack |= tmp; 1186 } 1187 fxp_intr_body(sc, statack, count); 1188 } 1189 #endif /* DEVICE_POLLING */ 1190 1191 /* 1192 * Process interface interrupts. 1193 */ 1194 static void 1195 fxp_intr(void *xsc) 1196 { 1197 struct fxp_softc *sc = xsc; 1198 u_int8_t statack; 1199 1200 #ifdef DEVICE_POLLING 1201 struct ifnet *ifp = &sc->sc_if; 1202 1203 if (ifp->if_ipending & IFF_POLLING) 1204 return; 1205 if (ether_poll_register(fxp_poll, ifp)) { 1206 /* disable interrupts */ 1207 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1208 fxp_poll(ifp, 0, 1); 1209 return; 1210 } 1211 #endif 1212 1213 if (sc->suspended) { 1214 return; 1215 } 1216 1217 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1218 /* 1219 * It should not be possible to have all bits set; the 1220 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1221 * all bits are set, this may indicate that the card has 1222 * been physically ejected, so ignore it. 1223 */ 1224 if (statack == 0xff) 1225 return; 1226 1227 /* 1228 * First ACK all the interrupts in this pass. 1229 */ 1230 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1231 fxp_intr_body(sc, statack, -1); 1232 } 1233 } 1234 1235 static void 1236 fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count) 1237 { 1238 struct ifnet *ifp = &sc->sc_if; 1239 struct mbuf *m; 1240 struct fxp_rfa *rfa; 1241 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1242 1243 if (rnr) 1244 fxp_rnr++; 1245 #ifdef DEVICE_POLLING 1246 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1247 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1248 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1249 rnr = 1; 1250 } 1251 #endif 1252 1253 /* 1254 * Free any finished transmit mbuf chains. 1255 * 1256 * Handle the CNA event likt a CXTNO event. It used to 1257 * be that this event (control unit not ready) was not 1258 * encountered, but it is now with the SMPng modifications. 1259 * The exact sequence of events that occur when the interface 1260 * is brought up are different now, and if this event 1261 * goes unhandled, the configuration/rxfilter setup sequence 1262 * can stall for several seconds. The result is that no 1263 * packets go out onto the wire for about 5 to 10 seconds 1264 * after the interface is ifconfig'ed for the first time. 1265 */ 1266 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1267 struct fxp_cb_tx *txp; 1268 1269 for (txp = sc->cbl_first; sc->tx_queued && 1270 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1271 txp = txp->next) { 1272 if (txp->mb_head != NULL) { 1273 m_freem(txp->mb_head); 1274 txp->mb_head = NULL; 1275 } 1276 sc->tx_queued--; 1277 } 1278 sc->cbl_first = txp; 1279 ifp->if_timer = 0; 1280 if (sc->tx_queued == 0) { 1281 if (sc->need_mcsetup) 1282 fxp_mc_setup(sc); 1283 } 1284 /* 1285 * Try to start more packets transmitting. 1286 */ 1287 if (ifp->if_snd.ifq_head != NULL) 1288 fxp_start(ifp); 1289 } 1290 1291 /* 1292 * Just return if nothing happened on the receive side. 1293 */ 1294 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1295 return; 1296 1297 /* 1298 * Process receiver interrupts. If a no-resource (RNR) 1299 * condition exists, get whatever packets we can and 1300 * re-start the receiver. 1301 * 1302 * When using polling, we do not process the list to completion, 1303 * so when we get an RNR interrupt we must defer the restart 1304 * until we hit the last buffer with the C bit set. 1305 * If we run out of cycles and rfa_headm has the C bit set, 1306 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1307 * that the info will be used in the subsequent polling cycle. 1308 */ 1309 for (;;) { 1310 m = sc->rfa_headm; 1311 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1312 RFA_ALIGNMENT_FUDGE); 1313 1314 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1315 if (count >= 0 && count-- == 0) { 1316 if (rnr) { 1317 /* Defer RNR processing until the next time. */ 1318 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1319 rnr = 0; 1320 } 1321 break; 1322 } 1323 #endif /* DEVICE_POLLING */ 1324 1325 if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0) 1326 break; 1327 1328 /* 1329 * Remove first packet from the chain. 1330 */ 1331 sc->rfa_headm = m->m_next; 1332 m->m_next = NULL; 1333 1334 /* 1335 * Add a new buffer to the receive chain. 1336 * If this fails, the old buffer is recycled 1337 * instead. 1338 */ 1339 if (fxp_add_rfabuf(sc, m) == 0) { 1340 int total_len; 1341 1342 /* 1343 * Fetch packet length (the top 2 bits of 1344 * actual_size are flags set by the controller 1345 * upon completion), and drop the packet in case 1346 * of bogus length or CRC errors. 1347 */ 1348 total_len = rfa->actual_size & 0x3fff; 1349 if (total_len < sizeof(struct ether_header) || 1350 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1351 sizeof(struct fxp_rfa) || 1352 rfa->rfa_status & FXP_RFA_STATUS_CRC) { 1353 m_freem(m); 1354 continue; 1355 } 1356 m->m_pkthdr.len = m->m_len = total_len; 1357 ether_input(ifp, NULL, m); 1358 } 1359 } 1360 if (rnr) { 1361 fxp_scb_wait(sc); 1362 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1363 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1364 RFA_ALIGNMENT_FUDGE); 1365 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1366 } 1367 } 1368 1369 /* 1370 * Update packet in/out/collision statistics. The i82557 doesn't 1371 * allow you to access these counters without doing a fairly 1372 * expensive DMA to get _all_ of the statistics it maintains, so 1373 * we do this operation here only once per second. The statistics 1374 * counters in the kernel are updated from the previous dump-stats 1375 * DMA and then a new dump-stats DMA is started. The on-chip 1376 * counters are zeroed when the DMA completes. If we can't start 1377 * the DMA immediately, we don't wait - we just prepare to read 1378 * them again next time. 1379 */ 1380 static void 1381 fxp_tick(void *xsc) 1382 { 1383 struct fxp_softc *sc = xsc; 1384 struct ifnet *ifp = &sc->sc_if; 1385 struct fxp_stats *sp = sc->fxp_stats; 1386 struct fxp_cb_tx *txp; 1387 int s; 1388 1389 ifp->if_opackets += sp->tx_good; 1390 ifp->if_collisions += sp->tx_total_collisions; 1391 if (sp->rx_good) { 1392 ifp->if_ipackets += sp->rx_good; 1393 sc->rx_idle_secs = 0; 1394 } else { 1395 /* 1396 * Receiver's been idle for another second. 1397 */ 1398 sc->rx_idle_secs++; 1399 } 1400 ifp->if_ierrors += 1401 sp->rx_crc_errors + 1402 sp->rx_alignment_errors + 1403 sp->rx_rnr_errors + 1404 sp->rx_overrun_errors; 1405 /* 1406 * If any transmit underruns occured, bump up the transmit 1407 * threshold by another 512 bytes (64 * 8). 1408 */ 1409 if (sp->tx_underruns) { 1410 ifp->if_oerrors += sp->tx_underruns; 1411 if (tx_threshold < 192) 1412 tx_threshold += 64; 1413 } 1414 s = splimp(); 1415 /* 1416 * Release any xmit buffers that have completed DMA. This isn't 1417 * strictly necessary to do here, but it's advantagous for mbufs 1418 * with external storage to be released in a timely manner rather 1419 * than being defered for a potentially long time. This limits 1420 * the delay to a maximum of one second. 1421 */ 1422 for (txp = sc->cbl_first; sc->tx_queued && 1423 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1424 txp = txp->next) { 1425 if (txp->mb_head != NULL) { 1426 m_freem(txp->mb_head); 1427 txp->mb_head = NULL; 1428 } 1429 sc->tx_queued--; 1430 } 1431 sc->cbl_first = txp; 1432 /* 1433 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1434 * then assume the receiver has locked up and attempt to clear 1435 * the condition by reprogramming the multicast filter. This is 1436 * a work-around for a bug in the 82557 where the receiver locks 1437 * up if it gets certain types of garbage in the syncronization 1438 * bits prior to the packet header. This bug is supposed to only 1439 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1440 * mode as well (perhaps due to a 10/100 speed transition). 1441 */ 1442 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1443 sc->rx_idle_secs = 0; 1444 fxp_mc_setup(sc); 1445 } 1446 /* 1447 * If there is no pending command, start another stats 1448 * dump. Otherwise punt for now. 1449 */ 1450 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1451 /* 1452 * Start another stats dump. 1453 */ 1454 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1455 } else { 1456 /* 1457 * A previous command is still waiting to be accepted. 1458 * Just zero our copy of the stats and wait for the 1459 * next timer event to update them. 1460 */ 1461 sp->tx_good = 0; 1462 sp->tx_underruns = 0; 1463 sp->tx_total_collisions = 0; 1464 1465 sp->rx_good = 0; 1466 sp->rx_crc_errors = 0; 1467 sp->rx_alignment_errors = 0; 1468 sp->rx_rnr_errors = 0; 1469 sp->rx_overrun_errors = 0; 1470 } 1471 if (sc->miibus != NULL) 1472 mii_tick(device_get_softc(sc->miibus)); 1473 splx(s); 1474 /* 1475 * Schedule another timeout one second from now. 1476 */ 1477 sc->stat_ch = timeout(fxp_tick, sc, hz); 1478 } 1479 1480 /* 1481 * Stop the interface. Cancels the statistics updater and resets 1482 * the interface. 1483 */ 1484 static void 1485 fxp_stop(struct fxp_softc *sc) 1486 { 1487 struct ifnet *ifp = &sc->sc_if; 1488 struct fxp_cb_tx *txp; 1489 int i; 1490 1491 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1492 ifp->if_timer = 0; 1493 1494 #ifdef DEVICE_POLLING 1495 ether_poll_deregister(ifp); 1496 #endif 1497 /* 1498 * Cancel stats updater. 1499 */ 1500 untimeout(fxp_tick, sc, sc->stat_ch); 1501 1502 /* 1503 * Issue software reset, which also unloads the microcode. 1504 */ 1505 sc->flags &= ~FXP_FLAG_UCODE; 1506 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1507 DELAY(50); 1508 1509 /* 1510 * Release any xmit buffers. 1511 */ 1512 txp = sc->cbl_base; 1513 if (txp != NULL) { 1514 for (i = 0; i < FXP_NTXCB; i++) { 1515 if (txp[i].mb_head != NULL) { 1516 m_freem(txp[i].mb_head); 1517 txp[i].mb_head = NULL; 1518 } 1519 } 1520 } 1521 sc->tx_queued = 0; 1522 1523 /* 1524 * Free all the receive buffers then reallocate/reinitialize 1525 */ 1526 if (sc->rfa_headm != NULL) 1527 m_freem(sc->rfa_headm); 1528 sc->rfa_headm = NULL; 1529 sc->rfa_tailm = NULL; 1530 for (i = 0; i < FXP_NRFABUFS; i++) { 1531 if (fxp_add_rfabuf(sc, NULL) != 0) { 1532 /* 1533 * This "can't happen" - we're at splimp() 1534 * and we just freed all the buffers we need 1535 * above. 1536 */ 1537 panic("fxp_stop: no buffers!"); 1538 } 1539 } 1540 } 1541 1542 /* 1543 * Watchdog/transmission transmit timeout handler. Called when a 1544 * transmission is started on the interface, but no interrupt is 1545 * received before the timeout. This usually indicates that the 1546 * card has wedged for some reason. 1547 */ 1548 static void 1549 fxp_watchdog(struct ifnet *ifp) 1550 { 1551 struct fxp_softc *sc = ifp->if_softc; 1552 1553 device_printf(sc->dev, "device timeout\n"); 1554 ifp->if_oerrors++; 1555 1556 fxp_init(sc); 1557 } 1558 1559 static void 1560 fxp_init(void *xsc) 1561 { 1562 struct fxp_softc *sc = xsc; 1563 struct ifnet *ifp = &sc->sc_if; 1564 struct fxp_cb_config *cbp; 1565 struct fxp_cb_ias *cb_ias; 1566 struct fxp_cb_tx *txp; 1567 struct fxp_cb_mcs *mcsp; 1568 int i, prm, s; 1569 1570 s = splimp(); 1571 /* 1572 * Cancel any pending I/O 1573 */ 1574 fxp_stop(sc); 1575 1576 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1577 1578 /* 1579 * Initialize base of CBL and RFA memory. Loading with zero 1580 * sets it up for regular linear addressing. 1581 */ 1582 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1583 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1584 1585 fxp_scb_wait(sc); 1586 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1587 1588 /* 1589 * Initialize base of dump-stats buffer. 1590 */ 1591 fxp_scb_wait(sc); 1592 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1593 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1594 1595 /* 1596 * Attempt to load microcode if requested. 1597 */ 1598 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1599 fxp_load_ucode(sc); 1600 1601 /* 1602 * Initialize the multicast address list. 1603 */ 1604 if (fxp_mc_addrs(sc)) { 1605 mcsp = sc->mcsp; 1606 mcsp->cb_status = 0; 1607 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL; 1608 mcsp->link_addr = -1; 1609 /* 1610 * Start the multicast setup command. 1611 */ 1612 fxp_scb_wait(sc); 1613 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 1614 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1615 /* ...and wait for it to complete. */ 1616 fxp_dma_wait(&mcsp->cb_status, sc); 1617 } 1618 1619 /* 1620 * We temporarily use memory that contains the TxCB list to 1621 * construct the config CB. The TxCB list memory is rebuilt 1622 * later. 1623 */ 1624 cbp = (struct fxp_cb_config *) sc->cbl_base; 1625 1626 /* 1627 * This bcopy is kind of disgusting, but there are a bunch of must be 1628 * zero and must be one bits in this structure and this is the easiest 1629 * way to initialize them all to proper values. 1630 */ 1631 bcopy(fxp_cb_config_template, 1632 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1633 sizeof(fxp_cb_config_template)); 1634 1635 cbp->cb_status = 0; 1636 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1637 cbp->link_addr = -1; /* (no) next command */ 1638 cbp->byte_count = 22; /* (22) bytes to config */ 1639 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1640 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1641 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1642 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1643 cbp->type_enable = 0; /* actually reserved */ 1644 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1645 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1646 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1647 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1648 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1649 cbp->late_scb = 0; /* (don't) defer SCB update */ 1650 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 1651 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1652 cbp->ci_int = 1; /* interrupt on CU idle */ 1653 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 1654 cbp->ext_stats_dis = 1; /* disable extended counters */ 1655 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1656 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 1657 cbp->disc_short_rx = !prm; /* discard short packets */ 1658 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 1659 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1660 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1661 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 1662 cbp->csma_dis = 0; /* (don't) disable link */ 1663 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1664 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1665 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1666 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1667 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 1668 cbp->nsai = 1; /* (don't) disable source addr insert */ 1669 cbp->preamble_length = 2; /* (7 byte) preamble */ 1670 cbp->loopback = 0; /* (don't) loopback */ 1671 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1672 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1673 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1674 cbp->promiscuous = prm; /* promiscuous mode */ 1675 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1676 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1677 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1678 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1679 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 1680 1681 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1682 cbp->padding = 1; /* (do) pad short tx packets */ 1683 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1684 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 1685 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1686 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1687 /* must set wake_en in PMCSR also */ 1688 cbp->force_fdx = 0; /* (don't) force full duplex */ 1689 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1690 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1691 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 1692 1693 if (sc->revision == FXP_REV_82557) { 1694 /* 1695 * The 82557 has no hardware flow control, the values 1696 * below are the defaults for the chip. 1697 */ 1698 cbp->fc_delay_lsb = 0; 1699 cbp->fc_delay_msb = 0x40; 1700 cbp->pri_fc_thresh = 3; 1701 cbp->tx_fc_dis = 0; 1702 cbp->rx_fc_restop = 0; 1703 cbp->rx_fc_restart = 0; 1704 cbp->fc_filter = 0; 1705 cbp->pri_fc_loc = 1; 1706 } else { 1707 cbp->fc_delay_lsb = 0x1f; 1708 cbp->fc_delay_msb = 0x01; 1709 cbp->pri_fc_thresh = 3; 1710 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1711 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1712 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1713 cbp->fc_filter = !prm; /* drop FC frames to host */ 1714 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1715 } 1716 1717 /* 1718 * Start the config command/DMA. 1719 */ 1720 fxp_scb_wait(sc); 1721 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1722 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1723 /* ...and wait for it to complete. */ 1724 fxp_dma_wait(&cbp->cb_status, sc); 1725 1726 /* 1727 * Now initialize the station address. Temporarily use the TxCB 1728 * memory area like we did above for the config CB. 1729 */ 1730 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1731 cb_ias->cb_status = 0; 1732 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1733 cb_ias->link_addr = -1; 1734 bcopy(sc->arpcom.ac_enaddr, 1735 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1736 sizeof(sc->arpcom.ac_enaddr)); 1737 1738 /* 1739 * Start the IAS (Individual Address Setup) command/DMA. 1740 */ 1741 fxp_scb_wait(sc); 1742 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1743 /* ...and wait for it to complete. */ 1744 fxp_dma_wait(&cb_ias->cb_status, sc); 1745 1746 /* 1747 * Initialize transmit control block (TxCB) list. 1748 */ 1749 1750 txp = sc->cbl_base; 1751 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1752 for (i = 0; i < FXP_NTXCB; i++) { 1753 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1754 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1755 txp[i].link_addr = 1756 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1757 if (sc->flags & FXP_FLAG_EXT_TXCB) 1758 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]); 1759 else 1760 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1761 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1762 } 1763 /* 1764 * Set the suspend flag on the first TxCB and start the control 1765 * unit. It will execute the NOP and then suspend. 1766 */ 1767 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1768 sc->cbl_first = sc->cbl_last = txp; 1769 sc->tx_queued = 1; 1770 1771 fxp_scb_wait(sc); 1772 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1773 1774 /* 1775 * Initialize receiver buffer area - RFA. 1776 */ 1777 fxp_scb_wait(sc); 1778 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1779 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1780 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1781 1782 /* 1783 * Set current media. 1784 */ 1785 if (sc->miibus != NULL) 1786 mii_mediachg(device_get_softc(sc->miibus)); 1787 1788 ifp->if_flags |= IFF_RUNNING; 1789 ifp->if_flags &= ~IFF_OACTIVE; 1790 1791 /* 1792 * Enable interrupts. 1793 */ 1794 #ifdef DEVICE_POLLING 1795 /* 1796 * ... but only do that if we are not polling. And because (presumably) 1797 * the default is interrupts on, we need to disable them explicitly! 1798 */ 1799 if ( ifp->if_ipending & IFF_POLLING ) 1800 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1801 else 1802 #endif /* DEVICE_POLLING */ 1803 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1804 splx(s); 1805 1806 /* 1807 * Start stats updater. 1808 */ 1809 sc->stat_ch = timeout(fxp_tick, sc, hz); 1810 } 1811 1812 static int 1813 fxp_serial_ifmedia_upd(struct ifnet *ifp) 1814 { 1815 1816 return (0); 1817 } 1818 1819 static void 1820 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1821 { 1822 1823 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 1824 } 1825 1826 /* 1827 * Change media according to request. 1828 */ 1829 static int 1830 fxp_ifmedia_upd(struct ifnet *ifp) 1831 { 1832 struct fxp_softc *sc = ifp->if_softc; 1833 struct mii_data *mii; 1834 1835 mii = device_get_softc(sc->miibus); 1836 mii_mediachg(mii); 1837 return (0); 1838 } 1839 1840 /* 1841 * Notify the world which media we're using. 1842 */ 1843 static void 1844 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1845 { 1846 struct fxp_softc *sc = ifp->if_softc; 1847 struct mii_data *mii; 1848 1849 mii = device_get_softc(sc->miibus); 1850 mii_pollstat(mii); 1851 ifmr->ifm_active = mii->mii_media_active; 1852 ifmr->ifm_status = mii->mii_media_status; 1853 1854 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 1855 sc->cu_resume_bug = 1; 1856 else 1857 sc->cu_resume_bug = 0; 1858 } 1859 1860 /* 1861 * Add a buffer to the end of the RFA buffer list. 1862 * Return 0 if successful, 1 for failure. A failure results in 1863 * adding the 'oldm' (if non-NULL) on to the end of the list - 1864 * tossing out its old contents and recycling it. 1865 * The RFA struct is stuck at the beginning of mbuf cluster and the 1866 * data pointer is fixed up to point just past it. 1867 */ 1868 static int 1869 fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm) 1870 { 1871 u_int32_t v; 1872 struct mbuf *m; 1873 struct fxp_rfa *rfa, *p_rfa; 1874 1875 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1876 if (m == NULL) { /* try to recycle the old mbuf instead */ 1877 if (oldm == NULL) 1878 return 1; 1879 m = oldm; 1880 m->m_data = m->m_ext.ext_buf; 1881 } 1882 1883 /* 1884 * Move the data pointer up so that the incoming data packet 1885 * will be 32-bit aligned. 1886 */ 1887 m->m_data += RFA_ALIGNMENT_FUDGE; 1888 1889 /* 1890 * Get a pointer to the base of the mbuf cluster and move 1891 * data start past it. 1892 */ 1893 rfa = mtod(m, struct fxp_rfa *); 1894 m->m_data += sizeof(struct fxp_rfa); 1895 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); 1896 1897 /* 1898 * Initialize the rest of the RFA. Note that since the RFA 1899 * is misaligned, we cannot store values directly. Instead, 1900 * we use an optimized, inline copy. 1901 */ 1902 1903 rfa->rfa_status = 0; 1904 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1905 rfa->actual_size = 0; 1906 1907 v = -1; 1908 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 1909 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 1910 1911 /* 1912 * If there are other buffers already on the list, attach this 1913 * one to the end by fixing up the tail to point to this one. 1914 */ 1915 if (sc->rfa_headm != NULL) { 1916 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 1917 RFA_ALIGNMENT_FUDGE); 1918 sc->rfa_tailm->m_next = m; 1919 v = vtophys(rfa); 1920 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 1921 p_rfa->rfa_control = 0; 1922 } else { 1923 sc->rfa_headm = m; 1924 } 1925 sc->rfa_tailm = m; 1926 1927 return (m == oldm); 1928 } 1929 1930 static volatile int 1931 fxp_miibus_readreg(device_t dev, int phy, int reg) 1932 { 1933 struct fxp_softc *sc = device_get_softc(dev); 1934 int count = 10000; 1935 int value; 1936 1937 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1938 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1939 1940 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1941 && count--) 1942 DELAY(10); 1943 1944 if (count <= 0) 1945 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 1946 1947 return (value & 0xffff); 1948 } 1949 1950 static void 1951 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 1952 { 1953 struct fxp_softc *sc = device_get_softc(dev); 1954 int count = 10000; 1955 1956 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1957 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1958 (value & 0xffff)); 1959 1960 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1961 count--) 1962 DELAY(10); 1963 1964 if (count <= 0) 1965 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 1966 } 1967 1968 static int 1969 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1970 { 1971 struct fxp_softc *sc = ifp->if_softc; 1972 struct ifreq *ifr = (struct ifreq *)data; 1973 struct mii_data *mii; 1974 int s, error = 0; 1975 1976 s = splimp(); 1977 1978 switch (command) { 1979 case SIOCSIFADDR: 1980 case SIOCGIFADDR: 1981 case SIOCSIFMTU: 1982 error = ether_ioctl(ifp, command, data); 1983 break; 1984 1985 case SIOCSIFFLAGS: 1986 if (ifp->if_flags & IFF_ALLMULTI) 1987 sc->flags |= FXP_FLAG_ALL_MCAST; 1988 else 1989 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1990 1991 /* 1992 * If interface is marked up and not running, then start it. 1993 * If it is marked down and running, stop it. 1994 * XXX If it's up then re-initialize it. This is so flags 1995 * such as IFF_PROMISC are handled. 1996 */ 1997 if (ifp->if_flags & IFF_UP) { 1998 fxp_init(sc); 1999 } else { 2000 if (ifp->if_flags & IFF_RUNNING) 2001 fxp_stop(sc); 2002 } 2003 break; 2004 2005 case SIOCADDMULTI: 2006 case SIOCDELMULTI: 2007 if (ifp->if_flags & IFF_ALLMULTI) 2008 sc->flags |= FXP_FLAG_ALL_MCAST; 2009 else 2010 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2011 /* 2012 * Multicast list has changed; set the hardware filter 2013 * accordingly. 2014 */ 2015 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2016 fxp_mc_setup(sc); 2017 /* 2018 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2019 * again rather than else {}. 2020 */ 2021 if (sc->flags & FXP_FLAG_ALL_MCAST) 2022 fxp_init(sc); 2023 error = 0; 2024 break; 2025 2026 case SIOCSIFMEDIA: 2027 case SIOCGIFMEDIA: 2028 if (sc->miibus != NULL) { 2029 mii = device_get_softc(sc->miibus); 2030 error = ifmedia_ioctl(ifp, ifr, 2031 &mii->mii_media, command); 2032 } else { 2033 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2034 } 2035 break; 2036 2037 default: 2038 error = EINVAL; 2039 } 2040 splx(s); 2041 return (error); 2042 } 2043 2044 /* 2045 * Fill in the multicast address list and return number of entries. 2046 */ 2047 static int 2048 fxp_mc_addrs(struct fxp_softc *sc) 2049 { 2050 struct fxp_cb_mcs *mcsp = sc->mcsp; 2051 struct ifnet *ifp = &sc->sc_if; 2052 struct ifmultiaddr *ifma; 2053 int nmcasts; 2054 2055 nmcasts = 0; 2056 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2057 #if __FreeBSD_version < 500000 2058 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2059 #else 2060 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2061 #endif 2062 if (ifma->ifma_addr->sa_family != AF_LINK) 2063 continue; 2064 if (nmcasts >= MAXMCADDR) { 2065 sc->flags |= FXP_FLAG_ALL_MCAST; 2066 nmcasts = 0; 2067 break; 2068 } 2069 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2070 (void *)(uintptr_t)(volatile void *) 2071 &sc->mcsp->mc_addr[nmcasts][0], 6); 2072 nmcasts++; 2073 } 2074 } 2075 mcsp->mc_cnt = nmcasts * 6; 2076 return (nmcasts); 2077 } 2078 2079 /* 2080 * Program the multicast filter. 2081 * 2082 * We have an artificial restriction that the multicast setup command 2083 * must be the first command in the chain, so we take steps to ensure 2084 * this. By requiring this, it allows us to keep up the performance of 2085 * the pre-initialized command ring (esp. link pointers) by not actually 2086 * inserting the mcsetup command in the ring - i.e. its link pointer 2087 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2088 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2089 * lead into the regular TxCB ring when it completes. 2090 * 2091 * This function must be called at splimp. 2092 */ 2093 static void 2094 fxp_mc_setup(struct fxp_softc *sc) 2095 { 2096 struct fxp_cb_mcs *mcsp = sc->mcsp; 2097 struct ifnet *ifp = &sc->sc_if; 2098 int count; 2099 2100 /* 2101 * If there are queued commands, we must wait until they are all 2102 * completed. If we are already waiting, then add a NOP command 2103 * with interrupt option so that we're notified when all commands 2104 * have been completed - fxp_start() ensures that no additional 2105 * TX commands will be added when need_mcsetup is true. 2106 */ 2107 if (sc->tx_queued) { 2108 struct fxp_cb_tx *txp; 2109 2110 /* 2111 * need_mcsetup will be true if we are already waiting for the 2112 * NOP command to be completed (see below). In this case, bail. 2113 */ 2114 if (sc->need_mcsetup) 2115 return; 2116 sc->need_mcsetup = 1; 2117 2118 /* 2119 * Add a NOP command with interrupt so that we are notified 2120 * when all TX commands have been processed. 2121 */ 2122 txp = sc->cbl_last->next; 2123 txp->mb_head = NULL; 2124 txp->cb_status = 0; 2125 txp->cb_command = FXP_CB_COMMAND_NOP | 2126 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2127 /* 2128 * Advance the end of list forward. 2129 */ 2130 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 2131 sc->cbl_last = txp; 2132 sc->tx_queued++; 2133 /* 2134 * Issue a resume in case the CU has just suspended. 2135 */ 2136 fxp_scb_wait(sc); 2137 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2138 /* 2139 * Set a 5 second timer just in case we don't hear from the 2140 * card again. 2141 */ 2142 ifp->if_timer = 5; 2143 2144 return; 2145 } 2146 sc->need_mcsetup = 0; 2147 2148 /* 2149 * Initialize multicast setup descriptor. 2150 */ 2151 mcsp->next = sc->cbl_base; 2152 mcsp->mb_head = NULL; 2153 mcsp->cb_status = 0; 2154 mcsp->cb_command = FXP_CB_COMMAND_MCAS | 2155 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2156 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 2157 (void) fxp_mc_addrs(sc); 2158 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 2159 sc->tx_queued = 1; 2160 2161 /* 2162 * Wait until command unit is not active. This should never 2163 * be the case when nothing is queued, but make sure anyway. 2164 */ 2165 count = 100; 2166 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2167 FXP_SCB_CUS_ACTIVE && --count) 2168 DELAY(10); 2169 if (count == 0) { 2170 device_printf(sc->dev, "command queue timeout\n"); 2171 return; 2172 } 2173 2174 /* 2175 * Start the multicast setup command. 2176 */ 2177 fxp_scb_wait(sc); 2178 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 2179 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2180 2181 ifp->if_timer = 2; 2182 return; 2183 } 2184 2185 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2186 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2187 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2188 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2189 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2190 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2191 2192 #define UCODE(x) x, sizeof(x) 2193 2194 struct ucode { 2195 u_int32_t revision; 2196 u_int32_t *ucode; 2197 int length; 2198 u_short int_delay_offset; 2199 u_short bundle_max_offset; 2200 } ucode_table[] = { 2201 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2202 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2203 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2204 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2205 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2206 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2207 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2208 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2209 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2210 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2211 { 0, NULL, 0, 0, 0 } 2212 }; 2213 2214 static void 2215 fxp_load_ucode(struct fxp_softc *sc) 2216 { 2217 struct ucode *uc; 2218 struct fxp_cb_ucode *cbp; 2219 2220 for (uc = ucode_table; uc->ucode != NULL; uc++) 2221 if (sc->revision == uc->revision) 2222 break; 2223 if (uc->ucode == NULL) 2224 return; 2225 cbp = (struct fxp_cb_ucode *)sc->cbl_base; 2226 cbp->cb_status = 0; 2227 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL; 2228 cbp->link_addr = -1; /* (no) next command */ 2229 memcpy(cbp->ucode, uc->ucode, uc->length); 2230 if (uc->int_delay_offset) 2231 *(u_short *)&cbp->ucode[uc->int_delay_offset] = 2232 sc->tunable_int_delay + sc->tunable_int_delay / 2; 2233 if (uc->bundle_max_offset) 2234 *(u_short *)&cbp->ucode[uc->bundle_max_offset] = 2235 sc->tunable_bundle_max; 2236 /* 2237 * Download the ucode to the chip. 2238 */ 2239 fxp_scb_wait(sc); 2240 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 2241 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2242 /* ...and wait for it to complete. */ 2243 fxp_dma_wait(&cbp->cb_status, sc); 2244 device_printf(sc->dev, 2245 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2246 sc->tunable_int_delay, 2247 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2248 sc->flags |= FXP_FLAG_UCODE; 2249 } 2250 2251 static int 2252 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2253 { 2254 int error, value; 2255 2256 value = *(int *)arg1; 2257 error = sysctl_handle_int(oidp, &value, 0, req); 2258 if (error || !req->newptr) 2259 return (error); 2260 if (value < low || value > high) 2261 return (EINVAL); 2262 *(int *)arg1 = value; 2263 return (0); 2264 } 2265 2266 /* 2267 * Interrupt delay is expressed in microseconds, a multiplier is used 2268 * to convert this to the appropriate clock ticks before using. 2269 */ 2270 static int 2271 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2272 { 2273 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2274 } 2275 2276 static int 2277 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2278 { 2279 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2280 } 2281