1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.110.2.30 2003/06/12 16:47:05 mux Exp $ 29 * $DragonFly: src/sys/dev/netif/fxp/if_fxp.c,v 1.48 2006/12/24 03:30:56 sephe Exp $ 30 */ 31 32 /* 33 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 34 */ 35 36 #include "opt_polling.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/mbuf.h> 41 #include <sys/malloc.h> 42 #include <sys/kernel.h> 43 #include <sys/socket.h> 44 #include <sys/sysctl.h> 45 #include <sys/thread2.h> 46 47 #include <net/if.h> 48 #include <net/ifq_var.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 52 #ifdef NS 53 #include <netns/ns.h> 54 #include <netns/ns_if.h> 55 #endif 56 57 #include <net/bpf.h> 58 #include <sys/sockio.h> 59 #include <sys/bus.h> 60 #include <sys/rman.h> 61 62 #include <net/ethernet.h> 63 #include <net/if_arp.h> 64 65 #include <vm/vm.h> /* for vtophys */ 66 #include <vm/pmap.h> /* for vtophys */ 67 68 #include <net/if_types.h> 69 #include <net/vlan/if_vlan_var.h> 70 71 #include <bus/pci/pcivar.h> 72 #include <bus/pci/pcireg.h> /* for PCIM_CMD_xxx */ 73 74 #include "../mii_layer/mii.h" 75 #include "../mii_layer/miivar.h" 76 77 #include "if_fxpreg.h" 78 #include "if_fxpvar.h" 79 #include "rcvbundl.h" 80 81 #include "miibus_if.h" 82 83 /* 84 * NOTE! On the Alpha, we have an alignment constraint. The 85 * card DMAs the packet immediately following the RFA. However, 86 * the first thing in the packet is a 14-byte Ethernet header. 87 * This means that the packet is misaligned. To compensate, 88 * we actually offset the RFA 2 bytes into the cluster. This 89 * alignes the packet after the Ethernet header at a 32-bit 90 * boundary. HOWEVER! This means that the RFA is misaligned! 91 */ 92 #define RFA_ALIGNMENT_FUDGE 2 93 94 /* 95 * Set initial transmit threshold at 64 (512 bytes). This is 96 * increased by 64 (512 bytes) at a time, to maximum of 192 97 * (1536 bytes), if an underrun occurs. 98 */ 99 static int tx_threshold = 64; 100 101 /* 102 * The configuration byte map has several undefined fields which 103 * must be one or must be zero. Set up a template for these bits 104 * only, (assuming a 82557 chip) leaving the actual configuration 105 * to fxp_init. 106 * 107 * See struct fxp_cb_config for the bit definitions. 108 */ 109 static u_char fxp_cb_config_template[] = { 110 0x0, 0x0, /* cb_status */ 111 0x0, 0x0, /* cb_command */ 112 0x0, 0x0, 0x0, 0x0, /* link_addr */ 113 0x0, /* 0 */ 114 0x0, /* 1 */ 115 0x0, /* 2 */ 116 0x0, /* 3 */ 117 0x0, /* 4 */ 118 0x0, /* 5 */ 119 0x32, /* 6 */ 120 0x0, /* 7 */ 121 0x0, /* 8 */ 122 0x0, /* 9 */ 123 0x6, /* 10 */ 124 0x0, /* 11 */ 125 0x0, /* 12 */ 126 0x0, /* 13 */ 127 0xf2, /* 14 */ 128 0x48, /* 15 */ 129 0x0, /* 16 */ 130 0x40, /* 17 */ 131 0xf0, /* 18 */ 132 0x0, /* 19 */ 133 0x3f, /* 20 */ 134 0x5 /* 21 */ 135 }; 136 137 struct fxp_ident { 138 u_int16_t devid; 139 int16_t revid; /* -1 matches anything */ 140 char *name; 141 }; 142 143 /* 144 * Claim various Intel PCI device identifiers for this driver. The 145 * sub-vendor and sub-device field are extensively used to identify 146 * particular variants, but we don't currently differentiate between 147 * them. 148 */ 149 static struct fxp_ident fxp_ident_table[] = { 150 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 151 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 152 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 153 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 154 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 155 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 156 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 157 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 158 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 159 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 160 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 161 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 162 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 163 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 164 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 165 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 166 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 167 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 168 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 169 { 0x1064, -1, "Intel 82562ET/EZ/GT/GZ (ICH6/ICH6R) Pro/100 VE Ethernet" }, 170 { 0x1065, -1, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" }, 171 { 0x1068, -1, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" }, 172 { 0x1069, -1, "Intel 82562EM/EX/GX Pro/100 Ethernet" }, 173 { 0x1092, -1, "Intel Pro/100 VE Network Connection" }, 174 { 0x1093, -1, "Intel Pro/100 VM Network Connection" }, 175 { 0x1094, -1, "Intel Pro/100 946GZ (ICH7) Network Connection" }, 176 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 177 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 178 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 179 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 180 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 181 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 182 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 183 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 184 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 185 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 186 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 187 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 188 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 189 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 190 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 191 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 192 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 193 { 0x27dc, -1, "Intel 82801GB (ICH7) 10/100 Ethernet" }, 194 { 0, -1, NULL }, 195 }; 196 197 static int fxp_probe(device_t dev); 198 static int fxp_attach(device_t dev); 199 static int fxp_detach(device_t dev); 200 static int fxp_shutdown(device_t dev); 201 static int fxp_suspend(device_t dev); 202 static int fxp_resume(device_t dev); 203 204 static void fxp_intr(void *xsc); 205 static void fxp_intr_body(struct fxp_softc *sc, 206 u_int8_t statack, int count); 207 208 static void fxp_init(void *xsc); 209 static void fxp_tick(void *xsc); 210 static void fxp_powerstate_d0(device_t dev); 211 static void fxp_start(struct ifnet *ifp); 212 static void fxp_stop(struct fxp_softc *sc); 213 static void fxp_release(device_t dev); 214 static int fxp_ioctl(struct ifnet *ifp, u_long command, 215 caddr_t data, struct ucred *); 216 static void fxp_watchdog(struct ifnet *ifp); 217 static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm); 218 static int fxp_mc_addrs(struct fxp_softc *sc); 219 static void fxp_mc_setup(struct fxp_softc *sc); 220 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 221 int autosize); 222 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 223 u_int16_t data); 224 static void fxp_autosize_eeprom(struct fxp_softc *sc); 225 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 226 int offset, int words); 227 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 228 int offset, int words); 229 static int fxp_ifmedia_upd(struct ifnet *ifp); 230 static void fxp_ifmedia_sts(struct ifnet *ifp, 231 struct ifmediareq *ifmr); 232 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 233 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 234 struct ifmediareq *ifmr); 235 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 236 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 237 int value); 238 static void fxp_load_ucode(struct fxp_softc *sc); 239 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 240 int low, int high); 241 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 242 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 243 #ifdef DEVICE_POLLING 244 static poll_handler_t fxp_poll; 245 #endif 246 247 static void fxp_lwcopy(volatile u_int32_t *src, 248 volatile u_int32_t *dst); 249 static void fxp_scb_wait(struct fxp_softc *sc); 250 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 251 static void fxp_dma_wait(volatile u_int16_t *status, 252 struct fxp_softc *sc); 253 254 static device_method_t fxp_methods[] = { 255 /* Device interface */ 256 DEVMETHOD(device_probe, fxp_probe), 257 DEVMETHOD(device_attach, fxp_attach), 258 DEVMETHOD(device_detach, fxp_detach), 259 DEVMETHOD(device_shutdown, fxp_shutdown), 260 DEVMETHOD(device_suspend, fxp_suspend), 261 DEVMETHOD(device_resume, fxp_resume), 262 263 /* MII interface */ 264 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 265 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 266 267 { 0, 0 } 268 }; 269 270 static driver_t fxp_driver = { 271 "fxp", 272 fxp_methods, 273 sizeof(struct fxp_softc), 274 }; 275 276 static devclass_t fxp_devclass; 277 278 DECLARE_DUMMY_MODULE(if_fxp); 279 MODULE_DEPEND(if_fxp, miibus, 1, 1, 1); 280 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 281 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 282 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 283 284 static int fxp_rnr; 285 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 286 287 /* 288 * Copy a 16-bit aligned 32-bit quantity. 289 */ 290 static void 291 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst) 292 { 293 #ifdef __i386__ 294 *dst = *src; 295 #else 296 volatile u_int16_t *a = (volatile u_int16_t *)src; 297 volatile u_int16_t *b = (volatile u_int16_t *)dst; 298 299 b[0] = a[0]; 300 b[1] = a[1]; 301 #endif 302 } 303 304 /* 305 * Wait for the previous command to be accepted (but not necessarily 306 * completed). 307 */ 308 static void 309 fxp_scb_wait(struct fxp_softc *sc) 310 { 311 int i = 10000; 312 313 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 314 DELAY(2); 315 if (i == 0) { 316 if_printf(&sc->arpcom.ac_if, 317 "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 318 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 319 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 320 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 321 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 322 } 323 } 324 325 static void 326 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 327 { 328 329 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 330 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 331 fxp_scb_wait(sc); 332 } 333 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 334 } 335 336 static void 337 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc) 338 { 339 int i = 10000; 340 341 while (!(*status & FXP_CB_STATUS_C) && --i) 342 DELAY(2); 343 if (i == 0) 344 if_printf(&sc->arpcom.ac_if, "DMA timeout\n"); 345 } 346 347 /* 348 * Return identification string if this is device is ours. 349 */ 350 static int 351 fxp_probe(device_t dev) 352 { 353 u_int16_t devid; 354 u_int8_t revid; 355 struct fxp_ident *ident; 356 357 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 358 devid = pci_get_device(dev); 359 revid = pci_get_revid(dev); 360 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 361 if (ident->devid == devid && 362 (ident->revid == revid || ident->revid == -1)) { 363 device_set_desc(dev, ident->name); 364 return (0); 365 } 366 } 367 } 368 return (ENXIO); 369 } 370 371 static void 372 fxp_powerstate_d0(device_t dev) 373 { 374 u_int32_t iobase, membase, irq; 375 376 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 377 /* Save important PCI config data. */ 378 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 379 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 380 irq = pci_read_config(dev, PCIR_INTLINE, 4); 381 382 /* Reset the power state. */ 383 device_printf(dev, "chip is in D%d power mode " 384 "-- setting to D0\n", pci_get_powerstate(dev)); 385 386 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 387 388 /* Restore PCI config data. */ 389 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 390 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 391 pci_write_config(dev, PCIR_INTLINE, irq, 4); 392 } 393 } 394 395 static int 396 fxp_attach(device_t dev) 397 { 398 int error = 0; 399 struct fxp_softc *sc = device_get_softc(dev); 400 struct ifnet *ifp; 401 u_int32_t val; 402 u_int16_t data; 403 int i, rid, m1, m2, prefer_iomap; 404 405 callout_init(&sc->fxp_stat_timer); 406 sysctl_ctx_init(&sc->sysctl_ctx); 407 408 /* 409 * Enable bus mastering. Enable memory space too, in case 410 * BIOS/Prom forgot about it. 411 */ 412 pci_enable_busmaster(dev); 413 pci_enable_io(dev, SYS_RES_MEMORY); 414 val = pci_read_config(dev, PCIR_COMMAND, 2); 415 416 fxp_powerstate_d0(dev); 417 418 /* 419 * Figure out which we should try first - memory mapping or i/o mapping? 420 * We default to memory mapping. Then we accept an override from the 421 * command line. Then we check to see which one is enabled. 422 */ 423 m1 = PCIM_CMD_MEMEN; 424 m2 = PCIM_CMD_PORTEN; 425 prefer_iomap = 0; 426 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 427 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 428 m1 = PCIM_CMD_PORTEN; 429 m2 = PCIM_CMD_MEMEN; 430 } 431 432 if (val & m1) { 433 sc->rtp = 434 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 435 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 436 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 437 RF_ACTIVE); 438 } 439 if (sc->mem == NULL && (val & m2)) { 440 sc->rtp = 441 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 442 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 443 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 444 RF_ACTIVE); 445 } 446 447 if (!sc->mem) { 448 device_printf(dev, "could not map device registers\n"); 449 error = ENXIO; 450 goto fail; 451 } 452 if (bootverbose) { 453 device_printf(dev, "using %s space register mapping\n", 454 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 455 } 456 457 sc->sc_st = rman_get_bustag(sc->mem); 458 sc->sc_sh = rman_get_bushandle(sc->mem); 459 460 /* 461 * Allocate our interrupt. 462 */ 463 rid = 0; 464 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 465 RF_SHAREABLE | RF_ACTIVE); 466 if (sc->irq == NULL) { 467 device_printf(dev, "could not map interrupt\n"); 468 error = ENXIO; 469 goto fail; 470 } 471 472 /* 473 * Reset to a stable state. 474 */ 475 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 476 DELAY(10); 477 478 sc->cbl_base = kmalloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 479 M_DEVBUF, M_WAITOK | M_ZERO); 480 481 sc->fxp_stats = kmalloc(sizeof(struct fxp_stats), M_DEVBUF, 482 M_WAITOK | M_ZERO); 483 484 sc->mcsp = kmalloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_WAITOK); 485 486 /* 487 * Pre-allocate our receive buffers. 488 */ 489 for (i = 0; i < FXP_NRFABUFS; i++) { 490 if (fxp_add_rfabuf(sc, NULL) != 0) { 491 goto failmem; 492 } 493 } 494 495 /* 496 * Find out how large of an SEEPROM we have. 497 */ 498 fxp_autosize_eeprom(sc); 499 500 /* 501 * Determine whether we must use the 503 serial interface. 502 */ 503 fxp_read_eeprom(sc, &data, 6, 1); 504 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 505 (data & FXP_PHY_SERIAL_ONLY)) 506 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 507 508 /* 509 * Create the sysctl tree 510 */ 511 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 512 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 513 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 514 if (sc->sysctl_tree == NULL) 515 goto fail; 516 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 517 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 518 &sc->tunable_int_delay, 0, &sysctl_hw_fxp_int_delay, "I", 519 "FXP driver receive interrupt microcode bundling delay"); 520 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 521 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 522 &sc->tunable_bundle_max, 0, &sysctl_hw_fxp_bundle_max, "I", 523 "FXP driver receive interrupt microcode bundle size limit"); 524 525 /* 526 * Pull in device tunables. 527 */ 528 sc->tunable_int_delay = TUNABLE_INT_DELAY; 529 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 530 resource_int_value(device_get_name(dev), device_get_unit(dev), 531 "int_delay", &sc->tunable_int_delay); 532 resource_int_value(device_get_name(dev), device_get_unit(dev), 533 "bundle_max", &sc->tunable_bundle_max); 534 535 /* 536 * Find out the chip revision; lump all 82557 revs together. 537 */ 538 fxp_read_eeprom(sc, &data, 5, 1); 539 if ((data >> 8) == 1) 540 sc->revision = FXP_REV_82557; 541 else 542 sc->revision = pci_get_revid(dev); 543 544 /* 545 * Enable workarounds for certain chip revision deficiencies. 546 * 547 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 548 * some systems based a normal 82559 design, have a defect where 549 * the chip can cause a PCI protocol violation if it receives 550 * a CU_RESUME command when it is entering the IDLE state. The 551 * workaround is to disable Dynamic Standby Mode, so the chip never 552 * deasserts CLKRUN#, and always remains in an active state. 553 * 554 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 555 */ 556 i = pci_get_device(dev); 557 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 558 sc->revision >= FXP_REV_82559_A0) { 559 fxp_read_eeprom(sc, &data, 10, 1); 560 if (data & 0x02) { /* STB enable */ 561 u_int16_t cksum; 562 int i; 563 564 device_printf(dev, 565 "Disabling dynamic standby mode in EEPROM\n"); 566 data &= ~0x02; 567 fxp_write_eeprom(sc, &data, 10, 1); 568 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 569 cksum = 0; 570 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 571 fxp_read_eeprom(sc, &data, i, 1); 572 cksum += data; 573 } 574 i = (1 << sc->eeprom_size) - 1; 575 cksum = 0xBABA - cksum; 576 fxp_read_eeprom(sc, &data, i, 1); 577 fxp_write_eeprom(sc, &cksum, i, 1); 578 device_printf(dev, 579 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 580 i, data, cksum); 581 #if 1 582 /* 583 * If the user elects to continue, try the software 584 * workaround, as it is better than nothing. 585 */ 586 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 587 #endif 588 } 589 } 590 591 /* 592 * If we are not a 82557 chip, we can enable extended features. 593 */ 594 if (sc->revision != FXP_REV_82557) { 595 /* 596 * If MWI is enabled in the PCI configuration, and there 597 * is a valid cacheline size (8 or 16 dwords), then tell 598 * the board to turn on MWI. 599 */ 600 if (val & PCIM_CMD_MWRICEN && 601 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 602 sc->flags |= FXP_FLAG_MWI_ENABLE; 603 604 /* turn on the extended TxCB feature */ 605 sc->flags |= FXP_FLAG_EXT_TXCB; 606 607 /* enable reception of long frames for VLAN */ 608 sc->flags |= FXP_FLAG_LONG_PKT_EN; 609 } 610 611 /* 612 * Read MAC address. 613 */ 614 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3); 615 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) 616 device_printf(dev, "10Mbps\n"); 617 if (bootverbose) { 618 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 619 pci_get_vendor(dev), pci_get_device(dev), 620 pci_get_subvendor(dev), pci_get_subdevice(dev), 621 pci_get_revid(dev)); 622 fxp_read_eeprom(sc, &data, 10, 1); 623 device_printf(dev, "Dynamic Standby mode is %s\n", 624 data & 0x02 ? "enabled" : "disabled"); 625 } 626 627 /* 628 * If this is only a 10Mbps device, then there is no MII, and 629 * the PHY will use a serial interface instead. 630 * 631 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 632 * doesn't have a programming interface of any sort. The 633 * media is sensed automatically based on how the link partner 634 * is configured. This is, in essence, manual configuration. 635 */ 636 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 637 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 638 fxp_serial_ifmedia_sts); 639 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 640 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 641 } else { 642 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 643 fxp_ifmedia_sts)) { 644 device_printf(dev, "MII without any PHY!\n"); 645 error = ENXIO; 646 goto fail; 647 } 648 } 649 650 ifp = &sc->arpcom.ac_if; 651 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 652 ifp->if_baudrate = 100000000; 653 ifp->if_init = fxp_init; 654 ifp->if_softc = sc; 655 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 656 ifp->if_ioctl = fxp_ioctl; 657 ifp->if_start = fxp_start; 658 #ifdef DEVICE_POLLING 659 ifp->if_poll = fxp_poll; 660 #endif 661 ifp->if_watchdog = fxp_watchdog; 662 663 /* 664 * Attach the interface. 665 */ 666 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL); 667 668 /* 669 * Tell the upper layer(s) we support long frames. 670 */ 671 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 672 673 /* 674 * Let the system queue as many packets as we have available 675 * TX descriptors. 676 */ 677 ifq_set_maxlen(&ifp->if_snd, FXP_NTXCB - 1); 678 ifq_set_ready(&ifp->if_snd); 679 680 error = bus_setup_intr(dev, sc->irq, INTR_NETSAFE, 681 fxp_intr, sc, &sc->ih, 682 ifp->if_serializer); 683 if (error) { 684 ether_ifdetach(ifp); 685 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) 686 ifmedia_removeall(&sc->sc_media); 687 device_printf(dev, "could not setup irq\n"); 688 goto fail; 689 } 690 691 return (0); 692 693 failmem: 694 device_printf(dev, "Failed to malloc memory\n"); 695 error = ENOMEM; 696 fail: 697 fxp_release(dev); 698 return (error); 699 } 700 701 /* 702 * release all resources 703 */ 704 static void 705 fxp_release(device_t dev) 706 { 707 struct fxp_softc *sc = device_get_softc(dev); 708 709 if (sc->miibus) 710 device_delete_child(dev, sc->miibus); 711 bus_generic_detach(dev); 712 713 if (sc->cbl_base) 714 kfree(sc->cbl_base, M_DEVBUF); 715 if (sc->fxp_stats) 716 kfree(sc->fxp_stats, M_DEVBUF); 717 if (sc->mcsp) 718 kfree(sc->mcsp, M_DEVBUF); 719 if (sc->rfa_headm) 720 m_freem(sc->rfa_headm); 721 722 if (sc->irq) 723 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 724 if (sc->mem) 725 bus_release_resource(dev, sc->rtp, sc->rgd, sc->mem); 726 727 sysctl_ctx_free(&sc->sysctl_ctx); 728 } 729 730 /* 731 * Detach interface. 732 */ 733 static int 734 fxp_detach(device_t dev) 735 { 736 struct fxp_softc *sc = device_get_softc(dev); 737 738 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 739 740 /* 741 * Stop DMA and drop transmit queue. 742 */ 743 fxp_stop(sc); 744 745 /* 746 * Disable interrupts. 747 * 748 * NOTE: This should be done after fxp_stop(), because software 749 * resetting in fxp_stop() may leave interrupts turned on. 750 */ 751 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 752 753 /* 754 * Free all media structures. 755 */ 756 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) 757 ifmedia_removeall(&sc->sc_media); 758 759 if (sc->ih) 760 bus_teardown_intr(dev, sc->irq, sc->ih); 761 762 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 763 764 /* 765 * Close down routes etc. 766 */ 767 ether_ifdetach(&sc->arpcom.ac_if); 768 769 /* Release our allocated resources. */ 770 fxp_release(dev); 771 772 return (0); 773 } 774 775 /* 776 * Device shutdown routine. Called at system shutdown after sync. The 777 * main purpose of this routine is to shut off receiver DMA so that 778 * kernel memory doesn't get clobbered during warmboot. 779 */ 780 static int 781 fxp_shutdown(device_t dev) 782 { 783 /* 784 * Make sure that DMA is disabled prior to reboot. Not doing 785 * do could allow DMA to corrupt kernel memory during the 786 * reboot before the driver initializes. 787 */ 788 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 789 return (0); 790 } 791 792 /* 793 * Device suspend routine. Stop the interface and save some PCI 794 * settings in case the BIOS doesn't restore them properly on 795 * resume. 796 */ 797 static int 798 fxp_suspend(device_t dev) 799 { 800 struct fxp_softc *sc = device_get_softc(dev); 801 int i; 802 803 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 804 805 fxp_stop(sc); 806 807 for (i = 0; i < 5; i++) 808 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 809 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 810 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 811 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 812 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 813 814 sc->suspended = 1; 815 816 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 817 return (0); 818 } 819 820 /* 821 * Device resume routine. Restore some PCI settings in case the BIOS 822 * doesn't, re-enable busmastering, and restart the interface if 823 * appropriate. 824 */ 825 static int 826 fxp_resume(device_t dev) 827 { 828 struct fxp_softc *sc = device_get_softc(dev); 829 struct ifnet *ifp = &sc->arpcom.ac_if; 830 int i; 831 832 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 833 834 fxp_powerstate_d0(dev); 835 836 /* better way to do this? */ 837 for (i = 0; i < 5; i++) 838 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 839 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 840 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 841 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 842 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 843 844 /* reenable busmastering and memory space */ 845 pci_enable_busmaster(dev); 846 pci_enable_io(dev, SYS_RES_MEMORY); 847 848 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 849 DELAY(10); 850 851 /* reinitialize interface if necessary */ 852 if (ifp->if_flags & IFF_UP) 853 fxp_init(sc); 854 855 sc->suspended = 0; 856 857 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 858 return (0); 859 } 860 861 static void 862 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 863 { 864 u_int16_t reg; 865 int x; 866 867 /* 868 * Shift in data. 869 */ 870 for (x = 1 << (length - 1); x; x >>= 1) { 871 if (data & x) 872 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 873 else 874 reg = FXP_EEPROM_EECS; 875 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 876 DELAY(1); 877 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 878 DELAY(1); 879 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 880 DELAY(1); 881 } 882 } 883 884 /* 885 * Read from the serial EEPROM. Basically, you manually shift in 886 * the read opcode (one bit at a time) and then shift in the address, 887 * and then you shift out the data (all of this one bit at a time). 888 * The word size is 16 bits, so you have to provide the address for 889 * every 16 bits of data. 890 */ 891 static u_int16_t 892 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 893 { 894 u_int16_t reg, data; 895 int x; 896 897 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 898 /* 899 * Shift in read opcode. 900 */ 901 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 902 /* 903 * Shift in address. 904 */ 905 data = 0; 906 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 907 if (offset & x) 908 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 909 else 910 reg = FXP_EEPROM_EECS; 911 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 912 DELAY(1); 913 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 914 DELAY(1); 915 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 916 DELAY(1); 917 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 918 data++; 919 if (autosize && reg == 0) { 920 sc->eeprom_size = data; 921 break; 922 } 923 } 924 /* 925 * Shift out data. 926 */ 927 data = 0; 928 reg = FXP_EEPROM_EECS; 929 for (x = 1 << 15; x; x >>= 1) { 930 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 931 DELAY(1); 932 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 933 data |= x; 934 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 935 DELAY(1); 936 } 937 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 938 DELAY(1); 939 940 return (data); 941 } 942 943 static void 944 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 945 { 946 int i; 947 948 /* 949 * Erase/write enable. 950 */ 951 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 952 fxp_eeprom_shiftin(sc, 0x4, 3); 953 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 954 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 955 DELAY(1); 956 /* 957 * Shift in write opcode, address, data. 958 */ 959 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 960 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 961 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 962 fxp_eeprom_shiftin(sc, data, 16); 963 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 964 DELAY(1); 965 /* 966 * Wait for EEPROM to finish up. 967 */ 968 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 969 DELAY(1); 970 for (i = 0; i < 1000; i++) { 971 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 972 break; 973 DELAY(50); 974 } 975 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 976 DELAY(1); 977 /* 978 * Erase/write disable. 979 */ 980 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 981 fxp_eeprom_shiftin(sc, 0x4, 3); 982 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 983 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 984 DELAY(1); 985 } 986 987 /* 988 * From NetBSD: 989 * 990 * Figure out EEPROM size. 991 * 992 * 559's can have either 64-word or 256-word EEPROMs, the 558 993 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 994 * talks about the existance of 16 to 256 word EEPROMs. 995 * 996 * The only known sizes are 64 and 256, where the 256 version is used 997 * by CardBus cards to store CIS information. 998 * 999 * The address is shifted in msb-to-lsb, and after the last 1000 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1001 * after which follows the actual data. We try to detect this zero, by 1002 * probing the data-out bit in the EEPROM control register just after 1003 * having shifted in a bit. If the bit is zero, we assume we've 1004 * shifted enough address bits. The data-out should be tri-state, 1005 * before this, which should translate to a logical one. 1006 */ 1007 static void 1008 fxp_autosize_eeprom(struct fxp_softc *sc) 1009 { 1010 1011 /* guess maximum size of 256 words */ 1012 sc->eeprom_size = 8; 1013 1014 /* autosize */ 1015 fxp_eeprom_getword(sc, 0, 1); 1016 } 1017 1018 static void 1019 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1020 { 1021 int i; 1022 1023 for (i = 0; i < words; i++) 1024 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1025 } 1026 1027 static void 1028 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1029 { 1030 int i; 1031 1032 for (i = 0; i < words; i++) 1033 fxp_eeprom_putword(sc, offset + i, data[i]); 1034 } 1035 1036 /* 1037 * Start packet transmission on the interface. 1038 */ 1039 static void 1040 fxp_start(struct ifnet *ifp) 1041 { 1042 struct fxp_softc *sc = ifp->if_softc; 1043 struct fxp_cb_tx *txp; 1044 1045 /* 1046 * See if we need to suspend xmit until the multicast filter 1047 * has been reprogrammed (which can only be done at the head 1048 * of the command chain). 1049 */ 1050 if (sc->need_mcsetup) { 1051 return; 1052 } 1053 1054 txp = NULL; 1055 1056 /* 1057 * We're finished if there is nothing more to add to the list or if 1058 * we're all filled up with buffers to transmit. 1059 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1060 * a NOP command when needed. 1061 */ 1062 while (!ifq_is_empty(&ifp->if_snd) && sc->tx_queued < FXP_NTXCB - 1) { 1063 struct mbuf *m, *mb_head; 1064 int segment, ntries = 0; 1065 1066 /* 1067 * Grab a packet to transmit. The packet is dequeued, 1068 * once we are sure that we have enough free descriptors. 1069 */ 1070 mb_head = ifq_poll(&ifp->if_snd); 1071 if (mb_head == NULL) 1072 break; 1073 1074 /* 1075 * Get pointer to next available tx desc. 1076 */ 1077 txp = sc->cbl_last->next; 1078 1079 /* 1080 * Go through each of the mbufs in the chain and initialize 1081 * the transmit buffer descriptors with the physical address 1082 * and size of the mbuf. 1083 */ 1084 tbdinit: 1085 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 1086 if (m->m_len != 0) { 1087 if (segment == FXP_NTXSEG) 1088 break; 1089 txp->tbd[segment].tb_addr = 1090 vtophys(mtod(m, vm_offset_t)); 1091 txp->tbd[segment].tb_size = m->m_len; 1092 segment++; 1093 } 1094 } 1095 if (m != NULL) { 1096 struct mbuf *mn; 1097 1098 /* 1099 * We ran out of segments. We have to recopy this 1100 * mbuf chain first. Bail out if we can't get the 1101 * new buffers. 1102 */ 1103 if (ntries > 0) 1104 break; 1105 mn = m_dup(mb_head, MB_DONTWAIT); 1106 if (mn == NULL) 1107 break; 1108 /* We can transmit the packet, dequeue it. */ 1109 ifq_dequeue(&ifp->if_snd, mb_head); 1110 m_freem(mb_head); 1111 mb_head = mn; 1112 ntries = 1; 1113 goto tbdinit; 1114 } else { 1115 /* Nothing to worry about, just dequeue. */ 1116 ifq_dequeue(&ifp->if_snd, mb_head); 1117 } 1118 1119 txp->tbd_number = segment; 1120 txp->mb_head = mb_head; 1121 txp->cb_status = 0; 1122 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1123 txp->cb_command = 1124 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1125 FXP_CB_COMMAND_S; 1126 } else { 1127 txp->cb_command = 1128 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1129 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1130 /* 1131 * Set a 5 second timer just in case we don't hear 1132 * from the card again. 1133 */ 1134 ifp->if_timer = 5; 1135 } 1136 txp->tx_threshold = tx_threshold; 1137 1138 /* 1139 * Advance the end of list forward. 1140 */ 1141 1142 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1143 sc->cbl_last = txp; 1144 1145 /* 1146 * Advance the beginning of the list forward if there are 1147 * no other packets queued (when nothing is queued, cbl_first 1148 * sits on the last TxCB that was sent out). 1149 */ 1150 if (sc->tx_queued == 0) 1151 sc->cbl_first = txp; 1152 1153 sc->tx_queued++; 1154 1155 BPF_MTAP(ifp, mb_head); 1156 } 1157 1158 /* 1159 * We're finished. If we added to the list, issue a RESUME to get DMA 1160 * going again if suspended. 1161 */ 1162 if (txp != NULL) { 1163 fxp_scb_wait(sc); 1164 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1165 } 1166 } 1167 1168 #ifdef DEVICE_POLLING 1169 1170 static void 1171 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1172 { 1173 struct fxp_softc *sc = ifp->if_softc; 1174 u_int8_t statack; 1175 1176 switch(cmd) { 1177 case POLL_REGISTER: 1178 /* disable interrupts */ 1179 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1180 break; 1181 case POLL_DEREGISTER: 1182 /* enable interrupts */ 1183 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1184 break; 1185 default: 1186 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1187 FXP_SCB_STATACK_FR; 1188 if (cmd == POLL_AND_CHECK_STATUS) { 1189 u_int8_t tmp; 1190 1191 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1192 if (tmp == 0xff || tmp == 0) 1193 return; /* nothing to do */ 1194 tmp &= ~statack; 1195 /* ack what we can */ 1196 if (tmp != 0) 1197 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1198 statack |= tmp; 1199 } 1200 fxp_intr_body(sc, statack, count); 1201 break; 1202 } 1203 } 1204 1205 #endif /* DEVICE_POLLING */ 1206 1207 /* 1208 * Process interface interrupts. 1209 */ 1210 static void 1211 fxp_intr(void *xsc) 1212 { 1213 struct fxp_softc *sc = xsc; 1214 u_int8_t statack; 1215 1216 if (sc->suspended) { 1217 return; 1218 } 1219 1220 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1221 /* 1222 * It should not be possible to have all bits set; the 1223 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1224 * all bits are set, this may indicate that the card has 1225 * been physically ejected, so ignore it. 1226 */ 1227 if (statack == 0xff) 1228 return; 1229 1230 /* 1231 * First ACK all the interrupts in this pass. 1232 */ 1233 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1234 fxp_intr_body(sc, statack, -1); 1235 } 1236 } 1237 1238 static void 1239 fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count) 1240 { 1241 struct ifnet *ifp = &sc->arpcom.ac_if; 1242 struct mbuf *m; 1243 struct fxp_rfa *rfa; 1244 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1245 1246 if (rnr) 1247 fxp_rnr++; 1248 #ifdef DEVICE_POLLING 1249 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1250 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1251 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1252 rnr = 1; 1253 } 1254 #endif 1255 1256 /* 1257 * Free any finished transmit mbuf chains. 1258 * 1259 * Handle the CNA event likt a CXTNO event. It used to 1260 * be that this event (control unit not ready) was not 1261 * encountered, but it is now with the SMPng modifications. 1262 * The exact sequence of events that occur when the interface 1263 * is brought up are different now, and if this event 1264 * goes unhandled, the configuration/rxfilter setup sequence 1265 * can stall for several seconds. The result is that no 1266 * packets go out onto the wire for about 5 to 10 seconds 1267 * after the interface is ifconfig'ed for the first time. 1268 */ 1269 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1270 struct fxp_cb_tx *txp; 1271 1272 for (txp = sc->cbl_first; sc->tx_queued && 1273 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1274 txp = txp->next) { 1275 if ((m = txp->mb_head) != NULL) { 1276 txp->mb_head = NULL; 1277 sc->tx_queued--; 1278 m_freem(m); 1279 } else { 1280 sc->tx_queued--; 1281 } 1282 } 1283 sc->cbl_first = txp; 1284 ifp->if_timer = 0; 1285 if (sc->tx_queued == 0) { 1286 if (sc->need_mcsetup) 1287 fxp_mc_setup(sc); 1288 } 1289 /* 1290 * Try to start more packets transmitting. 1291 */ 1292 if (!ifq_is_empty(&ifp->if_snd)) 1293 (*ifp->if_start)(ifp); 1294 } 1295 1296 /* 1297 * Just return if nothing happened on the receive side. 1298 */ 1299 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1300 return; 1301 1302 /* 1303 * Process receiver interrupts. If a no-resource (RNR) 1304 * condition exists, get whatever packets we can and 1305 * re-start the receiver. 1306 * 1307 * When using polling, we do not process the list to completion, 1308 * so when we get an RNR interrupt we must defer the restart 1309 * until we hit the last buffer with the C bit set. 1310 * If we run out of cycles and rfa_headm has the C bit set, 1311 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1312 * that the info will be used in the subsequent polling cycle. 1313 */ 1314 for (;;) { 1315 m = sc->rfa_headm; 1316 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1317 RFA_ALIGNMENT_FUDGE); 1318 1319 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1320 if (count >= 0 && count-- == 0) { 1321 if (rnr) { 1322 /* Defer RNR processing until the next time. */ 1323 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1324 rnr = 0; 1325 } 1326 break; 1327 } 1328 #endif /* DEVICE_POLLING */ 1329 1330 if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0) 1331 break; 1332 1333 /* 1334 * Remove first packet from the chain. 1335 */ 1336 sc->rfa_headm = m->m_next; 1337 m->m_next = NULL; 1338 1339 /* 1340 * Add a new buffer to the receive chain. 1341 * If this fails, the old buffer is recycled 1342 * instead. 1343 */ 1344 if (fxp_add_rfabuf(sc, m) == 0) { 1345 int total_len; 1346 1347 /* 1348 * Fetch packet length (the top 2 bits of 1349 * actual_size are flags set by the controller 1350 * upon completion), and drop the packet in case 1351 * of bogus length or CRC errors. 1352 */ 1353 total_len = rfa->actual_size & 0x3fff; 1354 if (total_len < sizeof(struct ether_header) || 1355 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1356 sizeof(struct fxp_rfa) || 1357 rfa->rfa_status & FXP_RFA_STATUS_CRC) { 1358 m_freem(m); 1359 continue; 1360 } 1361 m->m_pkthdr.len = m->m_len = total_len; 1362 ifp->if_input(ifp, m); 1363 } 1364 } 1365 if (rnr) { 1366 fxp_scb_wait(sc); 1367 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1368 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1369 RFA_ALIGNMENT_FUDGE); 1370 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1371 } 1372 } 1373 1374 /* 1375 * Update packet in/out/collision statistics. The i82557 doesn't 1376 * allow you to access these counters without doing a fairly 1377 * expensive DMA to get _all_ of the statistics it maintains, so 1378 * we do this operation here only once per second. The statistics 1379 * counters in the kernel are updated from the previous dump-stats 1380 * DMA and then a new dump-stats DMA is started. The on-chip 1381 * counters are zeroed when the DMA completes. If we can't start 1382 * the DMA immediately, we don't wait - we just prepare to read 1383 * them again next time. 1384 */ 1385 static void 1386 fxp_tick(void *xsc) 1387 { 1388 struct fxp_softc *sc = xsc; 1389 struct ifnet *ifp = &sc->arpcom.ac_if; 1390 struct fxp_stats *sp = sc->fxp_stats; 1391 struct fxp_cb_tx *txp; 1392 struct mbuf *m; 1393 1394 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 1395 1396 ifp->if_opackets += sp->tx_good; 1397 ifp->if_collisions += sp->tx_total_collisions; 1398 if (sp->rx_good) { 1399 ifp->if_ipackets += sp->rx_good; 1400 sc->rx_idle_secs = 0; 1401 } else { 1402 /* 1403 * Receiver's been idle for another second. 1404 */ 1405 sc->rx_idle_secs++; 1406 } 1407 ifp->if_ierrors += 1408 sp->rx_crc_errors + 1409 sp->rx_alignment_errors + 1410 sp->rx_rnr_errors + 1411 sp->rx_overrun_errors; 1412 /* 1413 * If any transmit underruns occured, bump up the transmit 1414 * threshold by another 512 bytes (64 * 8). 1415 */ 1416 if (sp->tx_underruns) { 1417 ifp->if_oerrors += sp->tx_underruns; 1418 if (tx_threshold < 192) 1419 tx_threshold += 64; 1420 } 1421 1422 /* 1423 * Release any xmit buffers that have completed DMA. This isn't 1424 * strictly necessary to do here, but it's advantagous for mbufs 1425 * with external storage to be released in a timely manner rather 1426 * than being defered for a potentially long time. This limits 1427 * the delay to a maximum of one second. 1428 */ 1429 for (txp = sc->cbl_first; sc->tx_queued && 1430 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1431 txp = txp->next) { 1432 if ((m = txp->mb_head) != NULL) { 1433 txp->mb_head = NULL; 1434 sc->tx_queued--; 1435 m_freem(m); 1436 } else { 1437 sc->tx_queued--; 1438 } 1439 } 1440 sc->cbl_first = txp; 1441 /* 1442 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1443 * then assume the receiver has locked up and attempt to clear 1444 * the condition by reprogramming the multicast filter. This is 1445 * a work-around for a bug in the 82557 where the receiver locks 1446 * up if it gets certain types of garbage in the syncronization 1447 * bits prior to the packet header. This bug is supposed to only 1448 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1449 * mode as well (perhaps due to a 10/100 speed transition). 1450 */ 1451 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1452 sc->rx_idle_secs = 0; 1453 fxp_mc_setup(sc); 1454 } 1455 /* 1456 * If there is no pending command, start another stats 1457 * dump. Otherwise punt for now. 1458 */ 1459 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1460 /* 1461 * Start another stats dump. 1462 */ 1463 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1464 } else { 1465 /* 1466 * A previous command is still waiting to be accepted. 1467 * Just zero our copy of the stats and wait for the 1468 * next timer event to update them. 1469 */ 1470 sp->tx_good = 0; 1471 sp->tx_underruns = 0; 1472 sp->tx_total_collisions = 0; 1473 1474 sp->rx_good = 0; 1475 sp->rx_crc_errors = 0; 1476 sp->rx_alignment_errors = 0; 1477 sp->rx_rnr_errors = 0; 1478 sp->rx_overrun_errors = 0; 1479 } 1480 if (sc->miibus != NULL) 1481 mii_tick(device_get_softc(sc->miibus)); 1482 /* 1483 * Schedule another timeout one second from now. 1484 */ 1485 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc); 1486 1487 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 1488 } 1489 1490 /* 1491 * Stop the interface. Cancels the statistics updater and resets 1492 * the interface. 1493 */ 1494 static void 1495 fxp_stop(struct fxp_softc *sc) 1496 { 1497 struct ifnet *ifp = &sc->arpcom.ac_if; 1498 struct fxp_cb_tx *txp; 1499 int i; 1500 1501 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1502 ifp->if_timer = 0; 1503 1504 /* 1505 * Cancel stats updater. 1506 */ 1507 callout_stop(&sc->fxp_stat_timer); 1508 1509 /* 1510 * Issue software reset, which also unloads the microcode. 1511 */ 1512 sc->flags &= ~FXP_FLAG_UCODE; 1513 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1514 DELAY(50); 1515 1516 /* 1517 * Release any xmit buffers. 1518 */ 1519 txp = sc->cbl_base; 1520 if (txp != NULL) { 1521 for (i = 0; i < FXP_NTXCB; i++) { 1522 if (txp[i].mb_head != NULL) { 1523 m_freem(txp[i].mb_head); 1524 txp[i].mb_head = NULL; 1525 } 1526 } 1527 } 1528 sc->tx_queued = 0; 1529 1530 /* 1531 * Free all the receive buffers then reallocate/reinitialize 1532 */ 1533 if (sc->rfa_headm != NULL) 1534 m_freem(sc->rfa_headm); 1535 sc->rfa_headm = NULL; 1536 sc->rfa_tailm = NULL; 1537 for (i = 0; i < FXP_NRFABUFS; i++) { 1538 if (fxp_add_rfabuf(sc, NULL) != 0) { 1539 /* 1540 * This "can't happen" - we're at splimp() 1541 * and we just freed all the buffers we need 1542 * above. 1543 */ 1544 panic("fxp_stop: no buffers!"); 1545 } 1546 } 1547 } 1548 1549 /* 1550 * Watchdog/transmission transmit timeout handler. Called when a 1551 * transmission is started on the interface, but no interrupt is 1552 * received before the timeout. This usually indicates that the 1553 * card has wedged for some reason. 1554 */ 1555 static void 1556 fxp_watchdog(struct ifnet *ifp) 1557 { 1558 if_printf(ifp, "device timeout\n"); 1559 ifp->if_oerrors++; 1560 fxp_init(ifp->if_softc); 1561 } 1562 1563 static void 1564 fxp_init(void *xsc) 1565 { 1566 struct fxp_softc *sc = xsc; 1567 struct ifnet *ifp = &sc->arpcom.ac_if; 1568 struct fxp_cb_config *cbp; 1569 struct fxp_cb_ias *cb_ias; 1570 struct fxp_cb_tx *txp; 1571 struct fxp_cb_mcs *mcsp; 1572 int i, prm; 1573 1574 /* 1575 * Cancel any pending I/O 1576 */ 1577 fxp_stop(sc); 1578 1579 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1580 1581 /* 1582 * Initialize base of CBL and RFA memory. Loading with zero 1583 * sets it up for regular linear addressing. 1584 */ 1585 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1586 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1587 1588 fxp_scb_wait(sc); 1589 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1590 1591 /* 1592 * Initialize base of dump-stats buffer. 1593 */ 1594 fxp_scb_wait(sc); 1595 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1596 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1597 1598 /* 1599 * Attempt to load microcode if requested. 1600 */ 1601 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1602 fxp_load_ucode(sc); 1603 1604 /* 1605 * Initialize the multicast address list. 1606 */ 1607 if (fxp_mc_addrs(sc)) { 1608 mcsp = sc->mcsp; 1609 mcsp->cb_status = 0; 1610 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL; 1611 mcsp->link_addr = -1; 1612 /* 1613 * Start the multicast setup command. 1614 */ 1615 fxp_scb_wait(sc); 1616 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 1617 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1618 /* ...and wait for it to complete. */ 1619 fxp_dma_wait(&mcsp->cb_status, sc); 1620 } 1621 1622 /* 1623 * We temporarily use memory that contains the TxCB list to 1624 * construct the config CB. The TxCB list memory is rebuilt 1625 * later. 1626 */ 1627 cbp = (struct fxp_cb_config *) sc->cbl_base; 1628 1629 /* 1630 * This bcopy is kind of disgusting, but there are a bunch of must be 1631 * zero and must be one bits in this structure and this is the easiest 1632 * way to initialize them all to proper values. 1633 */ 1634 bcopy(fxp_cb_config_template, 1635 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1636 sizeof(fxp_cb_config_template)); 1637 1638 cbp->cb_status = 0; 1639 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1640 cbp->link_addr = -1; /* (no) next command */ 1641 cbp->byte_count = 22; /* (22) bytes to config */ 1642 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1643 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1644 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1645 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1646 cbp->type_enable = 0; /* actually reserved */ 1647 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1648 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1649 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1650 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1651 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1652 cbp->late_scb = 0; /* (don't) defer SCB update */ 1653 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 1654 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1655 cbp->ci_int = 1; /* interrupt on CU idle */ 1656 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 1657 cbp->ext_stats_dis = 1; /* disable extended counters */ 1658 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1659 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 1660 cbp->disc_short_rx = !prm; /* discard short packets */ 1661 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 1662 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1663 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1664 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 1665 cbp->csma_dis = 0; /* (don't) disable link */ 1666 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1667 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1668 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1669 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1670 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 1671 cbp->nsai = 1; /* (don't) disable source addr insert */ 1672 cbp->preamble_length = 2; /* (7 byte) preamble */ 1673 cbp->loopback = 0; /* (don't) loopback */ 1674 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1675 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1676 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1677 cbp->promiscuous = prm; /* promiscuous mode */ 1678 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1679 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1680 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1681 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1682 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 1683 1684 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1685 cbp->padding = 1; /* (do) pad short tx packets */ 1686 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1687 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 1688 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1689 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1690 /* must set wake_en in PMCSR also */ 1691 cbp->force_fdx = 0; /* (don't) force full duplex */ 1692 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1693 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1694 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 1695 1696 if (sc->revision == FXP_REV_82557) { 1697 /* 1698 * The 82557 has no hardware flow control, the values 1699 * below are the defaults for the chip. 1700 */ 1701 cbp->fc_delay_lsb = 0; 1702 cbp->fc_delay_msb = 0x40; 1703 cbp->pri_fc_thresh = 3; 1704 cbp->tx_fc_dis = 0; 1705 cbp->rx_fc_restop = 0; 1706 cbp->rx_fc_restart = 0; 1707 cbp->fc_filter = 0; 1708 cbp->pri_fc_loc = 1; 1709 } else { 1710 cbp->fc_delay_lsb = 0x1f; 1711 cbp->fc_delay_msb = 0x01; 1712 cbp->pri_fc_thresh = 3; 1713 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1714 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1715 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1716 cbp->fc_filter = !prm; /* drop FC frames to host */ 1717 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1718 } 1719 1720 /* 1721 * Start the config command/DMA. 1722 */ 1723 fxp_scb_wait(sc); 1724 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1725 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1726 /* ...and wait for it to complete. */ 1727 fxp_dma_wait(&cbp->cb_status, sc); 1728 1729 /* 1730 * Now initialize the station address. Temporarily use the TxCB 1731 * memory area like we did above for the config CB. 1732 */ 1733 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1734 cb_ias->cb_status = 0; 1735 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1736 cb_ias->link_addr = -1; 1737 bcopy(sc->arpcom.ac_enaddr, 1738 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1739 sizeof(sc->arpcom.ac_enaddr)); 1740 1741 /* 1742 * Start the IAS (Individual Address Setup) command/DMA. 1743 */ 1744 fxp_scb_wait(sc); 1745 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1746 /* ...and wait for it to complete. */ 1747 fxp_dma_wait(&cb_ias->cb_status, sc); 1748 1749 /* 1750 * Initialize transmit control block (TxCB) list. 1751 */ 1752 1753 txp = sc->cbl_base; 1754 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1755 for (i = 0; i < FXP_NTXCB; i++) { 1756 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1757 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1758 txp[i].link_addr = 1759 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1760 if (sc->flags & FXP_FLAG_EXT_TXCB) 1761 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]); 1762 else 1763 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1764 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1765 } 1766 /* 1767 * Set the suspend flag on the first TxCB and start the control 1768 * unit. It will execute the NOP and then suspend. 1769 */ 1770 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1771 sc->cbl_first = sc->cbl_last = txp; 1772 sc->tx_queued = 1; 1773 1774 fxp_scb_wait(sc); 1775 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1776 1777 /* 1778 * Initialize receiver buffer area - RFA. 1779 */ 1780 fxp_scb_wait(sc); 1781 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1782 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1783 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1784 1785 /* 1786 * Set current media. 1787 */ 1788 if (sc->miibus != NULL) 1789 mii_mediachg(device_get_softc(sc->miibus)); 1790 1791 ifp->if_flags |= IFF_RUNNING; 1792 ifp->if_flags &= ~IFF_OACTIVE; 1793 1794 /* 1795 * Enable interrupts. 1796 */ 1797 #ifdef DEVICE_POLLING 1798 /* 1799 * ... but only do that if we are not polling. And because (presumably) 1800 * the default is interrupts on, we need to disable them explicitly! 1801 */ 1802 if ( ifp->if_flags & IFF_POLLING ) 1803 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1804 else 1805 #endif /* DEVICE_POLLING */ 1806 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1807 1808 /* 1809 * Start stats updater. 1810 */ 1811 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc); 1812 } 1813 1814 static int 1815 fxp_serial_ifmedia_upd(struct ifnet *ifp) 1816 { 1817 1818 return (0); 1819 } 1820 1821 static void 1822 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1823 { 1824 1825 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 1826 } 1827 1828 /* 1829 * Change media according to request. 1830 */ 1831 static int 1832 fxp_ifmedia_upd(struct ifnet *ifp) 1833 { 1834 struct fxp_softc *sc = ifp->if_softc; 1835 struct mii_data *mii; 1836 1837 mii = device_get_softc(sc->miibus); 1838 mii_mediachg(mii); 1839 return (0); 1840 } 1841 1842 /* 1843 * Notify the world which media we're using. 1844 */ 1845 static void 1846 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1847 { 1848 struct fxp_softc *sc = ifp->if_softc; 1849 struct mii_data *mii; 1850 1851 mii = device_get_softc(sc->miibus); 1852 mii_pollstat(mii); 1853 ifmr->ifm_active = mii->mii_media_active; 1854 ifmr->ifm_status = mii->mii_media_status; 1855 1856 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 1857 sc->cu_resume_bug = 1; 1858 else 1859 sc->cu_resume_bug = 0; 1860 } 1861 1862 /* 1863 * Add a buffer to the end of the RFA buffer list. 1864 * Return 0 if successful, 1 for failure. A failure results in 1865 * adding the 'oldm' (if non-NULL) on to the end of the list - 1866 * tossing out its old contents and recycling it. 1867 * The RFA struct is stuck at the beginning of mbuf cluster and the 1868 * data pointer is fixed up to point just past it. 1869 */ 1870 static int 1871 fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm) 1872 { 1873 u_int32_t v; 1874 struct mbuf *m; 1875 struct fxp_rfa *rfa, *p_rfa; 1876 1877 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1878 if (m == NULL) { /* try to recycle the old mbuf instead */ 1879 if (oldm == NULL) 1880 return 1; 1881 m = oldm; 1882 m->m_data = m->m_ext.ext_buf; 1883 } 1884 1885 /* 1886 * Move the data pointer up so that the incoming data packet 1887 * will be 32-bit aligned. 1888 */ 1889 m->m_data += RFA_ALIGNMENT_FUDGE; 1890 1891 /* 1892 * Get a pointer to the base of the mbuf cluster and move 1893 * data start past it. 1894 */ 1895 rfa = mtod(m, struct fxp_rfa *); 1896 m->m_data += sizeof(struct fxp_rfa); 1897 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); 1898 1899 /* 1900 * Initialize the rest of the RFA. Note that since the RFA 1901 * is misaligned, we cannot store values directly. Instead, 1902 * we use an optimized, inline copy. 1903 */ 1904 1905 rfa->rfa_status = 0; 1906 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1907 rfa->actual_size = 0; 1908 1909 v = -1; 1910 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 1911 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 1912 1913 /* 1914 * If there are other buffers already on the list, attach this 1915 * one to the end by fixing up the tail to point to this one. 1916 */ 1917 if (sc->rfa_headm != NULL) { 1918 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 1919 RFA_ALIGNMENT_FUDGE); 1920 sc->rfa_tailm->m_next = m; 1921 v = vtophys(rfa); 1922 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 1923 p_rfa->rfa_control = 0; 1924 } else { 1925 sc->rfa_headm = m; 1926 } 1927 sc->rfa_tailm = m; 1928 1929 return (m == oldm); 1930 } 1931 1932 static volatile int 1933 fxp_miibus_readreg(device_t dev, int phy, int reg) 1934 { 1935 struct fxp_softc *sc = device_get_softc(dev); 1936 int count = 10000; 1937 int value; 1938 1939 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1940 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1941 1942 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1943 && count--) 1944 DELAY(10); 1945 1946 if (count <= 0) 1947 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 1948 1949 return (value & 0xffff); 1950 } 1951 1952 static void 1953 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 1954 { 1955 struct fxp_softc *sc = device_get_softc(dev); 1956 int count = 10000; 1957 1958 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1959 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1960 (value & 0xffff)); 1961 1962 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1963 count--) 1964 DELAY(10); 1965 1966 if (count <= 0) 1967 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 1968 } 1969 1970 static int 1971 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1972 { 1973 struct fxp_softc *sc = ifp->if_softc; 1974 struct ifreq *ifr = (struct ifreq *)data; 1975 struct mii_data *mii; 1976 int error = 0; 1977 1978 switch (command) { 1979 1980 case SIOCSIFFLAGS: 1981 if (ifp->if_flags & IFF_ALLMULTI) 1982 sc->flags |= FXP_FLAG_ALL_MCAST; 1983 else 1984 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1985 1986 /* 1987 * If interface is marked up and not running, then start it. 1988 * If it is marked down and running, stop it. 1989 * XXX If it's up then re-initialize it. This is so flags 1990 * such as IFF_PROMISC are handled. 1991 */ 1992 if (ifp->if_flags & IFF_UP) { 1993 fxp_init(sc); 1994 } else { 1995 if (ifp->if_flags & IFF_RUNNING) 1996 fxp_stop(sc); 1997 } 1998 break; 1999 2000 case SIOCADDMULTI: 2001 case SIOCDELMULTI: 2002 if (ifp->if_flags & IFF_ALLMULTI) 2003 sc->flags |= FXP_FLAG_ALL_MCAST; 2004 else 2005 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2006 /* 2007 * Multicast list has changed; set the hardware filter 2008 * accordingly. 2009 */ 2010 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2011 fxp_mc_setup(sc); 2012 /* 2013 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2014 * again rather than else {}. 2015 */ 2016 if (sc->flags & FXP_FLAG_ALL_MCAST) 2017 fxp_init(sc); 2018 error = 0; 2019 break; 2020 2021 case SIOCSIFMEDIA: 2022 case SIOCGIFMEDIA: 2023 if (sc->miibus != NULL) { 2024 mii = device_get_softc(sc->miibus); 2025 error = ifmedia_ioctl(ifp, ifr, 2026 &mii->mii_media, command); 2027 } else { 2028 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2029 } 2030 break; 2031 2032 default: 2033 error = ether_ioctl(ifp, command, data); 2034 break; 2035 } 2036 return (error); 2037 } 2038 2039 /* 2040 * Fill in the multicast address list and return number of entries. 2041 */ 2042 static int 2043 fxp_mc_addrs(struct fxp_softc *sc) 2044 { 2045 struct fxp_cb_mcs *mcsp = sc->mcsp; 2046 struct ifnet *ifp = &sc->arpcom.ac_if; 2047 struct ifmultiaddr *ifma; 2048 int nmcasts; 2049 2050 nmcasts = 0; 2051 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2052 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2053 if (ifma->ifma_addr->sa_family != AF_LINK) 2054 continue; 2055 if (nmcasts >= MAXMCADDR) { 2056 sc->flags |= FXP_FLAG_ALL_MCAST; 2057 nmcasts = 0; 2058 break; 2059 } 2060 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2061 (void *)(uintptr_t)(volatile void *) 2062 &sc->mcsp->mc_addr[nmcasts][0], 6); 2063 nmcasts++; 2064 } 2065 } 2066 mcsp->mc_cnt = nmcasts * 6; 2067 return (nmcasts); 2068 } 2069 2070 /* 2071 * Program the multicast filter. 2072 * 2073 * We have an artificial restriction that the multicast setup command 2074 * must be the first command in the chain, so we take steps to ensure 2075 * this. By requiring this, it allows us to keep up the performance of 2076 * the pre-initialized command ring (esp. link pointers) by not actually 2077 * inserting the mcsetup command in the ring - i.e. its link pointer 2078 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2079 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2080 * lead into the regular TxCB ring when it completes. 2081 * 2082 * This function must be called at splimp. 2083 */ 2084 static void 2085 fxp_mc_setup(struct fxp_softc *sc) 2086 { 2087 struct fxp_cb_mcs *mcsp = sc->mcsp; 2088 struct ifnet *ifp = &sc->arpcom.ac_if; 2089 int count; 2090 2091 /* 2092 * If there are queued commands, we must wait until they are all 2093 * completed. If we are already waiting, then add a NOP command 2094 * with interrupt option so that we're notified when all commands 2095 * have been completed - fxp_start() ensures that no additional 2096 * TX commands will be added when need_mcsetup is true. 2097 */ 2098 if (sc->tx_queued) { 2099 struct fxp_cb_tx *txp; 2100 2101 /* 2102 * need_mcsetup will be true if we are already waiting for the 2103 * NOP command to be completed (see below). In this case, bail. 2104 */ 2105 if (sc->need_mcsetup) 2106 return; 2107 sc->need_mcsetup = 1; 2108 2109 /* 2110 * Add a NOP command with interrupt so that we are notified 2111 * when all TX commands have been processed. 2112 */ 2113 txp = sc->cbl_last->next; 2114 txp->mb_head = NULL; 2115 txp->cb_status = 0; 2116 txp->cb_command = FXP_CB_COMMAND_NOP | 2117 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2118 /* 2119 * Advance the end of list forward. 2120 */ 2121 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 2122 sc->cbl_last = txp; 2123 sc->tx_queued++; 2124 /* 2125 * Issue a resume in case the CU has just suspended. 2126 */ 2127 fxp_scb_wait(sc); 2128 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2129 /* 2130 * Set a 5 second timer just in case we don't hear from the 2131 * card again. 2132 */ 2133 ifp->if_timer = 5; 2134 2135 return; 2136 } 2137 sc->need_mcsetup = 0; 2138 2139 /* 2140 * Initialize multicast setup descriptor. 2141 */ 2142 mcsp->next = sc->cbl_base; 2143 mcsp->mb_head = NULL; 2144 mcsp->cb_status = 0; 2145 mcsp->cb_command = FXP_CB_COMMAND_MCAS | 2146 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2147 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 2148 fxp_mc_addrs(sc); 2149 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 2150 sc->tx_queued = 1; 2151 2152 /* 2153 * Wait until command unit is not active. This should never 2154 * be the case when nothing is queued, but make sure anyway. 2155 */ 2156 count = 100; 2157 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2158 FXP_SCB_CUS_ACTIVE && --count) 2159 DELAY(10); 2160 if (count == 0) { 2161 if_printf(&sc->arpcom.ac_if, "command queue timeout\n"); 2162 return; 2163 } 2164 2165 /* 2166 * Start the multicast setup command. 2167 */ 2168 fxp_scb_wait(sc); 2169 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 2170 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2171 2172 ifp->if_timer = 2; 2173 return; 2174 } 2175 2176 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2177 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2178 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2179 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2180 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2181 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2182 2183 #define UCODE(x) x, sizeof(x) 2184 2185 struct ucode { 2186 u_int32_t revision; 2187 u_int32_t *ucode; 2188 int length; 2189 u_short int_delay_offset; 2190 u_short bundle_max_offset; 2191 } ucode_table[] = { 2192 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2193 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2194 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2195 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2196 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2197 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2198 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2199 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2200 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2201 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2202 { 0, NULL, 0, 0, 0 } 2203 }; 2204 2205 static void 2206 fxp_load_ucode(struct fxp_softc *sc) 2207 { 2208 struct ucode *uc; 2209 struct fxp_cb_ucode *cbp; 2210 2211 for (uc = ucode_table; uc->ucode != NULL; uc++) 2212 if (sc->revision == uc->revision) 2213 break; 2214 if (uc->ucode == NULL) 2215 return; 2216 cbp = (struct fxp_cb_ucode *)sc->cbl_base; 2217 cbp->cb_status = 0; 2218 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL; 2219 cbp->link_addr = -1; /* (no) next command */ 2220 memcpy(cbp->ucode, uc->ucode, uc->length); 2221 if (uc->int_delay_offset) 2222 *(u_short *)&cbp->ucode[uc->int_delay_offset] = 2223 sc->tunable_int_delay + sc->tunable_int_delay / 2; 2224 if (uc->bundle_max_offset) 2225 *(u_short *)&cbp->ucode[uc->bundle_max_offset] = 2226 sc->tunable_bundle_max; 2227 /* 2228 * Download the ucode to the chip. 2229 */ 2230 fxp_scb_wait(sc); 2231 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 2232 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2233 /* ...and wait for it to complete. */ 2234 fxp_dma_wait(&cbp->cb_status, sc); 2235 if_printf(&sc->arpcom.ac_if, 2236 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2237 sc->tunable_int_delay, 2238 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2239 sc->flags |= FXP_FLAG_UCODE; 2240 } 2241 2242 static int 2243 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2244 { 2245 int error, value; 2246 2247 value = *(int *)arg1; 2248 error = sysctl_handle_int(oidp, &value, 0, req); 2249 if (error || !req->newptr) 2250 return (error); 2251 if (value < low || value > high) 2252 return (EINVAL); 2253 *(int *)arg1 = value; 2254 return (0); 2255 } 2256 2257 /* 2258 * Interrupt delay is expressed in microseconds, a multiplier is used 2259 * to convert this to the appropriate clock ticks before using. 2260 */ 2261 static int 2262 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2263 { 2264 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2265 } 2266 2267 static int 2268 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2269 { 2270 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2271 } 2272