1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.110.2.30 2003/06/12 16:47:05 mux Exp $ 29 * $DragonFly: src/sys/dev/netif/fxp/if_fxp.c,v 1.50 2007/09/15 21:28:15 swildner Exp $ 30 */ 31 32 /* 33 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 34 */ 35 36 #include "opt_polling.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/mbuf.h> 41 #include <sys/malloc.h> 42 #include <sys/kernel.h> 43 #include <sys/socket.h> 44 #include <sys/sysctl.h> 45 #include <sys/thread2.h> 46 47 #include <net/if.h> 48 #include <net/ifq_var.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 52 #ifdef NS 53 #include <netns/ns.h> 54 #include <netns/ns_if.h> 55 #endif 56 57 #include <net/bpf.h> 58 #include <sys/sockio.h> 59 #include <sys/bus.h> 60 #include <sys/rman.h> 61 62 #include <net/ethernet.h> 63 #include <net/if_arp.h> 64 65 #include <vm/vm.h> /* for vtophys */ 66 #include <vm/pmap.h> /* for vtophys */ 67 68 #include <net/if_types.h> 69 #include <net/vlan/if_vlan_var.h> 70 71 #include <bus/pci/pcivar.h> 72 #include <bus/pci/pcireg.h> /* for PCIM_CMD_xxx */ 73 74 #include "../mii_layer/mii.h" 75 #include "../mii_layer/miivar.h" 76 77 #include "if_fxpreg.h" 78 #include "if_fxpvar.h" 79 #include "rcvbundl.h" 80 81 #include "miibus_if.h" 82 83 /* 84 * NOTE! On the Alpha, we have an alignment constraint. The 85 * card DMAs the packet immediately following the RFA. However, 86 * the first thing in the packet is a 14-byte Ethernet header. 87 * This means that the packet is misaligned. To compensate, 88 * we actually offset the RFA 2 bytes into the cluster. This 89 * alignes the packet after the Ethernet header at a 32-bit 90 * boundary. HOWEVER! This means that the RFA is misaligned! 91 */ 92 #define RFA_ALIGNMENT_FUDGE 2 93 94 /* 95 * Set initial transmit threshold at 64 (512 bytes). This is 96 * increased by 64 (512 bytes) at a time, to maximum of 192 97 * (1536 bytes), if an underrun occurs. 98 */ 99 static int tx_threshold = 64; 100 101 /* 102 * The configuration byte map has several undefined fields which 103 * must be one or must be zero. Set up a template for these bits 104 * only, (assuming a 82557 chip) leaving the actual configuration 105 * to fxp_init. 106 * 107 * See struct fxp_cb_config for the bit definitions. 108 */ 109 static u_char fxp_cb_config_template[] = { 110 0x0, 0x0, /* cb_status */ 111 0x0, 0x0, /* cb_command */ 112 0x0, 0x0, 0x0, 0x0, /* link_addr */ 113 0x0, /* 0 */ 114 0x0, /* 1 */ 115 0x0, /* 2 */ 116 0x0, /* 3 */ 117 0x0, /* 4 */ 118 0x0, /* 5 */ 119 0x32, /* 6 */ 120 0x0, /* 7 */ 121 0x0, /* 8 */ 122 0x0, /* 9 */ 123 0x6, /* 10 */ 124 0x0, /* 11 */ 125 0x0, /* 12 */ 126 0x0, /* 13 */ 127 0xf2, /* 14 */ 128 0x48, /* 15 */ 129 0x0, /* 16 */ 130 0x40, /* 17 */ 131 0xf0, /* 18 */ 132 0x0, /* 19 */ 133 0x3f, /* 20 */ 134 0x5 /* 21 */ 135 }; 136 137 struct fxp_ident { 138 u_int16_t devid; 139 int16_t revid; /* -1 matches anything */ 140 char *name; 141 }; 142 143 /* 144 * Claim various Intel PCI device identifiers for this driver. The 145 * sub-vendor and sub-device field are extensively used to identify 146 * particular variants, but we don't currently differentiate between 147 * them. 148 */ 149 static struct fxp_ident fxp_ident_table[] = { 150 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, 151 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, 152 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 153 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, 154 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 155 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 156 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 157 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 158 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, 159 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, 160 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 161 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 162 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 163 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, 164 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, 165 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, 166 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, 167 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" }, 168 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, 169 { 0x1064, -1, "Intel 82562ET/EZ/GT/GZ (ICH6/ICH6R) Pro/100 VE Ethernet" }, 170 { 0x1065, -1, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" }, 171 { 0x1068, -1, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" }, 172 { 0x1069, -1, "Intel 82562EM/EX/GX Pro/100 Ethernet" }, 173 { 0x1091, -1, "Intel 82562GX Pro/100 Ethernet" }, 174 { 0x1092, -1, "Intel Pro/100 VE Network Connection" }, 175 { 0x1093, -1, "Intel Pro/100 VM Network Connection" }, 176 { 0x1094, -1, "Intel Pro/100 946GZ (ICH7) Network Connection" }, 177 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, 178 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, 179 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, 180 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, 181 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, 182 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, 183 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, 184 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, 185 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, 186 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, 187 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, 188 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, 189 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, 190 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, 191 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, 192 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, 193 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, 194 { 0x27dc, -1, "Intel 82801GB (ICH7) 10/100 Ethernet" }, 195 { 0, -1, NULL }, 196 }; 197 198 static int fxp_probe(device_t dev); 199 static int fxp_attach(device_t dev); 200 static int fxp_detach(device_t dev); 201 static int fxp_shutdown(device_t dev); 202 static int fxp_suspend(device_t dev); 203 static int fxp_resume(device_t dev); 204 205 static void fxp_intr(void *xsc); 206 static void fxp_intr_body(struct fxp_softc *sc, 207 u_int8_t statack, int count); 208 209 static void fxp_init(void *xsc); 210 static void fxp_tick(void *xsc); 211 static void fxp_powerstate_d0(device_t dev); 212 static void fxp_start(struct ifnet *ifp); 213 static void fxp_stop(struct fxp_softc *sc); 214 static void fxp_release(device_t dev); 215 static int fxp_ioctl(struct ifnet *ifp, u_long command, 216 caddr_t data, struct ucred *); 217 static void fxp_watchdog(struct ifnet *ifp); 218 static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm); 219 static int fxp_mc_addrs(struct fxp_softc *sc); 220 static void fxp_mc_setup(struct fxp_softc *sc); 221 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 222 int autosize); 223 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 224 u_int16_t data); 225 static void fxp_autosize_eeprom(struct fxp_softc *sc); 226 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 227 int offset, int words); 228 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 229 int offset, int words); 230 static int fxp_ifmedia_upd(struct ifnet *ifp); 231 static void fxp_ifmedia_sts(struct ifnet *ifp, 232 struct ifmediareq *ifmr); 233 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 234 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 235 struct ifmediareq *ifmr); 236 static int fxp_miibus_readreg(device_t dev, int phy, int reg); 237 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 238 int value); 239 static void fxp_load_ucode(struct fxp_softc *sc); 240 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 241 int low, int high); 242 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 243 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 244 #ifdef DEVICE_POLLING 245 static poll_handler_t fxp_poll; 246 #endif 247 248 static void fxp_lwcopy(volatile u_int32_t *src, 249 volatile u_int32_t *dst); 250 static void fxp_scb_wait(struct fxp_softc *sc); 251 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 252 static void fxp_dma_wait(volatile u_int16_t *status, 253 struct fxp_softc *sc); 254 255 static device_method_t fxp_methods[] = { 256 /* Device interface */ 257 DEVMETHOD(device_probe, fxp_probe), 258 DEVMETHOD(device_attach, fxp_attach), 259 DEVMETHOD(device_detach, fxp_detach), 260 DEVMETHOD(device_shutdown, fxp_shutdown), 261 DEVMETHOD(device_suspend, fxp_suspend), 262 DEVMETHOD(device_resume, fxp_resume), 263 264 /* MII interface */ 265 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 266 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 267 268 { 0, 0 } 269 }; 270 271 static driver_t fxp_driver = { 272 "fxp", 273 fxp_methods, 274 sizeof(struct fxp_softc), 275 }; 276 277 static devclass_t fxp_devclass; 278 279 DECLARE_DUMMY_MODULE(if_fxp); 280 MODULE_DEPEND(if_fxp, miibus, 1, 1, 1); 281 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 282 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 283 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 284 285 static int fxp_rnr; 286 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 287 288 /* 289 * Copy a 16-bit aligned 32-bit quantity. 290 */ 291 static void 292 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst) 293 { 294 #ifdef __i386__ 295 *dst = *src; 296 #else 297 volatile u_int16_t *a = (volatile u_int16_t *)src; 298 volatile u_int16_t *b = (volatile u_int16_t *)dst; 299 300 b[0] = a[0]; 301 b[1] = a[1]; 302 #endif 303 } 304 305 /* 306 * Wait for the previous command to be accepted (but not necessarily 307 * completed). 308 */ 309 static void 310 fxp_scb_wait(struct fxp_softc *sc) 311 { 312 int i = 10000; 313 314 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 315 DELAY(2); 316 if (i == 0) { 317 if_printf(&sc->arpcom.ac_if, 318 "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 319 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 320 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 321 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 322 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 323 } 324 } 325 326 static void 327 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 328 { 329 330 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 331 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 332 fxp_scb_wait(sc); 333 } 334 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 335 } 336 337 static void 338 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc) 339 { 340 int i = 10000; 341 342 while (!(*status & FXP_CB_STATUS_C) && --i) 343 DELAY(2); 344 if (i == 0) 345 if_printf(&sc->arpcom.ac_if, "DMA timeout\n"); 346 } 347 348 /* 349 * Return identification string if this is device is ours. 350 */ 351 static int 352 fxp_probe(device_t dev) 353 { 354 u_int16_t devid; 355 u_int8_t revid; 356 struct fxp_ident *ident; 357 358 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 359 devid = pci_get_device(dev); 360 revid = pci_get_revid(dev); 361 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 362 if (ident->devid == devid && 363 (ident->revid == revid || ident->revid == -1)) { 364 device_set_desc(dev, ident->name); 365 return (0); 366 } 367 } 368 } 369 return (ENXIO); 370 } 371 372 static void 373 fxp_powerstate_d0(device_t dev) 374 { 375 u_int32_t iobase, membase, irq; 376 377 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 378 /* Save important PCI config data. */ 379 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 380 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 381 irq = pci_read_config(dev, PCIR_INTLINE, 4); 382 383 /* Reset the power state. */ 384 device_printf(dev, "chip is in D%d power mode " 385 "-- setting to D0\n", pci_get_powerstate(dev)); 386 387 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 388 389 /* Restore PCI config data. */ 390 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 391 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 392 pci_write_config(dev, PCIR_INTLINE, irq, 4); 393 } 394 } 395 396 static int 397 fxp_attach(device_t dev) 398 { 399 int error = 0; 400 struct fxp_softc *sc = device_get_softc(dev); 401 struct ifnet *ifp; 402 u_int32_t val; 403 u_int16_t data; 404 int i, rid, m1, m2, prefer_iomap; 405 406 callout_init(&sc->fxp_stat_timer); 407 sysctl_ctx_init(&sc->sysctl_ctx); 408 409 /* 410 * Enable bus mastering. Enable memory space too, in case 411 * BIOS/Prom forgot about it. 412 */ 413 pci_enable_busmaster(dev); 414 pci_enable_io(dev, SYS_RES_MEMORY); 415 val = pci_read_config(dev, PCIR_COMMAND, 2); 416 417 fxp_powerstate_d0(dev); 418 419 /* 420 * Figure out which we should try first - memory mapping or i/o mapping? 421 * We default to memory mapping. Then we accept an override from the 422 * command line. Then we check to see which one is enabled. 423 */ 424 m1 = PCIM_CMD_MEMEN; 425 m2 = PCIM_CMD_PORTEN; 426 prefer_iomap = 0; 427 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 428 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 429 m1 = PCIM_CMD_PORTEN; 430 m2 = PCIM_CMD_MEMEN; 431 } 432 433 if (val & m1) { 434 sc->rtp = 435 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 436 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 437 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 438 RF_ACTIVE); 439 } 440 if (sc->mem == NULL && (val & m2)) { 441 sc->rtp = 442 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 443 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 444 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd, 445 RF_ACTIVE); 446 } 447 448 if (!sc->mem) { 449 device_printf(dev, "could not map device registers\n"); 450 error = ENXIO; 451 goto fail; 452 } 453 if (bootverbose) { 454 device_printf(dev, "using %s space register mapping\n", 455 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 456 } 457 458 sc->sc_st = rman_get_bustag(sc->mem); 459 sc->sc_sh = rman_get_bushandle(sc->mem); 460 461 /* 462 * Allocate our interrupt. 463 */ 464 rid = 0; 465 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 466 RF_SHAREABLE | RF_ACTIVE); 467 if (sc->irq == NULL) { 468 device_printf(dev, "could not map interrupt\n"); 469 error = ENXIO; 470 goto fail; 471 } 472 473 /* 474 * Reset to a stable state. 475 */ 476 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 477 DELAY(10); 478 479 sc->cbl_base = kmalloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 480 M_DEVBUF, M_WAITOK | M_ZERO); 481 482 sc->fxp_stats = kmalloc(sizeof(struct fxp_stats), M_DEVBUF, 483 M_WAITOK | M_ZERO); 484 485 sc->mcsp = kmalloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_WAITOK); 486 487 /* 488 * Pre-allocate our receive buffers. 489 */ 490 for (i = 0; i < FXP_NRFABUFS; i++) { 491 if (fxp_add_rfabuf(sc, NULL) != 0) { 492 goto failmem; 493 } 494 } 495 496 /* 497 * Find out how large of an SEEPROM we have. 498 */ 499 fxp_autosize_eeprom(sc); 500 501 /* 502 * Determine whether we must use the 503 serial interface. 503 */ 504 fxp_read_eeprom(sc, &data, 6, 1); 505 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 506 (data & FXP_PHY_SERIAL_ONLY)) 507 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 508 509 /* 510 * Create the sysctl tree 511 */ 512 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 513 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 514 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 515 if (sc->sysctl_tree == NULL) 516 goto fail; 517 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 518 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 519 &sc->tunable_int_delay, 0, &sysctl_hw_fxp_int_delay, "I", 520 "FXP driver receive interrupt microcode bundling delay"); 521 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 522 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 523 &sc->tunable_bundle_max, 0, &sysctl_hw_fxp_bundle_max, "I", 524 "FXP driver receive interrupt microcode bundle size limit"); 525 526 /* 527 * Pull in device tunables. 528 */ 529 sc->tunable_int_delay = TUNABLE_INT_DELAY; 530 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 531 resource_int_value(device_get_name(dev), device_get_unit(dev), 532 "int_delay", &sc->tunable_int_delay); 533 resource_int_value(device_get_name(dev), device_get_unit(dev), 534 "bundle_max", &sc->tunable_bundle_max); 535 536 /* 537 * Find out the chip revision; lump all 82557 revs together. 538 */ 539 fxp_read_eeprom(sc, &data, 5, 1); 540 if ((data >> 8) == 1) 541 sc->revision = FXP_REV_82557; 542 else 543 sc->revision = pci_get_revid(dev); 544 545 /* 546 * Enable workarounds for certain chip revision deficiencies. 547 * 548 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 549 * some systems based a normal 82559 design, have a defect where 550 * the chip can cause a PCI protocol violation if it receives 551 * a CU_RESUME command when it is entering the IDLE state. The 552 * workaround is to disable Dynamic Standby Mode, so the chip never 553 * deasserts CLKRUN#, and always remains in an active state. 554 * 555 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 556 */ 557 i = pci_get_device(dev); 558 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 559 sc->revision >= FXP_REV_82559_A0) { 560 fxp_read_eeprom(sc, &data, 10, 1); 561 if (data & 0x02) { /* STB enable */ 562 u_int16_t cksum; 563 int i; 564 565 device_printf(dev, 566 "Disabling dynamic standby mode in EEPROM\n"); 567 data &= ~0x02; 568 fxp_write_eeprom(sc, &data, 10, 1); 569 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 570 cksum = 0; 571 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 572 fxp_read_eeprom(sc, &data, i, 1); 573 cksum += data; 574 } 575 i = (1 << sc->eeprom_size) - 1; 576 cksum = 0xBABA - cksum; 577 fxp_read_eeprom(sc, &data, i, 1); 578 fxp_write_eeprom(sc, &cksum, i, 1); 579 device_printf(dev, 580 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 581 i, data, cksum); 582 #if 1 583 /* 584 * If the user elects to continue, try the software 585 * workaround, as it is better than nothing. 586 */ 587 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 588 #endif 589 } 590 } 591 592 /* 593 * If we are not a 82557 chip, we can enable extended features. 594 */ 595 if (sc->revision != FXP_REV_82557) { 596 /* 597 * If MWI is enabled in the PCI configuration, and there 598 * is a valid cacheline size (8 or 16 dwords), then tell 599 * the board to turn on MWI. 600 */ 601 if (val & PCIM_CMD_MWRICEN && 602 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 603 sc->flags |= FXP_FLAG_MWI_ENABLE; 604 605 /* turn on the extended TxCB feature */ 606 sc->flags |= FXP_FLAG_EXT_TXCB; 607 608 /* enable reception of long frames for VLAN */ 609 sc->flags |= FXP_FLAG_LONG_PKT_EN; 610 } 611 612 /* 613 * Read MAC address. 614 */ 615 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3); 616 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) 617 device_printf(dev, "10Mbps\n"); 618 if (bootverbose) { 619 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 620 pci_get_vendor(dev), pci_get_device(dev), 621 pci_get_subvendor(dev), pci_get_subdevice(dev), 622 pci_get_revid(dev)); 623 fxp_read_eeprom(sc, &data, 10, 1); 624 device_printf(dev, "Dynamic Standby mode is %s\n", 625 data & 0x02 ? "enabled" : "disabled"); 626 } 627 628 /* 629 * If this is only a 10Mbps device, then there is no MII, and 630 * the PHY will use a serial interface instead. 631 * 632 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 633 * doesn't have a programming interface of any sort. The 634 * media is sensed automatically based on how the link partner 635 * is configured. This is, in essence, manual configuration. 636 */ 637 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 638 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 639 fxp_serial_ifmedia_sts); 640 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 641 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 642 } else { 643 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 644 fxp_ifmedia_sts)) { 645 device_printf(dev, "MII without any PHY!\n"); 646 error = ENXIO; 647 goto fail; 648 } 649 } 650 651 ifp = &sc->arpcom.ac_if; 652 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 653 ifp->if_baudrate = 100000000; 654 ifp->if_init = fxp_init; 655 ifp->if_softc = sc; 656 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 657 ifp->if_ioctl = fxp_ioctl; 658 ifp->if_start = fxp_start; 659 #ifdef DEVICE_POLLING 660 ifp->if_poll = fxp_poll; 661 #endif 662 ifp->if_watchdog = fxp_watchdog; 663 664 /* 665 * Attach the interface. 666 */ 667 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL); 668 669 /* 670 * Tell the upper layer(s) we support long frames. 671 */ 672 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 673 674 /* 675 * Let the system queue as many packets as we have available 676 * TX descriptors. 677 */ 678 ifq_set_maxlen(&ifp->if_snd, FXP_NTXCB - 1); 679 ifq_set_ready(&ifp->if_snd); 680 681 error = bus_setup_intr(dev, sc->irq, INTR_NETSAFE, 682 fxp_intr, sc, &sc->ih, 683 ifp->if_serializer); 684 if (error) { 685 ether_ifdetach(ifp); 686 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) 687 ifmedia_removeall(&sc->sc_media); 688 device_printf(dev, "could not setup irq\n"); 689 goto fail; 690 } 691 692 return (0); 693 694 failmem: 695 device_printf(dev, "Failed to malloc memory\n"); 696 error = ENOMEM; 697 fail: 698 fxp_release(dev); 699 return (error); 700 } 701 702 /* 703 * release all resources 704 */ 705 static void 706 fxp_release(device_t dev) 707 { 708 struct fxp_softc *sc = device_get_softc(dev); 709 710 if (sc->miibus) 711 device_delete_child(dev, sc->miibus); 712 bus_generic_detach(dev); 713 714 if (sc->cbl_base) 715 kfree(sc->cbl_base, M_DEVBUF); 716 if (sc->fxp_stats) 717 kfree(sc->fxp_stats, M_DEVBUF); 718 if (sc->mcsp) 719 kfree(sc->mcsp, M_DEVBUF); 720 if (sc->rfa_headm) 721 m_freem(sc->rfa_headm); 722 723 if (sc->irq) 724 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq); 725 if (sc->mem) 726 bus_release_resource(dev, sc->rtp, sc->rgd, sc->mem); 727 728 sysctl_ctx_free(&sc->sysctl_ctx); 729 } 730 731 /* 732 * Detach interface. 733 */ 734 static int 735 fxp_detach(device_t dev) 736 { 737 struct fxp_softc *sc = device_get_softc(dev); 738 739 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 740 741 /* 742 * Stop DMA and drop transmit queue. 743 */ 744 fxp_stop(sc); 745 746 /* 747 * Disable interrupts. 748 * 749 * NOTE: This should be done after fxp_stop(), because software 750 * resetting in fxp_stop() may leave interrupts turned on. 751 */ 752 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 753 754 /* 755 * Free all media structures. 756 */ 757 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) 758 ifmedia_removeall(&sc->sc_media); 759 760 if (sc->ih) 761 bus_teardown_intr(dev, sc->irq, sc->ih); 762 763 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 764 765 /* 766 * Close down routes etc. 767 */ 768 ether_ifdetach(&sc->arpcom.ac_if); 769 770 /* Release our allocated resources. */ 771 fxp_release(dev); 772 773 return (0); 774 } 775 776 /* 777 * Device shutdown routine. Called at system shutdown after sync. The 778 * main purpose of this routine is to shut off receiver DMA so that 779 * kernel memory doesn't get clobbered during warmboot. 780 */ 781 static int 782 fxp_shutdown(device_t dev) 783 { 784 /* 785 * Make sure that DMA is disabled prior to reboot. Not doing 786 * do could allow DMA to corrupt kernel memory during the 787 * reboot before the driver initializes. 788 */ 789 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 790 return (0); 791 } 792 793 /* 794 * Device suspend routine. Stop the interface and save some PCI 795 * settings in case the BIOS doesn't restore them properly on 796 * resume. 797 */ 798 static int 799 fxp_suspend(device_t dev) 800 { 801 struct fxp_softc *sc = device_get_softc(dev); 802 int i; 803 804 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 805 806 fxp_stop(sc); 807 808 for (i = 0; i < 5; i++) 809 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 810 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 811 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 812 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 813 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 814 815 sc->suspended = 1; 816 817 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 818 return (0); 819 } 820 821 /* 822 * Device resume routine. Restore some PCI settings in case the BIOS 823 * doesn't, re-enable busmastering, and restart the interface if 824 * appropriate. 825 */ 826 static int 827 fxp_resume(device_t dev) 828 { 829 struct fxp_softc *sc = device_get_softc(dev); 830 struct ifnet *ifp = &sc->arpcom.ac_if; 831 int i; 832 833 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 834 835 fxp_powerstate_d0(dev); 836 837 /* better way to do this? */ 838 for (i = 0; i < 5; i++) 839 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 840 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 841 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 842 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 843 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 844 845 /* reenable busmastering and memory space */ 846 pci_enable_busmaster(dev); 847 pci_enable_io(dev, SYS_RES_MEMORY); 848 849 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 850 DELAY(10); 851 852 /* reinitialize interface if necessary */ 853 if (ifp->if_flags & IFF_UP) 854 fxp_init(sc); 855 856 sc->suspended = 0; 857 858 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 859 return (0); 860 } 861 862 static void 863 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 864 { 865 u_int16_t reg; 866 int x; 867 868 /* 869 * Shift in data. 870 */ 871 for (x = 1 << (length - 1); x; x >>= 1) { 872 if (data & x) 873 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 874 else 875 reg = FXP_EEPROM_EECS; 876 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 877 DELAY(1); 878 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 879 DELAY(1); 880 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 881 DELAY(1); 882 } 883 } 884 885 /* 886 * Read from the serial EEPROM. Basically, you manually shift in 887 * the read opcode (one bit at a time) and then shift in the address, 888 * and then you shift out the data (all of this one bit at a time). 889 * The word size is 16 bits, so you have to provide the address for 890 * every 16 bits of data. 891 */ 892 static u_int16_t 893 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 894 { 895 u_int16_t reg, data; 896 int x; 897 898 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 899 /* 900 * Shift in read opcode. 901 */ 902 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 903 /* 904 * Shift in address. 905 */ 906 data = 0; 907 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 908 if (offset & x) 909 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 910 else 911 reg = FXP_EEPROM_EECS; 912 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 913 DELAY(1); 914 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 915 DELAY(1); 916 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 917 DELAY(1); 918 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 919 data++; 920 if (autosize && reg == 0) { 921 sc->eeprom_size = data; 922 break; 923 } 924 } 925 /* 926 * Shift out data. 927 */ 928 data = 0; 929 reg = FXP_EEPROM_EECS; 930 for (x = 1 << 15; x; x >>= 1) { 931 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 932 DELAY(1); 933 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 934 data |= x; 935 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 936 DELAY(1); 937 } 938 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 939 DELAY(1); 940 941 return (data); 942 } 943 944 static void 945 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 946 { 947 int i; 948 949 /* 950 * Erase/write enable. 951 */ 952 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 953 fxp_eeprom_shiftin(sc, 0x4, 3); 954 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 955 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 956 DELAY(1); 957 /* 958 * Shift in write opcode, address, data. 959 */ 960 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 961 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 962 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 963 fxp_eeprom_shiftin(sc, data, 16); 964 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 965 DELAY(1); 966 /* 967 * Wait for EEPROM to finish up. 968 */ 969 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 970 DELAY(1); 971 for (i = 0; i < 1000; i++) { 972 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 973 break; 974 DELAY(50); 975 } 976 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 977 DELAY(1); 978 /* 979 * Erase/write disable. 980 */ 981 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 982 fxp_eeprom_shiftin(sc, 0x4, 3); 983 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 984 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 985 DELAY(1); 986 } 987 988 /* 989 * From NetBSD: 990 * 991 * Figure out EEPROM size. 992 * 993 * 559's can have either 64-word or 256-word EEPROMs, the 558 994 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 995 * talks about the existance of 16 to 256 word EEPROMs. 996 * 997 * The only known sizes are 64 and 256, where the 256 version is used 998 * by CardBus cards to store CIS information. 999 * 1000 * The address is shifted in msb-to-lsb, and after the last 1001 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 1002 * after which follows the actual data. We try to detect this zero, by 1003 * probing the data-out bit in the EEPROM control register just after 1004 * having shifted in a bit. If the bit is zero, we assume we've 1005 * shifted enough address bits. The data-out should be tri-state, 1006 * before this, which should translate to a logical one. 1007 */ 1008 static void 1009 fxp_autosize_eeprom(struct fxp_softc *sc) 1010 { 1011 1012 /* guess maximum size of 256 words */ 1013 sc->eeprom_size = 8; 1014 1015 /* autosize */ 1016 fxp_eeprom_getword(sc, 0, 1); 1017 } 1018 1019 static void 1020 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1021 { 1022 int i; 1023 1024 for (i = 0; i < words; i++) 1025 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 1026 } 1027 1028 static void 1029 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1030 { 1031 int i; 1032 1033 for (i = 0; i < words; i++) 1034 fxp_eeprom_putword(sc, offset + i, data[i]); 1035 } 1036 1037 /* 1038 * Start packet transmission on the interface. 1039 */ 1040 static void 1041 fxp_start(struct ifnet *ifp) 1042 { 1043 struct fxp_softc *sc = ifp->if_softc; 1044 struct fxp_cb_tx *txp; 1045 1046 /* 1047 * See if we need to suspend xmit until the multicast filter 1048 * has been reprogrammed (which can only be done at the head 1049 * of the command chain). 1050 */ 1051 if (sc->need_mcsetup) { 1052 return; 1053 } 1054 1055 txp = NULL; 1056 1057 /* 1058 * We're finished if there is nothing more to add to the list or if 1059 * we're all filled up with buffers to transmit. 1060 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1061 * a NOP command when needed. 1062 */ 1063 while (!ifq_is_empty(&ifp->if_snd) && sc->tx_queued < FXP_NTXCB - 1) { 1064 struct mbuf *m, *mb_head; 1065 int segment, ntries = 0; 1066 1067 /* 1068 * Grab a packet to transmit. The packet is dequeued, 1069 * once we are sure that we have enough free descriptors. 1070 */ 1071 mb_head = ifq_poll(&ifp->if_snd); 1072 if (mb_head == NULL) 1073 break; 1074 1075 /* 1076 * Get pointer to next available tx desc. 1077 */ 1078 txp = sc->cbl_last->next; 1079 1080 /* 1081 * Go through each of the mbufs in the chain and initialize 1082 * the transmit buffer descriptors with the physical address 1083 * and size of the mbuf. 1084 */ 1085 tbdinit: 1086 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 1087 if (m->m_len != 0) { 1088 if (segment == FXP_NTXSEG) 1089 break; 1090 txp->tbd[segment].tb_addr = 1091 vtophys(mtod(m, vm_offset_t)); 1092 txp->tbd[segment].tb_size = m->m_len; 1093 segment++; 1094 } 1095 } 1096 if (m != NULL) { 1097 struct mbuf *mn; 1098 1099 /* 1100 * We ran out of segments. We have to recopy this 1101 * mbuf chain first. Bail out if we can't get the 1102 * new buffers. 1103 */ 1104 if (ntries > 0) 1105 break; 1106 mn = m_dup(mb_head, MB_DONTWAIT); 1107 if (mn == NULL) 1108 break; 1109 /* We can transmit the packet, dequeue it. */ 1110 ifq_dequeue(&ifp->if_snd, mb_head); 1111 m_freem(mb_head); 1112 mb_head = mn; 1113 ntries = 1; 1114 goto tbdinit; 1115 } else { 1116 /* Nothing to worry about, just dequeue. */ 1117 ifq_dequeue(&ifp->if_snd, mb_head); 1118 } 1119 1120 txp->tbd_number = segment; 1121 txp->mb_head = mb_head; 1122 txp->cb_status = 0; 1123 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1124 txp->cb_command = 1125 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1126 FXP_CB_COMMAND_S; 1127 } else { 1128 txp->cb_command = 1129 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1130 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1131 /* 1132 * Set a 5 second timer just in case we don't hear 1133 * from the card again. 1134 */ 1135 ifp->if_timer = 5; 1136 } 1137 txp->tx_threshold = tx_threshold; 1138 1139 /* 1140 * Advance the end of list forward. 1141 */ 1142 1143 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1144 sc->cbl_last = txp; 1145 1146 /* 1147 * Advance the beginning of the list forward if there are 1148 * no other packets queued (when nothing is queued, cbl_first 1149 * sits on the last TxCB that was sent out). 1150 */ 1151 if (sc->tx_queued == 0) 1152 sc->cbl_first = txp; 1153 1154 sc->tx_queued++; 1155 1156 BPF_MTAP(ifp, mb_head); 1157 } 1158 1159 /* 1160 * We're finished. If we added to the list, issue a RESUME to get DMA 1161 * going again if suspended. 1162 */ 1163 if (txp != NULL) { 1164 fxp_scb_wait(sc); 1165 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1166 } 1167 } 1168 1169 #ifdef DEVICE_POLLING 1170 1171 static void 1172 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1173 { 1174 struct fxp_softc *sc = ifp->if_softc; 1175 u_int8_t statack; 1176 1177 switch(cmd) { 1178 case POLL_REGISTER: 1179 /* disable interrupts */ 1180 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1181 break; 1182 case POLL_DEREGISTER: 1183 /* enable interrupts */ 1184 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1185 break; 1186 default: 1187 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1188 FXP_SCB_STATACK_FR; 1189 if (cmd == POLL_AND_CHECK_STATUS) { 1190 u_int8_t tmp; 1191 1192 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1193 if (tmp == 0xff || tmp == 0) 1194 return; /* nothing to do */ 1195 tmp &= ~statack; 1196 /* ack what we can */ 1197 if (tmp != 0) 1198 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1199 statack |= tmp; 1200 } 1201 fxp_intr_body(sc, statack, count); 1202 break; 1203 } 1204 } 1205 1206 #endif /* DEVICE_POLLING */ 1207 1208 /* 1209 * Process interface interrupts. 1210 */ 1211 static void 1212 fxp_intr(void *xsc) 1213 { 1214 struct fxp_softc *sc = xsc; 1215 u_int8_t statack; 1216 1217 if (sc->suspended) { 1218 return; 1219 } 1220 1221 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1222 /* 1223 * It should not be possible to have all bits set; the 1224 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1225 * all bits are set, this may indicate that the card has 1226 * been physically ejected, so ignore it. 1227 */ 1228 if (statack == 0xff) 1229 return; 1230 1231 /* 1232 * First ACK all the interrupts in this pass. 1233 */ 1234 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1235 fxp_intr_body(sc, statack, -1); 1236 } 1237 } 1238 1239 static void 1240 fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count) 1241 { 1242 struct ifnet *ifp = &sc->arpcom.ac_if; 1243 struct mbuf *m; 1244 struct fxp_rfa *rfa; 1245 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1246 1247 if (rnr) 1248 fxp_rnr++; 1249 #ifdef DEVICE_POLLING 1250 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1251 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1252 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1253 rnr = 1; 1254 } 1255 #endif 1256 1257 /* 1258 * Free any finished transmit mbuf chains. 1259 * 1260 * Handle the CNA event likt a CXTNO event. It used to 1261 * be that this event (control unit not ready) was not 1262 * encountered, but it is now with the SMPng modifications. 1263 * The exact sequence of events that occur when the interface 1264 * is brought up are different now, and if this event 1265 * goes unhandled, the configuration/rxfilter setup sequence 1266 * can stall for several seconds. The result is that no 1267 * packets go out onto the wire for about 5 to 10 seconds 1268 * after the interface is ifconfig'ed for the first time. 1269 */ 1270 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1271 struct fxp_cb_tx *txp; 1272 1273 for (txp = sc->cbl_first; sc->tx_queued && 1274 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1275 txp = txp->next) { 1276 if ((m = txp->mb_head) != NULL) { 1277 txp->mb_head = NULL; 1278 sc->tx_queued--; 1279 m_freem(m); 1280 } else { 1281 sc->tx_queued--; 1282 } 1283 } 1284 sc->cbl_first = txp; 1285 ifp->if_timer = 0; 1286 if (sc->tx_queued == 0) { 1287 if (sc->need_mcsetup) 1288 fxp_mc_setup(sc); 1289 } 1290 /* 1291 * Try to start more packets transmitting. 1292 */ 1293 if (!ifq_is_empty(&ifp->if_snd)) 1294 (*ifp->if_start)(ifp); 1295 } 1296 1297 /* 1298 * Just return if nothing happened on the receive side. 1299 */ 1300 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1301 return; 1302 1303 /* 1304 * Process receiver interrupts. If a no-resource (RNR) 1305 * condition exists, get whatever packets we can and 1306 * re-start the receiver. 1307 * 1308 * When using polling, we do not process the list to completion, 1309 * so when we get an RNR interrupt we must defer the restart 1310 * until we hit the last buffer with the C bit set. 1311 * If we run out of cycles and rfa_headm has the C bit set, 1312 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1313 * that the info will be used in the subsequent polling cycle. 1314 */ 1315 for (;;) { 1316 m = sc->rfa_headm; 1317 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1318 RFA_ALIGNMENT_FUDGE); 1319 1320 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1321 if (count >= 0 && count-- == 0) { 1322 if (rnr) { 1323 /* Defer RNR processing until the next time. */ 1324 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1325 rnr = 0; 1326 } 1327 break; 1328 } 1329 #endif /* DEVICE_POLLING */ 1330 1331 if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0) 1332 break; 1333 1334 /* 1335 * Remove first packet from the chain. 1336 */ 1337 sc->rfa_headm = m->m_next; 1338 m->m_next = NULL; 1339 1340 /* 1341 * Add a new buffer to the receive chain. 1342 * If this fails, the old buffer is recycled 1343 * instead. 1344 */ 1345 if (fxp_add_rfabuf(sc, m) == 0) { 1346 int total_len; 1347 1348 /* 1349 * Fetch packet length (the top 2 bits of 1350 * actual_size are flags set by the controller 1351 * upon completion), and drop the packet in case 1352 * of bogus length or CRC errors. 1353 */ 1354 total_len = rfa->actual_size & 0x3fff; 1355 if (total_len < sizeof(struct ether_header) || 1356 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1357 sizeof(struct fxp_rfa) || 1358 rfa->rfa_status & FXP_RFA_STATUS_CRC) { 1359 m_freem(m); 1360 continue; 1361 } 1362 m->m_pkthdr.len = m->m_len = total_len; 1363 ifp->if_input(ifp, m); 1364 } 1365 } 1366 if (rnr) { 1367 fxp_scb_wait(sc); 1368 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1369 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1370 RFA_ALIGNMENT_FUDGE); 1371 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1372 } 1373 } 1374 1375 /* 1376 * Update packet in/out/collision statistics. The i82557 doesn't 1377 * allow you to access these counters without doing a fairly 1378 * expensive DMA to get _all_ of the statistics it maintains, so 1379 * we do this operation here only once per second. The statistics 1380 * counters in the kernel are updated from the previous dump-stats 1381 * DMA and then a new dump-stats DMA is started. The on-chip 1382 * counters are zeroed when the DMA completes. If we can't start 1383 * the DMA immediately, we don't wait - we just prepare to read 1384 * them again next time. 1385 */ 1386 static void 1387 fxp_tick(void *xsc) 1388 { 1389 struct fxp_softc *sc = xsc; 1390 struct ifnet *ifp = &sc->arpcom.ac_if; 1391 struct fxp_stats *sp = sc->fxp_stats; 1392 struct fxp_cb_tx *txp; 1393 struct mbuf *m; 1394 1395 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); 1396 1397 ifp->if_opackets += sp->tx_good; 1398 ifp->if_collisions += sp->tx_total_collisions; 1399 if (sp->rx_good) { 1400 ifp->if_ipackets += sp->rx_good; 1401 sc->rx_idle_secs = 0; 1402 } else { 1403 /* 1404 * Receiver's been idle for another second. 1405 */ 1406 sc->rx_idle_secs++; 1407 } 1408 ifp->if_ierrors += 1409 sp->rx_crc_errors + 1410 sp->rx_alignment_errors + 1411 sp->rx_rnr_errors + 1412 sp->rx_overrun_errors; 1413 /* 1414 * If any transmit underruns occured, bump up the transmit 1415 * threshold by another 512 bytes (64 * 8). 1416 */ 1417 if (sp->tx_underruns) { 1418 ifp->if_oerrors += sp->tx_underruns; 1419 if (tx_threshold < 192) 1420 tx_threshold += 64; 1421 } 1422 1423 /* 1424 * Release any xmit buffers that have completed DMA. This isn't 1425 * strictly necessary to do here, but it's advantagous for mbufs 1426 * with external storage to be released in a timely manner rather 1427 * than being defered for a potentially long time. This limits 1428 * the delay to a maximum of one second. 1429 */ 1430 for (txp = sc->cbl_first; sc->tx_queued && 1431 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1432 txp = txp->next) { 1433 if ((m = txp->mb_head) != NULL) { 1434 txp->mb_head = NULL; 1435 sc->tx_queued--; 1436 m_freem(m); 1437 } else { 1438 sc->tx_queued--; 1439 } 1440 } 1441 sc->cbl_first = txp; 1442 /* 1443 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1444 * then assume the receiver has locked up and attempt to clear 1445 * the condition by reprogramming the multicast filter. This is 1446 * a work-around for a bug in the 82557 where the receiver locks 1447 * up if it gets certain types of garbage in the syncronization 1448 * bits prior to the packet header. This bug is supposed to only 1449 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1450 * mode as well (perhaps due to a 10/100 speed transition). 1451 */ 1452 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1453 sc->rx_idle_secs = 0; 1454 fxp_mc_setup(sc); 1455 } 1456 /* 1457 * If there is no pending command, start another stats 1458 * dump. Otherwise punt for now. 1459 */ 1460 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1461 /* 1462 * Start another stats dump. 1463 */ 1464 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1465 } else { 1466 /* 1467 * A previous command is still waiting to be accepted. 1468 * Just zero our copy of the stats and wait for the 1469 * next timer event to update them. 1470 */ 1471 sp->tx_good = 0; 1472 sp->tx_underruns = 0; 1473 sp->tx_total_collisions = 0; 1474 1475 sp->rx_good = 0; 1476 sp->rx_crc_errors = 0; 1477 sp->rx_alignment_errors = 0; 1478 sp->rx_rnr_errors = 0; 1479 sp->rx_overrun_errors = 0; 1480 } 1481 if (sc->miibus != NULL) 1482 mii_tick(device_get_softc(sc->miibus)); 1483 /* 1484 * Schedule another timeout one second from now. 1485 */ 1486 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc); 1487 1488 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); 1489 } 1490 1491 /* 1492 * Stop the interface. Cancels the statistics updater and resets 1493 * the interface. 1494 */ 1495 static void 1496 fxp_stop(struct fxp_softc *sc) 1497 { 1498 struct ifnet *ifp = &sc->arpcom.ac_if; 1499 struct fxp_cb_tx *txp; 1500 int i; 1501 1502 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1503 ifp->if_timer = 0; 1504 1505 /* 1506 * Cancel stats updater. 1507 */ 1508 callout_stop(&sc->fxp_stat_timer); 1509 1510 /* 1511 * Issue software reset, which also unloads the microcode. 1512 */ 1513 sc->flags &= ~FXP_FLAG_UCODE; 1514 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1515 DELAY(50); 1516 1517 /* 1518 * Release any xmit buffers. 1519 */ 1520 txp = sc->cbl_base; 1521 if (txp != NULL) { 1522 for (i = 0; i < FXP_NTXCB; i++) { 1523 if (txp[i].mb_head != NULL) { 1524 m_freem(txp[i].mb_head); 1525 txp[i].mb_head = NULL; 1526 } 1527 } 1528 } 1529 sc->tx_queued = 0; 1530 1531 /* 1532 * Free all the receive buffers then reallocate/reinitialize 1533 */ 1534 if (sc->rfa_headm != NULL) 1535 m_freem(sc->rfa_headm); 1536 sc->rfa_headm = NULL; 1537 sc->rfa_tailm = NULL; 1538 for (i = 0; i < FXP_NRFABUFS; i++) { 1539 if (fxp_add_rfabuf(sc, NULL) != 0) { 1540 /* 1541 * This "can't happen" - we're at splimp() 1542 * and we just freed all the buffers we need 1543 * above. 1544 */ 1545 panic("fxp_stop: no buffers!"); 1546 } 1547 } 1548 } 1549 1550 /* 1551 * Watchdog/transmission transmit timeout handler. Called when a 1552 * transmission is started on the interface, but no interrupt is 1553 * received before the timeout. This usually indicates that the 1554 * card has wedged for some reason. 1555 */ 1556 static void 1557 fxp_watchdog(struct ifnet *ifp) 1558 { 1559 if_printf(ifp, "device timeout\n"); 1560 ifp->if_oerrors++; 1561 fxp_init(ifp->if_softc); 1562 } 1563 1564 static void 1565 fxp_init(void *xsc) 1566 { 1567 struct fxp_softc *sc = xsc; 1568 struct ifnet *ifp = &sc->arpcom.ac_if; 1569 struct fxp_cb_config *cbp; 1570 struct fxp_cb_ias *cb_ias; 1571 struct fxp_cb_tx *txp; 1572 struct fxp_cb_mcs *mcsp; 1573 int i, prm; 1574 1575 /* 1576 * Cancel any pending I/O 1577 */ 1578 fxp_stop(sc); 1579 1580 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1581 1582 /* 1583 * Initialize base of CBL and RFA memory. Loading with zero 1584 * sets it up for regular linear addressing. 1585 */ 1586 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1587 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1588 1589 fxp_scb_wait(sc); 1590 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1591 1592 /* 1593 * Initialize base of dump-stats buffer. 1594 */ 1595 fxp_scb_wait(sc); 1596 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1597 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1598 1599 /* 1600 * Attempt to load microcode if requested. 1601 */ 1602 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1603 fxp_load_ucode(sc); 1604 1605 /* 1606 * Initialize the multicast address list. 1607 */ 1608 if (fxp_mc_addrs(sc)) { 1609 mcsp = sc->mcsp; 1610 mcsp->cb_status = 0; 1611 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL; 1612 mcsp->link_addr = -1; 1613 /* 1614 * Start the multicast setup command. 1615 */ 1616 fxp_scb_wait(sc); 1617 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 1618 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1619 /* ...and wait for it to complete. */ 1620 fxp_dma_wait(&mcsp->cb_status, sc); 1621 } 1622 1623 /* 1624 * We temporarily use memory that contains the TxCB list to 1625 * construct the config CB. The TxCB list memory is rebuilt 1626 * later. 1627 */ 1628 cbp = (struct fxp_cb_config *) sc->cbl_base; 1629 1630 /* 1631 * This bcopy is kind of disgusting, but there are a bunch of must be 1632 * zero and must be one bits in this structure and this is the easiest 1633 * way to initialize them all to proper values. 1634 */ 1635 bcopy(fxp_cb_config_template, 1636 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1637 sizeof(fxp_cb_config_template)); 1638 1639 cbp->cb_status = 0; 1640 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1641 cbp->link_addr = -1; /* (no) next command */ 1642 cbp->byte_count = 22; /* (22) bytes to config */ 1643 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1644 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1645 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1646 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1647 cbp->type_enable = 0; /* actually reserved */ 1648 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1649 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1650 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1651 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1652 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1653 cbp->late_scb = 0; /* (don't) defer SCB update */ 1654 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 1655 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1656 cbp->ci_int = 1; /* interrupt on CU idle */ 1657 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 1658 cbp->ext_stats_dis = 1; /* disable extended counters */ 1659 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1660 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 1661 cbp->disc_short_rx = !prm; /* discard short packets */ 1662 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 1663 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1664 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1665 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 1666 cbp->csma_dis = 0; /* (don't) disable link */ 1667 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1668 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1669 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1670 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1671 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 1672 cbp->nsai = 1; /* (don't) disable source addr insert */ 1673 cbp->preamble_length = 2; /* (7 byte) preamble */ 1674 cbp->loopback = 0; /* (don't) loopback */ 1675 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1676 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1677 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1678 cbp->promiscuous = prm; /* promiscuous mode */ 1679 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1680 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1681 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1682 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1683 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 1684 1685 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1686 cbp->padding = 1; /* (do) pad short tx packets */ 1687 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1688 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 1689 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1690 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1691 /* must set wake_en in PMCSR also */ 1692 cbp->force_fdx = 0; /* (don't) force full duplex */ 1693 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1694 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1695 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 1696 1697 if (sc->revision == FXP_REV_82557) { 1698 /* 1699 * The 82557 has no hardware flow control, the values 1700 * below are the defaults for the chip. 1701 */ 1702 cbp->fc_delay_lsb = 0; 1703 cbp->fc_delay_msb = 0x40; 1704 cbp->pri_fc_thresh = 3; 1705 cbp->tx_fc_dis = 0; 1706 cbp->rx_fc_restop = 0; 1707 cbp->rx_fc_restart = 0; 1708 cbp->fc_filter = 0; 1709 cbp->pri_fc_loc = 1; 1710 } else { 1711 cbp->fc_delay_lsb = 0x1f; 1712 cbp->fc_delay_msb = 0x01; 1713 cbp->pri_fc_thresh = 3; 1714 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1715 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1716 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1717 cbp->fc_filter = !prm; /* drop FC frames to host */ 1718 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1719 } 1720 1721 /* 1722 * Start the config command/DMA. 1723 */ 1724 fxp_scb_wait(sc); 1725 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1726 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1727 /* ...and wait for it to complete. */ 1728 fxp_dma_wait(&cbp->cb_status, sc); 1729 1730 /* 1731 * Now initialize the station address. Temporarily use the TxCB 1732 * memory area like we did above for the config CB. 1733 */ 1734 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1735 cb_ias->cb_status = 0; 1736 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1737 cb_ias->link_addr = -1; 1738 bcopy(sc->arpcom.ac_enaddr, 1739 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1740 sizeof(sc->arpcom.ac_enaddr)); 1741 1742 /* 1743 * Start the IAS (Individual Address Setup) command/DMA. 1744 */ 1745 fxp_scb_wait(sc); 1746 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1747 /* ...and wait for it to complete. */ 1748 fxp_dma_wait(&cb_ias->cb_status, sc); 1749 1750 /* 1751 * Initialize transmit control block (TxCB) list. 1752 */ 1753 1754 txp = sc->cbl_base; 1755 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1756 for (i = 0; i < FXP_NTXCB; i++) { 1757 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1758 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1759 txp[i].link_addr = 1760 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1761 if (sc->flags & FXP_FLAG_EXT_TXCB) 1762 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]); 1763 else 1764 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1765 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1766 } 1767 /* 1768 * Set the suspend flag on the first TxCB and start the control 1769 * unit. It will execute the NOP and then suspend. 1770 */ 1771 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1772 sc->cbl_first = sc->cbl_last = txp; 1773 sc->tx_queued = 1; 1774 1775 fxp_scb_wait(sc); 1776 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1777 1778 /* 1779 * Initialize receiver buffer area - RFA. 1780 */ 1781 fxp_scb_wait(sc); 1782 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1783 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1784 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1785 1786 /* 1787 * Set current media. 1788 */ 1789 if (sc->miibus != NULL) 1790 mii_mediachg(device_get_softc(sc->miibus)); 1791 1792 ifp->if_flags |= IFF_RUNNING; 1793 ifp->if_flags &= ~IFF_OACTIVE; 1794 1795 /* 1796 * Enable interrupts. 1797 */ 1798 #ifdef DEVICE_POLLING 1799 /* 1800 * ... but only do that if we are not polling. And because (presumably) 1801 * the default is interrupts on, we need to disable them explicitly! 1802 */ 1803 if ( ifp->if_flags & IFF_POLLING ) 1804 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1805 else 1806 #endif /* DEVICE_POLLING */ 1807 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1808 1809 /* 1810 * Start stats updater. 1811 */ 1812 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc); 1813 } 1814 1815 static int 1816 fxp_serial_ifmedia_upd(struct ifnet *ifp) 1817 { 1818 1819 return (0); 1820 } 1821 1822 static void 1823 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1824 { 1825 1826 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 1827 } 1828 1829 /* 1830 * Change media according to request. 1831 */ 1832 static int 1833 fxp_ifmedia_upd(struct ifnet *ifp) 1834 { 1835 struct fxp_softc *sc = ifp->if_softc; 1836 struct mii_data *mii; 1837 1838 mii = device_get_softc(sc->miibus); 1839 mii_mediachg(mii); 1840 return (0); 1841 } 1842 1843 /* 1844 * Notify the world which media we're using. 1845 */ 1846 static void 1847 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1848 { 1849 struct fxp_softc *sc = ifp->if_softc; 1850 struct mii_data *mii; 1851 1852 mii = device_get_softc(sc->miibus); 1853 mii_pollstat(mii); 1854 ifmr->ifm_active = mii->mii_media_active; 1855 ifmr->ifm_status = mii->mii_media_status; 1856 1857 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 1858 sc->cu_resume_bug = 1; 1859 else 1860 sc->cu_resume_bug = 0; 1861 } 1862 1863 /* 1864 * Add a buffer to the end of the RFA buffer list. 1865 * Return 0 if successful, 1 for failure. A failure results in 1866 * adding the 'oldm' (if non-NULL) on to the end of the list - 1867 * tossing out its old contents and recycling it. 1868 * The RFA struct is stuck at the beginning of mbuf cluster and the 1869 * data pointer is fixed up to point just past it. 1870 */ 1871 static int 1872 fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm) 1873 { 1874 u_int32_t v; 1875 struct mbuf *m; 1876 struct fxp_rfa *rfa, *p_rfa; 1877 1878 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 1879 if (m == NULL) { /* try to recycle the old mbuf instead */ 1880 if (oldm == NULL) 1881 return 1; 1882 m = oldm; 1883 m->m_data = m->m_ext.ext_buf; 1884 } 1885 1886 /* 1887 * Move the data pointer up so that the incoming data packet 1888 * will be 32-bit aligned. 1889 */ 1890 m->m_data += RFA_ALIGNMENT_FUDGE; 1891 1892 /* 1893 * Get a pointer to the base of the mbuf cluster and move 1894 * data start past it. 1895 */ 1896 rfa = mtod(m, struct fxp_rfa *); 1897 m->m_data += sizeof(struct fxp_rfa); 1898 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); 1899 1900 /* 1901 * Initialize the rest of the RFA. Note that since the RFA 1902 * is misaligned, we cannot store values directly. Instead, 1903 * we use an optimized, inline copy. 1904 */ 1905 1906 rfa->rfa_status = 0; 1907 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1908 rfa->actual_size = 0; 1909 1910 v = -1; 1911 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 1912 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 1913 1914 /* 1915 * If there are other buffers already on the list, attach this 1916 * one to the end by fixing up the tail to point to this one. 1917 */ 1918 if (sc->rfa_headm != NULL) { 1919 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 1920 RFA_ALIGNMENT_FUDGE); 1921 sc->rfa_tailm->m_next = m; 1922 v = vtophys(rfa); 1923 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 1924 p_rfa->rfa_control = 0; 1925 } else { 1926 sc->rfa_headm = m; 1927 } 1928 sc->rfa_tailm = m; 1929 1930 return (m == oldm); 1931 } 1932 1933 static int 1934 fxp_miibus_readreg(device_t dev, int phy, int reg) 1935 { 1936 struct fxp_softc *sc = device_get_softc(dev); 1937 int count = 10000; 1938 int value; 1939 1940 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1941 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1942 1943 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1944 && count--) 1945 DELAY(10); 1946 1947 if (count <= 0) 1948 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 1949 1950 return (value & 0xffff); 1951 } 1952 1953 static void 1954 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 1955 { 1956 struct fxp_softc *sc = device_get_softc(dev); 1957 int count = 10000; 1958 1959 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1960 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1961 (value & 0xffff)); 1962 1963 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1964 count--) 1965 DELAY(10); 1966 1967 if (count <= 0) 1968 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 1969 } 1970 1971 static int 1972 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1973 { 1974 struct fxp_softc *sc = ifp->if_softc; 1975 struct ifreq *ifr = (struct ifreq *)data; 1976 struct mii_data *mii; 1977 int error = 0; 1978 1979 switch (command) { 1980 1981 case SIOCSIFFLAGS: 1982 if (ifp->if_flags & IFF_ALLMULTI) 1983 sc->flags |= FXP_FLAG_ALL_MCAST; 1984 else 1985 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1986 1987 /* 1988 * If interface is marked up and not running, then start it. 1989 * If it is marked down and running, stop it. 1990 * XXX If it's up then re-initialize it. This is so flags 1991 * such as IFF_PROMISC are handled. 1992 */ 1993 if (ifp->if_flags & IFF_UP) { 1994 fxp_init(sc); 1995 } else { 1996 if (ifp->if_flags & IFF_RUNNING) 1997 fxp_stop(sc); 1998 } 1999 break; 2000 2001 case SIOCADDMULTI: 2002 case SIOCDELMULTI: 2003 if (ifp->if_flags & IFF_ALLMULTI) 2004 sc->flags |= FXP_FLAG_ALL_MCAST; 2005 else 2006 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2007 /* 2008 * Multicast list has changed; set the hardware filter 2009 * accordingly. 2010 */ 2011 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2012 fxp_mc_setup(sc); 2013 /* 2014 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2015 * again rather than else {}. 2016 */ 2017 if (sc->flags & FXP_FLAG_ALL_MCAST) 2018 fxp_init(sc); 2019 error = 0; 2020 break; 2021 2022 case SIOCSIFMEDIA: 2023 case SIOCGIFMEDIA: 2024 if (sc->miibus != NULL) { 2025 mii = device_get_softc(sc->miibus); 2026 error = ifmedia_ioctl(ifp, ifr, 2027 &mii->mii_media, command); 2028 } else { 2029 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2030 } 2031 break; 2032 2033 default: 2034 error = ether_ioctl(ifp, command, data); 2035 break; 2036 } 2037 return (error); 2038 } 2039 2040 /* 2041 * Fill in the multicast address list and return number of entries. 2042 */ 2043 static int 2044 fxp_mc_addrs(struct fxp_softc *sc) 2045 { 2046 struct fxp_cb_mcs *mcsp = sc->mcsp; 2047 struct ifnet *ifp = &sc->arpcom.ac_if; 2048 struct ifmultiaddr *ifma; 2049 int nmcasts; 2050 2051 nmcasts = 0; 2052 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2053 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2054 if (ifma->ifma_addr->sa_family != AF_LINK) 2055 continue; 2056 if (nmcasts >= MAXMCADDR) { 2057 sc->flags |= FXP_FLAG_ALL_MCAST; 2058 nmcasts = 0; 2059 break; 2060 } 2061 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2062 (void *)(uintptr_t)(volatile void *) 2063 &sc->mcsp->mc_addr[nmcasts][0], 6); 2064 nmcasts++; 2065 } 2066 } 2067 mcsp->mc_cnt = nmcasts * 6; 2068 return (nmcasts); 2069 } 2070 2071 /* 2072 * Program the multicast filter. 2073 * 2074 * We have an artificial restriction that the multicast setup command 2075 * must be the first command in the chain, so we take steps to ensure 2076 * this. By requiring this, it allows us to keep up the performance of 2077 * the pre-initialized command ring (esp. link pointers) by not actually 2078 * inserting the mcsetup command in the ring - i.e. its link pointer 2079 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2080 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2081 * lead into the regular TxCB ring when it completes. 2082 * 2083 * This function must be called at splimp. 2084 */ 2085 static void 2086 fxp_mc_setup(struct fxp_softc *sc) 2087 { 2088 struct fxp_cb_mcs *mcsp = sc->mcsp; 2089 struct ifnet *ifp = &sc->arpcom.ac_if; 2090 int count; 2091 2092 /* 2093 * If there are queued commands, we must wait until they are all 2094 * completed. If we are already waiting, then add a NOP command 2095 * with interrupt option so that we're notified when all commands 2096 * have been completed - fxp_start() ensures that no additional 2097 * TX commands will be added when need_mcsetup is true. 2098 */ 2099 if (sc->tx_queued) { 2100 struct fxp_cb_tx *txp; 2101 2102 /* 2103 * need_mcsetup will be true if we are already waiting for the 2104 * NOP command to be completed (see below). In this case, bail. 2105 */ 2106 if (sc->need_mcsetup) 2107 return; 2108 sc->need_mcsetup = 1; 2109 2110 /* 2111 * Add a NOP command with interrupt so that we are notified 2112 * when all TX commands have been processed. 2113 */ 2114 txp = sc->cbl_last->next; 2115 txp->mb_head = NULL; 2116 txp->cb_status = 0; 2117 txp->cb_command = FXP_CB_COMMAND_NOP | 2118 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2119 /* 2120 * Advance the end of list forward. 2121 */ 2122 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 2123 sc->cbl_last = txp; 2124 sc->tx_queued++; 2125 /* 2126 * Issue a resume in case the CU has just suspended. 2127 */ 2128 fxp_scb_wait(sc); 2129 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2130 /* 2131 * Set a 5 second timer just in case we don't hear from the 2132 * card again. 2133 */ 2134 ifp->if_timer = 5; 2135 2136 return; 2137 } 2138 sc->need_mcsetup = 0; 2139 2140 /* 2141 * Initialize multicast setup descriptor. 2142 */ 2143 mcsp->next = sc->cbl_base; 2144 mcsp->mb_head = NULL; 2145 mcsp->cb_status = 0; 2146 mcsp->cb_command = FXP_CB_COMMAND_MCAS | 2147 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2148 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 2149 fxp_mc_addrs(sc); 2150 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 2151 sc->tx_queued = 1; 2152 2153 /* 2154 * Wait until command unit is not active. This should never 2155 * be the case when nothing is queued, but make sure anyway. 2156 */ 2157 count = 100; 2158 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2159 FXP_SCB_CUS_ACTIVE && --count) 2160 DELAY(10); 2161 if (count == 0) { 2162 if_printf(&sc->arpcom.ac_if, "command queue timeout\n"); 2163 return; 2164 } 2165 2166 /* 2167 * Start the multicast setup command. 2168 */ 2169 fxp_scb_wait(sc); 2170 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 2171 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2172 2173 ifp->if_timer = 2; 2174 return; 2175 } 2176 2177 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2178 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2179 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2180 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2181 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2182 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2183 2184 #define UCODE(x) x, sizeof(x) 2185 2186 struct ucode { 2187 u_int32_t revision; 2188 u_int32_t *ucode; 2189 int length; 2190 u_short int_delay_offset; 2191 u_short bundle_max_offset; 2192 } ucode_table[] = { 2193 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2194 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2195 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2196 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2197 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2198 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2199 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2200 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2201 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2202 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2203 { 0, NULL, 0, 0, 0 } 2204 }; 2205 2206 static void 2207 fxp_load_ucode(struct fxp_softc *sc) 2208 { 2209 struct ucode *uc; 2210 struct fxp_cb_ucode *cbp; 2211 2212 for (uc = ucode_table; uc->ucode != NULL; uc++) 2213 if (sc->revision == uc->revision) 2214 break; 2215 if (uc->ucode == NULL) 2216 return; 2217 cbp = (struct fxp_cb_ucode *)sc->cbl_base; 2218 cbp->cb_status = 0; 2219 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL; 2220 cbp->link_addr = -1; /* (no) next command */ 2221 memcpy(cbp->ucode, uc->ucode, uc->length); 2222 if (uc->int_delay_offset) 2223 *(u_short *)&cbp->ucode[uc->int_delay_offset] = 2224 sc->tunable_int_delay + sc->tunable_int_delay / 2; 2225 if (uc->bundle_max_offset) 2226 *(u_short *)&cbp->ucode[uc->bundle_max_offset] = 2227 sc->tunable_bundle_max; 2228 /* 2229 * Download the ucode to the chip. 2230 */ 2231 fxp_scb_wait(sc); 2232 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 2233 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2234 /* ...and wait for it to complete. */ 2235 fxp_dma_wait(&cbp->cb_status, sc); 2236 if_printf(&sc->arpcom.ac_if, 2237 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2238 sc->tunable_int_delay, 2239 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2240 sc->flags |= FXP_FLAG_UCODE; 2241 } 2242 2243 static int 2244 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2245 { 2246 int error, value; 2247 2248 value = *(int *)arg1; 2249 error = sysctl_handle_int(oidp, &value, 0, req); 2250 if (error || !req->newptr) 2251 return (error); 2252 if (value < low || value > high) 2253 return (EINVAL); 2254 *(int *)arg1 = value; 2255 return (0); 2256 } 2257 2258 /* 2259 * Interrupt delay is expressed in microseconds, a multiplier is used 2260 * to convert this to the appropriate clock ticks before using. 2261 */ 2262 static int 2263 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2264 { 2265 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2266 } 2267 2268 static int 2269 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2270 { 2271 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2272 } 2273