1 /* 2 * Copyright (c) 1995, David Greenman 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/fxp/if_fxpvar.h,v 1.17.2.6 2002/11/13 20:58:31 iedowse Exp $ 28 * $DragonFly: src/sys/dev/netif/fxp/if_fxpvar.h,v 1.9 2008/06/15 10:41:00 sephe Exp $ 29 */ 30 31 /* 32 * Misc. defintions for the Intel EtherExpress Pro/100B PCI Fast 33 * Ethernet driver 34 */ 35 36 /* 37 * Number of transmit control blocks. This determines the number 38 * of transmit buffers that can be chained in the CB list. 39 * This must be a power of two. 40 */ 41 #define FXP_NTXCB 128 42 #define FXP_USABLE_TXCB (FXP_NTXCB - 1) 43 44 /* 45 * Number of completed TX commands at which point an interrupt 46 * will be generated to garbage collect the attached buffers. 47 * Must be at least one less than FXP_NTXCB, and should be 48 * enough less so that the transmitter doesn't becomes idle 49 * during the buffer rundown (which would reduce performance). 50 */ 51 #define FXP_CXINT_THRESH 120 52 53 /* 54 * TxCB list index mask. This is used to do list wrap-around. 55 */ 56 #define FXP_TXCB_MASK (FXP_NTXCB - 1) 57 58 /* 59 * Number of receive frame area buffers. These are large so chose 60 * wisely. 61 */ 62 #ifdef IFPOLL_ENABLE 63 #define FXP_NRFABUFS 192 64 #else 65 #define FXP_NRFABUFS 64 66 #endif 67 68 /* 69 * Maximum number of seconds that the receiver can be idle before we 70 * assume it's dead and attempt to reset it by reprogramming the 71 * multicast filter. This is part of a work-around for a bug in the 72 * NIC. See fxp_stats_update(). 73 */ 74 #define FXP_MAX_RX_IDLE 15 75 76 /* 77 * Default maximum time, in microseconds, that an interrupt may be delayed 78 * in an attempt to coalesce interrupts. This is only effective if the Intel 79 * microcode is loaded, and may be changed via either loader tunables or 80 * sysctl. See also the CPUSAVER_DWORD entry in rcvbundl.h. 81 */ 82 #define TUNABLE_INT_DELAY 1000 83 84 /* 85 * Default number of packets that will be bundled, before an interrupt is 86 * generated. This is only effective if the Intel microcode is loaded, and 87 * may be changed via either loader tunables or sysctl. This may not be 88 * present in all microcode revisions, see also the CPUSAVER_BUNDLE_MAX_DWORD 89 * entry in rcvbundl.h. 90 */ 91 #define TUNABLE_BUNDLE_MAX 6 92 93 /* 94 * NOTE: Elements are ordered for optimal cacheline behavior, and NOT 95 * for functional grouping. 96 */ 97 struct fxp_softc { 98 struct arpcom arpcom; /* per-interface network data */ 99 struct resource *mem; /* resource descriptor for registers */ 100 int rtp; /* register resource type */ 101 int rgd; /* register descriptor in use */ 102 struct resource *irq; /* resource descriptor for interrupt */ 103 void *ih; /* interrupt handler cookie */ 104 bus_space_tag_t sc_st; /* bus space tag */ 105 bus_space_handle_t sc_sh; /* bus space handle */ 106 struct mbuf *rfa_headm; /* first mbuf in receive frame area */ 107 struct mbuf *rfa_tailm; /* last mbuf in receive frame area */ 108 struct fxp_cb_tx *cbl_first; /* first active TxCB in list */ 109 int tx_queued; /* # of active TxCB's */ 110 int need_mcsetup; /* multicast filter needs programming */ 111 struct fxp_cb_tx *cbl_last; /* last active TxCB in list */ 112 struct fxp_stats *fxp_stats; /* Pointer to interface stats */ 113 int rx_idle_secs; /* # of seconds RX has been idle */ 114 struct callout fxp_stat_timer; /* Handle for stat timeouts */ 115 struct fxp_cb_tx *cbl_base; /* base of TxCB list */ 116 struct fxp_cb_mcs *mcsp; /* Pointer to mcast setup descriptor */ 117 struct ifmedia sc_media; /* media information */ 118 struct ifpoll_compat fxp_npoll; /* polling */ 119 device_t miibus; 120 struct sysctl_ctx_list sysctl_ctx; 121 struct sysctl_oid *sysctl_tree; 122 int tunable_int_delay; /* interrupt delay value for ucode */ 123 int tunable_bundle_max; /* max # frames per interrupt (ucode) */ 124 int eeprom_size; /* size of serial EEPROM */ 125 int suspended; /* 0 = normal 1 = suspended (APM) */ 126 int cu_resume_bug; 127 int revision; 128 int flags; 129 u_int32_t saved_maps[5]; /* pci data */ 130 u_int32_t saved_biosaddr; 131 u_int8_t saved_intline; 132 u_int8_t saved_cachelnsz; 133 u_int8_t saved_lattimer; 134 }; 135 136 #define FXP_FLAG_MWI_ENABLE 0x0001 /* MWI enable */ 137 #define FXP_FLAG_READ_ALIGN 0x0002 /* align read access with cacheline */ 138 #define FXP_FLAG_WRITE_ALIGN 0x0004 /* end write on cacheline */ 139 #define FXP_FLAG_EXT_TXCB 0x0008 /* enable use of extended TXCB */ 140 #define FXP_FLAG_SERIAL_MEDIA 0x0010 /* 10Mbps serial interface */ 141 #define FXP_FLAG_LONG_PKT_EN 0x0020 /* enable long packet reception */ 142 #define FXP_FLAG_ALL_MCAST 0x0040 /* accept all multicast frames */ 143 #define FXP_FLAG_CU_RESUME_BUG 0x0080 /* requires workaround for CU_RESUME */ 144 #define FXP_FLAG_UCODE 0x0100 /* ucode is loaded */ 145 #define FXP_FLAG_DEFERRED_RNR 0x0200 /* IFPOLL_ENABLE deferred RNR */ 146 147 /* Macros to ease CSR access. */ 148 #define CSR_READ_1(sc, reg) \ 149 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg)) 150 #define CSR_READ_2(sc, reg) \ 151 bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg)) 152 #define CSR_READ_4(sc, reg) \ 153 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 154 #define CSR_WRITE_1(sc, reg, val) \ 155 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 156 #define CSR_WRITE_2(sc, reg, val) \ 157 bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 158 #define CSR_WRITE_4(sc, reg, val) \ 159 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 160