1 /****************************************************************************** 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 /* 36 * 80003ES2LAN Gigabit Ethernet Controller (Copper) 37 * 80003ES2LAN Gigabit Ethernet Controller (Serdes) 38 */ 39 40 #include "e1000_api.h" 41 42 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw); 43 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw); 44 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw); 45 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw); 46 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw); 47 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw); 48 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw); 49 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw); 50 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw); 51 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 52 u32 offset, 53 u16 *data); 54 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 55 u32 offset, 56 u16 data); 57 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, 58 u16 words, u16 *data); 59 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw); 60 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw); 61 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw); 62 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, 63 u16 *duplex); 64 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw); 65 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw); 66 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw); 67 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw); 68 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); 69 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex); 70 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw); 71 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw); 72 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 73 u16 *data); 74 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 75 u16 data); 76 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw); 77 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw); 78 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); 79 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw); 80 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw); 81 82 /* 83 * A table for the GG82563 cable length where the range is defined 84 * with a lower bound at "index" and the upper bound at 85 * "index + 5". 86 */ 87 static const u16 e1000_gg82563_cable_length_table[] = 88 { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF }; 89 #define GG82563_CABLE_LENGTH_TABLE_SIZE \ 90 (sizeof(e1000_gg82563_cable_length_table) / \ 91 sizeof(e1000_gg82563_cable_length_table[0])) 92 93 /** 94 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs. 95 * @hw: pointer to the HW structure 96 **/ 97 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw) 98 { 99 struct e1000_phy_info *phy = &hw->phy; 100 s32 ret_val = E1000_SUCCESS; 101 102 DEBUGFUNC("e1000_init_phy_params_80003es2lan"); 103 104 if (hw->phy.media_type != e1000_media_type_copper) { 105 phy->type = e1000_phy_none; 106 goto out; 107 } else { 108 phy->ops.power_up = e1000_power_up_phy_copper; 109 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan; 110 } 111 112 phy->addr = 1; 113 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 114 phy->reset_delay_us = 100; 115 phy->type = e1000_phy_gg82563; 116 117 phy->ops.acquire = e1000_acquire_phy_80003es2lan; 118 phy->ops.check_polarity = e1000_check_polarity_m88; 119 phy->ops.check_reset_block = e1000_check_reset_block_generic; 120 phy->ops.commit = e1000_phy_sw_reset_generic; 121 phy->ops.get_cfg_done = e1000_get_cfg_done_80003es2lan; 122 phy->ops.get_info = e1000_get_phy_info_m88; 123 phy->ops.release = e1000_release_phy_80003es2lan; 124 phy->ops.reset = e1000_phy_hw_reset_generic; 125 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 126 127 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan; 128 phy->ops.get_cable_length = e1000_get_cable_length_80003es2lan; 129 phy->ops.read_reg = e1000_read_phy_reg_gg82563_80003es2lan; 130 phy->ops.write_reg = e1000_write_phy_reg_gg82563_80003es2lan; 131 132 phy->ops.cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan; 133 134 /* This can only be done after all function pointers are setup. */ 135 ret_val = e1000_get_phy_id(hw); 136 137 /* Verify phy id */ 138 if (phy->id != GG82563_E_PHY_ID) { 139 ret_val = -E1000_ERR_PHY; 140 goto out; 141 } 142 143 out: 144 return ret_val; 145 } 146 147 /** 148 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs. 149 * @hw: pointer to the HW structure 150 **/ 151 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw) 152 { 153 struct e1000_nvm_info *nvm = &hw->nvm; 154 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 155 u16 size; 156 157 DEBUGFUNC("e1000_init_nvm_params_80003es2lan"); 158 159 nvm->opcode_bits = 8; 160 nvm->delay_usec = 1; 161 switch (nvm->override) { 162 case e1000_nvm_override_spi_large: 163 nvm->page_size = 32; 164 nvm->address_bits = 16; 165 break; 166 case e1000_nvm_override_spi_small: 167 nvm->page_size = 8; 168 nvm->address_bits = 8; 169 break; 170 default: 171 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 172 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 173 break; 174 } 175 176 nvm->type = e1000_nvm_eeprom_spi; 177 178 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 179 E1000_EECD_SIZE_EX_SHIFT); 180 181 /* 182 * Added to a constant, "size" becomes the left-shift value 183 * for setting word_size. 184 */ 185 size += NVM_WORD_SIZE_BASE_SHIFT; 186 187 /* EEPROM access above 16k is unsupported */ 188 if (size > 14) 189 size = 14; 190 nvm->word_size = 1 << size; 191 192 /* Function Pointers */ 193 nvm->ops.acquire = e1000_acquire_nvm_80003es2lan; 194 nvm->ops.read = e1000_read_nvm_eerd; 195 nvm->ops.release = e1000_release_nvm_80003es2lan; 196 nvm->ops.update = e1000_update_nvm_checksum_generic; 197 nvm->ops.valid_led_default = e1000_valid_led_default_generic; 198 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 199 nvm->ops.write = e1000_write_nvm_80003es2lan; 200 201 return E1000_SUCCESS; 202 } 203 204 /** 205 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs. 206 * @hw: pointer to the HW structure 207 **/ 208 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw) 209 { 210 struct e1000_mac_info *mac = &hw->mac; 211 s32 ret_val = E1000_SUCCESS; 212 213 DEBUGFUNC("e1000_init_mac_params_80003es2lan"); 214 215 /* Set media type */ 216 switch (hw->device_id) { 217 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 218 hw->phy.media_type = e1000_media_type_internal_serdes; 219 break; 220 default: 221 hw->phy.media_type = e1000_media_type_copper; 222 break; 223 } 224 225 /* Set mta register count */ 226 mac->mta_reg_count = 128; 227 /* Set rar entry count */ 228 mac->rar_entry_count = E1000_RAR_ENTRIES; 229 /* Set if part includes ASF firmware */ 230 mac->asf_firmware_present = TRUE; 231 /* Set if manageability features are enabled. */ 232 mac->arc_subsystem_valid = 233 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) 234 ? TRUE : FALSE; 235 236 /* Function pointers */ 237 238 /* bus type/speed/width */ 239 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 240 /* reset */ 241 mac->ops.reset_hw = e1000_reset_hw_80003es2lan; 242 /* hw initialization */ 243 mac->ops.init_hw = e1000_init_hw_80003es2lan; 244 /* link setup */ 245 mac->ops.setup_link = e1000_setup_link_generic; 246 /* physical interface link setup */ 247 mac->ops.setup_physical_interface = 248 (hw->phy.media_type == e1000_media_type_copper) 249 ? e1000_setup_copper_link_80003es2lan 250 : e1000_setup_fiber_serdes_link_generic; 251 /* check for link */ 252 switch (hw->phy.media_type) { 253 case e1000_media_type_copper: 254 mac->ops.check_for_link = e1000_check_for_copper_link_generic; 255 break; 256 case e1000_media_type_fiber: 257 mac->ops.check_for_link = e1000_check_for_fiber_link_generic; 258 break; 259 case e1000_media_type_internal_serdes: 260 mac->ops.check_for_link = e1000_check_for_serdes_link_generic; 261 break; 262 default: 263 ret_val = -E1000_ERR_CONFIG; 264 goto out; 265 break; 266 } 267 /* check management mode */ 268 mac->ops.check_mng_mode = e1000_check_mng_mode_generic; 269 /* multicast address update */ 270 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 271 /* writing VFTA */ 272 mac->ops.write_vfta = e1000_write_vfta_generic; 273 /* clearing VFTA */ 274 mac->ops.clear_vfta = e1000_clear_vfta_generic; 275 /* setting MTA */ 276 mac->ops.mta_set = e1000_mta_set_generic; 277 /* read mac address */ 278 mac->ops.read_mac_addr = e1000_read_mac_addr_80003es2lan; 279 /* blink LED */ 280 mac->ops.blink_led = e1000_blink_led_generic; 281 /* setup LED */ 282 mac->ops.setup_led = e1000_setup_led_generic; 283 /* cleanup LED */ 284 mac->ops.cleanup_led = e1000_cleanup_led_generic; 285 /* turn on/off LED */ 286 mac->ops.led_on = e1000_led_on_generic; 287 mac->ops.led_off = e1000_led_off_generic; 288 /* clear hardware counters */ 289 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan; 290 /* link info */ 291 mac->ops.get_link_up_info = e1000_get_link_up_info_80003es2lan; 292 293 out: 294 return ret_val; 295 } 296 297 /** 298 * e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs. 299 * @hw: pointer to the HW structure 300 * 301 * Called to initialize all function pointers and parameters. 302 **/ 303 void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw) 304 { 305 DEBUGFUNC("e1000_init_function_pointers_80003es2lan"); 306 307 hw->mac.ops.init_params = e1000_init_mac_params_80003es2lan; 308 hw->nvm.ops.init_params = e1000_init_nvm_params_80003es2lan; 309 hw->phy.ops.init_params = e1000_init_phy_params_80003es2lan; 310 e1000_get_bus_info_pcie_generic(hw); 311 } 312 313 /** 314 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY 315 * @hw: pointer to the HW structure 316 * 317 * A wrapper to acquire access rights to the correct PHY. 318 **/ 319 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw) 320 { 321 u16 mask; 322 323 DEBUGFUNC("e1000_acquire_phy_80003es2lan"); 324 325 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 326 return e1000_acquire_swfw_sync_80003es2lan(hw, mask); 327 } 328 329 /** 330 * e1000_release_phy_80003es2lan - Release rights to access PHY 331 * @hw: pointer to the HW structure 332 * 333 * A wrapper to release access rights to the correct PHY. 334 **/ 335 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw) 336 { 337 u16 mask; 338 339 DEBUGFUNC("e1000_release_phy_80003es2lan"); 340 341 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 342 e1000_release_swfw_sync_80003es2lan(hw, mask); 343 } 344 345 346 /** 347 * e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register 348 * @hw: pointer to the HW structure 349 * 350 * Acquire the semaphore to access the Kumeran interface. 351 * 352 **/ 353 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw) 354 { 355 u16 mask; 356 357 DEBUGFUNC("e1000_acquire_mac_csr_80003es2lan"); 358 359 mask = E1000_SWFW_CSR_SM; 360 361 return e1000_acquire_swfw_sync_80003es2lan(hw, mask); 362 } 363 364 /** 365 * e1000_release_mac_csr_80003es2lan - Release rights to access Kumeran Register 366 * @hw: pointer to the HW structure 367 * 368 * Release the semaphore used to access the Kumeran interface 369 **/ 370 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw) 371 { 372 u16 mask; 373 374 DEBUGFUNC("e1000_release_mac_csr_80003es2lan"); 375 376 mask = E1000_SWFW_CSR_SM; 377 378 e1000_release_swfw_sync_80003es2lan(hw, mask); 379 } 380 381 /** 382 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM 383 * @hw: pointer to the HW structure 384 * 385 * Acquire the semaphore to access the EEPROM. 386 **/ 387 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw) 388 { 389 s32 ret_val; 390 391 DEBUGFUNC("e1000_acquire_nvm_80003es2lan"); 392 393 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 394 if (ret_val) 395 goto out; 396 397 ret_val = e1000_acquire_nvm_generic(hw); 398 399 if (ret_val) 400 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 401 402 out: 403 return ret_val; 404 } 405 406 /** 407 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM 408 * @hw: pointer to the HW structure 409 * 410 * Release the semaphore used to access the EEPROM. 411 **/ 412 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw) 413 { 414 DEBUGFUNC("e1000_release_nvm_80003es2lan"); 415 416 e1000_release_nvm_generic(hw); 417 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 418 } 419 420 /** 421 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore 422 * @hw: pointer to the HW structure 423 * @mask: specifies which semaphore to acquire 424 * 425 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 426 * will also specify which port we're acquiring the lock for. 427 **/ 428 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) 429 { 430 u32 swfw_sync; 431 u32 swmask = mask; 432 u32 fwmask = mask << 16; 433 s32 ret_val = E1000_SUCCESS; 434 s32 i = 0, timeout = 50; 435 436 DEBUGFUNC("e1000_acquire_swfw_sync_80003es2lan"); 437 438 while (i < timeout) { 439 if (e1000_get_hw_semaphore_generic(hw)) { 440 ret_val = -E1000_ERR_SWFW_SYNC; 441 goto out; 442 } 443 444 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 445 if (!(swfw_sync & (fwmask | swmask))) 446 break; 447 448 /* 449 * Firmware currently using resource (fwmask) 450 * or other software thread using resource (swmask) 451 */ 452 e1000_put_hw_semaphore_generic(hw); 453 msec_delay_irq(5); 454 i++; 455 } 456 457 if (i == timeout) { 458 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 459 ret_val = -E1000_ERR_SWFW_SYNC; 460 goto out; 461 } 462 463 swfw_sync |= swmask; 464 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 465 466 e1000_put_hw_semaphore_generic(hw); 467 468 out: 469 return ret_val; 470 } 471 472 /** 473 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore 474 * @hw: pointer to the HW structure 475 * @mask: specifies which semaphore to acquire 476 * 477 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 478 * will also specify which port we're releasing the lock for. 479 **/ 480 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) 481 { 482 u32 swfw_sync; 483 484 DEBUGFUNC("e1000_release_swfw_sync_80003es2lan"); 485 486 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS) 487 ; /* Empty */ 488 489 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 490 swfw_sync &= ~mask; 491 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 492 493 e1000_put_hw_semaphore_generic(hw); 494 } 495 496 /** 497 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register 498 * @hw: pointer to the HW structure 499 * @offset: offset of the register to read 500 * @data: pointer to the data returned from the operation 501 * 502 * Read the GG82563 PHY register. 503 **/ 504 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 505 u32 offset, u16 *data) 506 { 507 s32 ret_val; 508 u32 page_select; 509 u16 temp; 510 511 DEBUGFUNC("e1000_read_phy_reg_gg82563_80003es2lan"); 512 513 ret_val = e1000_acquire_phy_80003es2lan(hw); 514 if (ret_val) 515 goto out; 516 517 /* Select Configuration Page */ 518 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 519 page_select = GG82563_PHY_PAGE_SELECT; 520 } else { 521 /* 522 * Use Alternative Page Select register to access 523 * registers 30 and 31 524 */ 525 page_select = GG82563_PHY_PAGE_SELECT_ALT; 526 } 527 528 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); 529 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp); 530 if (ret_val) { 531 e1000_release_phy_80003es2lan(hw); 532 goto out; 533 } 534 535 /* 536 * The "ready" bit in the MDIC register may be incorrectly set 537 * before the device has completed the "Page Select" MDI 538 * transaction. So we wait 200us after each MDI command... 539 */ 540 usec_delay(200); 541 542 /* ...and verify the command was successful. */ 543 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp); 544 545 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { 546 ret_val = -E1000_ERR_PHY; 547 e1000_release_phy_80003es2lan(hw); 548 goto out; 549 } 550 551 usec_delay(200); 552 553 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 554 data); 555 556 usec_delay(200); 557 e1000_release_phy_80003es2lan(hw); 558 559 out: 560 return ret_val; 561 } 562 563 /** 564 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register 565 * @hw: pointer to the HW structure 566 * @offset: offset of the register to read 567 * @data: value to write to the register 568 * 569 * Write to the GG82563 PHY register. 570 **/ 571 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 572 u32 offset, u16 data) 573 { 574 s32 ret_val; 575 u32 page_select; 576 u16 temp; 577 578 DEBUGFUNC("e1000_write_phy_reg_gg82563_80003es2lan"); 579 580 ret_val = e1000_acquire_phy_80003es2lan(hw); 581 if (ret_val) 582 goto out; 583 584 /* Select Configuration Page */ 585 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 586 page_select = GG82563_PHY_PAGE_SELECT; 587 } else { 588 /* 589 * Use Alternative Page Select register to access 590 * registers 30 and 31 591 */ 592 page_select = GG82563_PHY_PAGE_SELECT_ALT; 593 } 594 595 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); 596 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp); 597 if (ret_val) { 598 e1000_release_phy_80003es2lan(hw); 599 goto out; 600 } 601 602 603 /* 604 * The "ready" bit in the MDIC register may be incorrectly set 605 * before the device has completed the "Page Select" MDI 606 * transaction. So we wait 200us after each MDI command... 607 */ 608 usec_delay(200); 609 610 /* ...and verify the command was successful. */ 611 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp); 612 613 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { 614 ret_val = -E1000_ERR_PHY; 615 e1000_release_phy_80003es2lan(hw); 616 goto out; 617 } 618 619 usec_delay(200); 620 621 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 622 data); 623 624 usec_delay(200); 625 e1000_release_phy_80003es2lan(hw); 626 627 out: 628 return ret_val; 629 } 630 631 /** 632 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM 633 * @hw: pointer to the HW structure 634 * @offset: offset of the register to read 635 * @words: number of words to write 636 * @data: buffer of data to write to the NVM 637 * 638 * Write "words" of data to the ESB2 NVM. 639 **/ 640 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, 641 u16 words, u16 *data) 642 { 643 DEBUGFUNC("e1000_write_nvm_80003es2lan"); 644 645 return e1000_write_nvm_spi(hw, offset, words, data); 646 } 647 648 /** 649 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete 650 * @hw: pointer to the HW structure 651 * 652 * Wait a specific amount of time for manageability processes to complete. 653 * This is a function pointer entry point called by the phy module. 654 **/ 655 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw) 656 { 657 s32 timeout = PHY_CFG_TIMEOUT; 658 s32 ret_val = E1000_SUCCESS; 659 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 660 661 DEBUGFUNC("e1000_get_cfg_done_80003es2lan"); 662 663 if (hw->bus.func == 1) 664 mask = E1000_NVM_CFG_DONE_PORT_1; 665 666 while (timeout) { 667 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) 668 break; 669 msec_delay(1); 670 timeout--; 671 } 672 if (!timeout) { 673 DEBUGOUT("MNG configuration cycle has not completed.\n"); 674 ret_val = -E1000_ERR_RESET; 675 goto out; 676 } 677 678 out: 679 return ret_val; 680 } 681 682 /** 683 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex 684 * @hw: pointer to the HW structure 685 * 686 * Force the speed and duplex settings onto the PHY. This is a 687 * function pointer entry point called by the phy module. 688 **/ 689 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) 690 { 691 s32 ret_val = E1000_SUCCESS; 692 u16 phy_data; 693 bool link; 694 695 DEBUGFUNC("e1000_phy_force_speed_duplex_80003es2lan"); 696 697 if (!(hw->phy.ops.read_reg)) 698 goto out; 699 700 /* 701 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 702 * forced whenever speed and duplex are forced. 703 */ 704 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 705 if (ret_val) 706 goto out; 707 708 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO; 709 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); 710 if (ret_val) 711 goto out; 712 713 DEBUGOUT1("GG82563 PSCR: %X\n", phy_data); 714 715 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data); 716 if (ret_val) 717 goto out; 718 719 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 720 721 /* Reset the phy to commit changes. */ 722 phy_data |= MII_CR_RESET; 723 724 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data); 725 if (ret_val) 726 goto out; 727 728 usec_delay(1); 729 730 if (hw->phy.autoneg_wait_to_complete) { 731 DEBUGOUT("Waiting for forced speed/duplex link " 732 "on GG82563 phy.\n"); 733 734 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 735 100000, &link); 736 if (ret_val) 737 goto out; 738 739 if (!link) { 740 /* 741 * We didn't get link. 742 * Reset the DSP and cross our fingers. 743 */ 744 ret_val = e1000_phy_reset_dsp_generic(hw); 745 if (ret_val) 746 goto out; 747 } 748 749 /* Try once more */ 750 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 751 100000, &link); 752 if (ret_val) 753 goto out; 754 } 755 756 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); 757 if (ret_val) 758 goto out; 759 760 /* 761 * Resetting the phy means we need to verify the TX_CLK corresponds 762 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz. 763 */ 764 phy_data &= ~GG82563_MSCR_TX_CLK_MASK; 765 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED) 766 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5; 767 else 768 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25; 769 770 /* 771 * In addition, we must re-enable CRS on Tx for both half and full 772 * duplex. 773 */ 774 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 775 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data); 776 777 out: 778 return ret_val; 779 } 780 781 /** 782 * e1000_get_cable_length_80003es2lan - Set approximate cable length 783 * @hw: pointer to the HW structure 784 * 785 * Find the approximate cable length as measured by the GG82563 PHY. 786 * This is a function pointer entry point called by the phy module. 787 **/ 788 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw) 789 { 790 struct e1000_phy_info *phy = &hw->phy; 791 s32 ret_val = E1000_SUCCESS; 792 u16 phy_data, index; 793 794 DEBUGFUNC("e1000_get_cable_length_80003es2lan"); 795 796 if (!(hw->phy.ops.read_reg)) 797 goto out; 798 799 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data); 800 if (ret_val) 801 goto out; 802 803 index = phy_data & GG82563_DSPD_CABLE_LENGTH; 804 805 if (index < GG82563_CABLE_LENGTH_TABLE_SIZE + 5) { 806 phy->min_cable_length = e1000_gg82563_cable_length_table[index]; 807 phy->max_cable_length = 808 e1000_gg82563_cable_length_table[index+5]; 809 810 phy->cable_length = (phy->min_cable_length + 811 phy->max_cable_length) / 2; 812 } else { 813 ret_val = E1000_ERR_PHY; 814 } 815 816 out: 817 return ret_val; 818 } 819 820 /** 821 * e1000_get_link_up_info_80003es2lan - Report speed and duplex 822 * @hw: pointer to the HW structure 823 * @speed: pointer to speed buffer 824 * @duplex: pointer to duplex buffer 825 * 826 * Retrieve the current speed and duplex configuration. 827 **/ 828 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, 829 u16 *duplex) 830 { 831 s32 ret_val; 832 833 DEBUGFUNC("e1000_get_link_up_info_80003es2lan"); 834 835 if (hw->phy.media_type == e1000_media_type_copper) { 836 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, 837 speed, 838 duplex); 839 hw->phy.ops.cfg_on_link_up(hw); 840 } else { 841 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw, 842 speed, 843 duplex); 844 } 845 846 return ret_val; 847 } 848 849 /** 850 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller 851 * @hw: pointer to the HW structure 852 * 853 * Perform a global reset to the ESB2 controller. 854 **/ 855 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw) 856 { 857 u32 ctrl, icr; 858 s32 ret_val; 859 860 DEBUGFUNC("e1000_reset_hw_80003es2lan"); 861 862 /* 863 * Prevent the PCI-E bus from sticking if there is no TLP connection 864 * on the last TLP read/write transaction when MAC is reset. 865 */ 866 ret_val = e1000_disable_pcie_master_generic(hw); 867 if (ret_val) 868 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 869 870 DEBUGOUT("Masking off all interrupts\n"); 871 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 872 873 E1000_WRITE_REG(hw, E1000_RCTL, 0); 874 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 875 E1000_WRITE_FLUSH(hw); 876 877 msec_delay(10); 878 879 ctrl = E1000_READ_REG(hw, E1000_CTRL); 880 881 ret_val = e1000_acquire_phy_80003es2lan(hw); 882 DEBUGOUT("Issuing a global reset to MAC\n"); 883 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 884 e1000_release_phy_80003es2lan(hw); 885 886 ret_val = e1000_get_auto_rd_done_generic(hw); 887 if (ret_val) 888 /* We don't want to continue accessing MAC registers. */ 889 goto out; 890 891 /* Clear any pending interrupt events. */ 892 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 893 icr = E1000_READ_REG(hw, E1000_ICR); 894 895 e1000_check_alt_mac_addr_generic(hw); 896 897 out: 898 return ret_val; 899 } 900 901 /** 902 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller 903 * @hw: pointer to the HW structure 904 * 905 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters. 906 **/ 907 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw) 908 { 909 struct e1000_mac_info *mac = &hw->mac; 910 u32 reg_data; 911 s32 ret_val; 912 u16 i; 913 914 DEBUGFUNC("e1000_init_hw_80003es2lan"); 915 916 e1000_initialize_hw_bits_80003es2lan(hw); 917 918 /* Initialize identification LED */ 919 ret_val = e1000_id_led_init_generic(hw); 920 if (ret_val) { 921 DEBUGOUT("Error initializing identification LED\n"); 922 /* This is not fatal and we should not stop init due to this */ 923 } 924 925 /* Disabling VLAN filtering */ 926 DEBUGOUT("Initializing the IEEE VLAN\n"); 927 mac->ops.clear_vfta(hw); 928 929 /* Setup the receive address. */ 930 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 931 932 /* Zero out the Multicast HASH table */ 933 DEBUGOUT("Zeroing the MTA\n"); 934 for (i = 0; i < mac->mta_reg_count; i++) 935 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 936 937 /* Setup link and flow control */ 938 ret_val = mac->ops.setup_link(hw); 939 940 /* Set the transmit descriptor write-back policy */ 941 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0)); 942 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 943 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; 944 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data); 945 946 /* ...for both queues. */ 947 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1)); 948 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 949 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; 950 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data); 951 952 /* Enable retransmit on late collisions */ 953 reg_data = E1000_READ_REG(hw, E1000_TCTL); 954 reg_data |= E1000_TCTL_RTLC; 955 E1000_WRITE_REG(hw, E1000_TCTL, reg_data); 956 957 /* Configure Gigabit Carry Extend Padding */ 958 reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT); 959 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 960 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN; 961 E1000_WRITE_REG(hw, E1000_TCTL_EXT, reg_data); 962 963 /* Configure Transmit Inter-Packet Gap */ 964 reg_data = E1000_READ_REG(hw, E1000_TIPG); 965 reg_data &= ~E1000_TIPG_IPGT_MASK; 966 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; 967 E1000_WRITE_REG(hw, E1000_TIPG, reg_data); 968 969 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001); 970 reg_data &= ~0x00100000; 971 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data); 972 973 /* 974 * Clear all of the statistics registers (clear on read). It is 975 * important that we do this after we have tried to establish link 976 * because the symbol error count will increment wildly if there 977 * is no link. 978 */ 979 e1000_clear_hw_cntrs_80003es2lan(hw); 980 981 return ret_val; 982 } 983 984 /** 985 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2 986 * @hw: pointer to the HW structure 987 * 988 * Initializes required hardware-dependent bits needed for normal operation. 989 **/ 990 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw) 991 { 992 u32 reg; 993 994 DEBUGFUNC("e1000_initialize_hw_bits_80003es2lan"); 995 996 /* Transmit Descriptor Control 0 */ 997 reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 998 reg |= (1 << 22); 999 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 1000 1001 /* Transmit Descriptor Control 1 */ 1002 reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 1003 reg |= (1 << 22); 1004 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 1005 1006 /* Transmit Arbitration Control 0 */ 1007 reg = E1000_READ_REG(hw, E1000_TARC(0)); 1008 reg &= ~(0xF << 27); /* 30:27 */ 1009 if (hw->phy.media_type != e1000_media_type_copper) 1010 reg &= ~(1 << 20); 1011 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 1012 1013 /* Transmit Arbitration Control 1 */ 1014 reg = E1000_READ_REG(hw, E1000_TARC(1)); 1015 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 1016 reg &= ~(1 << 28); 1017 else 1018 reg |= (1 << 28); 1019 E1000_WRITE_REG(hw, E1000_TARC(1), reg); 1020 1021 return; 1022 } 1023 1024 /** 1025 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link 1026 * @hw: pointer to the HW structure 1027 * 1028 * Setup some GG82563 PHY registers for obtaining link 1029 **/ 1030 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) 1031 { 1032 struct e1000_phy_info *phy = &hw->phy; 1033 s32 ret_val; 1034 u32 ctrl_ext; 1035 u16 data; 1036 1037 DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan"); 1038 1039 if (!phy->reset_disable) { 1040 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 1041 &data); 1042 if (ret_val) 1043 goto out; 1044 1045 data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 1046 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */ 1047 data |= GG82563_MSCR_TX_CLK_1000MBPS_25; 1048 1049 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 1050 data); 1051 if (ret_val) 1052 goto out; 1053 1054 /* 1055 * Options: 1056 * MDI/MDI-X = 0 (default) 1057 * 0 - Auto for all speeds 1058 * 1 - MDI mode 1059 * 2 - MDI-X mode 1060 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1061 */ 1062 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL, &data); 1063 if (ret_val) 1064 goto out; 1065 1066 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 1067 1068 switch (phy->mdix) { 1069 case 1: 1070 data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 1071 break; 1072 case 2: 1073 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 1074 break; 1075 case 0: 1076 default: 1077 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 1078 break; 1079 } 1080 1081 /* 1082 * Options: 1083 * disable_polarity_correction = 0 (default) 1084 * Automatic Correction for Reversed Cable Polarity 1085 * 0 - Disabled 1086 * 1 - Enabled 1087 */ 1088 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1089 if (phy->disable_polarity_correction) 1090 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1091 1092 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data); 1093 if (ret_val) 1094 goto out; 1095 1096 /* SW Reset the PHY so all changes take effect */ 1097 ret_val = hw->phy.ops.commit(hw); 1098 if (ret_val) { 1099 DEBUGOUT("Error Resetting the PHY\n"); 1100 goto out; 1101 } 1102 1103 } 1104 1105 /* Bypass Rx and Tx FIFO's */ 1106 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, 1107 E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL, 1108 E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS | 1109 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS); 1110 if (ret_val) 1111 goto out; 1112 1113 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, 1114 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, 1115 &data); 1116 if (ret_val) 1117 goto out; 1118 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE; 1119 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, 1120 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, 1121 data); 1122 if (ret_val) 1123 goto out; 1124 1125 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data); 1126 if (ret_val) 1127 goto out; 1128 1129 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 1130 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data); 1131 if (ret_val) 1132 goto out; 1133 1134 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1135 ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 1136 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1137 1138 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data); 1139 if (ret_val) 1140 goto out; 1141 1142 /* 1143 * Do not init these registers when the HW is in IAMT mode, since the 1144 * firmware will have already initialized them. We only initialize 1145 * them if the HW is not in IAMT mode. 1146 */ 1147 if (!(hw->mac.ops.check_mng_mode(hw))) { 1148 /* Enable Electrical Idle on the PHY */ 1149 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 1150 ret_val = hw->phy.ops.write_reg(hw, 1151 GG82563_PHY_PWR_MGMT_CTRL, 1152 data); 1153 if (ret_val) 1154 goto out; 1155 ret_val = hw->phy.ops.read_reg(hw, 1156 GG82563_PHY_KMRN_MODE_CTRL, 1157 &data); 1158 if (ret_val) 1159 goto out; 1160 1161 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1162 ret_val = hw->phy.ops.write_reg(hw, 1163 GG82563_PHY_KMRN_MODE_CTRL, 1164 data); 1165 1166 if (ret_val) 1167 goto out; 1168 } 1169 1170 /* 1171 * Workaround: Disable padding in Kumeran interface in the MAC 1172 * and in the PHY to avoid CRC errors. 1173 */ 1174 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_INBAND_CTRL, &data); 1175 if (ret_val) 1176 goto out; 1177 1178 data |= GG82563_ICR_DIS_PADDING; 1179 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data); 1180 if (ret_val) 1181 goto out; 1182 1183 out: 1184 return ret_val; 1185 } 1186 1187 /** 1188 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2 1189 * @hw: pointer to the HW structure 1190 * 1191 * Essentially a wrapper for setting up all things "copper" related. 1192 * This is a function pointer entry point called by the mac module. 1193 **/ 1194 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw) 1195 { 1196 u32 ctrl; 1197 s32 ret_val; 1198 u16 reg_data; 1199 1200 DEBUGFUNC("e1000_setup_copper_link_80003es2lan"); 1201 1202 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1203 ctrl |= E1000_CTRL_SLU; 1204 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1205 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1206 1207 /* 1208 * Set the mac to wait the maximum time between each 1209 * iteration and increase the max iterations when 1210 * polling the phy; this fixes erroneous timeouts at 10Mbps. 1211 */ 1212 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4), 1213 0xFFFF); 1214 if (ret_val) 1215 goto out; 1216 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), 1217 ®_data); 1218 if (ret_val) 1219 goto out; 1220 reg_data |= 0x3F; 1221 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), 1222 reg_data); 1223 if (ret_val) 1224 goto out; 1225 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, 1226 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, 1227 ®_data); 1228 if (ret_val) 1229 goto out; 1230 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING; 1231 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, 1232 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, 1233 reg_data); 1234 if (ret_val) 1235 goto out; 1236 1237 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw); 1238 if (ret_val) 1239 goto out; 1240 1241 ret_val = e1000_setup_copper_link_generic(hw); 1242 1243 out: 1244 return ret_val; 1245 } 1246 1247 /** 1248 * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up 1249 * @hw: pointer to the HW structure 1250 * @duplex: current duplex setting 1251 * 1252 * Configure the KMRN interface by applying last minute quirks for 1253 * 10/100 operation. 1254 **/ 1255 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw) 1256 { 1257 s32 ret_val = E1000_SUCCESS; 1258 u16 speed; 1259 u16 duplex; 1260 1261 DEBUGFUNC("e1000_configure_on_link_up"); 1262 1263 if (hw->phy.media_type == e1000_media_type_copper) { 1264 1265 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, 1266 &speed, 1267 &duplex); 1268 if (ret_val) 1269 goto out; 1270 1271 if (speed == SPEED_1000) 1272 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw); 1273 else 1274 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex); 1275 } 1276 1277 out: 1278 return ret_val; 1279 } 1280 1281 /** 1282 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation 1283 * @hw: pointer to the HW structure 1284 * @duplex: current duplex setting 1285 * 1286 * Configure the KMRN interface by applying last minute quirks for 1287 * 10/100 operation. 1288 **/ 1289 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) 1290 { 1291 s32 ret_val = E1000_SUCCESS; 1292 u32 tipg; 1293 u32 i = 0; 1294 u16 reg_data, reg_data2; 1295 1296 DEBUGFUNC("e1000_configure_kmrn_for_10_100"); 1297 1298 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT; 1299 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, 1300 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, 1301 reg_data); 1302 if (ret_val) 1303 goto out; 1304 1305 /* Configure Transmit Inter-Packet Gap */ 1306 tipg = E1000_READ_REG(hw, E1000_TIPG); 1307 tipg &= ~E1000_TIPG_IPGT_MASK; 1308 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN; 1309 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 1310 1311 1312 do { 1313 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1314 ®_data); 1315 if (ret_val) 1316 goto out; 1317 1318 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1319 ®_data2); 1320 if (ret_val) 1321 goto out; 1322 i++; 1323 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); 1324 1325 if (duplex == HALF_DUPLEX) 1326 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 1327 else 1328 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1329 1330 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 1331 1332 out: 1333 return ret_val; 1334 } 1335 1336 /** 1337 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation 1338 * @hw: pointer to the HW structure 1339 * 1340 * Configure the KMRN interface by applying last minute quirks for 1341 * gigabit operation. 1342 **/ 1343 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) 1344 { 1345 s32 ret_val = E1000_SUCCESS; 1346 u16 reg_data, reg_data2; 1347 u32 tipg; 1348 u32 i = 0; 1349 1350 DEBUGFUNC("e1000_configure_kmrn_for_1000"); 1351 1352 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT; 1353 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, 1354 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, 1355 reg_data); 1356 if (ret_val) 1357 goto out; 1358 1359 /* Configure Transmit Inter-Packet Gap */ 1360 tipg = E1000_READ_REG(hw, E1000_TIPG); 1361 tipg &= ~E1000_TIPG_IPGT_MASK; 1362 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; 1363 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 1364 1365 1366 do { 1367 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1368 ®_data); 1369 if (ret_val) 1370 goto out; 1371 1372 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1373 ®_data2); 1374 if (ret_val) 1375 goto out; 1376 i++; 1377 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); 1378 1379 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1380 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 1381 1382 out: 1383 return ret_val; 1384 } 1385 1386 /** 1387 * e1000_read_kmrn_reg_80003es2lan - Read kumeran register 1388 * @hw: pointer to the HW structure 1389 * @offset: register offset to be read 1390 * @data: pointer to the read data 1391 * 1392 * Acquire semaphore, then read the PHY register at offset 1393 * using the kumeran interface. The information retrieved is stored in data. 1394 * Release the semaphore before exiting. 1395 **/ 1396 s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, u16 *data) 1397 { 1398 u32 kmrnctrlsta; 1399 s32 ret_val = E1000_SUCCESS; 1400 1401 DEBUGFUNC("e1000_read_kmrn_reg_80003es2lan"); 1402 1403 ret_val = e1000_acquire_mac_csr_80003es2lan(hw); 1404 if (ret_val) 1405 goto out; 1406 1407 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 1408 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 1409 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 1410 1411 usec_delay(2); 1412 1413 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA); 1414 *data = (u16)kmrnctrlsta; 1415 1416 e1000_release_mac_csr_80003es2lan(hw); 1417 1418 out: 1419 return ret_val; 1420 } 1421 1422 /** 1423 * e1000_write_kmrn_reg_80003es2lan - Write kumeran register 1424 * @hw: pointer to the HW structure 1425 * @offset: register offset to write to 1426 * @data: data to write at register offset 1427 * 1428 * Acquire semaphore, then write the data to PHY register 1429 * at the offset using the kumeran interface. Release semaphore 1430 * before exiting. 1431 **/ 1432 s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, u16 data) 1433 { 1434 u32 kmrnctrlsta; 1435 s32 ret_val = E1000_SUCCESS; 1436 1437 DEBUGFUNC("e1000_write_kmrn_reg_80003es2lan"); 1438 1439 ret_val = e1000_acquire_mac_csr_80003es2lan(hw); 1440 if (ret_val) 1441 goto out; 1442 1443 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 1444 E1000_KMRNCTRLSTA_OFFSET) | data; 1445 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 1446 1447 usec_delay(2); 1448 1449 e1000_release_mac_csr_80003es2lan(hw); 1450 1451 out: 1452 return ret_val; 1453 } 1454 1455 /** 1456 * e1000_read_mac_addr_80003es2lan - Read device MAC address 1457 * @hw: pointer to the HW structure 1458 **/ 1459 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw) 1460 { 1461 s32 ret_val = E1000_SUCCESS; 1462 1463 DEBUGFUNC("e1000_read_mac_addr_80003es2lan"); 1464 if (e1000_check_alt_mac_addr_generic(hw)) 1465 ret_val = e1000_read_mac_addr_generic(hw); 1466 1467 return ret_val; 1468 } 1469 1470 /** 1471 * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down 1472 * @hw: pointer to the HW structure 1473 * 1474 * In the case of a PHY power down to save power, or to turn off link during a 1475 * driver unload, or wake on lan is not enabled, remove the link. 1476 **/ 1477 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw) 1478 { 1479 /* If the management interface is not enabled, then power down */ 1480 if (!(hw->mac.ops.check_mng_mode(hw) || 1481 hw->phy.ops.check_reset_block(hw))) 1482 e1000_power_down_phy_copper(hw); 1483 1484 return; 1485 } 1486 1487 /** 1488 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters 1489 * @hw: pointer to the HW structure 1490 * 1491 * Clears the hardware counters by reading the counter registers. 1492 **/ 1493 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw) 1494 { 1495 DEBUGFUNC("e1000_clear_hw_cntrs_80003es2lan"); 1496 1497 e1000_clear_hw_cntrs_base_generic(hw); 1498 1499 E1000_READ_REG(hw, E1000_PRC64); 1500 E1000_READ_REG(hw, E1000_PRC127); 1501 E1000_READ_REG(hw, E1000_PRC255); 1502 E1000_READ_REG(hw, E1000_PRC511); 1503 E1000_READ_REG(hw, E1000_PRC1023); 1504 E1000_READ_REG(hw, E1000_PRC1522); 1505 E1000_READ_REG(hw, E1000_PTC64); 1506 E1000_READ_REG(hw, E1000_PTC127); 1507 E1000_READ_REG(hw, E1000_PTC255); 1508 E1000_READ_REG(hw, E1000_PTC511); 1509 E1000_READ_REG(hw, E1000_PTC1023); 1510 E1000_READ_REG(hw, E1000_PTC1522); 1511 1512 E1000_READ_REG(hw, E1000_ALGNERRC); 1513 E1000_READ_REG(hw, E1000_RXERRC); 1514 E1000_READ_REG(hw, E1000_TNCRS); 1515 E1000_READ_REG(hw, E1000_CEXTERR); 1516 E1000_READ_REG(hw, E1000_TSCTC); 1517 E1000_READ_REG(hw, E1000_TSCTFC); 1518 1519 E1000_READ_REG(hw, E1000_MGTPRC); 1520 E1000_READ_REG(hw, E1000_MGTPDC); 1521 E1000_READ_REG(hw, E1000_MGTPTC); 1522 1523 E1000_READ_REG(hw, E1000_IAC); 1524 E1000_READ_REG(hw, E1000_ICRXOC); 1525 1526 E1000_READ_REG(hw, E1000_ICRXPTC); 1527 E1000_READ_REG(hw, E1000_ICRXATC); 1528 E1000_READ_REG(hw, E1000_ICTXPTC); 1529 E1000_READ_REG(hw, E1000_ICTXATC); 1530 E1000_READ_REG(hw, E1000_ICTXQEC); 1531 E1000_READ_REG(hw, E1000_ICTXQMTC); 1532 E1000_READ_REG(hw, E1000_ICRXDMTC); 1533 } 1534