1 /****************************************************************************** 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 /* 36 * 82540EM Gigabit Ethernet Controller 37 * 82540EP Gigabit Ethernet Controller 38 * 82545EM Gigabit Ethernet Controller (Copper) 39 * 82545EM Gigabit Ethernet Controller (Fiber) 40 * 82545GM Gigabit Ethernet Controller 41 * 82546EB Gigabit Ethernet Controller (Copper) 42 * 82546EB Gigabit Ethernet Controller (Fiber) 43 * 82546GB Gigabit Ethernet Controller 44 */ 45 46 #include "e1000_api.h" 47 48 static s32 e1000_init_phy_params_82540(struct e1000_hw *hw); 49 static s32 e1000_init_nvm_params_82540(struct e1000_hw *hw); 50 static s32 e1000_init_mac_params_82540(struct e1000_hw *hw); 51 static s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw); 52 static void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw); 53 static s32 e1000_init_hw_82540(struct e1000_hw *hw); 54 static s32 e1000_reset_hw_82540(struct e1000_hw *hw); 55 static s32 e1000_set_phy_mode_82540(struct e1000_hw *hw); 56 static s32 e1000_set_vco_speed_82540(struct e1000_hw *hw); 57 static s32 e1000_setup_copper_link_82540(struct e1000_hw *hw); 58 static s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw); 59 static void e1000_power_down_phy_copper_82540(struct e1000_hw *hw); 60 61 /** 62 * e1000_init_phy_params_82540 - Init PHY func ptrs. 63 * @hw: pointer to the HW structure 64 **/ 65 static s32 e1000_init_phy_params_82540(struct e1000_hw *hw) 66 { 67 struct e1000_phy_info *phy = &hw->phy; 68 s32 ret_val = E1000_SUCCESS; 69 70 phy->addr = 1; 71 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 72 phy->reset_delay_us = 10000; 73 phy->type = e1000_phy_m88; 74 75 /* Function Pointers */ 76 phy->ops.check_polarity = e1000_check_polarity_m88; 77 phy->ops.commit = e1000_phy_sw_reset_generic; 78 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 79 phy->ops.get_cable_length = e1000_get_cable_length_m88; 80 phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 81 phy->ops.read_reg = e1000_read_phy_reg_m88; 82 phy->ops.reset = e1000_phy_hw_reset_generic; 83 phy->ops.write_reg = e1000_write_phy_reg_m88; 84 phy->ops.get_info = e1000_get_phy_info_m88; 85 phy->ops.power_up = e1000_power_up_phy_copper; 86 phy->ops.power_down = e1000_power_down_phy_copper_82540; 87 88 ret_val = e1000_get_phy_id(hw); 89 if (ret_val) 90 goto out; 91 92 /* Verify phy id */ 93 switch (hw->mac.type) { 94 case e1000_82540: 95 case e1000_82545: 96 case e1000_82545_rev_3: 97 case e1000_82546: 98 case e1000_82546_rev_3: 99 if (phy->id == M88E1011_I_PHY_ID) 100 break; 101 /* Fall Through */ 102 default: 103 ret_val = -E1000_ERR_PHY; 104 goto out; 105 break; 106 } 107 108 out: 109 return ret_val; 110 } 111 112 /** 113 * e1000_init_nvm_params_82540 - Init NVM func ptrs. 114 * @hw: pointer to the HW structure 115 **/ 116 static s32 e1000_init_nvm_params_82540(struct e1000_hw *hw) 117 { 118 struct e1000_nvm_info *nvm = &hw->nvm; 119 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 120 121 DEBUGFUNC("e1000_init_nvm_params_82540"); 122 123 nvm->type = e1000_nvm_eeprom_microwire; 124 nvm->delay_usec = 50; 125 nvm->opcode_bits = 3; 126 switch (nvm->override) { 127 case e1000_nvm_override_microwire_large: 128 nvm->address_bits = 8; 129 nvm->word_size = 256; 130 break; 131 case e1000_nvm_override_microwire_small: 132 nvm->address_bits = 6; 133 nvm->word_size = 64; 134 break; 135 default: 136 nvm->address_bits = eecd & E1000_EECD_SIZE ? 8 : 6; 137 nvm->word_size = eecd & E1000_EECD_SIZE ? 256 : 64; 138 break; 139 } 140 141 /* Function Pointers */ 142 nvm->ops.acquire = e1000_acquire_nvm_generic; 143 nvm->ops.read = e1000_read_nvm_microwire; 144 nvm->ops.release = e1000_release_nvm_generic; 145 nvm->ops.update = e1000_update_nvm_checksum_generic; 146 nvm->ops.valid_led_default = e1000_valid_led_default_generic; 147 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 148 nvm->ops.write = e1000_write_nvm_microwire; 149 150 return E1000_SUCCESS; 151 } 152 153 /** 154 * e1000_init_mac_params_82540 - Init MAC func ptrs. 155 * @hw: pointer to the HW structure 156 **/ 157 static s32 e1000_init_mac_params_82540(struct e1000_hw *hw) 158 { 159 struct e1000_mac_info *mac = &hw->mac; 160 s32 ret_val = E1000_SUCCESS; 161 162 DEBUGFUNC("e1000_init_mac_params_82540"); 163 164 /* Set media type */ 165 switch (hw->device_id) { 166 case E1000_DEV_ID_82545EM_FIBER: 167 case E1000_DEV_ID_82545GM_FIBER: 168 case E1000_DEV_ID_82546EB_FIBER: 169 case E1000_DEV_ID_82546GB_FIBER: 170 hw->phy.media_type = e1000_media_type_fiber; 171 break; 172 case E1000_DEV_ID_82545GM_SERDES: 173 case E1000_DEV_ID_82546GB_SERDES: 174 hw->phy.media_type = e1000_media_type_internal_serdes; 175 break; 176 default: 177 hw->phy.media_type = e1000_media_type_copper; 178 break; 179 } 180 181 /* Set mta register count */ 182 mac->mta_reg_count = 128; 183 /* Set rar entry count */ 184 mac->rar_entry_count = E1000_RAR_ENTRIES; 185 186 /* Function pointers */ 187 188 /* bus type/speed/width */ 189 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic; 190 /* function id */ 191 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci; 192 /* reset */ 193 mac->ops.reset_hw = e1000_reset_hw_82540; 194 /* hw initialization */ 195 mac->ops.init_hw = e1000_init_hw_82540; 196 /* link setup */ 197 mac->ops.setup_link = e1000_setup_link_generic; 198 /* physical interface setup */ 199 mac->ops.setup_physical_interface = 200 (hw->phy.media_type == e1000_media_type_copper) 201 ? e1000_setup_copper_link_82540 202 : e1000_setup_fiber_serdes_link_82540; 203 /* check for link */ 204 switch (hw->phy.media_type) { 205 case e1000_media_type_copper: 206 mac->ops.check_for_link = e1000_check_for_copper_link_generic; 207 break; 208 case e1000_media_type_fiber: 209 mac->ops.check_for_link = e1000_check_for_fiber_link_generic; 210 break; 211 case e1000_media_type_internal_serdes: 212 mac->ops.check_for_link = e1000_check_for_serdes_link_generic; 213 break; 214 default: 215 ret_val = -E1000_ERR_CONFIG; 216 goto out; 217 break; 218 } 219 /* link info */ 220 mac->ops.get_link_up_info = 221 (hw->phy.media_type == e1000_media_type_copper) 222 ? e1000_get_speed_and_duplex_copper_generic 223 : e1000_get_speed_and_duplex_fiber_serdes_generic; 224 /* multicast address update */ 225 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 226 /* writing VFTA */ 227 mac->ops.write_vfta = e1000_write_vfta_generic; 228 /* clearing VFTA */ 229 mac->ops.clear_vfta = e1000_clear_vfta_generic; 230 /* setting MTA */ 231 mac->ops.mta_set = e1000_mta_set_generic; 232 /* setup LED */ 233 mac->ops.setup_led = e1000_setup_led_generic; 234 /* cleanup LED */ 235 mac->ops.cleanup_led = e1000_cleanup_led_generic; 236 /* turn on/off LED */ 237 mac->ops.led_on = e1000_led_on_generic; 238 mac->ops.led_off = e1000_led_off_generic; 239 /* clear hardware counters */ 240 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82540; 241 242 out: 243 return ret_val; 244 } 245 246 /** 247 * e1000_init_function_pointers_82540 - Init func ptrs. 248 * @hw: pointer to the HW structure 249 * 250 * Called to initialize all function pointers and parameters. 251 **/ 252 void e1000_init_function_pointers_82540(struct e1000_hw *hw) 253 { 254 DEBUGFUNC("e1000_init_function_pointers_82540"); 255 256 hw->mac.ops.init_params = e1000_init_mac_params_82540; 257 hw->nvm.ops.init_params = e1000_init_nvm_params_82540; 258 hw->phy.ops.init_params = e1000_init_phy_params_82540; 259 } 260 261 /** 262 * e1000_reset_hw_82540 - Reset hardware 263 * @hw: pointer to the HW structure 264 * 265 * This resets the hardware into a known state. 266 **/ 267 static s32 e1000_reset_hw_82540(struct e1000_hw *hw) 268 { 269 u32 ctrl, icr, manc; 270 s32 ret_val = E1000_SUCCESS; 271 272 DEBUGFUNC("e1000_reset_hw_82540"); 273 274 DEBUGOUT("Masking off all interrupts\n"); 275 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 276 277 E1000_WRITE_REG(hw, E1000_RCTL, 0); 278 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 279 E1000_WRITE_FLUSH(hw); 280 281 /* 282 * Delay to allow any outstanding PCI transactions to complete 283 * before resetting the device. 284 */ 285 msec_delay(10); 286 287 ctrl = E1000_READ_REG(hw, E1000_CTRL); 288 289 DEBUGOUT("Issuing a global reset to 82540/82545/82546 MAC\n"); 290 switch (hw->mac.type) { 291 case e1000_82545_rev_3: 292 case e1000_82546_rev_3: 293 E1000_WRITE_REG(hw, E1000_CTRL_DUP, ctrl | E1000_CTRL_RST); 294 break; 295 default: 296 /* 297 * These controllers can't ack the 64-bit write when 298 * issuing the reset, so we use IO-mapping as a 299 * workaround to issue the reset. 300 */ 301 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 302 break; 303 } 304 305 /* Wait for EEPROM reload */ 306 msec_delay(5); 307 308 /* Disable HW ARPs on ASF enabled adapters */ 309 manc = E1000_READ_REG(hw, E1000_MANC); 310 manc &= ~E1000_MANC_ARP_EN; 311 E1000_WRITE_REG(hw, E1000_MANC, manc); 312 313 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 314 icr = E1000_READ_REG(hw, E1000_ICR); 315 316 return ret_val; 317 } 318 319 /** 320 * e1000_init_hw_82540 - Initialize hardware 321 * @hw: pointer to the HW structure 322 * 323 * This inits the hardware readying it for operation. 324 **/ 325 static s32 e1000_init_hw_82540(struct e1000_hw *hw) 326 { 327 struct e1000_mac_info *mac = &hw->mac; 328 u32 txdctl, ctrl_ext; 329 s32 ret_val = E1000_SUCCESS; 330 u16 i; 331 332 DEBUGFUNC("e1000_init_hw_82540"); 333 334 /* Initialize identification LED */ 335 ret_val = e1000_id_led_init_generic(hw); 336 if (ret_val) { 337 DEBUGOUT("Error initializing identification LED\n"); 338 /* This is not fatal and we should not stop init due to this */ 339 } 340 341 /* Disabling VLAN filtering */ 342 DEBUGOUT("Initializing the IEEE VLAN\n"); 343 if (mac->type < e1000_82545_rev_3) 344 E1000_WRITE_REG(hw, E1000_VET, 0); 345 346 mac->ops.clear_vfta(hw); 347 348 /* Setup the receive address. */ 349 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 350 351 /* Zero out the Multicast HASH table */ 352 DEBUGOUT("Zeroing the MTA\n"); 353 for (i = 0; i < mac->mta_reg_count; i++) { 354 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 355 /* 356 * Avoid back to back register writes by adding the register 357 * read (flush). This is to protect against some strange 358 * bridge configurations that may issue Memory Write Block 359 * (MWB) to our register space. The *_rev_3 hardware at 360 * least doesn't respond correctly to every other dword in an 361 * MWB to our register space. 362 */ 363 E1000_WRITE_FLUSH(hw); 364 } 365 366 if (mac->type < e1000_82545_rev_3) 367 e1000_pcix_mmrbc_workaround_generic(hw); 368 369 /* Setup link and flow control */ 370 ret_val = mac->ops.setup_link(hw); 371 372 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); 373 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 374 E1000_TXDCTL_FULL_TX_DESC_WB; 375 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); 376 377 /* 378 * Clear all of the statistics registers (clear on read). It is 379 * important that we do this after we have tried to establish link 380 * because the symbol error count will increment wildly if there 381 * is no link. 382 */ 383 e1000_clear_hw_cntrs_82540(hw); 384 385 if ((hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER) || 386 (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3)) { 387 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 388 /* 389 * Relaxed ordering must be disabled to avoid a parity 390 * error crash in a PCI slot. 391 */ 392 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 393 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 394 } 395 396 return ret_val; 397 } 398 399 /** 400 * e1000_setup_copper_link_82540 - Configure copper link settings 401 * @hw: pointer to the HW structure 402 * 403 * Calls the appropriate function to configure the link for auto-neg or forced 404 * speed and duplex. Then we check for link, once link is established calls 405 * to configure collision distance and flow control are called. If link is 406 * not established, we return -E1000_ERR_PHY (-2). 407 **/ 408 static s32 e1000_setup_copper_link_82540(struct e1000_hw *hw) 409 { 410 u32 ctrl; 411 s32 ret_val = E1000_SUCCESS; 412 u16 data; 413 414 DEBUGFUNC("e1000_setup_copper_link_82540"); 415 416 ctrl = E1000_READ_REG(hw, E1000_CTRL); 417 ctrl |= E1000_CTRL_SLU; 418 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 419 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 420 421 ret_val = e1000_set_phy_mode_82540(hw); 422 if (ret_val) 423 goto out; 424 425 if (hw->mac.type == e1000_82545_rev_3 || 426 hw->mac.type == e1000_82546_rev_3) { 427 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &data); 428 if (ret_val) 429 goto out; 430 data |= 0x00000008; 431 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, data); 432 if (ret_val) 433 goto out; 434 } 435 436 ret_val = e1000_copper_link_setup_m88(hw); 437 if (ret_val) 438 goto out; 439 440 ret_val = e1000_setup_copper_link_generic(hw); 441 442 out: 443 return ret_val; 444 } 445 446 /** 447 * e1000_setup_fiber_serdes_link_82540 - Setup link for fiber/serdes 448 * @hw: pointer to the HW structure 449 * 450 * Set the output amplitude to the value in the EEPROM and adjust the VCO 451 * speed to improve Bit Error Rate (BER) performance. Configures collision 452 * distance and flow control for fiber and serdes links. Upon successful 453 * setup, poll for link. 454 **/ 455 static s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw) 456 { 457 struct e1000_mac_info *mac = &hw->mac; 458 s32 ret_val = E1000_SUCCESS; 459 460 DEBUGFUNC("e1000_setup_fiber_serdes_link_82540"); 461 462 switch (mac->type) { 463 case e1000_82545_rev_3: 464 case e1000_82546_rev_3: 465 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 466 /* 467 * If we're on serdes media, adjust the output 468 * amplitude to value set in the EEPROM. 469 */ 470 ret_val = e1000_adjust_serdes_amplitude_82540(hw); 471 if (ret_val) 472 goto out; 473 } 474 /* Adjust VCO speed to improve BER performance */ 475 ret_val = e1000_set_vco_speed_82540(hw); 476 if (ret_val) 477 goto out; 478 default: 479 break; 480 } 481 482 ret_val = e1000_setup_fiber_serdes_link_generic(hw); 483 484 out: 485 return ret_val; 486 } 487 488 /** 489 * e1000_adjust_serdes_amplitude_82540 - Adjust amplitude based on EEPROM 490 * @hw: pointer to the HW structure 491 * 492 * Adjust the SERDES output amplitude based on the EEPROM settings. 493 **/ 494 static s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw) 495 { 496 s32 ret_val = E1000_SUCCESS; 497 u16 nvm_data; 498 499 DEBUGFUNC("e1000_adjust_serdes_amplitude_82540"); 500 501 ret_val = hw->nvm.ops.read(hw, NVM_SERDES_AMPLITUDE, 1, &nvm_data); 502 if (ret_val) 503 goto out; 504 505 if (nvm_data != NVM_RESERVED_WORD) { 506 /* Adjust serdes output amplitude only. */ 507 nvm_data &= NVM_SERDES_AMPLITUDE_MASK; 508 ret_val = hw->phy.ops.write_reg(hw, 509 M88E1000_PHY_EXT_CTRL, 510 nvm_data); 511 if (ret_val) 512 goto out; 513 } 514 515 out: 516 return ret_val; 517 } 518 519 /** 520 * e1000_set_vco_speed_82540 - Set VCO speed for better performance 521 * @hw: pointer to the HW structure 522 * 523 * Set the VCO speed to improve Bit Error Rate (BER) performance. 524 **/ 525 static s32 e1000_set_vco_speed_82540(struct e1000_hw *hw) 526 { 527 s32 ret_val = E1000_SUCCESS; 528 u16 default_page = 0; 529 u16 phy_data; 530 531 DEBUGFUNC("e1000_set_vco_speed_82540"); 532 533 /* Set PHY register 30, page 5, bit 8 to 0 */ 534 535 ret_val = hw->phy.ops.read_reg(hw, 536 M88E1000_PHY_PAGE_SELECT, 537 &default_page); 538 if (ret_val) 539 goto out; 540 541 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); 542 if (ret_val) 543 goto out; 544 545 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 546 if (ret_val) 547 goto out; 548 549 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; 550 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 551 if (ret_val) 552 goto out; 553 554 /* Set PHY register 30, page 4, bit 11 to 1 */ 555 556 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); 557 if (ret_val) 558 goto out; 559 560 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 561 if (ret_val) 562 goto out; 563 564 phy_data |= M88E1000_PHY_VCO_REG_BIT11; 565 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 566 if (ret_val) 567 goto out; 568 569 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 570 default_page); 571 572 out: 573 return ret_val; 574 } 575 576 /** 577 * e1000_set_phy_mode_82540 - Set PHY to class A mode 578 * @hw: pointer to the HW structure 579 * 580 * Sets the PHY to class A mode and assumes the following operations will 581 * follow to enable the new class mode: 582 * 1. Do a PHY soft reset. 583 * 2. Restart auto-negotiation or force link. 584 **/ 585 static s32 e1000_set_phy_mode_82540(struct e1000_hw *hw) 586 { 587 struct e1000_phy_info *phy = &hw->phy; 588 s32 ret_val = E1000_SUCCESS; 589 u16 nvm_data; 590 591 DEBUGFUNC("e1000_set_phy_mode_82540"); 592 593 if (hw->mac.type != e1000_82545_rev_3) 594 goto out; 595 596 ret_val = hw->nvm.ops.read(hw, NVM_PHY_CLASS_WORD, 1, &nvm_data); 597 if (ret_val) { 598 ret_val = -E1000_ERR_PHY; 599 goto out; 600 } 601 602 if ((nvm_data != NVM_RESERVED_WORD) && (nvm_data & NVM_PHY_CLASS_A)) { 603 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 604 0x000B); 605 if (ret_val) { 606 ret_val = -E1000_ERR_PHY; 607 goto out; 608 } 609 ret_val = hw->phy.ops.write_reg(hw, 610 M88E1000_PHY_GEN_CONTROL, 611 0x8104); 612 if (ret_val) { 613 ret_val = -E1000_ERR_PHY; 614 goto out; 615 } 616 617 phy->reset_disable = FALSE; 618 } 619 620 out: 621 return ret_val; 622 } 623 624 /** 625 * e1000_power_down_phy_copper_82540 - Remove link in case of PHY power down 626 * @hw: pointer to the HW structure 627 * 628 * In the case of a PHY power down to save power, or to turn off link during a 629 * driver unload, or wake on lan is not enabled, remove the link. 630 **/ 631 static void e1000_power_down_phy_copper_82540(struct e1000_hw *hw) 632 { 633 /* If the management interface is not enabled, then power down */ 634 if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN)) 635 e1000_power_down_phy_copper(hw); 636 637 return; 638 } 639 640 /** 641 * e1000_clear_hw_cntrs_82540 - Clear device specific hardware counters 642 * @hw: pointer to the HW structure 643 * 644 * Clears the hardware counters by reading the counter registers. 645 **/ 646 static void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw) 647 { 648 DEBUGFUNC("e1000_clear_hw_cntrs_82540"); 649 650 e1000_clear_hw_cntrs_base_generic(hw); 651 652 E1000_READ_REG(hw, E1000_PRC64); 653 E1000_READ_REG(hw, E1000_PRC127); 654 E1000_READ_REG(hw, E1000_PRC255); 655 E1000_READ_REG(hw, E1000_PRC511); 656 E1000_READ_REG(hw, E1000_PRC1023); 657 E1000_READ_REG(hw, E1000_PRC1522); 658 E1000_READ_REG(hw, E1000_PTC64); 659 E1000_READ_REG(hw, E1000_PTC127); 660 E1000_READ_REG(hw, E1000_PTC255); 661 E1000_READ_REG(hw, E1000_PTC511); 662 E1000_READ_REG(hw, E1000_PTC1023); 663 E1000_READ_REG(hw, E1000_PTC1522); 664 665 E1000_READ_REG(hw, E1000_ALGNERRC); 666 E1000_READ_REG(hw, E1000_RXERRC); 667 E1000_READ_REG(hw, E1000_TNCRS); 668 E1000_READ_REG(hw, E1000_CEXTERR); 669 E1000_READ_REG(hw, E1000_TSCTC); 670 E1000_READ_REG(hw, E1000_TSCTFC); 671 672 E1000_READ_REG(hw, E1000_MGTPRC); 673 E1000_READ_REG(hw, E1000_MGTPDC); 674 E1000_READ_REG(hw, E1000_MGTPTC); 675 } 676 677