1 /****************************************************************************** 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 /* 36 * 82543GC Gigabit Ethernet Controller (Fiber) 37 * 82543GC Gigabit Ethernet Controller (Copper) 38 * 82544EI Gigabit Ethernet Controller (Copper) 39 * 82544EI Gigabit Ethernet Controller (Fiber) 40 * 82544GC Gigabit Ethernet Controller (Copper) 41 * 82544GC Gigabit Ethernet Controller (LOM) 42 */ 43 44 #include "e1000_api.h" 45 46 static s32 e1000_init_phy_params_82543(struct e1000_hw *hw); 47 static s32 e1000_init_nvm_params_82543(struct e1000_hw *hw); 48 static s32 e1000_init_mac_params_82543(struct e1000_hw *hw); 49 static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, 50 u16 *data); 51 static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, 52 u16 data); 53 static s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw); 54 static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw); 55 static s32 e1000_reset_hw_82543(struct e1000_hw *hw); 56 static s32 e1000_init_hw_82543(struct e1000_hw *hw); 57 static s32 e1000_setup_link_82543(struct e1000_hw *hw); 58 static s32 e1000_setup_copper_link_82543(struct e1000_hw *hw); 59 static s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw); 60 static s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw); 61 static s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw); 62 static s32 e1000_led_on_82543(struct e1000_hw *hw); 63 static s32 e1000_led_off_82543(struct e1000_hw *hw); 64 static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, 65 u32 value); 66 static void e1000_mta_set_82543(struct e1000_hw *hw, u32 hash_value); 67 static void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw); 68 static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw); 69 static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw); 70 static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl); 71 static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw); 72 static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl); 73 static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw); 74 static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data, 75 u16 count); 76 static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw); 77 static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state); 78 79 /** 80 * e1000_init_phy_params_82543 - Init PHY func ptrs. 81 * @hw: pointer to the HW structure 82 **/ 83 static s32 e1000_init_phy_params_82543(struct e1000_hw *hw) 84 { 85 struct e1000_phy_info *phy = &hw->phy; 86 s32 ret_val = E1000_SUCCESS; 87 88 DEBUGFUNC("e1000_init_phy_params_82543"); 89 90 if (hw->phy.media_type != e1000_media_type_copper) { 91 phy->type = e1000_phy_none; 92 goto out; 93 } else { 94 phy->ops.power_up = e1000_power_up_phy_copper; 95 phy->ops.power_down = e1000_power_down_phy_copper; 96 } 97 98 phy->addr = 1; 99 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 100 phy->reset_delay_us = 10000; 101 phy->type = e1000_phy_m88; 102 103 /* Function Pointers */ 104 phy->ops.check_polarity = e1000_check_polarity_m88; 105 phy->ops.commit = e1000_phy_sw_reset_generic; 106 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82543; 107 phy->ops.get_cable_length = e1000_get_cable_length_m88; 108 phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 109 phy->ops.read_reg = (hw->mac.type == e1000_82543) 110 ? e1000_read_phy_reg_82543 111 : e1000_read_phy_reg_m88; 112 phy->ops.reset = (hw->mac.type == e1000_82543) 113 ? e1000_phy_hw_reset_82543 114 : e1000_phy_hw_reset_generic; 115 phy->ops.write_reg = (hw->mac.type == e1000_82543) 116 ? e1000_write_phy_reg_82543 117 : e1000_write_phy_reg_m88; 118 phy->ops.get_info = e1000_get_phy_info_m88; 119 120 /* 121 * The external PHY of the 82543 can be in a funky state. 122 * Resetting helps us read the PHY registers for acquiring 123 * the PHY ID. 124 */ 125 if (!e1000_init_phy_disabled_82543(hw)) { 126 ret_val = phy->ops.reset(hw); 127 if (ret_val) { 128 DEBUGOUT("Resetting PHY during init failed.\n"); 129 goto out; 130 } 131 msec_delay(20); 132 } 133 134 ret_val = e1000_get_phy_id(hw); 135 if (ret_val) 136 goto out; 137 138 /* Verify phy id */ 139 switch (hw->mac.type) { 140 case e1000_82543: 141 if (phy->id != M88E1000_E_PHY_ID) { 142 ret_val = -E1000_ERR_PHY; 143 goto out; 144 } 145 break; 146 case e1000_82544: 147 if (phy->id != M88E1000_I_PHY_ID) { 148 ret_val = -E1000_ERR_PHY; 149 goto out; 150 } 151 break; 152 default: 153 ret_val = -E1000_ERR_PHY; 154 goto out; 155 break; 156 } 157 158 out: 159 return ret_val; 160 } 161 162 /** 163 * e1000_init_nvm_params_82543 - Init NVM func ptrs. 164 * @hw: pointer to the HW structure 165 **/ 166 static s32 e1000_init_nvm_params_82543(struct e1000_hw *hw) 167 { 168 struct e1000_nvm_info *nvm = &hw->nvm; 169 170 DEBUGFUNC("e1000_init_nvm_params_82543"); 171 172 nvm->type = e1000_nvm_eeprom_microwire; 173 nvm->word_size = 64; 174 nvm->delay_usec = 50; 175 nvm->address_bits = 6; 176 nvm->opcode_bits = 3; 177 178 /* Function Pointers */ 179 nvm->ops.read = e1000_read_nvm_microwire; 180 nvm->ops.update = e1000_update_nvm_checksum_generic; 181 nvm->ops.valid_led_default = e1000_valid_led_default_generic; 182 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 183 nvm->ops.write = e1000_write_nvm_microwire; 184 185 return E1000_SUCCESS; 186 } 187 188 /** 189 * e1000_init_mac_params_82543 - Init MAC func ptrs. 190 * @hw: pointer to the HW structure 191 **/ 192 static s32 e1000_init_mac_params_82543(struct e1000_hw *hw) 193 { 194 struct e1000_mac_info *mac = &hw->mac; 195 196 DEBUGFUNC("e1000_init_mac_params_82543"); 197 198 /* Set media type */ 199 switch (hw->device_id) { 200 case E1000_DEV_ID_82543GC_FIBER: 201 case E1000_DEV_ID_82544EI_FIBER: 202 hw->phy.media_type = e1000_media_type_fiber; 203 break; 204 default: 205 hw->phy.media_type = e1000_media_type_copper; 206 break; 207 } 208 209 /* Set mta register count */ 210 mac->mta_reg_count = 128; 211 /* Set rar entry count */ 212 mac->rar_entry_count = E1000_RAR_ENTRIES; 213 214 /* Function pointers */ 215 216 /* bus type/speed/width */ 217 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic; 218 /* function id */ 219 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci; 220 /* reset */ 221 mac->ops.reset_hw = e1000_reset_hw_82543; 222 /* hw initialization */ 223 mac->ops.init_hw = e1000_init_hw_82543; 224 /* link setup */ 225 mac->ops.setup_link = e1000_setup_link_82543; 226 /* physical interface setup */ 227 mac->ops.setup_physical_interface = 228 (hw->phy.media_type == e1000_media_type_copper) 229 ? e1000_setup_copper_link_82543 230 : e1000_setup_fiber_link_82543; 231 /* check for link */ 232 mac->ops.check_for_link = 233 (hw->phy.media_type == e1000_media_type_copper) 234 ? e1000_check_for_copper_link_82543 235 : e1000_check_for_fiber_link_82543; 236 /* link info */ 237 mac->ops.get_link_up_info = 238 (hw->phy.media_type == e1000_media_type_copper) 239 ? e1000_get_speed_and_duplex_copper_generic 240 : e1000_get_speed_and_duplex_fiber_serdes_generic; 241 /* multicast address update */ 242 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 243 /* writing VFTA */ 244 mac->ops.write_vfta = e1000_write_vfta_82543; 245 /* clearing VFTA */ 246 mac->ops.clear_vfta = e1000_clear_vfta_generic; 247 /* setting MTA */ 248 mac->ops.mta_set = e1000_mta_set_82543; 249 /* turn on/off LED */ 250 mac->ops.led_on = e1000_led_on_82543; 251 mac->ops.led_off = e1000_led_off_82543; 252 /* clear hardware counters */ 253 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82543; 254 255 /* Set tbi compatibility */ 256 if ((hw->mac.type != e1000_82543) || 257 (hw->phy.media_type == e1000_media_type_fiber)) 258 e1000_set_tbi_compatibility_82543(hw, FALSE); 259 260 return E1000_SUCCESS; 261 } 262 263 /** 264 * e1000_init_function_pointers_82543 - Init func ptrs. 265 * @hw: pointer to the HW structure 266 * 267 * Called to initialize all function pointers and parameters. 268 **/ 269 void e1000_init_function_pointers_82543(struct e1000_hw *hw) 270 { 271 DEBUGFUNC("e1000_init_function_pointers_82543"); 272 273 hw->mac.ops.init_params = e1000_init_mac_params_82543; 274 hw->nvm.ops.init_params = e1000_init_nvm_params_82543; 275 hw->phy.ops.init_params = e1000_init_phy_params_82543; 276 } 277 278 /** 279 * e1000_tbi_compatibility_enabled_82543 - Returns TBI compat status 280 * @hw: pointer to the HW structure 281 * 282 * Returns the current status of 10-bit Interface (TBI) compatibility 283 * (enabled/disabled). 284 **/ 285 static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw) 286 { 287 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 288 bool state = FALSE; 289 290 DEBUGFUNC("e1000_tbi_compatibility_enabled_82543"); 291 292 if (hw->mac.type != e1000_82543) { 293 DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 294 goto out; 295 } 296 297 state = (dev_spec->tbi_compatibility & TBI_COMPAT_ENABLED) 298 ? TRUE : FALSE; 299 300 out: 301 return state; 302 } 303 304 /** 305 * e1000_set_tbi_compatibility_82543 - Set TBI compatibility 306 * @hw: pointer to the HW structure 307 * @state: enable/disable TBI compatibility 308 * 309 * Enables or disabled 10-bit Interface (TBI) compatibility. 310 **/ 311 void e1000_set_tbi_compatibility_82543(struct e1000_hw *hw, bool state) 312 { 313 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 314 315 DEBUGFUNC("e1000_set_tbi_compatibility_82543"); 316 317 if (hw->mac.type != e1000_82543) { 318 DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 319 goto out; 320 } 321 322 if (state) 323 dev_spec->tbi_compatibility |= TBI_COMPAT_ENABLED; 324 else 325 dev_spec->tbi_compatibility &= ~TBI_COMPAT_ENABLED; 326 327 out: 328 return; 329 } 330 331 /** 332 * e1000_tbi_sbp_enabled_82543 - Returns TBI SBP status 333 * @hw: pointer to the HW structure 334 * 335 * Returns the current status of 10-bit Interface (TBI) store bad packet (SBP) 336 * (enabled/disabled). 337 **/ 338 bool e1000_tbi_sbp_enabled_82543(struct e1000_hw *hw) 339 { 340 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 341 bool state = FALSE; 342 343 DEBUGFUNC("e1000_tbi_sbp_enabled_82543"); 344 345 if (hw->mac.type != e1000_82543) { 346 DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 347 goto out; 348 } 349 350 state = (dev_spec->tbi_compatibility & TBI_SBP_ENABLED) 351 ? TRUE : FALSE; 352 353 out: 354 return state; 355 } 356 357 /** 358 * e1000_set_tbi_sbp_82543 - Set TBI SBP 359 * @hw: pointer to the HW structure 360 * @state: enable/disable TBI store bad packet 361 * 362 * Enables or disabled 10-bit Interface (TBI) store bad packet (SBP). 363 **/ 364 static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state) 365 { 366 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 367 368 DEBUGFUNC("e1000_set_tbi_sbp_82543"); 369 370 if (state && e1000_tbi_compatibility_enabled_82543(hw)) 371 dev_spec->tbi_compatibility |= TBI_SBP_ENABLED; 372 else 373 dev_spec->tbi_compatibility &= ~TBI_SBP_ENABLED; 374 375 return; 376 } 377 378 /** 379 * e1000_init_phy_disabled_82543 - Returns init PHY status 380 * @hw: pointer to the HW structure 381 * 382 * Returns the current status of whether PHY initialization is disabled. 383 * True if PHY initialization is disabled else FALSE. 384 **/ 385 static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw) 386 { 387 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 388 bool ret_val; 389 390 DEBUGFUNC("e1000_init_phy_disabled_82543"); 391 392 if (hw->mac.type != e1000_82543) { 393 ret_val = FALSE; 394 goto out; 395 } 396 397 ret_val = dev_spec->init_phy_disabled; 398 399 out: 400 return ret_val; 401 } 402 403 /** 404 * e1000_tbi_adjust_stats_82543 - Adjust stats when TBI enabled 405 * @hw: pointer to the HW structure 406 * @stats: Struct containing statistic register values 407 * @frame_len: The length of the frame in question 408 * @mac_addr: The Ethernet destination address of the frame in question 409 * @max_frame_size: The maximum frame size 410 * 411 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT 412 **/ 413 void e1000_tbi_adjust_stats_82543(struct e1000_hw *hw, 414 struct e1000_hw_stats *stats, u32 frame_len, 415 u8 *mac_addr, u32 max_frame_size) 416 { 417 if (!(e1000_tbi_sbp_enabled_82543(hw))) 418 goto out; 419 420 /* First adjust the frame length. */ 421 frame_len--; 422 /* 423 * We need to adjust the statistics counters, since the hardware 424 * counters overcount this packet as a CRC error and undercount 425 * the packet as a good packet 426 */ 427 /* This packet should not be counted as a CRC error. */ 428 stats->crcerrs--; 429 /* This packet does count as a Good Packet Received. */ 430 stats->gprc++; 431 432 /* Adjust the Good Octets received counters */ 433 stats->gorc += frame_len; 434 435 /* 436 * Is this a broadcast or multicast? Check broadcast first, 437 * since the test for a multicast frame will test positive on 438 * a broadcast frame. 439 */ 440 if ((mac_addr[0] == 0xff) && (mac_addr[1] == 0xff)) 441 /* Broadcast packet */ 442 stats->bprc++; 443 else if (*mac_addr & 0x01) 444 /* Multicast packet */ 445 stats->mprc++; 446 447 /* 448 * In this case, the hardware has overcounted the number of 449 * oversize frames. 450 */ 451 if ((frame_len == max_frame_size) && (stats->roc > 0)) 452 stats->roc--; 453 454 /* 455 * Adjust the bin counters when the extra byte put the frame in the 456 * wrong bin. Remember that the frame_len was adjusted above. 457 */ 458 if (frame_len == 64) { 459 stats->prc64++; 460 stats->prc127--; 461 } else if (frame_len == 127) { 462 stats->prc127++; 463 stats->prc255--; 464 } else if (frame_len == 255) { 465 stats->prc255++; 466 stats->prc511--; 467 } else if (frame_len == 511) { 468 stats->prc511++; 469 stats->prc1023--; 470 } else if (frame_len == 1023) { 471 stats->prc1023++; 472 stats->prc1522--; 473 } else if (frame_len == 1522) { 474 stats->prc1522++; 475 } 476 477 out: 478 return; 479 } 480 481 /** 482 * e1000_read_phy_reg_82543 - Read PHY register 483 * @hw: pointer to the HW structure 484 * @offset: register offset to be read 485 * @data: pointer to the read data 486 * 487 * Reads the PHY at offset and stores the information read to data. 488 **/ 489 static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 *data) 490 { 491 u32 mdic; 492 s32 ret_val = E1000_SUCCESS; 493 494 DEBUGFUNC("e1000_read_phy_reg_82543"); 495 496 if (offset > MAX_PHY_REG_ADDRESS) { 497 DEBUGOUT1("PHY Address %d is out of range\n", offset); 498 ret_val = -E1000_ERR_PARAM; 499 goto out; 500 } 501 502 /* 503 * We must first send a preamble through the MDIO pin to signal the 504 * beginning of an MII instruction. This is done by sending 32 505 * consecutive "1" bits. 506 */ 507 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 508 509 /* 510 * Now combine the next few fields that are required for a read 511 * operation. We use this method instead of calling the 512 * e1000_shift_out_mdi_bits routine five different times. The format 513 * of an MII read instruction consists of a shift out of 14 bits and 514 * is defined as follows: 515 * <Preamble><SOF><Op Code><Phy Addr><Offset> 516 * followed by a shift in of 18 bits. This first two bits shifted in 517 * are TurnAround bits used to avoid contention on the MDIO pin when a 518 * READ operation is performed. These two bits are thrown away 519 * followed by a shift in of 16 bits which contains the desired data. 520 */ 521 mdic = (offset | (hw->phy.addr << 5) | 522 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 523 524 e1000_shift_out_mdi_bits_82543(hw, mdic, 14); 525 526 /* 527 * Now that we've shifted out the read command to the MII, we need to 528 * "shift in" the 16-bit value (18 total bits) of the requested PHY 529 * register address. 530 */ 531 *data = e1000_shift_in_mdi_bits_82543(hw); 532 533 out: 534 return ret_val; 535 } 536 537 /** 538 * e1000_write_phy_reg_82543 - Write PHY register 539 * @hw: pointer to the HW structure 540 * @offset: register offset to be written 541 * @data: pointer to the data to be written at offset 542 * 543 * Writes data to the PHY at offset. 544 **/ 545 static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 data) 546 { 547 u32 mdic; 548 s32 ret_val = E1000_SUCCESS; 549 550 DEBUGFUNC("e1000_write_phy_reg_82543"); 551 552 if (offset > MAX_PHY_REG_ADDRESS) { 553 DEBUGOUT1("PHY Address %d is out of range\n", offset); 554 ret_val = -E1000_ERR_PARAM; 555 goto out; 556 } 557 558 /* 559 * We'll need to use the SW defined pins to shift the write command 560 * out to the PHY. We first send a preamble to the PHY to signal the 561 * beginning of the MII instruction. This is done by sending 32 562 * consecutive "1" bits. 563 */ 564 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 565 566 /* 567 * Now combine the remaining required fields that will indicate a 568 * write operation. We use this method instead of calling the 569 * e1000_shift_out_mdi_bits routine for each field in the command. The 570 * format of a MII write instruction is as follows: 571 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 572 */ 573 mdic = ((PHY_TURNAROUND) | (offset << 2) | (hw->phy.addr << 7) | 574 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 575 mdic <<= 16; 576 mdic |= (u32) data; 577 578 e1000_shift_out_mdi_bits_82543(hw, mdic, 32); 579 580 out: 581 return ret_val; 582 } 583 584 /** 585 * e1000_raise_mdi_clk_82543 - Raise Management Data Input clock 586 * @hw: pointer to the HW structure 587 * @ctrl: pointer to the control register 588 * 589 * Raise the management data input clock by setting the MDC bit in the control 590 * register. 591 **/ 592 static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl) 593 { 594 /* 595 * Raise the clock input to the Management Data Clock (by setting the 596 * MDC bit), and then delay a sufficient amount of time. 597 */ 598 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl | E1000_CTRL_MDC)); 599 E1000_WRITE_FLUSH(hw); 600 usec_delay(10); 601 } 602 603 /** 604 * e1000_lower_mdi_clk_82543 - Lower Management Data Input clock 605 * @hw: pointer to the HW structure 606 * @ctrl: pointer to the control register 607 * 608 * Lower the management data input clock by clearing the MDC bit in the 609 * control register. 610 **/ 611 static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl) 612 { 613 /* 614 * Lower the clock input to the Management Data Clock (by clearing the 615 * MDC bit), and then delay a sufficient amount of time. 616 */ 617 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl & ~E1000_CTRL_MDC)); 618 E1000_WRITE_FLUSH(hw); 619 usec_delay(10); 620 } 621 622 /** 623 * e1000_shift_out_mdi_bits_82543 - Shift data bits our to the PHY 624 * @hw: pointer to the HW structure 625 * @data: data to send to the PHY 626 * @count: number of bits to shift out 627 * 628 * We need to shift 'count' bits out to the PHY. So, the value in the 629 * "data" parameter will be shifted out to the PHY one bit at a time. 630 * In order to do this, "data" must be broken down into bits. 631 **/ 632 static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data, 633 u16 count) 634 { 635 u32 ctrl, mask; 636 637 /* 638 * We need to shift "count" number of bits out to the PHY. So, the 639 * value in the "data" parameter will be shifted out to the PHY one 640 * bit at a time. In order to do this, "data" must be broken down 641 * into bits. 642 */ 643 mask = 0x01; 644 mask <<= (count -1); 645 646 ctrl = E1000_READ_REG(hw, E1000_CTRL); 647 648 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 649 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 650 651 while (mask) { 652 /* 653 * A "1" is shifted out to the PHY by setting the MDIO bit to 654 * "1" and then raising and lowering the Management Data Clock. 655 * A "0" is shifted out to the PHY by setting the MDIO bit to 656 * "0" and then raising and lowering the clock. 657 */ 658 if (data & mask) ctrl |= E1000_CTRL_MDIO; 659 else ctrl &= ~E1000_CTRL_MDIO; 660 661 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 662 E1000_WRITE_FLUSH(hw); 663 664 usec_delay(10); 665 666 e1000_raise_mdi_clk_82543(hw, &ctrl); 667 e1000_lower_mdi_clk_82543(hw, &ctrl); 668 669 mask >>= 1; 670 } 671 } 672 673 /** 674 * e1000_shift_in_mdi_bits_82543 - Shift data bits in from the PHY 675 * @hw: pointer to the HW structure 676 * 677 * In order to read a register from the PHY, we need to shift 18 bits 678 * in from the PHY. Bits are "shifted in" by raising the clock input to 679 * the PHY (setting the MDC bit), and then reading the value of the data out 680 * MDIO bit. 681 **/ 682 static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw) 683 { 684 u32 ctrl; 685 u16 data = 0; 686 u8 i; 687 688 /* 689 * In order to read a register from the PHY, we need to shift in a 690 * total of 18 bits from the PHY. The first two bit (turnaround) 691 * times are used to avoid contention on the MDIO pin when a read 692 * operation is performed. These two bits are ignored by us and 693 * thrown away. Bits are "shifted in" by raising the input to the 694 * Management Data Clock (setting the MDC bit) and then reading the 695 * value of the MDIO bit. 696 */ 697 ctrl = E1000_READ_REG(hw, E1000_CTRL); 698 699 /* 700 * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as 701 * input. 702 */ 703 ctrl &= ~E1000_CTRL_MDIO_DIR; 704 ctrl &= ~E1000_CTRL_MDIO; 705 706 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 707 E1000_WRITE_FLUSH(hw); 708 709 /* 710 * Raise and lower the clock before reading in the data. This accounts 711 * for the turnaround bits. The first clock occurred when we clocked 712 * out the last bit of the Register Address. 713 */ 714 e1000_raise_mdi_clk_82543(hw, &ctrl); 715 e1000_lower_mdi_clk_82543(hw, &ctrl); 716 717 for (data = 0, i = 0; i < 16; i++) { 718 data <<= 1; 719 e1000_raise_mdi_clk_82543(hw, &ctrl); 720 ctrl = E1000_READ_REG(hw, E1000_CTRL); 721 /* Check to see if we shifted in a "1". */ 722 if (ctrl & E1000_CTRL_MDIO) 723 data |= 1; 724 e1000_lower_mdi_clk_82543(hw, &ctrl); 725 } 726 727 e1000_raise_mdi_clk_82543(hw, &ctrl); 728 e1000_lower_mdi_clk_82543(hw, &ctrl); 729 730 return data; 731 } 732 733 /** 734 * e1000_phy_force_speed_duplex_82543 - Force speed/duplex for PHY 735 * @hw: pointer to the HW structure 736 * 737 * Calls the function to force speed and duplex for the m88 PHY, and 738 * if the PHY is not auto-negotiating and the speed is forced to 10Mbit, 739 * then call the function for polarity reversal workaround. 740 **/ 741 static s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw) 742 { 743 s32 ret_val; 744 745 DEBUGFUNC("e1000_phy_force_speed_duplex_82543"); 746 747 ret_val = e1000_phy_force_speed_duplex_m88(hw); 748 if (ret_val) 749 goto out; 750 751 if (!hw->mac.autoneg && 752 (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)) 753 ret_val = e1000_polarity_reversal_workaround_82543(hw); 754 755 out: 756 return ret_val; 757 } 758 759 /** 760 * e1000_polarity_reversal_workaround_82543 - Workaround polarity reversal 761 * @hw: pointer to the HW structure 762 * 763 * When forcing link to 10 Full or 10 Half, the PHY can reverse the polarity 764 * inadvertently. To workaround the issue, we disable the transmitter on 765 * the PHY until we have established the link partner's link parameters. 766 **/ 767 static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw) 768 { 769 s32 ret_val = E1000_SUCCESS; 770 u16 mii_status_reg; 771 u16 i; 772 bool link; 773 774 if (!(hw->phy.ops.write_reg)) 775 goto out; 776 777 /* Polarity reversal workaround for forced 10F/10H links. */ 778 779 /* Disable the transmitter on the PHY */ 780 781 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 782 if (ret_val) 783 goto out; 784 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 785 if (ret_val) 786 goto out; 787 788 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 789 if (ret_val) 790 goto out; 791 792 /* 793 * This loop will early-out if the NO link condition has been met. 794 * In other words, DO NOT use e1000_phy_has_link_generic() here. 795 */ 796 for (i = PHY_FORCE_TIME; i > 0; i--) { 797 /* 798 * Read the MII Status Register and wait for Link Status bit 799 * to be clear. 800 */ 801 802 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 803 if (ret_val) 804 goto out; 805 806 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 807 if (ret_val) 808 goto out; 809 810 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) 811 break; 812 msec_delay_irq(100); 813 } 814 815 /* Recommended delay time after link has been lost */ 816 msec_delay_irq(1000); 817 818 /* Now we will re-enable the transmitter on the PHY */ 819 820 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 821 if (ret_val) 822 goto out; 823 msec_delay_irq(50); 824 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 825 if (ret_val) 826 goto out; 827 msec_delay_irq(50); 828 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 829 if (ret_val) 830 goto out; 831 msec_delay_irq(50); 832 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 833 if (ret_val) 834 goto out; 835 836 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 837 if (ret_val) 838 goto out; 839 840 /* 841 * Read the MII Status Register and wait for Link Status bit 842 * to be set. 843 */ 844 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_TIME, 100000, &link); 845 if (ret_val) 846 goto out; 847 848 out: 849 return ret_val; 850 } 851 852 /** 853 * e1000_phy_hw_reset_82543 - PHY hardware reset 854 * @hw: pointer to the HW structure 855 * 856 * Sets the PHY_RESET_DIR bit in the extended device control register 857 * to put the PHY into a reset and waits for completion. Once the reset 858 * has been accomplished, clear the PHY_RESET_DIR bit to take the PHY out 859 * of reset. 860 **/ 861 static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw) 862 { 863 u32 ctrl_ext; 864 s32 ret_val; 865 866 DEBUGFUNC("e1000_phy_hw_reset_82543"); 867 868 /* 869 * Read the Extended Device Control Register, assert the PHY_RESET_DIR 870 * bit to put the PHY into reset... 871 */ 872 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 873 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 874 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 875 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 876 E1000_WRITE_FLUSH(hw); 877 878 msec_delay(10); 879 880 /* ...then take it out of reset. */ 881 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 882 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 883 E1000_WRITE_FLUSH(hw); 884 885 usec_delay(150); 886 887 if (!(hw->phy.ops.get_cfg_done)) 888 return E1000_SUCCESS; 889 890 ret_val = hw->phy.ops.get_cfg_done(hw); 891 892 return ret_val; 893 } 894 895 /** 896 * e1000_reset_hw_82543 - Reset hardware 897 * @hw: pointer to the HW structure 898 * 899 * This resets the hardware into a known state. 900 **/ 901 static s32 e1000_reset_hw_82543(struct e1000_hw *hw) 902 { 903 u32 ctrl, icr; 904 s32 ret_val = E1000_SUCCESS; 905 906 DEBUGFUNC("e1000_reset_hw_82543"); 907 908 DEBUGOUT("Masking off all interrupts\n"); 909 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 910 911 E1000_WRITE_REG(hw, E1000_RCTL, 0); 912 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 913 E1000_WRITE_FLUSH(hw); 914 915 e1000_set_tbi_sbp_82543(hw, FALSE); 916 917 /* 918 * Delay to allow any outstanding PCI transactions to complete before 919 * resetting the device 920 */ 921 msec_delay(10); 922 923 ctrl = E1000_READ_REG(hw, E1000_CTRL); 924 925 DEBUGOUT("Issuing a global reset to 82543/82544 MAC\n"); 926 if (hw->mac.type == e1000_82543) { 927 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 928 } else { 929 /* 930 * The 82544 can't ACK the 64-bit write when issuing the 931 * reset, so use IO-mapping as a workaround. 932 */ 933 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 934 } 935 936 /* 937 * After MAC reset, force reload of NVM to restore power-on 938 * settings to device. 939 */ 940 hw->nvm.ops.reload(hw); 941 msec_delay(2); 942 943 /* Masking off and clearing any pending interrupts */ 944 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 945 icr = E1000_READ_REG(hw, E1000_ICR); 946 947 return ret_val; 948 } 949 950 /** 951 * e1000_init_hw_82543 - Initialize hardware 952 * @hw: pointer to the HW structure 953 * 954 * This inits the hardware readying it for operation. 955 **/ 956 static s32 e1000_init_hw_82543(struct e1000_hw *hw) 957 { 958 struct e1000_mac_info *mac = &hw->mac; 959 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 960 u32 ctrl; 961 s32 ret_val; 962 u16 i; 963 964 DEBUGFUNC("e1000_init_hw_82543"); 965 966 /* Disabling VLAN filtering */ 967 E1000_WRITE_REG(hw, E1000_VET, 0); 968 mac->ops.clear_vfta(hw); 969 970 /* Setup the receive address. */ 971 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 972 973 /* Zero out the Multicast HASH table */ 974 DEBUGOUT("Zeroing the MTA\n"); 975 for (i = 0; i < mac->mta_reg_count; i++) { 976 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 977 E1000_WRITE_FLUSH(hw); 978 } 979 980 /* 981 * Set the PCI priority bit correctly in the CTRL register. This 982 * determines if the adapter gives priority to receives, or if it 983 * gives equal priority to transmits and receives. 984 */ 985 if (hw->mac.type == e1000_82543 && dev_spec->dma_fairness) { 986 ctrl = E1000_READ_REG(hw, E1000_CTRL); 987 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR); 988 } 989 990 e1000_pcix_mmrbc_workaround_generic(hw); 991 992 /* Setup link and flow control */ 993 ret_val = mac->ops.setup_link(hw); 994 995 /* 996 * Clear all of the statistics registers (clear on read). It is 997 * important that we do this after we have tried to establish link 998 * because the symbol error count will increment wildly if there 999 * is no link. 1000 */ 1001 e1000_clear_hw_cntrs_82543(hw); 1002 1003 return ret_val; 1004 } 1005 1006 /** 1007 * e1000_setup_link_82543 - Setup flow control and link settings 1008 * @hw: pointer to the HW structure 1009 * 1010 * Read the EEPROM to determine the initial polarity value and write the 1011 * extended device control register with the information before calling 1012 * the generic setup link function, which does the following: 1013 * Determines which flow control settings to use, then configures flow 1014 * control. Calls the appropriate media-specific link configuration 1015 * function. Assuming the adapter has a valid link partner, a valid link 1016 * should be established. Assumes the hardware has previously been reset 1017 * and the transmitter and receiver are not enabled. 1018 **/ 1019 static s32 e1000_setup_link_82543(struct e1000_hw *hw) 1020 { 1021 u32 ctrl_ext; 1022 s32 ret_val; 1023 u16 data; 1024 1025 DEBUGFUNC("e1000_setup_link_82543"); 1026 1027 /* 1028 * Take the 4 bits from NVM word 0xF that determine the initial 1029 * polarity value for the SW controlled pins, and setup the 1030 * Extended Device Control reg with that info. 1031 * This is needed because one of the SW controlled pins is used for 1032 * signal detection. So this should be done before phy setup. 1033 */ 1034 if (hw->mac.type == e1000_82543) { 1035 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data); 1036 if (ret_val) { 1037 DEBUGOUT("NVM Read Error\n"); 1038 ret_val = -E1000_ERR_NVM; 1039 goto out; 1040 } 1041 ctrl_ext = ((data & NVM_WORD0F_SWPDIO_EXT_MASK) << 1042 NVM_SWDPIO_EXT_SHIFT); 1043 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1044 } 1045 1046 ret_val = e1000_setup_link_generic(hw); 1047 1048 out: 1049 return ret_val; 1050 } 1051 1052 /** 1053 * e1000_setup_copper_link_82543 - Configure copper link settings 1054 * @hw: pointer to the HW structure 1055 * 1056 * Configures the link for auto-neg or forced speed and duplex. Then we check 1057 * for link, once link is established calls to configure collision distance 1058 * and flow control are called. 1059 **/ 1060 static s32 e1000_setup_copper_link_82543(struct e1000_hw *hw) 1061 { 1062 u32 ctrl; 1063 s32 ret_val; 1064 bool link; 1065 1066 DEBUGFUNC("e1000_setup_copper_link_82543"); 1067 1068 ctrl = E1000_READ_REG(hw, E1000_CTRL) | E1000_CTRL_SLU; 1069 /* 1070 * With 82543, we need to force speed and duplex on the MAC 1071 * equal to what the PHY speed and duplex configuration is. 1072 * In addition, we need to perform a hardware reset on the 1073 * PHY to take it out of reset. 1074 */ 1075 if (hw->mac.type == e1000_82543) { 1076 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1077 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1078 ret_val = hw->phy.ops.reset(hw); 1079 if (ret_val) 1080 goto out; 1081 hw->phy.reset_disable = FALSE; 1082 } else { 1083 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1084 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1085 } 1086 1087 /* Set MDI/MDI-X, Polarity Reversal, and downshift settings */ 1088 ret_val = e1000_copper_link_setup_m88(hw); 1089 if (ret_val) 1090 goto out; 1091 1092 if (hw->mac.autoneg) { 1093 /* 1094 * Setup autoneg and flow control advertisement and perform 1095 * autonegotiation. 1096 */ 1097 ret_val = e1000_copper_link_autoneg(hw); 1098 if (ret_val) 1099 goto out; 1100 } else { 1101 /* 1102 * PHY will be set to 10H, 10F, 100H or 100F 1103 * depending on user settings. 1104 */ 1105 DEBUGOUT("Forcing Speed and Duplex\n"); 1106 ret_val = e1000_phy_force_speed_duplex_82543(hw); 1107 if (ret_val) { 1108 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1109 goto out; 1110 } 1111 } 1112 1113 /* 1114 * Check link status. Wait up to 100 microseconds for link to become 1115 * valid. 1116 */ 1117 ret_val = e1000_phy_has_link_generic(hw, 1118 COPPER_LINK_UP_LIMIT, 1119 10, 1120 &link); 1121 if (ret_val) 1122 goto out; 1123 1124 1125 if (link) { 1126 DEBUGOUT("Valid link established!!!\n"); 1127 /* Config the MAC and PHY after link is up */ 1128 if (hw->mac.type == e1000_82544) { 1129 e1000_config_collision_dist_generic(hw); 1130 } else { 1131 ret_val = e1000_config_mac_to_phy_82543(hw); 1132 if (ret_val) 1133 goto out; 1134 } 1135 ret_val = e1000_config_fc_after_link_up_generic(hw); 1136 } else { 1137 DEBUGOUT("Unable to establish link!!!\n"); 1138 } 1139 1140 out: 1141 return ret_val; 1142 } 1143 1144 /** 1145 * e1000_setup_fiber_link_82543 - Setup link for fiber 1146 * @hw: pointer to the HW structure 1147 * 1148 * Configures collision distance and flow control for fiber links. Upon 1149 * successful setup, poll for link. 1150 **/ 1151 static s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw) 1152 { 1153 u32 ctrl; 1154 s32 ret_val; 1155 1156 DEBUGFUNC("e1000_setup_fiber_link_82543"); 1157 1158 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1159 1160 /* Take the link out of reset */ 1161 ctrl &= ~E1000_CTRL_LRST; 1162 1163 e1000_config_collision_dist_generic(hw); 1164 1165 ret_val = e1000_commit_fc_settings_generic(hw); 1166 if (ret_val) 1167 goto out; 1168 1169 DEBUGOUT("Auto-negotiation enabled\n"); 1170 1171 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1172 E1000_WRITE_FLUSH(hw); 1173 msec_delay(1); 1174 1175 /* 1176 * For these adapters, the SW definable pin 1 is cleared when the 1177 * optics detect a signal. If we have a signal, then poll for a 1178 * "Link-Up" indication. 1179 */ 1180 if (!(E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1181 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1182 } else { 1183 DEBUGOUT("No signal detected\n"); 1184 } 1185 1186 out: 1187 return ret_val; 1188 } 1189 1190 /** 1191 * e1000_check_for_copper_link_82543 - Check for link (Copper) 1192 * @hw: pointer to the HW structure 1193 * 1194 * Checks the phy for link, if link exists, do the following: 1195 * - check for downshift 1196 * - do polarity workaround (if necessary) 1197 * - configure collision distance 1198 * - configure flow control after link up 1199 * - configure tbi compatibility 1200 **/ 1201 static s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw) 1202 { 1203 struct e1000_mac_info *mac = &hw->mac; 1204 u32 icr, rctl; 1205 s32 ret_val; 1206 u16 speed, duplex; 1207 bool link; 1208 1209 DEBUGFUNC("e1000_check_for_copper_link_82543"); 1210 1211 if (!mac->get_link_status) { 1212 ret_val = E1000_SUCCESS; 1213 goto out; 1214 } 1215 1216 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 1217 if (ret_val) 1218 goto out; 1219 1220 if (!link) 1221 goto out; /* No link detected */ 1222 1223 mac->get_link_status = FALSE; 1224 1225 e1000_check_downshift_generic(hw); 1226 1227 /* 1228 * If we are forcing speed/duplex, then we can return since 1229 * we have already determined whether we have link or not. 1230 */ 1231 if (!mac->autoneg) { 1232 /* 1233 * If speed and duplex are forced to 10H or 10F, then we will 1234 * implement the polarity reversal workaround. We disable 1235 * interrupts first, and upon returning, place the devices 1236 * interrupt state to its previous value except for the link 1237 * status change interrupt which will happened due to the 1238 * execution of this workaround. 1239 */ 1240 if (mac->forced_speed_duplex & E1000_ALL_10_SPEED) { 1241 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 1242 ret_val = e1000_polarity_reversal_workaround_82543(hw); 1243 icr = E1000_READ_REG(hw, E1000_ICR); 1244 E1000_WRITE_REG(hw, E1000_ICS, (icr & ~E1000_ICS_LSC)); 1245 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 1246 } 1247 1248 ret_val = -E1000_ERR_CONFIG; 1249 goto out; 1250 } 1251 1252 /* 1253 * We have a M88E1000 PHY and Auto-Neg is enabled. If we 1254 * have Si on board that is 82544 or newer, Auto 1255 * Speed Detection takes care of MAC speed/duplex 1256 * configuration. So we only need to configure Collision 1257 * Distance in the MAC. Otherwise, we need to force 1258 * speed/duplex on the MAC to the current PHY speed/duplex 1259 * settings. 1260 */ 1261 if (mac->type == e1000_82544) 1262 e1000_config_collision_dist_generic(hw); 1263 else { 1264 ret_val = e1000_config_mac_to_phy_82543(hw); 1265 if (ret_val) { 1266 DEBUGOUT("Error configuring MAC to PHY settings\n"); 1267 goto out; 1268 } 1269 } 1270 1271 /* 1272 * Configure Flow Control now that Auto-Neg has completed. 1273 * First, we need to restore the desired flow control 1274 * settings because we may have had to re-autoneg with a 1275 * different link partner. 1276 */ 1277 ret_val = e1000_config_fc_after_link_up_generic(hw); 1278 if (ret_val) { 1279 DEBUGOUT("Error configuring flow control\n"); 1280 } 1281 1282 /* 1283 * At this point we know that we are on copper and we have 1284 * auto-negotiated link. These are conditions for checking the link 1285 * partner capability register. We use the link speed to determine if 1286 * TBI compatibility needs to be turned on or off. If the link is not 1287 * at gigabit speed, then TBI compatibility is not needed. If we are 1288 * at gigabit speed, we turn on TBI compatibility. 1289 */ 1290 if (e1000_tbi_compatibility_enabled_82543(hw)) { 1291 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1292 if (ret_val) { 1293 DEBUGOUT("Error getting link speed and duplex\n"); 1294 return ret_val; 1295 } 1296 if (speed != SPEED_1000) { 1297 /* 1298 * If link speed is not set to gigabit speed, 1299 * we do not need to enable TBI compatibility. 1300 */ 1301 if (e1000_tbi_sbp_enabled_82543(hw)) { 1302 /* 1303 * If we previously were in the mode, 1304 * turn it off. 1305 */ 1306 e1000_set_tbi_sbp_82543(hw, FALSE); 1307 rctl = E1000_READ_REG(hw, E1000_RCTL); 1308 rctl &= ~E1000_RCTL_SBP; 1309 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1310 } 1311 } else { 1312 /* 1313 * If TBI compatibility is was previously off, 1314 * turn it on. For compatibility with a TBI link 1315 * partner, we will store bad packets. Some 1316 * frames have an additional byte on the end and 1317 * will look like CRC errors to to the hardware. 1318 */ 1319 if (!e1000_tbi_sbp_enabled_82543(hw)) { 1320 e1000_set_tbi_sbp_82543(hw, TRUE); 1321 rctl = E1000_READ_REG(hw, E1000_RCTL); 1322 rctl |= E1000_RCTL_SBP; 1323 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1324 } 1325 } 1326 } 1327 out: 1328 return ret_val; 1329 } 1330 1331 /** 1332 * e1000_check_for_fiber_link_82543 - Check for link (Fiber) 1333 * @hw: pointer to the HW structure 1334 * 1335 * Checks for link up on the hardware. If link is not up and we have 1336 * a signal, then we need to force link up. 1337 **/ 1338 static s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw) 1339 { 1340 struct e1000_mac_info *mac = &hw->mac; 1341 u32 rxcw, ctrl, status; 1342 s32 ret_val = E1000_SUCCESS; 1343 1344 DEBUGFUNC("e1000_check_for_fiber_link_82543"); 1345 1346 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1347 status = E1000_READ_REG(hw, E1000_STATUS); 1348 rxcw = E1000_READ_REG(hw, E1000_RXCW); 1349 1350 /* 1351 * If we don't have link (auto-negotiation failed or link partner 1352 * cannot auto-negotiate), the cable is plugged in (we have signal), 1353 * and our link partner is not trying to auto-negotiate with us (we 1354 * are receiving idles or data), we need to force link up. We also 1355 * need to give auto-negotiation time to complete, in case the cable 1356 * was just plugged in. The autoneg_failed flag does this. 1357 */ 1358 /* (ctrl & E1000_CTRL_SWDPIN1) == 0 == have signal */ 1359 if ((!(ctrl & E1000_CTRL_SWDPIN1)) && 1360 (!(status & E1000_STATUS_LU)) && 1361 (!(rxcw & E1000_RXCW_C))) { 1362 if (mac->autoneg_failed == 0) { 1363 mac->autoneg_failed = 1; 1364 ret_val = 0; 1365 goto out; 1366 } 1367 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 1368 1369 /* Disable auto-negotiation in the TXCW register */ 1370 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 1371 1372 /* Force link-up and also force full-duplex. */ 1373 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1374 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 1375 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1376 1377 /* Configure Flow Control after forcing link up. */ 1378 ret_val = e1000_config_fc_after_link_up_generic(hw); 1379 if (ret_val) { 1380 DEBUGOUT("Error configuring flow control\n"); 1381 goto out; 1382 } 1383 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 1384 /* 1385 * If we are forcing link and we are receiving /C/ ordered 1386 * sets, re-enable auto-negotiation in the TXCW register 1387 * and disable forced link in the Device Control register 1388 * in an attempt to auto-negotiate with our link partner. 1389 */ 1390 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 1391 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1392 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 1393 1394 mac->serdes_has_link = TRUE; 1395 } 1396 1397 out: 1398 return ret_val; 1399 } 1400 1401 /** 1402 * e1000_config_mac_to_phy_82543 - Configure MAC to PHY settings 1403 * @hw: pointer to the HW structure 1404 * 1405 * For the 82543 silicon, we need to set the MAC to match the settings 1406 * of the PHY, even if the PHY is auto-negotiating. 1407 **/ 1408 static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw) 1409 { 1410 u32 ctrl; 1411 s32 ret_val = E1000_SUCCESS; 1412 u16 phy_data; 1413 1414 DEBUGFUNC("e1000_config_mac_to_phy_82543"); 1415 1416 if (!(hw->phy.ops.read_reg)) 1417 goto out; 1418 1419 /* Set the bits to force speed and duplex */ 1420 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1421 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1422 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 1423 1424 /* 1425 * Set up duplex in the Device Control and Transmit Control 1426 * registers depending on negotiated values. 1427 */ 1428 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1429 if (ret_val) 1430 goto out; 1431 1432 ctrl &= ~E1000_CTRL_FD; 1433 if (phy_data & M88E1000_PSSR_DPLX) 1434 ctrl |= E1000_CTRL_FD; 1435 1436 e1000_config_collision_dist_generic(hw); 1437 1438 /* 1439 * Set up speed in the Device Control register depending on 1440 * negotiated values. 1441 */ 1442 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 1443 ctrl |= E1000_CTRL_SPD_1000; 1444 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 1445 ctrl |= E1000_CTRL_SPD_100; 1446 1447 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1448 1449 out: 1450 return ret_val; 1451 } 1452 1453 /** 1454 * e1000_write_vfta_82543 - Write value to VLAN filter table 1455 * @hw: pointer to the HW structure 1456 * @offset: the 32-bit offset in which to write the value to. 1457 * @value: the 32-bit value to write at location offset. 1458 * 1459 * This writes a 32-bit value to a 32-bit offset in the VLAN filter 1460 * table. 1461 **/ 1462 static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, u32 value) 1463 { 1464 u32 temp; 1465 1466 DEBUGFUNC("e1000_write_vfta_82543"); 1467 1468 if ((hw->mac.type == e1000_82544) && (offset & 1)) { 1469 temp = E1000_READ_REG_ARRAY(hw, E1000_VFTA, offset - 1); 1470 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 1471 E1000_WRITE_FLUSH(hw); 1472 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset - 1, temp); 1473 E1000_WRITE_FLUSH(hw); 1474 } else { 1475 e1000_write_vfta_generic(hw, offset, value); 1476 } 1477 } 1478 1479 /** 1480 * e1000_mta_set_82543 - Set multicast filter table address 1481 * @hw: pointer to the HW structure 1482 * @hash_value: determines the MTA register and bit to set 1483 * 1484 * The multicast table address is a register array of 32-bit registers. 1485 * The hash_value is used to determine what register the bit is in, the 1486 * current value is read, the new bit is OR'd in and the new value is 1487 * written back into the register. 1488 **/ 1489 static void e1000_mta_set_82543(struct e1000_hw *hw, u32 hash_value) 1490 { 1491 u32 hash_bit, hash_reg, mta, temp; 1492 1493 DEBUGFUNC("e1000_mta_set_82543"); 1494 1495 hash_reg = (hash_value >> 5); 1496 1497 /* 1498 * If we are on an 82544 and we are trying to write an odd offset 1499 * in the MTA, save off the previous entry before writing and 1500 * restore the old value after writing. 1501 */ 1502 if ((hw->mac.type == e1000_82544) && (hash_reg & 1)) { 1503 hash_reg &= (hw->mac.mta_reg_count - 1); 1504 hash_bit = hash_value & 0x1F; 1505 mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); 1506 mta |= (1 << hash_bit); 1507 temp = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg - 1); 1508 1509 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); 1510 E1000_WRITE_FLUSH(hw); 1511 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg - 1, temp); 1512 E1000_WRITE_FLUSH(hw); 1513 } else { 1514 e1000_mta_set_generic(hw, hash_value); 1515 } 1516 } 1517 1518 /** 1519 * e1000_led_on_82543 - Turn on SW controllable LED 1520 * @hw: pointer to the HW structure 1521 * 1522 * Turns the SW defined LED on. 1523 **/ 1524 static s32 e1000_led_on_82543(struct e1000_hw *hw) 1525 { 1526 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1527 1528 DEBUGFUNC("e1000_led_on_82543"); 1529 1530 if (hw->mac.type == e1000_82544 && 1531 hw->phy.media_type == e1000_media_type_copper) { 1532 /* Clear SW-definable Pin 0 to turn on the LED */ 1533 ctrl &= ~E1000_CTRL_SWDPIN0; 1534 ctrl |= E1000_CTRL_SWDPIO0; 1535 } else { 1536 /* Fiber 82544 and all 82543 use this method */ 1537 ctrl |= E1000_CTRL_SWDPIN0; 1538 ctrl |= E1000_CTRL_SWDPIO0; 1539 } 1540 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1541 1542 return E1000_SUCCESS; 1543 } 1544 1545 /** 1546 * e1000_led_off_82543 - Turn off SW controllable LED 1547 * @hw: pointer to the HW structure 1548 * 1549 * Turns the SW defined LED off. 1550 **/ 1551 static s32 e1000_led_off_82543(struct e1000_hw *hw) 1552 { 1553 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1554 1555 DEBUGFUNC("e1000_led_off_82543"); 1556 1557 if (hw->mac.type == e1000_82544 && 1558 hw->phy.media_type == e1000_media_type_copper) { 1559 /* Set SW-definable Pin 0 to turn off the LED */ 1560 ctrl |= E1000_CTRL_SWDPIN0; 1561 ctrl |= E1000_CTRL_SWDPIO0; 1562 } else { 1563 ctrl &= ~E1000_CTRL_SWDPIN0; 1564 ctrl |= E1000_CTRL_SWDPIO0; 1565 } 1566 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1567 1568 return E1000_SUCCESS; 1569 } 1570 1571 /** 1572 * e1000_clear_hw_cntrs_82543 - Clear device specific hardware counters 1573 * @hw: pointer to the HW structure 1574 * 1575 * Clears the hardware counters by reading the counter registers. 1576 **/ 1577 static void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw) 1578 { 1579 DEBUGFUNC("e1000_clear_hw_cntrs_82543"); 1580 1581 e1000_clear_hw_cntrs_base_generic(hw); 1582 1583 E1000_READ_REG(hw, E1000_PRC64); 1584 E1000_READ_REG(hw, E1000_PRC127); 1585 E1000_READ_REG(hw, E1000_PRC255); 1586 E1000_READ_REG(hw, E1000_PRC511); 1587 E1000_READ_REG(hw, E1000_PRC1023); 1588 E1000_READ_REG(hw, E1000_PRC1522); 1589 E1000_READ_REG(hw, E1000_PTC64); 1590 E1000_READ_REG(hw, E1000_PTC127); 1591 E1000_READ_REG(hw, E1000_PTC255); 1592 E1000_READ_REG(hw, E1000_PTC511); 1593 E1000_READ_REG(hw, E1000_PTC1023); 1594 E1000_READ_REG(hw, E1000_PTC1522); 1595 1596 E1000_READ_REG(hw, E1000_ALGNERRC); 1597 E1000_READ_REG(hw, E1000_RXERRC); 1598 E1000_READ_REG(hw, E1000_TNCRS); 1599 E1000_READ_REG(hw, E1000_CEXTERR); 1600 E1000_READ_REG(hw, E1000_TSCTC); 1601 E1000_READ_REG(hw, E1000_TSCTFC); 1602 } 1603