1 /****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD: $*/ 34 35 /* 36 * 82543GC Gigabit Ethernet Controller (Fiber) 37 * 82543GC Gigabit Ethernet Controller (Copper) 38 * 82544EI Gigabit Ethernet Controller (Copper) 39 * 82544EI Gigabit Ethernet Controller (Fiber) 40 * 82544GC Gigabit Ethernet Controller (Copper) 41 * 82544GC Gigabit Ethernet Controller (LOM) 42 */ 43 44 #include "e1000_api.h" 45 46 static s32 e1000_init_phy_params_82543(struct e1000_hw *hw); 47 static s32 e1000_init_nvm_params_82543(struct e1000_hw *hw); 48 static s32 e1000_init_mac_params_82543(struct e1000_hw *hw); 49 static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, 50 u16 *data); 51 static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, 52 u16 data); 53 static s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw); 54 static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw); 55 static s32 e1000_reset_hw_82543(struct e1000_hw *hw); 56 static s32 e1000_init_hw_82543(struct e1000_hw *hw); 57 static s32 e1000_setup_link_82543(struct e1000_hw *hw); 58 static s32 e1000_setup_copper_link_82543(struct e1000_hw *hw); 59 static s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw); 60 static s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw); 61 static s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw); 62 static s32 e1000_led_on_82543(struct e1000_hw *hw); 63 static s32 e1000_led_off_82543(struct e1000_hw *hw); 64 static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, 65 u32 value); 66 static void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw); 67 static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw); 68 static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw); 69 static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl); 70 static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw); 71 static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl); 72 static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw); 73 static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data, 74 u16 count); 75 static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw); 76 static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state); 77 78 /** 79 * e1000_init_phy_params_82543 - Init PHY func ptrs. 80 * @hw: pointer to the HW structure 81 **/ 82 static s32 e1000_init_phy_params_82543(struct e1000_hw *hw) 83 { 84 struct e1000_phy_info *phy = &hw->phy; 85 s32 ret_val = E1000_SUCCESS; 86 87 DEBUGFUNC("e1000_init_phy_params_82543"); 88 89 if (hw->phy.media_type != e1000_media_type_copper) { 90 phy->type = e1000_phy_none; 91 goto out; 92 } else { 93 phy->ops.power_up = e1000_power_up_phy_copper; 94 phy->ops.power_down = e1000_power_down_phy_copper; 95 } 96 97 phy->addr = 1; 98 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 99 phy->reset_delay_us = 10000; 100 phy->type = e1000_phy_m88; 101 102 /* Function Pointers */ 103 phy->ops.check_polarity = e1000_check_polarity_m88; 104 phy->ops.commit = e1000_phy_sw_reset_generic; 105 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82543; 106 phy->ops.get_cable_length = e1000_get_cable_length_m88; 107 phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 108 phy->ops.read_reg = (hw->mac.type == e1000_82543) 109 ? e1000_read_phy_reg_82543 110 : e1000_read_phy_reg_m88; 111 phy->ops.reset = (hw->mac.type == e1000_82543) 112 ? e1000_phy_hw_reset_82543 113 : e1000_phy_hw_reset_generic; 114 phy->ops.write_reg = (hw->mac.type == e1000_82543) 115 ? e1000_write_phy_reg_82543 116 : e1000_write_phy_reg_m88; 117 phy->ops.get_info = e1000_get_phy_info_m88; 118 119 /* 120 * The external PHY of the 82543 can be in a funky state. 121 * Resetting helps us read the PHY registers for acquiring 122 * the PHY ID. 123 */ 124 if (!e1000_init_phy_disabled_82543(hw)) { 125 ret_val = phy->ops.reset(hw); 126 if (ret_val) { 127 DEBUGOUT("Resetting PHY during init failed.\n"); 128 goto out; 129 } 130 msec_delay(20); 131 } 132 133 ret_val = e1000_get_phy_id(hw); 134 if (ret_val) 135 goto out; 136 137 /* Verify phy id */ 138 switch (hw->mac.type) { 139 case e1000_82543: 140 if (phy->id != M88E1000_E_PHY_ID) { 141 ret_val = -E1000_ERR_PHY; 142 goto out; 143 } 144 break; 145 case e1000_82544: 146 if (phy->id != M88E1000_I_PHY_ID) { 147 ret_val = -E1000_ERR_PHY; 148 goto out; 149 } 150 break; 151 default: 152 ret_val = -E1000_ERR_PHY; 153 goto out; 154 break; 155 } 156 157 out: 158 return ret_val; 159 } 160 161 /** 162 * e1000_init_nvm_params_82543 - Init NVM func ptrs. 163 * @hw: pointer to the HW structure 164 **/ 165 static s32 e1000_init_nvm_params_82543(struct e1000_hw *hw) 166 { 167 struct e1000_nvm_info *nvm = &hw->nvm; 168 169 DEBUGFUNC("e1000_init_nvm_params_82543"); 170 171 nvm->type = e1000_nvm_eeprom_microwire; 172 nvm->word_size = 64; 173 nvm->delay_usec = 50; 174 nvm->address_bits = 6; 175 nvm->opcode_bits = 3; 176 177 /* Function Pointers */ 178 nvm->ops.read = e1000_read_nvm_microwire; 179 nvm->ops.update = e1000_update_nvm_checksum_generic; 180 nvm->ops.valid_led_default = e1000_valid_led_default_generic; 181 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 182 nvm->ops.write = e1000_write_nvm_microwire; 183 184 return E1000_SUCCESS; 185 } 186 187 /** 188 * e1000_init_mac_params_82543 - Init MAC func ptrs. 189 * @hw: pointer to the HW structure 190 **/ 191 static s32 e1000_init_mac_params_82543(struct e1000_hw *hw) 192 { 193 struct e1000_mac_info *mac = &hw->mac; 194 195 DEBUGFUNC("e1000_init_mac_params_82543"); 196 197 /* Set media type */ 198 switch (hw->device_id) { 199 case E1000_DEV_ID_82543GC_FIBER: 200 case E1000_DEV_ID_82544EI_FIBER: 201 hw->phy.media_type = e1000_media_type_fiber; 202 break; 203 default: 204 hw->phy.media_type = e1000_media_type_copper; 205 break; 206 } 207 208 /* Set mta register count */ 209 mac->mta_reg_count = 128; 210 /* Set rar entry count */ 211 mac->rar_entry_count = E1000_RAR_ENTRIES; 212 213 /* Function pointers */ 214 215 /* bus type/speed/width */ 216 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic; 217 /* function id */ 218 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci; 219 /* reset */ 220 mac->ops.reset_hw = e1000_reset_hw_82543; 221 /* hw initialization */ 222 mac->ops.init_hw = e1000_init_hw_82543; 223 /* link setup */ 224 mac->ops.setup_link = e1000_setup_link_82543; 225 /* physical interface setup */ 226 mac->ops.setup_physical_interface = 227 (hw->phy.media_type == e1000_media_type_copper) 228 ? e1000_setup_copper_link_82543 229 : e1000_setup_fiber_link_82543; 230 /* check for link */ 231 mac->ops.check_for_link = 232 (hw->phy.media_type == e1000_media_type_copper) 233 ? e1000_check_for_copper_link_82543 234 : e1000_check_for_fiber_link_82543; 235 /* link info */ 236 mac->ops.get_link_up_info = 237 (hw->phy.media_type == e1000_media_type_copper) 238 ? e1000_get_speed_and_duplex_copper_generic 239 : e1000_get_speed_and_duplex_fiber_serdes_generic; 240 /* multicast address update */ 241 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 242 /* writing VFTA */ 243 mac->ops.write_vfta = e1000_write_vfta_82543; 244 /* clearing VFTA */ 245 mac->ops.clear_vfta = e1000_clear_vfta_generic; 246 /* turn on/off LED */ 247 mac->ops.led_on = e1000_led_on_82543; 248 mac->ops.led_off = e1000_led_off_82543; 249 /* clear hardware counters */ 250 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82543; 251 252 /* Set tbi compatibility */ 253 if ((hw->mac.type != e1000_82543) || 254 (hw->phy.media_type == e1000_media_type_fiber)) 255 e1000_set_tbi_compatibility_82543(hw, FALSE); 256 257 return E1000_SUCCESS; 258 } 259 260 /** 261 * e1000_init_function_pointers_82543 - Init func ptrs. 262 * @hw: pointer to the HW structure 263 * 264 * Called to initialize all function pointers and parameters. 265 **/ 266 void e1000_init_function_pointers_82543(struct e1000_hw *hw) 267 { 268 DEBUGFUNC("e1000_init_function_pointers_82543"); 269 270 hw->mac.ops.init_params = e1000_init_mac_params_82543; 271 hw->nvm.ops.init_params = e1000_init_nvm_params_82543; 272 hw->phy.ops.init_params = e1000_init_phy_params_82543; 273 } 274 275 /** 276 * e1000_tbi_compatibility_enabled_82543 - Returns TBI compat status 277 * @hw: pointer to the HW structure 278 * 279 * Returns the current status of 10-bit Interface (TBI) compatibility 280 * (enabled/disabled). 281 **/ 282 static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw) 283 { 284 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 285 bool state = FALSE; 286 287 DEBUGFUNC("e1000_tbi_compatibility_enabled_82543"); 288 289 if (hw->mac.type != e1000_82543) { 290 DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 291 goto out; 292 } 293 294 state = (dev_spec->tbi_compatibility & TBI_COMPAT_ENABLED) 295 ? TRUE : FALSE; 296 297 out: 298 return state; 299 } 300 301 /** 302 * e1000_set_tbi_compatibility_82543 - Set TBI compatibility 303 * @hw: pointer to the HW structure 304 * @state: enable/disable TBI compatibility 305 * 306 * Enables or disabled 10-bit Interface (TBI) compatibility. 307 **/ 308 void e1000_set_tbi_compatibility_82543(struct e1000_hw *hw, bool state) 309 { 310 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 311 312 DEBUGFUNC("e1000_set_tbi_compatibility_82543"); 313 314 if (hw->mac.type != e1000_82543) { 315 DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 316 goto out; 317 } 318 319 if (state) 320 dev_spec->tbi_compatibility |= TBI_COMPAT_ENABLED; 321 else 322 dev_spec->tbi_compatibility &= ~TBI_COMPAT_ENABLED; 323 324 out: 325 return; 326 } 327 328 /** 329 * e1000_tbi_sbp_enabled_82543 - Returns TBI SBP status 330 * @hw: pointer to the HW structure 331 * 332 * Returns the current status of 10-bit Interface (TBI) store bad packet (SBP) 333 * (enabled/disabled). 334 **/ 335 bool e1000_tbi_sbp_enabled_82543(struct e1000_hw *hw) 336 { 337 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 338 bool state = FALSE; 339 340 DEBUGFUNC("e1000_tbi_sbp_enabled_82543"); 341 342 if (hw->mac.type != e1000_82543) { 343 DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 344 goto out; 345 } 346 347 state = (dev_spec->tbi_compatibility & TBI_SBP_ENABLED) 348 ? TRUE : FALSE; 349 350 out: 351 return state; 352 } 353 354 /** 355 * e1000_set_tbi_sbp_82543 - Set TBI SBP 356 * @hw: pointer to the HW structure 357 * @state: enable/disable TBI store bad packet 358 * 359 * Enables or disabled 10-bit Interface (TBI) store bad packet (SBP). 360 **/ 361 static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state) 362 { 363 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 364 365 DEBUGFUNC("e1000_set_tbi_sbp_82543"); 366 367 if (state && e1000_tbi_compatibility_enabled_82543(hw)) 368 dev_spec->tbi_compatibility |= TBI_SBP_ENABLED; 369 else 370 dev_spec->tbi_compatibility &= ~TBI_SBP_ENABLED; 371 372 return; 373 } 374 375 /** 376 * e1000_init_phy_disabled_82543 - Returns init PHY status 377 * @hw: pointer to the HW structure 378 * 379 * Returns the current status of whether PHY initialization is disabled. 380 * True if PHY initialization is disabled else FALSE. 381 **/ 382 static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw) 383 { 384 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 385 bool ret_val; 386 387 DEBUGFUNC("e1000_init_phy_disabled_82543"); 388 389 if (hw->mac.type != e1000_82543) { 390 ret_val = FALSE; 391 goto out; 392 } 393 394 ret_val = dev_spec->init_phy_disabled; 395 396 out: 397 return ret_val; 398 } 399 400 /** 401 * e1000_tbi_adjust_stats_82543 - Adjust stats when TBI enabled 402 * @hw: pointer to the HW structure 403 * @stats: Struct containing statistic register values 404 * @frame_len: The length of the frame in question 405 * @mac_addr: The Ethernet destination address of the frame in question 406 * @max_frame_size: The maximum frame size 407 * 408 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT 409 **/ 410 void e1000_tbi_adjust_stats_82543(struct e1000_hw *hw, 411 struct e1000_hw_stats *stats, u32 frame_len, 412 u8 *mac_addr, u32 max_frame_size) 413 { 414 if (!(e1000_tbi_sbp_enabled_82543(hw))) 415 goto out; 416 417 /* First adjust the frame length. */ 418 frame_len--; 419 /* 420 * We need to adjust the statistics counters, since the hardware 421 * counters overcount this packet as a CRC error and undercount 422 * the packet as a good packet 423 */ 424 /* This packet should not be counted as a CRC error. */ 425 stats->crcerrs--; 426 /* This packet does count as a Good Packet Received. */ 427 stats->gprc++; 428 429 /* Adjust the Good Octets received counters */ 430 stats->gorc += frame_len; 431 432 /* 433 * Is this a broadcast or multicast? Check broadcast first, 434 * since the test for a multicast frame will test positive on 435 * a broadcast frame. 436 */ 437 if ((mac_addr[0] == 0xff) && (mac_addr[1] == 0xff)) 438 /* Broadcast packet */ 439 stats->bprc++; 440 else if (*mac_addr & 0x01) 441 /* Multicast packet */ 442 stats->mprc++; 443 444 /* 445 * In this case, the hardware has overcounted the number of 446 * oversize frames. 447 */ 448 if ((frame_len == max_frame_size) && (stats->roc > 0)) 449 stats->roc--; 450 451 /* 452 * Adjust the bin counters when the extra byte put the frame in the 453 * wrong bin. Remember that the frame_len was adjusted above. 454 */ 455 if (frame_len == 64) { 456 stats->prc64++; 457 stats->prc127--; 458 } else if (frame_len == 127) { 459 stats->prc127++; 460 stats->prc255--; 461 } else if (frame_len == 255) { 462 stats->prc255++; 463 stats->prc511--; 464 } else if (frame_len == 511) { 465 stats->prc511++; 466 stats->prc1023--; 467 } else if (frame_len == 1023) { 468 stats->prc1023++; 469 stats->prc1522--; 470 } else if (frame_len == 1522) { 471 stats->prc1522++; 472 } 473 474 out: 475 return; 476 } 477 478 /** 479 * e1000_read_phy_reg_82543 - Read PHY register 480 * @hw: pointer to the HW structure 481 * @offset: register offset to be read 482 * @data: pointer to the read data 483 * 484 * Reads the PHY at offset and stores the information read to data. 485 **/ 486 static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 *data) 487 { 488 u32 mdic; 489 s32 ret_val = E1000_SUCCESS; 490 491 DEBUGFUNC("e1000_read_phy_reg_82543"); 492 493 if (offset > MAX_PHY_REG_ADDRESS) { 494 DEBUGOUT1("PHY Address %d is out of range\n", offset); 495 ret_val = -E1000_ERR_PARAM; 496 goto out; 497 } 498 499 /* 500 * We must first send a preamble through the MDIO pin to signal the 501 * beginning of an MII instruction. This is done by sending 32 502 * consecutive "1" bits. 503 */ 504 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 505 506 /* 507 * Now combine the next few fields that are required for a read 508 * operation. We use this method instead of calling the 509 * e1000_shift_out_mdi_bits routine five different times. The format 510 * of an MII read instruction consists of a shift out of 14 bits and 511 * is defined as follows: 512 * <Preamble><SOF><Op Code><Phy Addr><Offset> 513 * followed by a shift in of 18 bits. This first two bits shifted in 514 * are TurnAround bits used to avoid contention on the MDIO pin when a 515 * READ operation is performed. These two bits are thrown away 516 * followed by a shift in of 16 bits which contains the desired data. 517 */ 518 mdic = (offset | (hw->phy.addr << 5) | 519 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 520 521 e1000_shift_out_mdi_bits_82543(hw, mdic, 14); 522 523 /* 524 * Now that we've shifted out the read command to the MII, we need to 525 * "shift in" the 16-bit value (18 total bits) of the requested PHY 526 * register address. 527 */ 528 *data = e1000_shift_in_mdi_bits_82543(hw); 529 530 out: 531 return ret_val; 532 } 533 534 /** 535 * e1000_write_phy_reg_82543 - Write PHY register 536 * @hw: pointer to the HW structure 537 * @offset: register offset to be written 538 * @data: pointer to the data to be written at offset 539 * 540 * Writes data to the PHY at offset. 541 **/ 542 static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 data) 543 { 544 u32 mdic; 545 s32 ret_val = E1000_SUCCESS; 546 547 DEBUGFUNC("e1000_write_phy_reg_82543"); 548 549 if (offset > MAX_PHY_REG_ADDRESS) { 550 DEBUGOUT1("PHY Address %d is out of range\n", offset); 551 ret_val = -E1000_ERR_PARAM; 552 goto out; 553 } 554 555 /* 556 * We'll need to use the SW defined pins to shift the write command 557 * out to the PHY. We first send a preamble to the PHY to signal the 558 * beginning of the MII instruction. This is done by sending 32 559 * consecutive "1" bits. 560 */ 561 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 562 563 /* 564 * Now combine the remaining required fields that will indicate a 565 * write operation. We use this method instead of calling the 566 * e1000_shift_out_mdi_bits routine for each field in the command. The 567 * format of a MII write instruction is as follows: 568 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 569 */ 570 mdic = ((PHY_TURNAROUND) | (offset << 2) | (hw->phy.addr << 7) | 571 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 572 mdic <<= 16; 573 mdic |= (u32) data; 574 575 e1000_shift_out_mdi_bits_82543(hw, mdic, 32); 576 577 out: 578 return ret_val; 579 } 580 581 /** 582 * e1000_raise_mdi_clk_82543 - Raise Management Data Input clock 583 * @hw: pointer to the HW structure 584 * @ctrl: pointer to the control register 585 * 586 * Raise the management data input clock by setting the MDC bit in the control 587 * register. 588 **/ 589 static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl) 590 { 591 /* 592 * Raise the clock input to the Management Data Clock (by setting the 593 * MDC bit), and then delay a sufficient amount of time. 594 */ 595 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl | E1000_CTRL_MDC)); 596 E1000_WRITE_FLUSH(hw); 597 usec_delay(10); 598 } 599 600 /** 601 * e1000_lower_mdi_clk_82543 - Lower Management Data Input clock 602 * @hw: pointer to the HW structure 603 * @ctrl: pointer to the control register 604 * 605 * Lower the management data input clock by clearing the MDC bit in the 606 * control register. 607 **/ 608 static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl) 609 { 610 /* 611 * Lower the clock input to the Management Data Clock (by clearing the 612 * MDC bit), and then delay a sufficient amount of time. 613 */ 614 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl & ~E1000_CTRL_MDC)); 615 E1000_WRITE_FLUSH(hw); 616 usec_delay(10); 617 } 618 619 /** 620 * e1000_shift_out_mdi_bits_82543 - Shift data bits our to the PHY 621 * @hw: pointer to the HW structure 622 * @data: data to send to the PHY 623 * @count: number of bits to shift out 624 * 625 * We need to shift 'count' bits out to the PHY. So, the value in the 626 * "data" parameter will be shifted out to the PHY one bit at a time. 627 * In order to do this, "data" must be broken down into bits. 628 **/ 629 static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data, 630 u16 count) 631 { 632 u32 ctrl, mask; 633 634 /* 635 * We need to shift "count" number of bits out to the PHY. So, the 636 * value in the "data" parameter will be shifted out to the PHY one 637 * bit at a time. In order to do this, "data" must be broken down 638 * into bits. 639 */ 640 mask = 0x01; 641 mask <<= (count -1); 642 643 ctrl = E1000_READ_REG(hw, E1000_CTRL); 644 645 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 646 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 647 648 while (mask) { 649 /* 650 * A "1" is shifted out to the PHY by setting the MDIO bit to 651 * "1" and then raising and lowering the Management Data Clock. 652 * A "0" is shifted out to the PHY by setting the MDIO bit to 653 * "0" and then raising and lowering the clock. 654 */ 655 if (data & mask) ctrl |= E1000_CTRL_MDIO; 656 else ctrl &= ~E1000_CTRL_MDIO; 657 658 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 659 E1000_WRITE_FLUSH(hw); 660 661 usec_delay(10); 662 663 e1000_raise_mdi_clk_82543(hw, &ctrl); 664 e1000_lower_mdi_clk_82543(hw, &ctrl); 665 666 mask >>= 1; 667 } 668 } 669 670 /** 671 * e1000_shift_in_mdi_bits_82543 - Shift data bits in from the PHY 672 * @hw: pointer to the HW structure 673 * 674 * In order to read a register from the PHY, we need to shift 18 bits 675 * in from the PHY. Bits are "shifted in" by raising the clock input to 676 * the PHY (setting the MDC bit), and then reading the value of the data out 677 * MDIO bit. 678 **/ 679 static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw) 680 { 681 u32 ctrl; 682 u16 data = 0; 683 u8 i; 684 685 /* 686 * In order to read a register from the PHY, we need to shift in a 687 * total of 18 bits from the PHY. The first two bit (turnaround) 688 * times are used to avoid contention on the MDIO pin when a read 689 * operation is performed. These two bits are ignored by us and 690 * thrown away. Bits are "shifted in" by raising the input to the 691 * Management Data Clock (setting the MDC bit) and then reading the 692 * value of the MDIO bit. 693 */ 694 ctrl = E1000_READ_REG(hw, E1000_CTRL); 695 696 /* 697 * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as 698 * input. 699 */ 700 ctrl &= ~E1000_CTRL_MDIO_DIR; 701 ctrl &= ~E1000_CTRL_MDIO; 702 703 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 704 E1000_WRITE_FLUSH(hw); 705 706 /* 707 * Raise and lower the clock before reading in the data. This accounts 708 * for the turnaround bits. The first clock occurred when we clocked 709 * out the last bit of the Register Address. 710 */ 711 e1000_raise_mdi_clk_82543(hw, &ctrl); 712 e1000_lower_mdi_clk_82543(hw, &ctrl); 713 714 for (data = 0, i = 0; i < 16; i++) { 715 data <<= 1; 716 e1000_raise_mdi_clk_82543(hw, &ctrl); 717 ctrl = E1000_READ_REG(hw, E1000_CTRL); 718 /* Check to see if we shifted in a "1". */ 719 if (ctrl & E1000_CTRL_MDIO) 720 data |= 1; 721 e1000_lower_mdi_clk_82543(hw, &ctrl); 722 } 723 724 e1000_raise_mdi_clk_82543(hw, &ctrl); 725 e1000_lower_mdi_clk_82543(hw, &ctrl); 726 727 return data; 728 } 729 730 /** 731 * e1000_phy_force_speed_duplex_82543 - Force speed/duplex for PHY 732 * @hw: pointer to the HW structure 733 * 734 * Calls the function to force speed and duplex for the m88 PHY, and 735 * if the PHY is not auto-negotiating and the speed is forced to 10Mbit, 736 * then call the function for polarity reversal workaround. 737 **/ 738 static s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw) 739 { 740 s32 ret_val; 741 742 DEBUGFUNC("e1000_phy_force_speed_duplex_82543"); 743 744 ret_val = e1000_phy_force_speed_duplex_m88(hw); 745 if (ret_val) 746 goto out; 747 748 if (!hw->mac.autoneg && 749 (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)) 750 ret_val = e1000_polarity_reversal_workaround_82543(hw); 751 752 out: 753 return ret_val; 754 } 755 756 /** 757 * e1000_polarity_reversal_workaround_82543 - Workaround polarity reversal 758 * @hw: pointer to the HW structure 759 * 760 * When forcing link to 10 Full or 10 Half, the PHY can reverse the polarity 761 * inadvertently. To workaround the issue, we disable the transmitter on 762 * the PHY until we have established the link partner's link parameters. 763 **/ 764 static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw) 765 { 766 s32 ret_val = E1000_SUCCESS; 767 u16 mii_status_reg; 768 u16 i; 769 bool link; 770 771 if (!(hw->phy.ops.write_reg)) 772 goto out; 773 774 /* Polarity reversal workaround for forced 10F/10H links. */ 775 776 /* Disable the transmitter on the PHY */ 777 778 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 779 if (ret_val) 780 goto out; 781 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 782 if (ret_val) 783 goto out; 784 785 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 786 if (ret_val) 787 goto out; 788 789 /* 790 * This loop will early-out if the NO link condition has been met. 791 * In other words, DO NOT use e1000_phy_has_link_generic() here. 792 */ 793 for (i = PHY_FORCE_TIME; i > 0; i--) { 794 /* 795 * Read the MII Status Register and wait for Link Status bit 796 * to be clear. 797 */ 798 799 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 800 if (ret_val) 801 goto out; 802 803 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 804 if (ret_val) 805 goto out; 806 807 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) 808 break; 809 msec_delay_irq(100); 810 } 811 812 /* Recommended delay time after link has been lost */ 813 msec_delay_irq(1000); 814 815 /* Now we will re-enable the transmitter on the PHY */ 816 817 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 818 if (ret_val) 819 goto out; 820 msec_delay_irq(50); 821 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 822 if (ret_val) 823 goto out; 824 msec_delay_irq(50); 825 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 826 if (ret_val) 827 goto out; 828 msec_delay_irq(50); 829 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 830 if (ret_val) 831 goto out; 832 833 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 834 if (ret_val) 835 goto out; 836 837 /* 838 * Read the MII Status Register and wait for Link Status bit 839 * to be set. 840 */ 841 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_TIME, 100000, &link); 842 if (ret_val) 843 goto out; 844 845 out: 846 return ret_val; 847 } 848 849 /** 850 * e1000_phy_hw_reset_82543 - PHY hardware reset 851 * @hw: pointer to the HW structure 852 * 853 * Sets the PHY_RESET_DIR bit in the extended device control register 854 * to put the PHY into a reset and waits for completion. Once the reset 855 * has been accomplished, clear the PHY_RESET_DIR bit to take the PHY out 856 * of reset. 857 **/ 858 static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw) 859 { 860 u32 ctrl_ext; 861 s32 ret_val; 862 863 DEBUGFUNC("e1000_phy_hw_reset_82543"); 864 865 /* 866 * Read the Extended Device Control Register, assert the PHY_RESET_DIR 867 * bit to put the PHY into reset... 868 */ 869 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 870 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 871 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 872 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 873 E1000_WRITE_FLUSH(hw); 874 875 msec_delay(10); 876 877 /* ...then take it out of reset. */ 878 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 879 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 880 E1000_WRITE_FLUSH(hw); 881 882 usec_delay(150); 883 884 if (!(hw->phy.ops.get_cfg_done)) 885 return E1000_SUCCESS; 886 887 ret_val = hw->phy.ops.get_cfg_done(hw); 888 889 return ret_val; 890 } 891 892 /** 893 * e1000_reset_hw_82543 - Reset hardware 894 * @hw: pointer to the HW structure 895 * 896 * This resets the hardware into a known state. 897 **/ 898 static s32 e1000_reset_hw_82543(struct e1000_hw *hw) 899 { 900 u32 ctrl, icr; 901 s32 ret_val = E1000_SUCCESS; 902 903 DEBUGFUNC("e1000_reset_hw_82543"); 904 905 DEBUGOUT("Masking off all interrupts\n"); 906 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 907 908 E1000_WRITE_REG(hw, E1000_RCTL, 0); 909 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 910 E1000_WRITE_FLUSH(hw); 911 912 e1000_set_tbi_sbp_82543(hw, FALSE); 913 914 /* 915 * Delay to allow any outstanding PCI transactions to complete before 916 * resetting the device 917 */ 918 msec_delay(10); 919 920 ctrl = E1000_READ_REG(hw, E1000_CTRL); 921 922 DEBUGOUT("Issuing a global reset to 82543/82544 MAC\n"); 923 if (hw->mac.type == e1000_82543) { 924 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 925 } else { 926 /* 927 * The 82544 can't ACK the 64-bit write when issuing the 928 * reset, so use IO-mapping as a workaround. 929 */ 930 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 931 } 932 933 /* 934 * After MAC reset, force reload of NVM to restore power-on 935 * settings to device. 936 */ 937 hw->nvm.ops.reload(hw); 938 msec_delay(2); 939 940 /* Masking off and clearing any pending interrupts */ 941 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 942 icr = E1000_READ_REG(hw, E1000_ICR); 943 944 return ret_val; 945 } 946 947 /** 948 * e1000_init_hw_82543 - Initialize hardware 949 * @hw: pointer to the HW structure 950 * 951 * This inits the hardware readying it for operation. 952 **/ 953 static s32 e1000_init_hw_82543(struct e1000_hw *hw) 954 { 955 struct e1000_mac_info *mac = &hw->mac; 956 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 957 u32 ctrl; 958 s32 ret_val; 959 u16 i; 960 961 DEBUGFUNC("e1000_init_hw_82543"); 962 963 /* Disabling VLAN filtering */ 964 E1000_WRITE_REG(hw, E1000_VET, 0); 965 mac->ops.clear_vfta(hw); 966 967 /* Setup the receive address. */ 968 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 969 970 /* Zero out the Multicast HASH table */ 971 DEBUGOUT("Zeroing the MTA\n"); 972 for (i = 0; i < mac->mta_reg_count; i++) { 973 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 974 E1000_WRITE_FLUSH(hw); 975 } 976 977 /* 978 * Set the PCI priority bit correctly in the CTRL register. This 979 * determines if the adapter gives priority to receives, or if it 980 * gives equal priority to transmits and receives. 981 */ 982 if (hw->mac.type == e1000_82543 && dev_spec->dma_fairness) { 983 ctrl = E1000_READ_REG(hw, E1000_CTRL); 984 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR); 985 } 986 987 e1000_pcix_mmrbc_workaround_generic(hw); 988 989 /* Setup link and flow control */ 990 ret_val = mac->ops.setup_link(hw); 991 992 /* 993 * Clear all of the statistics registers (clear on read). It is 994 * important that we do this after we have tried to establish link 995 * because the symbol error count will increment wildly if there 996 * is no link. 997 */ 998 e1000_clear_hw_cntrs_82543(hw); 999 1000 return ret_val; 1001 } 1002 1003 /** 1004 * e1000_setup_link_82543 - Setup flow control and link settings 1005 * @hw: pointer to the HW structure 1006 * 1007 * Read the EEPROM to determine the initial polarity value and write the 1008 * extended device control register with the information before calling 1009 * the generic setup link function, which does the following: 1010 * Determines which flow control settings to use, then configures flow 1011 * control. Calls the appropriate media-specific link configuration 1012 * function. Assuming the adapter has a valid link partner, a valid link 1013 * should be established. Assumes the hardware has previously been reset 1014 * and the transmitter and receiver are not enabled. 1015 **/ 1016 static s32 e1000_setup_link_82543(struct e1000_hw *hw) 1017 { 1018 u32 ctrl_ext; 1019 s32 ret_val; 1020 u16 data; 1021 1022 DEBUGFUNC("e1000_setup_link_82543"); 1023 1024 /* 1025 * Take the 4 bits from NVM word 0xF that determine the initial 1026 * polarity value for the SW controlled pins, and setup the 1027 * Extended Device Control reg with that info. 1028 * This is needed because one of the SW controlled pins is used for 1029 * signal detection. So this should be done before phy setup. 1030 */ 1031 if (hw->mac.type == e1000_82543) { 1032 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data); 1033 if (ret_val) { 1034 DEBUGOUT("NVM Read Error\n"); 1035 ret_val = -E1000_ERR_NVM; 1036 goto out; 1037 } 1038 ctrl_ext = ((data & NVM_WORD0F_SWPDIO_EXT_MASK) << 1039 NVM_SWDPIO_EXT_SHIFT); 1040 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1041 } 1042 1043 ret_val = e1000_setup_link_generic(hw); 1044 1045 out: 1046 return ret_val; 1047 } 1048 1049 /** 1050 * e1000_setup_copper_link_82543 - Configure copper link settings 1051 * @hw: pointer to the HW structure 1052 * 1053 * Configures the link for auto-neg or forced speed and duplex. Then we check 1054 * for link, once link is established calls to configure collision distance 1055 * and flow control are called. 1056 **/ 1057 static s32 e1000_setup_copper_link_82543(struct e1000_hw *hw) 1058 { 1059 u32 ctrl; 1060 s32 ret_val; 1061 bool link; 1062 1063 DEBUGFUNC("e1000_setup_copper_link_82543"); 1064 1065 ctrl = E1000_READ_REG(hw, E1000_CTRL) | E1000_CTRL_SLU; 1066 /* 1067 * With 82543, we need to force speed and duplex on the MAC 1068 * equal to what the PHY speed and duplex configuration is. 1069 * In addition, we need to perform a hardware reset on the 1070 * PHY to take it out of reset. 1071 */ 1072 if (hw->mac.type == e1000_82543) { 1073 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1074 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1075 ret_val = hw->phy.ops.reset(hw); 1076 if (ret_val) 1077 goto out; 1078 hw->phy.reset_disable = FALSE; 1079 } else { 1080 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1081 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1082 } 1083 1084 /* Set MDI/MDI-X, Polarity Reversal, and downshift settings */ 1085 ret_val = e1000_copper_link_setup_m88(hw); 1086 if (ret_val) 1087 goto out; 1088 1089 if (hw->mac.autoneg) { 1090 /* 1091 * Setup autoneg and flow control advertisement and perform 1092 * autonegotiation. 1093 */ 1094 ret_val = e1000_copper_link_autoneg(hw); 1095 if (ret_val) 1096 goto out; 1097 } else { 1098 /* 1099 * PHY will be set to 10H, 10F, 100H or 100F 1100 * depending on user settings. 1101 */ 1102 DEBUGOUT("Forcing Speed and Duplex\n"); 1103 ret_val = e1000_phy_force_speed_duplex_82543(hw); 1104 if (ret_val) { 1105 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1106 goto out; 1107 } 1108 } 1109 1110 /* 1111 * Check link status. Wait up to 100 microseconds for link to become 1112 * valid. 1113 */ 1114 ret_val = e1000_phy_has_link_generic(hw, 1115 COPPER_LINK_UP_LIMIT, 1116 10, 1117 &link); 1118 if (ret_val) 1119 goto out; 1120 1121 1122 if (link) { 1123 DEBUGOUT("Valid link established!!!\n"); 1124 /* Config the MAC and PHY after link is up */ 1125 if (hw->mac.type == e1000_82544) { 1126 e1000_config_collision_dist_generic(hw); 1127 } else { 1128 ret_val = e1000_config_mac_to_phy_82543(hw); 1129 if (ret_val) 1130 goto out; 1131 } 1132 ret_val = e1000_config_fc_after_link_up_generic(hw); 1133 } else { 1134 DEBUGOUT("Unable to establish link!!!\n"); 1135 } 1136 1137 out: 1138 return ret_val; 1139 } 1140 1141 /** 1142 * e1000_setup_fiber_link_82543 - Setup link for fiber 1143 * @hw: pointer to the HW structure 1144 * 1145 * Configures collision distance and flow control for fiber links. Upon 1146 * successful setup, poll for link. 1147 **/ 1148 static s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw) 1149 { 1150 u32 ctrl; 1151 s32 ret_val; 1152 1153 DEBUGFUNC("e1000_setup_fiber_link_82543"); 1154 1155 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1156 1157 /* Take the link out of reset */ 1158 ctrl &= ~E1000_CTRL_LRST; 1159 1160 e1000_config_collision_dist_generic(hw); 1161 1162 ret_val = e1000_commit_fc_settings_generic(hw); 1163 if (ret_val) 1164 goto out; 1165 1166 DEBUGOUT("Auto-negotiation enabled\n"); 1167 1168 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1169 E1000_WRITE_FLUSH(hw); 1170 msec_delay(1); 1171 1172 /* 1173 * For these adapters, the SW definable pin 1 is cleared when the 1174 * optics detect a signal. If we have a signal, then poll for a 1175 * "Link-Up" indication. 1176 */ 1177 if (!(E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1178 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1179 } else { 1180 DEBUGOUT("No signal detected\n"); 1181 } 1182 1183 out: 1184 return ret_val; 1185 } 1186 1187 /** 1188 * e1000_check_for_copper_link_82543 - Check for link (Copper) 1189 * @hw: pointer to the HW structure 1190 * 1191 * Checks the phy for link, if link exists, do the following: 1192 * - check for downshift 1193 * - do polarity workaround (if necessary) 1194 * - configure collision distance 1195 * - configure flow control after link up 1196 * - configure tbi compatibility 1197 **/ 1198 static s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw) 1199 { 1200 struct e1000_mac_info *mac = &hw->mac; 1201 u32 icr, rctl; 1202 s32 ret_val; 1203 u16 speed, duplex; 1204 bool link; 1205 1206 DEBUGFUNC("e1000_check_for_copper_link_82543"); 1207 1208 if (!mac->get_link_status) { 1209 ret_val = E1000_SUCCESS; 1210 goto out; 1211 } 1212 1213 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 1214 if (ret_val) 1215 goto out; 1216 1217 if (!link) 1218 goto out; /* No link detected */ 1219 1220 mac->get_link_status = FALSE; 1221 1222 e1000_check_downshift_generic(hw); 1223 1224 /* 1225 * If we are forcing speed/duplex, then we can return since 1226 * we have already determined whether we have link or not. 1227 */ 1228 if (!mac->autoneg) { 1229 /* 1230 * If speed and duplex are forced to 10H or 10F, then we will 1231 * implement the polarity reversal workaround. We disable 1232 * interrupts first, and upon returning, place the devices 1233 * interrupt state to its previous value except for the link 1234 * status change interrupt which will happened due to the 1235 * execution of this workaround. 1236 */ 1237 if (mac->forced_speed_duplex & E1000_ALL_10_SPEED) { 1238 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 1239 ret_val = e1000_polarity_reversal_workaround_82543(hw); 1240 icr = E1000_READ_REG(hw, E1000_ICR); 1241 E1000_WRITE_REG(hw, E1000_ICS, (icr & ~E1000_ICS_LSC)); 1242 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 1243 } 1244 1245 ret_val = -E1000_ERR_CONFIG; 1246 goto out; 1247 } 1248 1249 /* 1250 * We have a M88E1000 PHY and Auto-Neg is enabled. If we 1251 * have Si on board that is 82544 or newer, Auto 1252 * Speed Detection takes care of MAC speed/duplex 1253 * configuration. So we only need to configure Collision 1254 * Distance in the MAC. Otherwise, we need to force 1255 * speed/duplex on the MAC to the current PHY speed/duplex 1256 * settings. 1257 */ 1258 if (mac->type == e1000_82544) 1259 e1000_config_collision_dist_generic(hw); 1260 else { 1261 ret_val = e1000_config_mac_to_phy_82543(hw); 1262 if (ret_val) { 1263 DEBUGOUT("Error configuring MAC to PHY settings\n"); 1264 goto out; 1265 } 1266 } 1267 1268 /* 1269 * Configure Flow Control now that Auto-Neg has completed. 1270 * First, we need to restore the desired flow control 1271 * settings because we may have had to re-autoneg with a 1272 * different link partner. 1273 */ 1274 ret_val = e1000_config_fc_after_link_up_generic(hw); 1275 if (ret_val) { 1276 DEBUGOUT("Error configuring flow control\n"); 1277 } 1278 1279 /* 1280 * At this point we know that we are on copper and we have 1281 * auto-negotiated link. These are conditions for checking the link 1282 * partner capability register. We use the link speed to determine if 1283 * TBI compatibility needs to be turned on or off. If the link is not 1284 * at gigabit speed, then TBI compatibility is not needed. If we are 1285 * at gigabit speed, we turn on TBI compatibility. 1286 */ 1287 if (e1000_tbi_compatibility_enabled_82543(hw)) { 1288 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1289 if (ret_val) { 1290 DEBUGOUT("Error getting link speed and duplex\n"); 1291 return ret_val; 1292 } 1293 if (speed != SPEED_1000) { 1294 /* 1295 * If link speed is not set to gigabit speed, 1296 * we do not need to enable TBI compatibility. 1297 */ 1298 if (e1000_tbi_sbp_enabled_82543(hw)) { 1299 /* 1300 * If we previously were in the mode, 1301 * turn it off. 1302 */ 1303 e1000_set_tbi_sbp_82543(hw, FALSE); 1304 rctl = E1000_READ_REG(hw, E1000_RCTL); 1305 rctl &= ~E1000_RCTL_SBP; 1306 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1307 } 1308 } else { 1309 /* 1310 * If TBI compatibility is was previously off, 1311 * turn it on. For compatibility with a TBI link 1312 * partner, we will store bad packets. Some 1313 * frames have an additional byte on the end and 1314 * will look like CRC errors to to the hardware. 1315 */ 1316 if (!e1000_tbi_sbp_enabled_82543(hw)) { 1317 e1000_set_tbi_sbp_82543(hw, TRUE); 1318 rctl = E1000_READ_REG(hw, E1000_RCTL); 1319 rctl |= E1000_RCTL_SBP; 1320 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1321 } 1322 } 1323 } 1324 out: 1325 return ret_val; 1326 } 1327 1328 /** 1329 * e1000_check_for_fiber_link_82543 - Check for link (Fiber) 1330 * @hw: pointer to the HW structure 1331 * 1332 * Checks for link up on the hardware. If link is not up and we have 1333 * a signal, then we need to force link up. 1334 **/ 1335 static s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw) 1336 { 1337 struct e1000_mac_info *mac = &hw->mac; 1338 u32 rxcw, ctrl, status; 1339 s32 ret_val = E1000_SUCCESS; 1340 1341 DEBUGFUNC("e1000_check_for_fiber_link_82543"); 1342 1343 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1344 status = E1000_READ_REG(hw, E1000_STATUS); 1345 rxcw = E1000_READ_REG(hw, E1000_RXCW); 1346 1347 /* 1348 * If we don't have link (auto-negotiation failed or link partner 1349 * cannot auto-negotiate), the cable is plugged in (we have signal), 1350 * and our link partner is not trying to auto-negotiate with us (we 1351 * are receiving idles or data), we need to force link up. We also 1352 * need to give auto-negotiation time to complete, in case the cable 1353 * was just plugged in. The autoneg_failed flag does this. 1354 */ 1355 /* (ctrl & E1000_CTRL_SWDPIN1) == 0 == have signal */ 1356 if ((!(ctrl & E1000_CTRL_SWDPIN1)) && 1357 (!(status & E1000_STATUS_LU)) && 1358 (!(rxcw & E1000_RXCW_C))) { 1359 if (mac->autoneg_failed == 0) { 1360 mac->autoneg_failed = 1; 1361 ret_val = 0; 1362 goto out; 1363 } 1364 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 1365 1366 /* Disable auto-negotiation in the TXCW register */ 1367 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 1368 1369 /* Force link-up and also force full-duplex. */ 1370 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1371 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 1372 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1373 1374 /* Configure Flow Control after forcing link up. */ 1375 ret_val = e1000_config_fc_after_link_up_generic(hw); 1376 if (ret_val) { 1377 DEBUGOUT("Error configuring flow control\n"); 1378 goto out; 1379 } 1380 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 1381 /* 1382 * If we are forcing link and we are receiving /C/ ordered 1383 * sets, re-enable auto-negotiation in the TXCW register 1384 * and disable forced link in the Device Control register 1385 * in an attempt to auto-negotiate with our link partner. 1386 */ 1387 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 1388 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1389 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 1390 1391 mac->serdes_has_link = TRUE; 1392 } 1393 1394 out: 1395 return ret_val; 1396 } 1397 1398 /** 1399 * e1000_config_mac_to_phy_82543 - Configure MAC to PHY settings 1400 * @hw: pointer to the HW structure 1401 * 1402 * For the 82543 silicon, we need to set the MAC to match the settings 1403 * of the PHY, even if the PHY is auto-negotiating. 1404 **/ 1405 static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw) 1406 { 1407 u32 ctrl; 1408 s32 ret_val = E1000_SUCCESS; 1409 u16 phy_data; 1410 1411 DEBUGFUNC("e1000_config_mac_to_phy_82543"); 1412 1413 if (!(hw->phy.ops.read_reg)) 1414 goto out; 1415 1416 /* Set the bits to force speed and duplex */ 1417 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1418 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1419 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 1420 1421 /* 1422 * Set up duplex in the Device Control and Transmit Control 1423 * registers depending on negotiated values. 1424 */ 1425 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1426 if (ret_val) 1427 goto out; 1428 1429 ctrl &= ~E1000_CTRL_FD; 1430 if (phy_data & M88E1000_PSSR_DPLX) 1431 ctrl |= E1000_CTRL_FD; 1432 1433 e1000_config_collision_dist_generic(hw); 1434 1435 /* 1436 * Set up speed in the Device Control register depending on 1437 * negotiated values. 1438 */ 1439 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 1440 ctrl |= E1000_CTRL_SPD_1000; 1441 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 1442 ctrl |= E1000_CTRL_SPD_100; 1443 1444 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1445 1446 out: 1447 return ret_val; 1448 } 1449 1450 /** 1451 * e1000_write_vfta_82543 - Write value to VLAN filter table 1452 * @hw: pointer to the HW structure 1453 * @offset: the 32-bit offset in which to write the value to. 1454 * @value: the 32-bit value to write at location offset. 1455 * 1456 * This writes a 32-bit value to a 32-bit offset in the VLAN filter 1457 * table. 1458 **/ 1459 static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, u32 value) 1460 { 1461 u32 temp; 1462 1463 DEBUGFUNC("e1000_write_vfta_82543"); 1464 1465 if ((hw->mac.type == e1000_82544) && (offset & 1)) { 1466 temp = E1000_READ_REG_ARRAY(hw, E1000_VFTA, offset - 1); 1467 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 1468 E1000_WRITE_FLUSH(hw); 1469 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset - 1, temp); 1470 E1000_WRITE_FLUSH(hw); 1471 } else { 1472 e1000_write_vfta_generic(hw, offset, value); 1473 } 1474 } 1475 1476 /** 1477 * e1000_led_on_82543 - Turn on SW controllable LED 1478 * @hw: pointer to the HW structure 1479 * 1480 * Turns the SW defined LED on. 1481 **/ 1482 static s32 e1000_led_on_82543(struct e1000_hw *hw) 1483 { 1484 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1485 1486 DEBUGFUNC("e1000_led_on_82543"); 1487 1488 if (hw->mac.type == e1000_82544 && 1489 hw->phy.media_type == e1000_media_type_copper) { 1490 /* Clear SW-definable Pin 0 to turn on the LED */ 1491 ctrl &= ~E1000_CTRL_SWDPIN0; 1492 ctrl |= E1000_CTRL_SWDPIO0; 1493 } else { 1494 /* Fiber 82544 and all 82543 use this method */ 1495 ctrl |= E1000_CTRL_SWDPIN0; 1496 ctrl |= E1000_CTRL_SWDPIO0; 1497 } 1498 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1499 1500 return E1000_SUCCESS; 1501 } 1502 1503 /** 1504 * e1000_led_off_82543 - Turn off SW controllable LED 1505 * @hw: pointer to the HW structure 1506 * 1507 * Turns the SW defined LED off. 1508 **/ 1509 static s32 e1000_led_off_82543(struct e1000_hw *hw) 1510 { 1511 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1512 1513 DEBUGFUNC("e1000_led_off_82543"); 1514 1515 if (hw->mac.type == e1000_82544 && 1516 hw->phy.media_type == e1000_media_type_copper) { 1517 /* Set SW-definable Pin 0 to turn off the LED */ 1518 ctrl |= E1000_CTRL_SWDPIN0; 1519 ctrl |= E1000_CTRL_SWDPIO0; 1520 } else { 1521 ctrl &= ~E1000_CTRL_SWDPIN0; 1522 ctrl |= E1000_CTRL_SWDPIO0; 1523 } 1524 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1525 1526 return E1000_SUCCESS; 1527 } 1528 1529 /** 1530 * e1000_clear_hw_cntrs_82543 - Clear device specific hardware counters 1531 * @hw: pointer to the HW structure 1532 * 1533 * Clears the hardware counters by reading the counter registers. 1534 **/ 1535 static void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw) 1536 { 1537 DEBUGFUNC("e1000_clear_hw_cntrs_82543"); 1538 1539 e1000_clear_hw_cntrs_base_generic(hw); 1540 1541 E1000_READ_REG(hw, E1000_PRC64); 1542 E1000_READ_REG(hw, E1000_PRC127); 1543 E1000_READ_REG(hw, E1000_PRC255); 1544 E1000_READ_REG(hw, E1000_PRC511); 1545 E1000_READ_REG(hw, E1000_PRC1023); 1546 E1000_READ_REG(hw, E1000_PRC1522); 1547 E1000_READ_REG(hw, E1000_PTC64); 1548 E1000_READ_REG(hw, E1000_PTC127); 1549 E1000_READ_REG(hw, E1000_PTC255); 1550 E1000_READ_REG(hw, E1000_PTC511); 1551 E1000_READ_REG(hw, E1000_PTC1023); 1552 E1000_READ_REG(hw, E1000_PTC1522); 1553 1554 E1000_READ_REG(hw, E1000_ALGNERRC); 1555 E1000_READ_REG(hw, E1000_RXERRC); 1556 E1000_READ_REG(hw, E1000_TNCRS); 1557 E1000_READ_REG(hw, E1000_CEXTERR); 1558 E1000_READ_REG(hw, E1000_TSCTC); 1559 E1000_READ_REG(hw, E1000_TSCTFC); 1560 } 1561