1 /****************************************************************************** 2 3 Copyright (c) 2001-2019, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 /* 36 * 82543GC Gigabit Ethernet Controller (Fiber) 37 * 82543GC Gigabit Ethernet Controller (Copper) 38 * 82544EI Gigabit Ethernet Controller (Copper) 39 * 82544EI Gigabit Ethernet Controller (Fiber) 40 * 82544GC Gigabit Ethernet Controller (Copper) 41 * 82544GC Gigabit Ethernet Controller (LOM) 42 */ 43 44 #include "e1000_api.h" 45 46 static s32 e1000_init_phy_params_82543(struct e1000_hw *hw); 47 static s32 e1000_init_nvm_params_82543(struct e1000_hw *hw); 48 static s32 e1000_init_mac_params_82543(struct e1000_hw *hw); 49 static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, 50 u16 *data); 51 static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, 52 u16 data); 53 static s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw); 54 static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw); 55 static s32 e1000_reset_hw_82543(struct e1000_hw *hw); 56 static s32 e1000_init_hw_82543(struct e1000_hw *hw); 57 static s32 e1000_setup_link_82543(struct e1000_hw *hw); 58 static s32 e1000_setup_copper_link_82543(struct e1000_hw *hw); 59 static s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw); 60 static s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw); 61 static s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw); 62 static s32 e1000_led_on_82543(struct e1000_hw *hw); 63 static s32 e1000_led_off_82543(struct e1000_hw *hw); 64 static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, 65 u32 value); 66 static void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw); 67 static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw); 68 static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw); 69 static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl); 70 static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw); 71 static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl); 72 static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw); 73 static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data, 74 u16 count); 75 static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw); 76 static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state); 77 78 /** 79 * e1000_init_phy_params_82543 - Init PHY func ptrs. 80 * @hw: pointer to the HW structure 81 **/ 82 static s32 e1000_init_phy_params_82543(struct e1000_hw *hw) 83 { 84 struct e1000_phy_info *phy = &hw->phy; 85 s32 ret_val = E1000_SUCCESS; 86 87 DEBUGFUNC("e1000_init_phy_params_82543"); 88 89 if (hw->phy.media_type != e1000_media_type_copper) { 90 phy->type = e1000_phy_none; 91 goto out; 92 } else { 93 phy->ops.power_up = e1000_power_up_phy_copper; 94 phy->ops.power_down = e1000_power_down_phy_copper; 95 } 96 97 phy->addr = 1; 98 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 99 phy->reset_delay_us = 10000; 100 phy->type = e1000_phy_m88; 101 102 /* Function Pointers */ 103 phy->ops.check_polarity = e1000_check_polarity_m88; 104 phy->ops.commit = e1000_phy_sw_reset_generic; 105 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82543; 106 phy->ops.get_cable_length = e1000_get_cable_length_m88; 107 phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 108 phy->ops.read_reg = (hw->mac.type == e1000_82543) 109 ? e1000_read_phy_reg_82543 110 : e1000_read_phy_reg_m88; 111 phy->ops.reset = (hw->mac.type == e1000_82543) 112 ? e1000_phy_hw_reset_82543 113 : e1000_phy_hw_reset_generic; 114 phy->ops.write_reg = (hw->mac.type == e1000_82543) 115 ? e1000_write_phy_reg_82543 116 : e1000_write_phy_reg_m88; 117 phy->ops.get_info = e1000_get_phy_info_m88; 118 119 /* 120 * The external PHY of the 82543 can be in a funky state. 121 * Resetting helps us read the PHY registers for acquiring 122 * the PHY ID. 123 */ 124 if (!e1000_init_phy_disabled_82543(hw)) { 125 ret_val = phy->ops.reset(hw); 126 if (ret_val) { 127 DEBUGOUT("Resetting PHY during init failed.\n"); 128 goto out; 129 } 130 msec_delay(20); 131 } 132 133 ret_val = e1000_get_phy_id(hw); 134 if (ret_val) 135 goto out; 136 137 /* Verify phy id */ 138 switch (hw->mac.type) { 139 case e1000_82543: 140 if (phy->id != M88E1000_E_PHY_ID) { 141 ret_val = -E1000_ERR_PHY; 142 goto out; 143 } 144 break; 145 case e1000_82544: 146 if (phy->id != M88E1000_I_PHY_ID) { 147 ret_val = -E1000_ERR_PHY; 148 goto out; 149 } 150 break; 151 default: 152 ret_val = -E1000_ERR_PHY; 153 goto out; 154 break; 155 } 156 157 out: 158 return ret_val; 159 } 160 161 /** 162 * e1000_init_nvm_params_82543 - Init NVM func ptrs. 163 * @hw: pointer to the HW structure 164 **/ 165 static s32 e1000_init_nvm_params_82543(struct e1000_hw *hw) 166 { 167 struct e1000_nvm_info *nvm = &hw->nvm; 168 169 DEBUGFUNC("e1000_init_nvm_params_82543"); 170 171 nvm->type = e1000_nvm_eeprom_microwire; 172 nvm->word_size = 64; 173 nvm->delay_usec = 50; 174 nvm->address_bits = 6; 175 nvm->opcode_bits = 3; 176 177 /* Function Pointers */ 178 nvm->ops.read = e1000_read_nvm_microwire; 179 nvm->ops.update = e1000_update_nvm_checksum_generic; 180 nvm->ops.valid_led_default = e1000_valid_led_default_generic; 181 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 182 nvm->ops.write = e1000_write_nvm_microwire; 183 184 return E1000_SUCCESS; 185 } 186 187 /** 188 * e1000_init_mac_params_82543 - Init MAC func ptrs. 189 * @hw: pointer to the HW structure 190 **/ 191 static s32 e1000_init_mac_params_82543(struct e1000_hw *hw) 192 { 193 struct e1000_mac_info *mac = &hw->mac; 194 195 DEBUGFUNC("e1000_init_mac_params_82543"); 196 197 /* Set media type */ 198 switch (hw->device_id) { 199 case E1000_DEV_ID_82543GC_FIBER: 200 case E1000_DEV_ID_82544EI_FIBER: 201 hw->phy.media_type = e1000_media_type_fiber; 202 break; 203 default: 204 hw->phy.media_type = e1000_media_type_copper; 205 break; 206 } 207 208 /* Set mta register count */ 209 mac->mta_reg_count = 128; 210 /* Set rar entry count */ 211 mac->rar_entry_count = E1000_RAR_ENTRIES; 212 213 /* Function pointers */ 214 215 /* bus type/speed/width */ 216 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic; 217 /* function id */ 218 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci; 219 /* reset */ 220 mac->ops.reset_hw = e1000_reset_hw_82543; 221 /* hw initialization */ 222 mac->ops.init_hw = e1000_init_hw_82543; 223 /* link setup */ 224 mac->ops.setup_link = e1000_setup_link_82543; 225 /* physical interface setup */ 226 mac->ops.setup_physical_interface = 227 (hw->phy.media_type == e1000_media_type_copper) 228 ? e1000_setup_copper_link_82543 : e1000_setup_fiber_link_82543; 229 /* check for link */ 230 mac->ops.check_for_link = 231 (hw->phy.media_type == e1000_media_type_copper) 232 ? e1000_check_for_copper_link_82543 233 : e1000_check_for_fiber_link_82543; 234 /* link info */ 235 mac->ops.get_link_up_info = 236 (hw->phy.media_type == e1000_media_type_copper) 237 ? e1000_get_speed_and_duplex_copper_generic 238 : e1000_get_speed_and_duplex_fiber_serdes_generic; 239 /* multicast address update */ 240 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 241 /* writing VFTA */ 242 mac->ops.write_vfta = e1000_write_vfta_82543; 243 /* clearing VFTA */ 244 mac->ops.clear_vfta = e1000_clear_vfta_generic; 245 /* turn on/off LED */ 246 mac->ops.led_on = e1000_led_on_82543; 247 mac->ops.led_off = e1000_led_off_82543; 248 /* clear hardware counters */ 249 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82543; 250 251 /* Set tbi compatibility */ 252 if ((hw->mac.type != e1000_82543) || 253 (hw->phy.media_type == e1000_media_type_fiber)) 254 e1000_set_tbi_compatibility_82543(hw, FALSE); 255 256 return E1000_SUCCESS; 257 } 258 259 /** 260 * e1000_init_function_pointers_82543 - Init func ptrs. 261 * @hw: pointer to the HW structure 262 * 263 * Called to initialize all function pointers and parameters. 264 **/ 265 void e1000_init_function_pointers_82543(struct e1000_hw *hw) 266 { 267 DEBUGFUNC("e1000_init_function_pointers_82543"); 268 269 hw->mac.ops.init_params = e1000_init_mac_params_82543; 270 hw->nvm.ops.init_params = e1000_init_nvm_params_82543; 271 hw->phy.ops.init_params = e1000_init_phy_params_82543; 272 } 273 274 /** 275 * e1000_tbi_compatibility_enabled_82543 - Returns TBI compat status 276 * @hw: pointer to the HW structure 277 * 278 * Returns the current status of 10-bit Interface (TBI) compatibility 279 * (enabled/disabled). 280 **/ 281 static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw) 282 { 283 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 284 bool state = FALSE; 285 286 DEBUGFUNC("e1000_tbi_compatibility_enabled_82543"); 287 288 if (hw->mac.type != e1000_82543) { 289 DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 290 goto out; 291 } 292 293 state = !!(dev_spec->tbi_compatibility & TBI_COMPAT_ENABLED); 294 295 out: 296 return state; 297 } 298 299 /** 300 * e1000_set_tbi_compatibility_82543 - Set TBI compatibility 301 * @hw: pointer to the HW structure 302 * @state: enable/disable TBI compatibility 303 * 304 * Enables or disabled 10-bit Interface (TBI) compatibility. 305 **/ 306 void e1000_set_tbi_compatibility_82543(struct e1000_hw *hw, bool state) 307 { 308 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 309 310 DEBUGFUNC("e1000_set_tbi_compatibility_82543"); 311 312 if (hw->mac.type != e1000_82543) { 313 DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 314 goto out; 315 } 316 317 if (state) 318 dev_spec->tbi_compatibility |= TBI_COMPAT_ENABLED; 319 else 320 dev_spec->tbi_compatibility &= ~TBI_COMPAT_ENABLED; 321 322 out: 323 return; 324 } 325 326 /** 327 * e1000_tbi_sbp_enabled_82543 - Returns TBI SBP status 328 * @hw: pointer to the HW structure 329 * 330 * Returns the current status of 10-bit Interface (TBI) store bad packet (SBP) 331 * (enabled/disabled). 332 **/ 333 bool e1000_tbi_sbp_enabled_82543(struct e1000_hw *hw) 334 { 335 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 336 bool state = FALSE; 337 338 DEBUGFUNC("e1000_tbi_sbp_enabled_82543"); 339 340 if (hw->mac.type != e1000_82543) { 341 DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 342 goto out; 343 } 344 345 state = !!(dev_spec->tbi_compatibility & TBI_SBP_ENABLED); 346 347 out: 348 return state; 349 } 350 351 /** 352 * e1000_set_tbi_sbp_82543 - Set TBI SBP 353 * @hw: pointer to the HW structure 354 * @state: enable/disable TBI store bad packet 355 * 356 * Enables or disabled 10-bit Interface (TBI) store bad packet (SBP). 357 **/ 358 static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state) 359 { 360 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 361 362 DEBUGFUNC("e1000_set_tbi_sbp_82543"); 363 364 if (state && e1000_tbi_compatibility_enabled_82543(hw)) 365 dev_spec->tbi_compatibility |= TBI_SBP_ENABLED; 366 else 367 dev_spec->tbi_compatibility &= ~TBI_SBP_ENABLED; 368 369 return; 370 } 371 372 /** 373 * e1000_init_phy_disabled_82543 - Returns init PHY status 374 * @hw: pointer to the HW structure 375 * 376 * Returns the current status of whether PHY initialization is disabled. 377 * True if PHY initialization is disabled else FALSE. 378 **/ 379 static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw) 380 { 381 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 382 bool ret_val; 383 384 DEBUGFUNC("e1000_init_phy_disabled_82543"); 385 386 if (hw->mac.type != e1000_82543) { 387 ret_val = FALSE; 388 goto out; 389 } 390 391 ret_val = dev_spec->init_phy_disabled; 392 393 out: 394 return ret_val; 395 } 396 397 /** 398 * e1000_tbi_adjust_stats_82543 - Adjust stats when TBI enabled 399 * @hw: pointer to the HW structure 400 * @stats: Struct containing statistic register values 401 * @frame_len: The length of the frame in question 402 * @mac_addr: The Ethernet destination address of the frame in question 403 * @max_frame_size: The maximum frame size 404 * 405 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT 406 **/ 407 void e1000_tbi_adjust_stats_82543(struct e1000_hw *hw, 408 struct e1000_hw_stats *stats, u32 frame_len, 409 u8 *mac_addr, u32 max_frame_size) 410 { 411 if (!(e1000_tbi_sbp_enabled_82543(hw))) 412 goto out; 413 414 /* First adjust the frame length. */ 415 frame_len--; 416 /* 417 * We need to adjust the statistics counters, since the hardware 418 * counters overcount this packet as a CRC error and undercount 419 * the packet as a good packet 420 */ 421 /* This packet should not be counted as a CRC error. */ 422 stats->crcerrs--; 423 /* This packet does count as a Good Packet Received. */ 424 stats->gprc++; 425 426 /* Adjust the Good Octets received counters */ 427 stats->gorc += frame_len; 428 429 /* 430 * Is this a broadcast or multicast? Check broadcast first, 431 * since the test for a multicast frame will test positive on 432 * a broadcast frame. 433 */ 434 if ((mac_addr[0] == 0xff) && (mac_addr[1] == 0xff)) 435 /* Broadcast packet */ 436 stats->bprc++; 437 else if (*mac_addr & 0x01) 438 /* Multicast packet */ 439 stats->mprc++; 440 441 /* 442 * In this case, the hardware has over counted the number of 443 * oversize frames. 444 */ 445 if ((frame_len == max_frame_size) && (stats->roc > 0)) 446 stats->roc--; 447 448 /* 449 * Adjust the bin counters when the extra byte put the frame in the 450 * wrong bin. Remember that the frame_len was adjusted above. 451 */ 452 if (frame_len == 64) { 453 stats->prc64++; 454 stats->prc127--; 455 } else if (frame_len == 127) { 456 stats->prc127++; 457 stats->prc255--; 458 } else if (frame_len == 255) { 459 stats->prc255++; 460 stats->prc511--; 461 } else if (frame_len == 511) { 462 stats->prc511++; 463 stats->prc1023--; 464 } else if (frame_len == 1023) { 465 stats->prc1023++; 466 stats->prc1522--; 467 } else if (frame_len == 1522) { 468 stats->prc1522++; 469 } 470 471 out: 472 return; 473 } 474 475 /** 476 * e1000_read_phy_reg_82543 - Read PHY register 477 * @hw: pointer to the HW structure 478 * @offset: register offset to be read 479 * @data: pointer to the read data 480 * 481 * Reads the PHY at offset and stores the information read to data. 482 **/ 483 static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 *data) 484 { 485 u32 mdic; 486 s32 ret_val = E1000_SUCCESS; 487 488 DEBUGFUNC("e1000_read_phy_reg_82543"); 489 490 if (offset > MAX_PHY_REG_ADDRESS) { 491 DEBUGOUT1("PHY Address %d is out of range\n", offset); 492 ret_val = -E1000_ERR_PARAM; 493 goto out; 494 } 495 496 /* 497 * We must first send a preamble through the MDIO pin to signal the 498 * beginning of an MII instruction. This is done by sending 32 499 * consecutive "1" bits. 500 */ 501 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 502 503 /* 504 * Now combine the next few fields that are required for a read 505 * operation. We use this method instead of calling the 506 * e1000_shift_out_mdi_bits routine five different times. The format 507 * of an MII read instruction consists of a shift out of 14 bits and 508 * is defined as follows: 509 * <Preamble><SOF><Op Code><Phy Addr><Offset> 510 * followed by a shift in of 18 bits. This first two bits shifted in 511 * are TurnAround bits used to avoid contention on the MDIO pin when a 512 * READ operation is performed. These two bits are thrown away 513 * followed by a shift in of 16 bits which contains the desired data. 514 */ 515 mdic = (offset | (hw->phy.addr << 5) | 516 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 517 518 e1000_shift_out_mdi_bits_82543(hw, mdic, 14); 519 520 /* 521 * Now that we've shifted out the read command to the MII, we need to 522 * "shift in" the 16-bit value (18 total bits) of the requested PHY 523 * register address. 524 */ 525 *data = e1000_shift_in_mdi_bits_82543(hw); 526 527 out: 528 return ret_val; 529 } 530 531 /** 532 * e1000_write_phy_reg_82543 - Write PHY register 533 * @hw: pointer to the HW structure 534 * @offset: register offset to be written 535 * @data: pointer to the data to be written at offset 536 * 537 * Writes data to the PHY at offset. 538 **/ 539 static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 data) 540 { 541 u32 mdic; 542 s32 ret_val = E1000_SUCCESS; 543 544 DEBUGFUNC("e1000_write_phy_reg_82543"); 545 546 if (offset > MAX_PHY_REG_ADDRESS) { 547 DEBUGOUT1("PHY Address %d is out of range\n", offset); 548 ret_val = -E1000_ERR_PARAM; 549 goto out; 550 } 551 552 /* 553 * We'll need to use the SW defined pins to shift the write command 554 * out to the PHY. We first send a preamble to the PHY to signal the 555 * beginning of the MII instruction. This is done by sending 32 556 * consecutive "1" bits. 557 */ 558 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 559 560 /* 561 * Now combine the remaining required fields that will indicate a 562 * write operation. We use this method instead of calling the 563 * e1000_shift_out_mdi_bits routine for each field in the command. The 564 * format of a MII write instruction is as follows: 565 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 566 */ 567 mdic = ((PHY_TURNAROUND) | (offset << 2) | (hw->phy.addr << 7) | 568 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 569 mdic <<= 16; 570 mdic |= (u32)data; 571 572 e1000_shift_out_mdi_bits_82543(hw, mdic, 32); 573 574 out: 575 return ret_val; 576 } 577 578 /** 579 * e1000_raise_mdi_clk_82543 - Raise Management Data Input clock 580 * @hw: pointer to the HW structure 581 * @ctrl: pointer to the control register 582 * 583 * Raise the management data input clock by setting the MDC bit in the control 584 * register. 585 **/ 586 static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl) 587 { 588 /* 589 * Raise the clock input to the Management Data Clock (by setting the 590 * MDC bit), and then delay a sufficient amount of time. 591 */ 592 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl | E1000_CTRL_MDC)); 593 E1000_WRITE_FLUSH(hw); 594 usec_delay(10); 595 } 596 597 /** 598 * e1000_lower_mdi_clk_82543 - Lower Management Data Input clock 599 * @hw: pointer to the HW structure 600 * @ctrl: pointer to the control register 601 * 602 * Lower the management data input clock by clearing the MDC bit in the 603 * control register. 604 **/ 605 static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl) 606 { 607 /* 608 * Lower the clock input to the Management Data Clock (by clearing the 609 * MDC bit), and then delay a sufficient amount of time. 610 */ 611 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl & ~E1000_CTRL_MDC)); 612 E1000_WRITE_FLUSH(hw); 613 usec_delay(10); 614 } 615 616 /** 617 * e1000_shift_out_mdi_bits_82543 - Shift data bits our to the PHY 618 * @hw: pointer to the HW structure 619 * @data: data to send to the PHY 620 * @count: number of bits to shift out 621 * 622 * We need to shift 'count' bits out to the PHY. So, the value in the 623 * "data" parameter will be shifted out to the PHY one bit at a time. 624 * In order to do this, "data" must be broken down into bits. 625 **/ 626 static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data, 627 u16 count) 628 { 629 u32 ctrl, mask; 630 631 /* 632 * We need to shift "count" number of bits out to the PHY. So, the 633 * value in the "data" parameter will be shifted out to the PHY one 634 * bit at a time. In order to do this, "data" must be broken down 635 * into bits. 636 */ 637 mask = 0x01; 638 mask <<= (count - 1); 639 640 ctrl = E1000_READ_REG(hw, E1000_CTRL); 641 642 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 643 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 644 645 while (mask) { 646 /* 647 * A "1" is shifted out to the PHY by setting the MDIO bit to 648 * "1" and then raising and lowering the Management Data Clock. 649 * A "0" is shifted out to the PHY by setting the MDIO bit to 650 * "0" and then raising and lowering the clock. 651 */ 652 if (data & mask) 653 ctrl |= E1000_CTRL_MDIO; 654 else 655 ctrl &= ~E1000_CTRL_MDIO; 656 657 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 658 E1000_WRITE_FLUSH(hw); 659 660 usec_delay(10); 661 662 e1000_raise_mdi_clk_82543(hw, &ctrl); 663 e1000_lower_mdi_clk_82543(hw, &ctrl); 664 665 mask >>= 1; 666 } 667 } 668 669 /** 670 * e1000_shift_in_mdi_bits_82543 - Shift data bits in from the PHY 671 * @hw: pointer to the HW structure 672 * 673 * In order to read a register from the PHY, we need to shift 18 bits 674 * in from the PHY. Bits are "shifted in" by raising the clock input to 675 * the PHY (setting the MDC bit), and then reading the value of the data out 676 * MDIO bit. 677 **/ 678 static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw) 679 { 680 u32 ctrl; 681 u16 data = 0; 682 u8 i; 683 684 /* 685 * In order to read a register from the PHY, we need to shift in a 686 * total of 18 bits from the PHY. The first two bit (turnaround) 687 * times are used to avoid contention on the MDIO pin when a read 688 * operation is performed. These two bits are ignored by us and 689 * thrown away. Bits are "shifted in" by raising the input to the 690 * Management Data Clock (setting the MDC bit) and then reading the 691 * value of the MDIO bit. 692 */ 693 ctrl = E1000_READ_REG(hw, E1000_CTRL); 694 695 /* 696 * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as 697 * input. 698 */ 699 ctrl &= ~E1000_CTRL_MDIO_DIR; 700 ctrl &= ~E1000_CTRL_MDIO; 701 702 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 703 E1000_WRITE_FLUSH(hw); 704 705 /* 706 * Raise and lower the clock before reading in the data. This accounts 707 * for the turnaround bits. The first clock occurred when we clocked 708 * out the last bit of the Register Address. 709 */ 710 e1000_raise_mdi_clk_82543(hw, &ctrl); 711 e1000_lower_mdi_clk_82543(hw, &ctrl); 712 713 for (data = 0, i = 0; i < 16; i++) { 714 data <<= 1; 715 e1000_raise_mdi_clk_82543(hw, &ctrl); 716 ctrl = E1000_READ_REG(hw, E1000_CTRL); 717 /* Check to see if we shifted in a "1". */ 718 if (ctrl & E1000_CTRL_MDIO) 719 data |= 1; 720 e1000_lower_mdi_clk_82543(hw, &ctrl); 721 } 722 723 e1000_raise_mdi_clk_82543(hw, &ctrl); 724 e1000_lower_mdi_clk_82543(hw, &ctrl); 725 726 return data; 727 } 728 729 /** 730 * e1000_phy_force_speed_duplex_82543 - Force speed/duplex for PHY 731 * @hw: pointer to the HW structure 732 * 733 * Calls the function to force speed and duplex for the m88 PHY, and 734 * if the PHY is not auto-negotiating and the speed is forced to 10Mbit, 735 * then call the function for polarity reversal workaround. 736 **/ 737 static s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw) 738 { 739 s32 ret_val; 740 741 DEBUGFUNC("e1000_phy_force_speed_duplex_82543"); 742 743 ret_val = e1000_phy_force_speed_duplex_m88(hw); 744 if (ret_val) 745 goto out; 746 747 if (!hw->mac.autoneg && (hw->mac.forced_speed_duplex & 748 E1000_ALL_10_SPEED)) 749 ret_val = e1000_polarity_reversal_workaround_82543(hw); 750 751 out: 752 return ret_val; 753 } 754 755 /** 756 * e1000_polarity_reversal_workaround_82543 - Workaround polarity reversal 757 * @hw: pointer to the HW structure 758 * 759 * When forcing link to 10 Full or 10 Half, the PHY can reverse the polarity 760 * inadvertently. To workaround the issue, we disable the transmitter on 761 * the PHY until we have established the link partner's link parameters. 762 **/ 763 static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw) 764 { 765 s32 ret_val = E1000_SUCCESS; 766 u16 mii_status_reg; 767 u16 i; 768 bool link; 769 770 if (!(hw->phy.ops.write_reg)) 771 goto out; 772 773 /* Polarity reversal workaround for forced 10F/10H links. */ 774 775 /* Disable the transmitter on the PHY */ 776 777 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 778 if (ret_val) 779 goto out; 780 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 781 if (ret_val) 782 goto out; 783 784 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 785 if (ret_val) 786 goto out; 787 788 /* 789 * This loop will early-out if the NO link condition has been met. 790 * In other words, DO NOT use e1000_phy_has_link_generic() here. 791 */ 792 for (i = PHY_FORCE_TIME; i > 0; i--) { 793 /* 794 * Read the MII Status Register and wait for Link Status bit 795 * to be clear. 796 */ 797 798 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 799 if (ret_val) 800 goto out; 801 802 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 803 if (ret_val) 804 goto out; 805 806 if (!(mii_status_reg & ~MII_SR_LINK_STATUS)) 807 break; 808 msec_delay_irq(100); 809 } 810 811 /* Recommended delay time after link has been lost */ 812 msec_delay_irq(1000); 813 814 /* Now we will re-enable the transmitter on the PHY */ 815 816 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 817 if (ret_val) 818 goto out; 819 msec_delay_irq(50); 820 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 821 if (ret_val) 822 goto out; 823 msec_delay_irq(50); 824 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 825 if (ret_val) 826 goto out; 827 msec_delay_irq(50); 828 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 829 if (ret_val) 830 goto out; 831 832 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 833 if (ret_val) 834 goto out; 835 836 /* 837 * Read the MII Status Register and wait for Link Status bit 838 * to be set. 839 */ 840 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_TIME, 100000, &link); 841 if (ret_val) 842 goto out; 843 844 out: 845 return ret_val; 846 } 847 848 /** 849 * e1000_phy_hw_reset_82543 - PHY hardware reset 850 * @hw: pointer to the HW structure 851 * 852 * Sets the PHY_RESET_DIR bit in the extended device control register 853 * to put the PHY into a reset and waits for completion. Once the reset 854 * has been accomplished, clear the PHY_RESET_DIR bit to take the PHY out 855 * of reset. 856 **/ 857 static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw) 858 { 859 u32 ctrl_ext; 860 s32 ret_val; 861 862 DEBUGFUNC("e1000_phy_hw_reset_82543"); 863 864 /* 865 * Read the Extended Device Control Register, assert the PHY_RESET_DIR 866 * bit to put the PHY into reset... 867 */ 868 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 869 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 870 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 871 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 872 E1000_WRITE_FLUSH(hw); 873 874 msec_delay(10); 875 876 /* ...then take it out of reset. */ 877 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 878 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 879 E1000_WRITE_FLUSH(hw); 880 881 usec_delay(150); 882 883 if (!(hw->phy.ops.get_cfg_done)) 884 return E1000_SUCCESS; 885 886 ret_val = hw->phy.ops.get_cfg_done(hw); 887 888 return ret_val; 889 } 890 891 /** 892 * e1000_reset_hw_82543 - Reset hardware 893 * @hw: pointer to the HW structure 894 * 895 * This resets the hardware into a known state. 896 **/ 897 static s32 e1000_reset_hw_82543(struct e1000_hw *hw) 898 { 899 u32 ctrl; 900 s32 ret_val = E1000_SUCCESS; 901 902 DEBUGFUNC("e1000_reset_hw_82543"); 903 904 DEBUGOUT("Masking off all interrupts\n"); 905 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 906 907 E1000_WRITE_REG(hw, E1000_RCTL, 0); 908 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 909 E1000_WRITE_FLUSH(hw); 910 911 e1000_set_tbi_sbp_82543(hw, FALSE); 912 913 /* 914 * Delay to allow any outstanding PCI transactions to complete before 915 * resetting the device 916 */ 917 msec_delay(10); 918 919 ctrl = E1000_READ_REG(hw, E1000_CTRL); 920 921 DEBUGOUT("Issuing a global reset to 82543/82544 MAC\n"); 922 if (hw->mac.type == e1000_82543) { 923 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 924 } else { 925 /* 926 * The 82544 can't ACK the 64-bit write when issuing the 927 * reset, so use IO-mapping as a workaround. 928 */ 929 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 930 } 931 932 /* 933 * After MAC reset, force reload of NVM to restore power-on 934 * settings to device. 935 */ 936 hw->nvm.ops.reload(hw); 937 msec_delay(2); 938 939 /* Masking off and clearing any pending interrupts */ 940 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 941 E1000_READ_REG(hw, E1000_ICR); 942 943 return ret_val; 944 } 945 946 /** 947 * e1000_init_hw_82543 - Initialize hardware 948 * @hw: pointer to the HW structure 949 * 950 * This inits the hardware readying it for operation. 951 **/ 952 static s32 e1000_init_hw_82543(struct e1000_hw *hw) 953 { 954 struct e1000_mac_info *mac = &hw->mac; 955 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 956 u32 ctrl; 957 s32 ret_val; 958 u16 i; 959 960 DEBUGFUNC("e1000_init_hw_82543"); 961 962 /* Disabling VLAN filtering */ 963 E1000_WRITE_REG(hw, E1000_VET, 0); 964 mac->ops.clear_vfta(hw); 965 966 /* Setup the receive address. */ 967 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 968 969 /* Zero out the Multicast HASH table */ 970 DEBUGOUT("Zeroing the MTA\n"); 971 for (i = 0; i < mac->mta_reg_count; i++) { 972 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 973 E1000_WRITE_FLUSH(hw); 974 } 975 976 /* 977 * Set the PCI priority bit correctly in the CTRL register. This 978 * determines if the adapter gives priority to receives, or if it 979 * gives equal priority to transmits and receives. 980 */ 981 if (hw->mac.type == e1000_82543 && dev_spec->dma_fairness) { 982 ctrl = E1000_READ_REG(hw, E1000_CTRL); 983 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR); 984 } 985 986 e1000_pcix_mmrbc_workaround_generic(hw); 987 988 /* Setup link and flow control */ 989 ret_val = mac->ops.setup_link(hw); 990 991 /* 992 * Clear all of the statistics registers (clear on read). It is 993 * important that we do this after we have tried to establish link 994 * because the symbol error count will increment wildly if there 995 * is no link. 996 */ 997 e1000_clear_hw_cntrs_82543(hw); 998 999 return ret_val; 1000 } 1001 1002 /** 1003 * e1000_setup_link_82543 - Setup flow control and link settings 1004 * @hw: pointer to the HW structure 1005 * 1006 * Read the EEPROM to determine the initial polarity value and write the 1007 * extended device control register with the information before calling 1008 * the generic setup link function, which does the following: 1009 * Determines which flow control settings to use, then configures flow 1010 * control. Calls the appropriate media-specific link configuration 1011 * function. Assuming the adapter has a valid link partner, a valid link 1012 * should be established. Assumes the hardware has previously been reset 1013 * and the transmitter and receiver are not enabled. 1014 **/ 1015 static s32 e1000_setup_link_82543(struct e1000_hw *hw) 1016 { 1017 u32 ctrl_ext; 1018 s32 ret_val; 1019 u16 data; 1020 1021 DEBUGFUNC("e1000_setup_link_82543"); 1022 1023 /* 1024 * Take the 4 bits from NVM word 0xF that determine the initial 1025 * polarity value for the SW controlled pins, and setup the 1026 * Extended Device Control reg with that info. 1027 * This is needed because one of the SW controlled pins is used for 1028 * signal detection. So this should be done before phy setup. 1029 */ 1030 if (hw->mac.type == e1000_82543) { 1031 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data); 1032 if (ret_val) { 1033 DEBUGOUT("NVM Read Error\n"); 1034 ret_val = -E1000_ERR_NVM; 1035 goto out; 1036 } 1037 ctrl_ext = ((data & NVM_WORD0F_SWPDIO_EXT_MASK) << 1038 NVM_SWDPIO_EXT_SHIFT); 1039 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1040 } 1041 1042 ret_val = e1000_setup_link_generic(hw); 1043 1044 out: 1045 return ret_val; 1046 } 1047 1048 /** 1049 * e1000_setup_copper_link_82543 - Configure copper link settings 1050 * @hw: pointer to the HW structure 1051 * 1052 * Configures the link for auto-neg or forced speed and duplex. Then we check 1053 * for link, once link is established calls to configure collision distance 1054 * and flow control are called. 1055 **/ 1056 static s32 e1000_setup_copper_link_82543(struct e1000_hw *hw) 1057 { 1058 u32 ctrl; 1059 s32 ret_val; 1060 bool link; 1061 1062 DEBUGFUNC("e1000_setup_copper_link_82543"); 1063 1064 ctrl = E1000_READ_REG(hw, E1000_CTRL) | E1000_CTRL_SLU; 1065 /* 1066 * With 82543, we need to force speed and duplex on the MAC 1067 * equal to what the PHY speed and duplex configuration is. 1068 * In addition, we need to perform a hardware reset on the 1069 * PHY to take it out of reset. 1070 */ 1071 if (hw->mac.type == e1000_82543) { 1072 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1073 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1074 ret_val = hw->phy.ops.reset(hw); 1075 if (ret_val) 1076 goto out; 1077 } else { 1078 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1079 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1080 } 1081 1082 /* Set MDI/MDI-X, Polarity Reversal, and downshift settings */ 1083 ret_val = e1000_copper_link_setup_m88(hw); 1084 if (ret_val) 1085 goto out; 1086 1087 if (hw->mac.autoneg) { 1088 /* 1089 * Setup autoneg and flow control advertisement and perform 1090 * autonegotiation. 1091 */ 1092 ret_val = e1000_copper_link_autoneg(hw); 1093 if (ret_val) 1094 goto out; 1095 } else { 1096 /* 1097 * PHY will be set to 10H, 10F, 100H or 100F 1098 * depending on user settings. 1099 */ 1100 DEBUGOUT("Forcing Speed and Duplex\n"); 1101 ret_val = e1000_phy_force_speed_duplex_82543(hw); 1102 if (ret_val) { 1103 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1104 goto out; 1105 } 1106 } 1107 1108 /* 1109 * Check link status. Wait up to 100 microseconds for link to become 1110 * valid. 1111 */ 1112 ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10, 1113 &link); 1114 if (ret_val) 1115 goto out; 1116 1117 1118 if (link) { 1119 DEBUGOUT("Valid link established!!!\n"); 1120 /* Config the MAC and PHY after link is up */ 1121 if (hw->mac.type == e1000_82544) { 1122 hw->mac.ops.config_collision_dist(hw); 1123 } else { 1124 ret_val = e1000_config_mac_to_phy_82543(hw); 1125 if (ret_val) 1126 goto out; 1127 } 1128 ret_val = e1000_config_fc_after_link_up_generic(hw); 1129 } else { 1130 DEBUGOUT("Unable to establish link!!!\n"); 1131 } 1132 1133 out: 1134 return ret_val; 1135 } 1136 1137 /** 1138 * e1000_setup_fiber_link_82543 - Setup link for fiber 1139 * @hw: pointer to the HW structure 1140 * 1141 * Configures collision distance and flow control for fiber links. Upon 1142 * successful setup, poll for link. 1143 **/ 1144 static s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw) 1145 { 1146 u32 ctrl; 1147 s32 ret_val; 1148 1149 DEBUGFUNC("e1000_setup_fiber_link_82543"); 1150 1151 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1152 1153 /* Take the link out of reset */ 1154 ctrl &= ~E1000_CTRL_LRST; 1155 1156 hw->mac.ops.config_collision_dist(hw); 1157 1158 ret_val = e1000_commit_fc_settings_generic(hw); 1159 if (ret_val) 1160 goto out; 1161 1162 DEBUGOUT("Auto-negotiation enabled\n"); 1163 1164 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1165 E1000_WRITE_FLUSH(hw); 1166 msec_delay(1); 1167 1168 /* 1169 * For these adapters, the SW definable pin 1 is cleared when the 1170 * optics detect a signal. If we have a signal, then poll for a 1171 * "Link-Up" indication. 1172 */ 1173 if (!(E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) 1174 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1175 else 1176 DEBUGOUT("No signal detected\n"); 1177 1178 out: 1179 return ret_val; 1180 } 1181 1182 /** 1183 * e1000_check_for_copper_link_82543 - Check for link (Copper) 1184 * @hw: pointer to the HW structure 1185 * 1186 * Checks the phy for link, if link exists, do the following: 1187 * - check for downshift 1188 * - do polarity workaround (if necessary) 1189 * - configure collision distance 1190 * - configure flow control after link up 1191 * - configure tbi compatibility 1192 **/ 1193 static s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw) 1194 { 1195 struct e1000_mac_info *mac = &hw->mac; 1196 u32 icr, rctl; 1197 s32 ret_val; 1198 u16 speed, duplex; 1199 bool link; 1200 1201 DEBUGFUNC("e1000_check_for_copper_link_82543"); 1202 1203 if (!mac->get_link_status) { 1204 ret_val = E1000_SUCCESS; 1205 goto out; 1206 } 1207 1208 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 1209 if (ret_val) 1210 goto out; 1211 1212 if (!link) 1213 goto out; /* No link detected */ 1214 1215 mac->get_link_status = FALSE; 1216 1217 e1000_check_downshift_generic(hw); 1218 1219 /* 1220 * If we are forcing speed/duplex, then we can return since 1221 * we have already determined whether we have link or not. 1222 */ 1223 if (!mac->autoneg) { 1224 /* 1225 * If speed and duplex are forced to 10H or 10F, then we will 1226 * implement the polarity reversal workaround. We disable 1227 * interrupts first, and upon returning, place the devices 1228 * interrupt state to its previous value except for the link 1229 * status change interrupt which will happened due to the 1230 * execution of this workaround. 1231 */ 1232 if (mac->forced_speed_duplex & E1000_ALL_10_SPEED) { 1233 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 1234 ret_val = e1000_polarity_reversal_workaround_82543(hw); 1235 icr = E1000_READ_REG(hw, E1000_ICR); 1236 E1000_WRITE_REG(hw, E1000_ICS, (icr & ~E1000_ICS_LSC)); 1237 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 1238 } 1239 1240 ret_val = -E1000_ERR_CONFIG; 1241 goto out; 1242 } 1243 1244 /* 1245 * We have a M88E1000 PHY and Auto-Neg is enabled. If we 1246 * have Si on board that is 82544 or newer, Auto 1247 * Speed Detection takes care of MAC speed/duplex 1248 * configuration. So we only need to configure Collision 1249 * Distance in the MAC. Otherwise, we need to force 1250 * speed/duplex on the MAC to the current PHY speed/duplex 1251 * settings. 1252 */ 1253 if (mac->type == e1000_82544) 1254 hw->mac.ops.config_collision_dist(hw); 1255 else { 1256 ret_val = e1000_config_mac_to_phy_82543(hw); 1257 if (ret_val) { 1258 DEBUGOUT("Error configuring MAC to PHY settings\n"); 1259 goto out; 1260 } 1261 } 1262 1263 /* 1264 * Configure Flow Control now that Auto-Neg has completed. 1265 * First, we need to restore the desired flow control 1266 * settings because we may have had to re-autoneg with a 1267 * different link partner. 1268 */ 1269 ret_val = e1000_config_fc_after_link_up_generic(hw); 1270 if (ret_val) 1271 DEBUGOUT("Error configuring flow control\n"); 1272 1273 /* 1274 * At this point we know that we are on copper and we have 1275 * auto-negotiated link. These are conditions for checking the link 1276 * partner capability register. We use the link speed to determine if 1277 * TBI compatibility needs to be turned on or off. If the link is not 1278 * at gigabit speed, then TBI compatibility is not needed. If we are 1279 * at gigabit speed, we turn on TBI compatibility. 1280 */ 1281 if (e1000_tbi_compatibility_enabled_82543(hw)) { 1282 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1283 if (ret_val) { 1284 DEBUGOUT("Error getting link speed and duplex\n"); 1285 return ret_val; 1286 } 1287 if (speed != SPEED_1000) { 1288 /* 1289 * If link speed is not set to gigabit speed, 1290 * we do not need to enable TBI compatibility. 1291 */ 1292 if (e1000_tbi_sbp_enabled_82543(hw)) { 1293 /* 1294 * If we previously were in the mode, 1295 * turn it off. 1296 */ 1297 e1000_set_tbi_sbp_82543(hw, FALSE); 1298 rctl = E1000_READ_REG(hw, E1000_RCTL); 1299 rctl &= ~E1000_RCTL_SBP; 1300 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1301 } 1302 } else { 1303 /* 1304 * If TBI compatibility is was previously off, 1305 * turn it on. For compatibility with a TBI link 1306 * partner, we will store bad packets. Some 1307 * frames have an additional byte on the end and 1308 * will look like CRC errors to to the hardware. 1309 */ 1310 if (!e1000_tbi_sbp_enabled_82543(hw)) { 1311 e1000_set_tbi_sbp_82543(hw, TRUE); 1312 rctl = E1000_READ_REG(hw, E1000_RCTL); 1313 rctl |= E1000_RCTL_SBP; 1314 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1315 } 1316 } 1317 } 1318 out: 1319 return ret_val; 1320 } 1321 1322 /** 1323 * e1000_check_for_fiber_link_82543 - Check for link (Fiber) 1324 * @hw: pointer to the HW structure 1325 * 1326 * Checks for link up on the hardware. If link is not up and we have 1327 * a signal, then we need to force link up. 1328 **/ 1329 static s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw) 1330 { 1331 struct e1000_mac_info *mac = &hw->mac; 1332 u32 rxcw, ctrl, status; 1333 s32 ret_val = E1000_SUCCESS; 1334 1335 DEBUGFUNC("e1000_check_for_fiber_link_82543"); 1336 1337 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1338 status = E1000_READ_REG(hw, E1000_STATUS); 1339 rxcw = E1000_READ_REG(hw, E1000_RXCW); 1340 1341 /* 1342 * If we don't have link (auto-negotiation failed or link partner 1343 * cannot auto-negotiate), the cable is plugged in (we have signal), 1344 * and our link partner is not trying to auto-negotiate with us (we 1345 * are receiving idles or data), we need to force link up. We also 1346 * need to give auto-negotiation time to complete, in case the cable 1347 * was just plugged in. The autoneg_failed flag does this. 1348 */ 1349 /* (ctrl & E1000_CTRL_SWDPIN1) == 0 == have signal */ 1350 if ((!(ctrl & E1000_CTRL_SWDPIN1)) && 1351 (!(status & E1000_STATUS_LU)) && 1352 (!(rxcw & E1000_RXCW_C))) { 1353 if (!mac->autoneg_failed) { 1354 mac->autoneg_failed = TRUE; 1355 ret_val = 0; 1356 goto out; 1357 } 1358 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 1359 1360 /* Disable auto-negotiation in the TXCW register */ 1361 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 1362 1363 /* Force link-up and also force full-duplex. */ 1364 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1365 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 1366 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1367 1368 /* Configure Flow Control after forcing link up. */ 1369 ret_val = e1000_config_fc_after_link_up_generic(hw); 1370 if (ret_val) { 1371 DEBUGOUT("Error configuring flow control\n"); 1372 goto out; 1373 } 1374 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 1375 /* 1376 * If we are forcing link and we are receiving /C/ ordered 1377 * sets, re-enable auto-negotiation in the TXCW register 1378 * and disable forced link in the Device Control register 1379 * in an attempt to auto-negotiate with our link partner. 1380 */ 1381 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 1382 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1383 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 1384 1385 mac->serdes_has_link = TRUE; 1386 } 1387 1388 out: 1389 return ret_val; 1390 } 1391 1392 /** 1393 * e1000_config_mac_to_phy_82543 - Configure MAC to PHY settings 1394 * @hw: pointer to the HW structure 1395 * 1396 * For the 82543 silicon, we need to set the MAC to match the settings 1397 * of the PHY, even if the PHY is auto-negotiating. 1398 **/ 1399 static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw) 1400 { 1401 u32 ctrl; 1402 s32 ret_val = E1000_SUCCESS; 1403 u16 phy_data; 1404 1405 DEBUGFUNC("e1000_config_mac_to_phy_82543"); 1406 1407 if (!(hw->phy.ops.read_reg)) 1408 goto out; 1409 1410 /* Set the bits to force speed and duplex */ 1411 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1412 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1413 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 1414 1415 /* 1416 * Set up duplex in the Device Control and Transmit Control 1417 * registers depending on negotiated values. 1418 */ 1419 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1420 if (ret_val) 1421 goto out; 1422 1423 ctrl &= ~E1000_CTRL_FD; 1424 if (phy_data & M88E1000_PSSR_DPLX) 1425 ctrl |= E1000_CTRL_FD; 1426 1427 hw->mac.ops.config_collision_dist(hw); 1428 1429 /* 1430 * Set up speed in the Device Control register depending on 1431 * negotiated values. 1432 */ 1433 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 1434 ctrl |= E1000_CTRL_SPD_1000; 1435 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 1436 ctrl |= E1000_CTRL_SPD_100; 1437 1438 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1439 1440 out: 1441 return ret_val; 1442 } 1443 1444 /** 1445 * e1000_write_vfta_82543 - Write value to VLAN filter table 1446 * @hw: pointer to the HW structure 1447 * @offset: the 32-bit offset in which to write the value to. 1448 * @value: the 32-bit value to write at location offset. 1449 * 1450 * This writes a 32-bit value to a 32-bit offset in the VLAN filter 1451 * table. 1452 **/ 1453 static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, u32 value) 1454 { 1455 u32 temp; 1456 1457 DEBUGFUNC("e1000_write_vfta_82543"); 1458 1459 if ((hw->mac.type == e1000_82544) && (offset & 1)) { 1460 temp = E1000_READ_REG_ARRAY(hw, E1000_VFTA, offset - 1); 1461 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 1462 E1000_WRITE_FLUSH(hw); 1463 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset - 1, temp); 1464 E1000_WRITE_FLUSH(hw); 1465 } else { 1466 e1000_write_vfta_generic(hw, offset, value); 1467 } 1468 } 1469 1470 /** 1471 * e1000_led_on_82543 - Turn on SW controllable LED 1472 * @hw: pointer to the HW structure 1473 * 1474 * Turns the SW defined LED on. 1475 **/ 1476 static s32 e1000_led_on_82543(struct e1000_hw *hw) 1477 { 1478 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1479 1480 DEBUGFUNC("e1000_led_on_82543"); 1481 1482 if (hw->mac.type == e1000_82544 && 1483 hw->phy.media_type == e1000_media_type_copper) { 1484 /* Clear SW-definable Pin 0 to turn on the LED */ 1485 ctrl &= ~E1000_CTRL_SWDPIN0; 1486 ctrl |= E1000_CTRL_SWDPIO0; 1487 } else { 1488 /* Fiber 82544 and all 82543 use this method */ 1489 ctrl |= E1000_CTRL_SWDPIN0; 1490 ctrl |= E1000_CTRL_SWDPIO0; 1491 } 1492 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1493 1494 return E1000_SUCCESS; 1495 } 1496 1497 /** 1498 * e1000_led_off_82543 - Turn off SW controllable LED 1499 * @hw: pointer to the HW structure 1500 * 1501 * Turns the SW defined LED off. 1502 **/ 1503 static s32 e1000_led_off_82543(struct e1000_hw *hw) 1504 { 1505 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1506 1507 DEBUGFUNC("e1000_led_off_82543"); 1508 1509 if (hw->mac.type == e1000_82544 && 1510 hw->phy.media_type == e1000_media_type_copper) { 1511 /* Set SW-definable Pin 0 to turn off the LED */ 1512 ctrl |= E1000_CTRL_SWDPIN0; 1513 ctrl |= E1000_CTRL_SWDPIO0; 1514 } else { 1515 ctrl &= ~E1000_CTRL_SWDPIN0; 1516 ctrl |= E1000_CTRL_SWDPIO0; 1517 } 1518 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1519 1520 return E1000_SUCCESS; 1521 } 1522 1523 /** 1524 * e1000_clear_hw_cntrs_82543 - Clear device specific hardware counters 1525 * @hw: pointer to the HW structure 1526 * 1527 * Clears the hardware counters by reading the counter registers. 1528 **/ 1529 static void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw) 1530 { 1531 DEBUGFUNC("e1000_clear_hw_cntrs_82543"); 1532 1533 e1000_clear_hw_cntrs_base_generic(hw); 1534 1535 E1000_READ_REG(hw, E1000_PRC64); 1536 E1000_READ_REG(hw, E1000_PRC127); 1537 E1000_READ_REG(hw, E1000_PRC255); 1538 E1000_READ_REG(hw, E1000_PRC511); 1539 E1000_READ_REG(hw, E1000_PRC1023); 1540 E1000_READ_REG(hw, E1000_PRC1522); 1541 E1000_READ_REG(hw, E1000_PTC64); 1542 E1000_READ_REG(hw, E1000_PTC127); 1543 E1000_READ_REG(hw, E1000_PTC255); 1544 E1000_READ_REG(hw, E1000_PTC511); 1545 E1000_READ_REG(hw, E1000_PTC1023); 1546 E1000_READ_REG(hw, E1000_PTC1522); 1547 1548 E1000_READ_REG(hw, E1000_ALGNERRC); 1549 E1000_READ_REG(hw, E1000_RXERRC); 1550 E1000_READ_REG(hw, E1000_TNCRS); 1551 E1000_READ_REG(hw, E1000_CEXTERR); 1552 E1000_READ_REG(hw, E1000_TSCTC); 1553 E1000_READ_REG(hw, E1000_TSCTFC); 1554 } 1555