1 /****************************************************************************** 2 3 Copyright (c) 2001-2019, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 /* 82571EB Gigabit Ethernet Controller 36 * 82571EB Gigabit Ethernet Controller (Copper) 37 * 82571EB Gigabit Ethernet Controller (Fiber) 38 * 82571EB Dual Port Gigabit Mezzanine Adapter 39 * 82571EB Quad Port Gigabit Mezzanine Adapter 40 * 82571PT Gigabit PT Quad Port Server ExpressModule 41 * 82572EI Gigabit Ethernet Controller (Copper) 42 * 82572EI Gigabit Ethernet Controller (Fiber) 43 * 82572EI Gigabit Ethernet Controller 44 * 82573V Gigabit Ethernet Controller (Copper) 45 * 82573E Gigabit Ethernet Controller (Copper) 46 * 82573L Gigabit Ethernet Controller 47 * 82574L Gigabit Network Connection 48 * 82583V Gigabit Network Connection 49 */ 50 51 #include "e1000_api.h" 52 53 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw); 54 static void e1000_release_nvm_82571(struct e1000_hw *hw); 55 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, 56 u16 words, u16 *data); 57 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw); 58 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw); 59 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw); 60 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, 61 bool active); 62 static s32 e1000_reset_hw_82571(struct e1000_hw *hw); 63 static s32 e1000_init_hw_82571(struct e1000_hw *hw); 64 static void e1000_clear_vfta_82571(struct e1000_hw *hw); 65 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw); 66 static s32 e1000_led_on_82574(struct e1000_hw *hw); 67 static s32 e1000_setup_link_82571(struct e1000_hw *hw); 68 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); 69 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw); 70 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); 71 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data); 72 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); 73 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw); 74 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); 75 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); 76 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); 77 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw); 78 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw); 79 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw); 80 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, 81 bool active); 82 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, 83 bool active); 84 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); 85 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 86 u16 words, u16 *data); 87 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw); 88 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw); 89 90 /** 91 * e1000_init_phy_params_82571 - Init PHY func ptrs. 92 * @hw: pointer to the HW structure 93 **/ 94 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) 95 { 96 struct e1000_phy_info *phy = &hw->phy; 97 s32 ret_val; 98 99 DEBUGFUNC("e1000_init_phy_params_82571"); 100 101 if (hw->phy.media_type != e1000_media_type_copper) { 102 phy->type = e1000_phy_none; 103 return E1000_SUCCESS; 104 } 105 106 phy->addr = 1; 107 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 108 phy->reset_delay_us = 100; 109 110 phy->ops.check_reset_block = e1000_check_reset_block_generic; 111 phy->ops.reset = e1000_phy_hw_reset_generic; 112 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82571; 113 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 114 phy->ops.power_up = e1000_power_up_phy_copper; 115 phy->ops.power_down = e1000_power_down_phy_copper_82571; 116 117 switch (hw->mac.type) { 118 case e1000_82571: 119 case e1000_82572: 120 phy->type = e1000_phy_igp_2; 121 phy->ops.get_cfg_done = e1000_get_cfg_done_82571; 122 phy->ops.get_info = e1000_get_phy_info_igp; 123 phy->ops.check_polarity = e1000_check_polarity_igp; 124 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 125 phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 126 phy->ops.read_reg = e1000_read_phy_reg_igp; 127 phy->ops.write_reg = e1000_write_phy_reg_igp; 128 phy->ops.acquire = e1000_get_hw_semaphore_82571; 129 phy->ops.release = e1000_put_hw_semaphore_82571; 130 break; 131 case e1000_82573: 132 phy->type = e1000_phy_m88; 133 phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 134 phy->ops.get_info = e1000_get_phy_info_m88; 135 phy->ops.check_polarity = e1000_check_polarity_m88; 136 phy->ops.commit = e1000_phy_sw_reset_generic; 137 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 138 phy->ops.get_cable_length = e1000_get_cable_length_m88; 139 phy->ops.read_reg = e1000_read_phy_reg_m88; 140 phy->ops.write_reg = e1000_write_phy_reg_m88; 141 phy->ops.acquire = e1000_get_hw_semaphore_82571; 142 phy->ops.release = e1000_put_hw_semaphore_82571; 143 break; 144 case e1000_82574: 145 case e1000_82583: 146 phy->type = e1000_phy_bm; 147 phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 148 phy->ops.get_info = e1000_get_phy_info_m88; 149 phy->ops.check_polarity = e1000_check_polarity_m88; 150 phy->ops.commit = e1000_phy_sw_reset_generic; 151 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 152 phy->ops.get_cable_length = e1000_get_cable_length_m88; 153 phy->ops.read_reg = e1000_read_phy_reg_bm2; 154 phy->ops.write_reg = e1000_write_phy_reg_bm2; 155 phy->ops.acquire = e1000_get_hw_semaphore_82574; 156 phy->ops.release = e1000_put_hw_semaphore_82574; 157 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574; 158 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574; 159 break; 160 default: 161 return -E1000_ERR_PHY; 162 break; 163 } 164 165 /* This can only be done after all function pointers are setup. */ 166 ret_val = e1000_get_phy_id_82571(hw); 167 if (ret_val) { 168 DEBUGOUT("Error getting PHY ID\n"); 169 return ret_val; 170 } 171 172 /* Verify phy id */ 173 switch (hw->mac.type) { 174 case e1000_82571: 175 case e1000_82572: 176 if (phy->id != IGP01E1000_I_PHY_ID) 177 ret_val = -E1000_ERR_PHY; 178 break; 179 case e1000_82573: 180 if (phy->id != M88E1111_I_PHY_ID) 181 ret_val = -E1000_ERR_PHY; 182 break; 183 case e1000_82574: 184 case e1000_82583: 185 if (phy->id != BME1000_E_PHY_ID_R2) 186 ret_val = -E1000_ERR_PHY; 187 break; 188 default: 189 ret_val = -E1000_ERR_PHY; 190 break; 191 } 192 193 if (ret_val) 194 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); 195 196 return ret_val; 197 } 198 199 /** 200 * e1000_init_nvm_params_82571 - Init NVM func ptrs. 201 * @hw: pointer to the HW structure 202 **/ 203 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) 204 { 205 struct e1000_nvm_info *nvm = &hw->nvm; 206 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 207 u16 size; 208 209 DEBUGFUNC("e1000_init_nvm_params_82571"); 210 211 nvm->opcode_bits = 8; 212 nvm->delay_usec = 1; 213 switch (nvm->override) { 214 case e1000_nvm_override_spi_large: 215 nvm->page_size = 32; 216 nvm->address_bits = 16; 217 break; 218 case e1000_nvm_override_spi_small: 219 nvm->page_size = 8; 220 nvm->address_bits = 8; 221 break; 222 default: 223 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 224 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 225 break; 226 } 227 228 switch (hw->mac.type) { 229 case e1000_82573: 230 case e1000_82574: 231 case e1000_82583: 232 if (((eecd >> 15) & 0x3) == 0x3) { 233 nvm->type = e1000_nvm_flash_hw; 234 nvm->word_size = 2048; 235 /* Autonomous Flash update bit must be cleared due 236 * to Flash update issue. 237 */ 238 eecd &= ~E1000_EECD_AUPDEN; 239 E1000_WRITE_REG(hw, E1000_EECD, eecd); 240 break; 241 } 242 /* Fall Through */ 243 default: 244 nvm->type = e1000_nvm_eeprom_spi; 245 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 246 E1000_EECD_SIZE_EX_SHIFT); 247 /* Added to a constant, "size" becomes the left-shift value 248 * for setting word_size. 249 */ 250 size += NVM_WORD_SIZE_BASE_SHIFT; 251 252 /* EEPROM access above 16k is unsupported */ 253 if (size > 14) 254 size = 14; 255 nvm->word_size = 1 << size; 256 break; 257 } 258 259 /* Function Pointers */ 260 switch (hw->mac.type) { 261 case e1000_82574: 262 case e1000_82583: 263 nvm->ops.acquire = e1000_get_hw_semaphore_82574; 264 nvm->ops.release = e1000_put_hw_semaphore_82574; 265 break; 266 default: 267 nvm->ops.acquire = e1000_acquire_nvm_82571; 268 nvm->ops.release = e1000_release_nvm_82571; 269 break; 270 } 271 nvm->ops.read = e1000_read_nvm_eerd; 272 nvm->ops.update = e1000_update_nvm_checksum_82571; 273 nvm->ops.validate = e1000_validate_nvm_checksum_82571; 274 nvm->ops.valid_led_default = e1000_valid_led_default_82571; 275 nvm->ops.write = e1000_write_nvm_82571; 276 277 return E1000_SUCCESS; 278 } 279 280 /** 281 * e1000_init_mac_params_82571 - Init MAC func ptrs. 282 * @hw: pointer to the HW structure 283 **/ 284 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw) 285 { 286 struct e1000_mac_info *mac = &hw->mac; 287 u32 swsm = 0; 288 u32 swsm2 = 0; 289 bool force_clear_smbi = FALSE; 290 291 DEBUGFUNC("e1000_init_mac_params_82571"); 292 293 /* Set media type and media-dependent function pointers */ 294 switch (hw->device_id) { 295 case E1000_DEV_ID_82571EB_FIBER: 296 case E1000_DEV_ID_82572EI_FIBER: 297 case E1000_DEV_ID_82571EB_QUAD_FIBER: 298 hw->phy.media_type = e1000_media_type_fiber; 299 mac->ops.setup_physical_interface = 300 e1000_setup_fiber_serdes_link_82571; 301 mac->ops.check_for_link = e1000_check_for_fiber_link_generic; 302 mac->ops.get_link_up_info = 303 e1000_get_speed_and_duplex_fiber_serdes_generic; 304 break; 305 case E1000_DEV_ID_82571EB_SERDES: 306 case E1000_DEV_ID_82571EB_SERDES_DUAL: 307 case E1000_DEV_ID_82571EB_SERDES_QUAD: 308 case E1000_DEV_ID_82572EI_SERDES: 309 hw->phy.media_type = e1000_media_type_internal_serdes; 310 mac->ops.setup_physical_interface = 311 e1000_setup_fiber_serdes_link_82571; 312 mac->ops.check_for_link = e1000_check_for_serdes_link_82571; 313 mac->ops.get_link_up_info = 314 e1000_get_speed_and_duplex_fiber_serdes_generic; 315 break; 316 default: 317 hw->phy.media_type = e1000_media_type_copper; 318 mac->ops.setup_physical_interface = 319 e1000_setup_copper_link_82571; 320 mac->ops.check_for_link = e1000_check_for_copper_link_generic; 321 mac->ops.get_link_up_info = 322 e1000_get_speed_and_duplex_copper_generic; 323 break; 324 } 325 326 /* Set mta register count */ 327 mac->mta_reg_count = 128; 328 /* Set rar entry count */ 329 mac->rar_entry_count = E1000_RAR_ENTRIES; 330 /* Set if part includes ASF firmware */ 331 mac->asf_firmware_present = TRUE; 332 /* Adaptive IFS supported */ 333 mac->adaptive_ifs = TRUE; 334 335 /* Function pointers */ 336 337 /* bus type/speed/width */ 338 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 339 /* reset */ 340 mac->ops.reset_hw = e1000_reset_hw_82571; 341 /* hw initialization */ 342 mac->ops.init_hw = e1000_init_hw_82571; 343 /* link setup */ 344 mac->ops.setup_link = e1000_setup_link_82571; 345 /* multicast address update */ 346 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 347 /* writing VFTA */ 348 mac->ops.write_vfta = e1000_write_vfta_generic; 349 /* clearing VFTA */ 350 mac->ops.clear_vfta = e1000_clear_vfta_82571; 351 /* read mac address */ 352 mac->ops.read_mac_addr = e1000_read_mac_addr_82571; 353 /* ID LED init */ 354 mac->ops.id_led_init = e1000_id_led_init_generic; 355 /* setup LED */ 356 mac->ops.setup_led = e1000_setup_led_generic; 357 /* cleanup LED */ 358 mac->ops.cleanup_led = e1000_cleanup_led_generic; 359 /* turn off LED */ 360 mac->ops.led_off = e1000_led_off_generic; 361 /* clear hardware counters */ 362 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571; 363 364 /* MAC-specific function pointers */ 365 switch (hw->mac.type) { 366 case e1000_82573: 367 mac->ops.set_lan_id = e1000_set_lan_id_single_port; 368 mac->ops.check_mng_mode = e1000_check_mng_mode_generic; 369 mac->ops.led_on = e1000_led_on_generic; 370 mac->ops.blink_led = e1000_blink_led_generic; 371 372 /* FWSM register */ 373 mac->has_fwsm = TRUE; 374 /* ARC supported; valid only if manageability features are 375 * enabled. 376 */ 377 mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) & 378 E1000_FWSM_MODE_MASK); 379 break; 380 case e1000_82574: 381 case e1000_82583: 382 mac->ops.set_lan_id = e1000_set_lan_id_single_port; 383 mac->ops.check_mng_mode = e1000_check_mng_mode_82574; 384 mac->ops.led_on = e1000_led_on_82574; 385 break; 386 default: 387 mac->ops.check_mng_mode = e1000_check_mng_mode_generic; 388 mac->ops.led_on = e1000_led_on_generic; 389 mac->ops.blink_led = e1000_blink_led_generic; 390 391 /* FWSM register */ 392 mac->has_fwsm = TRUE; 393 break; 394 } 395 396 /* Ensure that the inter-port SWSM.SMBI lock bit is clear before 397 * first NVM or PHY acess. This should be done for single-port 398 * devices, and for one port only on dual-port devices so that 399 * for those devices we can still use the SMBI lock to synchronize 400 * inter-port accesses to the PHY & NVM. 401 */ 402 switch (hw->mac.type) { 403 case e1000_82571: 404 case e1000_82572: 405 swsm2 = E1000_READ_REG(hw, E1000_SWSM2); 406 407 if (!(swsm2 & E1000_SWSM2_LOCK)) { 408 /* Only do this for the first interface on this card */ 409 E1000_WRITE_REG(hw, E1000_SWSM2, swsm2 | 410 E1000_SWSM2_LOCK); 411 force_clear_smbi = TRUE; 412 } else { 413 force_clear_smbi = FALSE; 414 } 415 break; 416 default: 417 force_clear_smbi = TRUE; 418 break; 419 } 420 421 if (force_clear_smbi) { 422 /* Make sure SWSM.SMBI is clear */ 423 swsm = E1000_READ_REG(hw, E1000_SWSM); 424 if (swsm & E1000_SWSM_SMBI) { 425 /* This bit should not be set on a first interface, and 426 * indicates that the bootagent or EFI code has 427 * improperly left this bit enabled 428 */ 429 DEBUGOUT("Please update your 82571 Bootagent\n"); 430 } 431 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI); 432 } 433 434 /* Initialze device specific counter of SMBI acquisition timeouts. */ 435 hw->dev_spec._82571.smb_counter = 0; 436 437 return E1000_SUCCESS; 438 } 439 440 /** 441 * e1000_init_function_pointers_82571 - Init func ptrs. 442 * @hw: pointer to the HW structure 443 * 444 * Called to initialize all function pointers and parameters. 445 **/ 446 void e1000_init_function_pointers_82571(struct e1000_hw *hw) 447 { 448 DEBUGFUNC("e1000_init_function_pointers_82571"); 449 450 hw->mac.ops.init_params = e1000_init_mac_params_82571; 451 hw->nvm.ops.init_params = e1000_init_nvm_params_82571; 452 hw->phy.ops.init_params = e1000_init_phy_params_82571; 453 } 454 455 /** 456 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision 457 * @hw: pointer to the HW structure 458 * 459 * Reads the PHY registers and stores the PHY ID and possibly the PHY 460 * revision in the hardware structure. 461 **/ 462 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) 463 { 464 struct e1000_phy_info *phy = &hw->phy; 465 s32 ret_val; 466 u16 phy_id = 0; 467 468 DEBUGFUNC("e1000_get_phy_id_82571"); 469 470 switch (hw->mac.type) { 471 case e1000_82571: 472 case e1000_82572: 473 /* The 82571 firmware may still be configuring the PHY. 474 * In this case, we cannot access the PHY until the 475 * configuration is done. So we explicitly set the 476 * PHY ID. 477 */ 478 phy->id = IGP01E1000_I_PHY_ID; 479 break; 480 case e1000_82573: 481 return e1000_get_phy_id(hw); 482 break; 483 case e1000_82574: 484 case e1000_82583: 485 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 486 if (ret_val) 487 return ret_val; 488 489 phy->id = (u32)(phy_id << 16); 490 usec_delay(20); 491 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 492 if (ret_val) 493 return ret_val; 494 495 phy->id |= (u32)(phy_id); 496 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 497 break; 498 default: 499 return -E1000_ERR_PHY; 500 break; 501 } 502 503 return E1000_SUCCESS; 504 } 505 506 /** 507 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore 508 * @hw: pointer to the HW structure 509 * 510 * Acquire the HW semaphore to access the PHY or NVM 511 **/ 512 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) 513 { 514 u32 swsm; 515 s32 sw_timeout = hw->nvm.word_size + 1; 516 s32 fw_timeout = hw->nvm.word_size + 1; 517 s32 i = 0; 518 519 DEBUGFUNC("e1000_get_hw_semaphore_82571"); 520 521 /* If we have timedout 3 times on trying to acquire 522 * the inter-port SMBI semaphore, there is old code 523 * operating on the other port, and it is not 524 * releasing SMBI. Modify the number of times that 525 * we try for the semaphore to interwork with this 526 * older code. 527 */ 528 if (hw->dev_spec._82571.smb_counter > 2) 529 sw_timeout = 1; 530 531 /* Get the SW semaphore */ 532 while (i < sw_timeout) { 533 swsm = E1000_READ_REG(hw, E1000_SWSM); 534 if (!(swsm & E1000_SWSM_SMBI)) 535 break; 536 537 usec_delay(50); 538 i++; 539 } 540 541 if (i == sw_timeout) { 542 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 543 hw->dev_spec._82571.smb_counter++; 544 } 545 /* Get the FW semaphore. */ 546 for (i = 0; i < fw_timeout; i++) { 547 swsm = E1000_READ_REG(hw, E1000_SWSM); 548 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 549 550 /* Semaphore acquired if bit latched */ 551 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 552 break; 553 554 usec_delay(50); 555 } 556 557 if (i == fw_timeout) { 558 /* Release semaphores */ 559 e1000_put_hw_semaphore_82571(hw); 560 DEBUGOUT("Driver can't access the NVM\n"); 561 return -E1000_ERR_NVM; 562 } 563 564 return E1000_SUCCESS; 565 } 566 567 /** 568 * e1000_put_hw_semaphore_82571 - Release hardware semaphore 569 * @hw: pointer to the HW structure 570 * 571 * Release hardware semaphore used to access the PHY or NVM 572 **/ 573 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) 574 { 575 u32 swsm; 576 577 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 578 579 swsm = E1000_READ_REG(hw, E1000_SWSM); 580 581 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 582 583 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 584 } 585 586 /** 587 * e1000_get_hw_semaphore_82573 - Acquire hardware semaphore 588 * @hw: pointer to the HW structure 589 * 590 * Acquire the HW semaphore during reset. 591 * 592 **/ 593 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw) 594 { 595 u32 extcnf_ctrl; 596 s32 i = 0; 597 598 DEBUGFUNC("e1000_get_hw_semaphore_82573"); 599 600 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 601 do { 602 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 603 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 604 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 605 606 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 607 break; 608 609 msec_delay(2); 610 i++; 611 } while (i < MDIO_OWNERSHIP_TIMEOUT); 612 613 if (i == MDIO_OWNERSHIP_TIMEOUT) { 614 /* Release semaphores */ 615 e1000_put_hw_semaphore_82573(hw); 616 DEBUGOUT("Driver can't access the PHY\n"); 617 return -E1000_ERR_PHY; 618 } 619 620 return E1000_SUCCESS; 621 } 622 623 /** 624 * e1000_put_hw_semaphore_82573 - Release hardware semaphore 625 * @hw: pointer to the HW structure 626 * 627 * Release hardware semaphore used during reset. 628 * 629 **/ 630 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw) 631 { 632 u32 extcnf_ctrl; 633 634 DEBUGFUNC("e1000_put_hw_semaphore_82573"); 635 636 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 637 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 638 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 639 } 640 641 /** 642 * e1000_get_hw_semaphore_82574 - Acquire hardware semaphore 643 * @hw: pointer to the HW structure 644 * 645 * Acquire the HW semaphore to access the PHY or NVM. 646 * 647 **/ 648 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw) 649 { 650 s32 ret_val; 651 652 DEBUGFUNC("e1000_get_hw_semaphore_82574"); 653 654 ret_val = e1000_get_hw_semaphore_82573(hw); 655 return ret_val; 656 } 657 658 /** 659 * e1000_put_hw_semaphore_82574 - Release hardware semaphore 660 * @hw: pointer to the HW structure 661 * 662 * Release hardware semaphore used to access the PHY or NVM 663 * 664 **/ 665 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw) 666 { 667 DEBUGFUNC("e1000_put_hw_semaphore_82574"); 668 669 e1000_put_hw_semaphore_82573(hw); 670 } 671 672 /** 673 * e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state 674 * @hw: pointer to the HW structure 675 * @active: TRUE to enable LPLU, FALSE to disable 676 * 677 * Sets the LPLU D0 state according to the active flag. 678 * LPLU will not be activated unless the 679 * device autonegotiation advertisement meets standards of 680 * either 10 or 10/100 or 10/100/1000 at all duplexes. 681 * This is a function pointer entry point only called by 682 * PHY setup routines. 683 **/ 684 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active) 685 { 686 u32 data = E1000_READ_REG(hw, E1000_POEMB); 687 688 DEBUGFUNC("e1000_set_d0_lplu_state_82574"); 689 690 if (active) 691 data |= E1000_PHY_CTRL_D0A_LPLU; 692 else 693 data &= ~E1000_PHY_CTRL_D0A_LPLU; 694 695 E1000_WRITE_REG(hw, E1000_POEMB, data); 696 return E1000_SUCCESS; 697 } 698 699 /** 700 * e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3 701 * @hw: pointer to the HW structure 702 * @active: boolean used to enable/disable lplu 703 * 704 * The low power link up (lplu) state is set to the power management level D3 705 * when active is TRUE, else clear lplu for D3. LPLU 706 * is used during Dx states where the power conservation is most important. 707 * During driver activity, SmartSpeed should be enabled so performance is 708 * maintained. 709 **/ 710 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active) 711 { 712 u32 data = E1000_READ_REG(hw, E1000_POEMB); 713 714 DEBUGFUNC("e1000_set_d3_lplu_state_82574"); 715 716 if (!active) { 717 data &= ~E1000_PHY_CTRL_NOND0A_LPLU; 718 } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 719 (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) || 720 (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) { 721 data |= E1000_PHY_CTRL_NOND0A_LPLU; 722 } 723 724 E1000_WRITE_REG(hw, E1000_POEMB, data); 725 return E1000_SUCCESS; 726 } 727 728 /** 729 * e1000_acquire_nvm_82571 - Request for access to the EEPROM 730 * @hw: pointer to the HW structure 731 * 732 * To gain access to the EEPROM, first we must obtain a hardware semaphore. 733 * Then for non-82573 hardware, set the EEPROM access request bit and wait 734 * for EEPROM access grant bit. If the access grant bit is not set, release 735 * hardware semaphore. 736 **/ 737 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) 738 { 739 s32 ret_val; 740 741 DEBUGFUNC("e1000_acquire_nvm_82571"); 742 743 ret_val = e1000_get_hw_semaphore_82571(hw); 744 if (ret_val) 745 return ret_val; 746 747 switch (hw->mac.type) { 748 case e1000_82573: 749 break; 750 default: 751 ret_val = e1000_acquire_nvm_generic(hw); 752 break; 753 } 754 755 if (ret_val) 756 e1000_put_hw_semaphore_82571(hw); 757 758 return ret_val; 759 } 760 761 /** 762 * e1000_release_nvm_82571 - Release exclusive access to EEPROM 763 * @hw: pointer to the HW structure 764 * 765 * Stop any current commands to the EEPROM and clear the EEPROM request bit. 766 **/ 767 static void e1000_release_nvm_82571(struct e1000_hw *hw) 768 { 769 DEBUGFUNC("e1000_release_nvm_82571"); 770 771 e1000_release_nvm_generic(hw); 772 e1000_put_hw_semaphore_82571(hw); 773 } 774 775 /** 776 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface 777 * @hw: pointer to the HW structure 778 * @offset: offset within the EEPROM to be written to 779 * @words: number of words to write 780 * @data: 16 bit word(s) to be written to the EEPROM 781 * 782 * For non-82573 silicon, write data to EEPROM at offset using SPI interface. 783 * 784 * If e1000_update_nvm_checksum is not called after this function, the 785 * EEPROM will most likely contain an invalid checksum. 786 **/ 787 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, 788 u16 *data) 789 { 790 s32 ret_val; 791 792 DEBUGFUNC("e1000_write_nvm_82571"); 793 794 switch (hw->mac.type) { 795 case e1000_82573: 796 case e1000_82574: 797 case e1000_82583: 798 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); 799 break; 800 case e1000_82571: 801 case e1000_82572: 802 ret_val = e1000_write_nvm_spi(hw, offset, words, data); 803 break; 804 default: 805 ret_val = -E1000_ERR_NVM; 806 break; 807 } 808 809 return ret_val; 810 } 811 812 /** 813 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum 814 * @hw: pointer to the HW structure 815 * 816 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 817 * up to the checksum. Then calculates the EEPROM checksum and writes the 818 * value to the EEPROM. 819 **/ 820 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) 821 { 822 u32 eecd; 823 s32 ret_val; 824 u16 i; 825 826 DEBUGFUNC("e1000_update_nvm_checksum_82571"); 827 828 ret_val = e1000_update_nvm_checksum_generic(hw); 829 if (ret_val) 830 return ret_val; 831 832 /* If our nvm is an EEPROM, then we're done 833 * otherwise, commit the checksum to the flash NVM. 834 */ 835 if (hw->nvm.type != e1000_nvm_flash_hw) 836 return E1000_SUCCESS; 837 838 /* Check for pending operations. */ 839 for (i = 0; i < E1000_FLASH_UPDATES; i++) { 840 msec_delay(1); 841 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD)) 842 break; 843 } 844 845 if (i == E1000_FLASH_UPDATES) 846 return -E1000_ERR_NVM; 847 848 /* Reset the firmware if using STM opcode. */ 849 if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) { 850 /* The enabling of and the actual reset must be done 851 * in two write cycles. 852 */ 853 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE); 854 E1000_WRITE_FLUSH(hw); 855 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET); 856 } 857 858 /* Commit the write to flash */ 859 eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD; 860 E1000_WRITE_REG(hw, E1000_EECD, eecd); 861 862 for (i = 0; i < E1000_FLASH_UPDATES; i++) { 863 msec_delay(1); 864 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD)) 865 break; 866 } 867 868 if (i == E1000_FLASH_UPDATES) 869 return -E1000_ERR_NVM; 870 871 return E1000_SUCCESS; 872 } 873 874 /** 875 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum 876 * @hw: pointer to the HW structure 877 * 878 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 879 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 880 **/ 881 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) 882 { 883 DEBUGFUNC("e1000_validate_nvm_checksum_82571"); 884 885 if (hw->nvm.type == e1000_nvm_flash_hw) 886 e1000_fix_nvm_checksum_82571(hw); 887 888 return e1000_validate_nvm_checksum_generic(hw); 889 } 890 891 /** 892 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon 893 * @hw: pointer to the HW structure 894 * @offset: offset within the EEPROM to be written to 895 * @words: number of words to write 896 * @data: 16 bit word(s) to be written to the EEPROM 897 * 898 * After checking for invalid values, poll the EEPROM to ensure the previous 899 * command has completed before trying to write the next word. After write 900 * poll for completion. 901 * 902 * If e1000_update_nvm_checksum is not called after this function, the 903 * EEPROM will most likely contain an invalid checksum. 904 **/ 905 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 906 u16 words, u16 *data) 907 { 908 struct e1000_nvm_info *nvm = &hw->nvm; 909 u32 i, eewr = 0; 910 s32 ret_val = E1000_SUCCESS; 911 912 DEBUGFUNC("e1000_write_nvm_eewr_82571"); 913 914 /* A check for invalid values: offset too large, too many words, 915 * and not enough words. 916 */ 917 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 918 (words == 0)) { 919 DEBUGOUT("nvm parameter(s) out of bounds\n"); 920 return -E1000_ERR_NVM; 921 } 922 923 for (i = 0; i < words; i++) { 924 eewr = ((data[i] << E1000_NVM_RW_REG_DATA) | 925 ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) | 926 E1000_NVM_RW_REG_START); 927 928 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 929 if (ret_val) 930 break; 931 932 E1000_WRITE_REG(hw, E1000_EEWR, eewr); 933 934 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 935 if (ret_val) 936 break; 937 } 938 939 return ret_val; 940 } 941 942 /** 943 * e1000_get_cfg_done_82571 - Poll for configuration done 944 * @hw: pointer to the HW structure 945 * 946 * Reads the management control register for the config done bit to be set. 947 **/ 948 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) 949 { 950 s32 timeout = PHY_CFG_TIMEOUT; 951 952 DEBUGFUNC("e1000_get_cfg_done_82571"); 953 954 while (timeout) { 955 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & 956 E1000_NVM_CFG_DONE_PORT_0) 957 break; 958 msec_delay(1); 959 timeout--; 960 } 961 if (!timeout) { 962 DEBUGOUT("MNG configuration cycle has not completed.\n"); 963 return -E1000_ERR_RESET; 964 } 965 966 return E1000_SUCCESS; 967 } 968 969 /** 970 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state 971 * @hw: pointer to the HW structure 972 * @active: TRUE to enable LPLU, FALSE to disable 973 * 974 * Sets the LPLU D0 state according to the active flag. When activating LPLU 975 * this function also disables smart speed and vice versa. LPLU will not be 976 * activated unless the device autonegotiation advertisement meets standards 977 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function 978 * pointer entry point only called by PHY setup routines. 979 **/ 980 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) 981 { 982 struct e1000_phy_info *phy = &hw->phy; 983 s32 ret_val; 984 u16 data; 985 986 DEBUGFUNC("e1000_set_d0_lplu_state_82571"); 987 988 if (!(phy->ops.read_reg)) 989 return E1000_SUCCESS; 990 991 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 992 if (ret_val) 993 return ret_val; 994 995 if (active) { 996 data |= IGP02E1000_PM_D0_LPLU; 997 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 998 data); 999 if (ret_val) 1000 return ret_val; 1001 1002 /* When LPLU is enabled, we should disable SmartSpeed */ 1003 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1004 &data); 1005 if (ret_val) 1006 return ret_val; 1007 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1008 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1009 data); 1010 if (ret_val) 1011 return ret_val; 1012 } else { 1013 data &= ~IGP02E1000_PM_D0_LPLU; 1014 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1015 data); 1016 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 1017 * during Dx states where the power conservation is most 1018 * important. During driver activity we should enable 1019 * SmartSpeed, so performance is maintained. 1020 */ 1021 if (phy->smart_speed == e1000_smart_speed_on) { 1022 ret_val = phy->ops.read_reg(hw, 1023 IGP01E1000_PHY_PORT_CONFIG, 1024 &data); 1025 if (ret_val) 1026 return ret_val; 1027 1028 data |= IGP01E1000_PSCFR_SMART_SPEED; 1029 ret_val = phy->ops.write_reg(hw, 1030 IGP01E1000_PHY_PORT_CONFIG, 1031 data); 1032 if (ret_val) 1033 return ret_val; 1034 } else if (phy->smart_speed == e1000_smart_speed_off) { 1035 ret_val = phy->ops.read_reg(hw, 1036 IGP01E1000_PHY_PORT_CONFIG, 1037 &data); 1038 if (ret_val) 1039 return ret_val; 1040 1041 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1042 ret_val = phy->ops.write_reg(hw, 1043 IGP01E1000_PHY_PORT_CONFIG, 1044 data); 1045 if (ret_val) 1046 return ret_val; 1047 } 1048 } 1049 1050 return E1000_SUCCESS; 1051 } 1052 1053 /** 1054 * e1000_reset_hw_82571 - Reset hardware 1055 * @hw: pointer to the HW structure 1056 * 1057 * This resets the hardware into a known state. 1058 **/ 1059 static s32 e1000_reset_hw_82571(struct e1000_hw *hw) 1060 { 1061 u32 ctrl, ctrl_ext, eecd, tctl; 1062 s32 ret_val; 1063 1064 DEBUGFUNC("e1000_reset_hw_82571"); 1065 1066 /* Prevent the PCI-E bus from sticking if there is no TLP connection 1067 * on the last TLP read/write transaction when MAC is reset. 1068 */ 1069 ret_val = e1000_disable_pcie_master_generic(hw); 1070 if (ret_val) 1071 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 1072 1073 DEBUGOUT("Masking off all interrupts\n"); 1074 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1075 1076 E1000_WRITE_REG(hw, E1000_RCTL, 0); 1077 tctl = E1000_READ_REG(hw, E1000_TCTL); 1078 tctl &= ~E1000_TCTL_EN; 1079 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 1080 E1000_WRITE_FLUSH(hw); 1081 1082 msec_delay(10); 1083 1084 /* Must acquire the MDIO ownership before MAC reset. 1085 * Ownership defaults to firmware after a reset. 1086 */ 1087 switch (hw->mac.type) { 1088 case e1000_82573: 1089 ret_val = e1000_get_hw_semaphore_82573(hw); 1090 break; 1091 case e1000_82574: 1092 case e1000_82583: 1093 ret_val = e1000_get_hw_semaphore_82574(hw); 1094 break; 1095 default: 1096 break; 1097 } 1098 1099 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1100 1101 DEBUGOUT("Issuing a global reset to MAC\n"); 1102 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 1103 1104 /* Must release MDIO ownership and mutex after MAC reset. */ 1105 switch (hw->mac.type) { 1106 case e1000_82573: 1107 /* Release mutex only if the hw semaphore is acquired */ 1108 if (!ret_val) 1109 e1000_put_hw_semaphore_82573(hw); 1110 break; 1111 case e1000_82574: 1112 case e1000_82583: 1113 /* Release mutex only if the hw semaphore is acquired */ 1114 if (!ret_val) 1115 e1000_put_hw_semaphore_82574(hw); 1116 break; 1117 default: 1118 break; 1119 } 1120 1121 if (hw->nvm.type == e1000_nvm_flash_hw) { 1122 usec_delay(10); 1123 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1124 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1125 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1126 E1000_WRITE_FLUSH(hw); 1127 } 1128 1129 ret_val = e1000_get_auto_rd_done_generic(hw); 1130 if (ret_val) 1131 /* We don't want to continue accessing MAC registers. */ 1132 return ret_val; 1133 1134 /* Phy configuration from NVM just starts after EECD_AUTO_RD is set. 1135 * Need to wait for Phy configuration completion before accessing 1136 * NVM and Phy. 1137 */ 1138 1139 switch (hw->mac.type) { 1140 case e1000_82571: 1141 case e1000_82572: 1142 /* REQ and GNT bits need to be cleared when using AUTO_RD 1143 * to access the EEPROM. 1144 */ 1145 eecd = E1000_READ_REG(hw, E1000_EECD); 1146 eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT); 1147 E1000_WRITE_REG(hw, E1000_EECD, eecd); 1148 break; 1149 case e1000_82573: 1150 case e1000_82574: 1151 case e1000_82583: 1152 msec_delay(25); 1153 break; 1154 default: 1155 break; 1156 } 1157 1158 /* Clear any pending interrupt events. */ 1159 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1160 E1000_READ_REG(hw, E1000_ICR); 1161 1162 if (hw->mac.type == e1000_82571) { 1163 /* Install any alternate MAC address into RAR0 */ 1164 ret_val = e1000_check_alt_mac_addr_generic(hw); 1165 if (ret_val) 1166 return ret_val; 1167 1168 e1000_set_laa_state_82571(hw, TRUE); 1169 } 1170 1171 /* Reinitialize the 82571 serdes link state machine */ 1172 if (hw->phy.media_type == e1000_media_type_internal_serdes) 1173 hw->mac.serdes_link_state = e1000_serdes_link_down; 1174 1175 return E1000_SUCCESS; 1176 } 1177 1178 /** 1179 * e1000_init_hw_82571 - Initialize hardware 1180 * @hw: pointer to the HW structure 1181 * 1182 * This inits the hardware readying it for operation. 1183 **/ 1184 static s32 e1000_init_hw_82571(struct e1000_hw *hw) 1185 { 1186 struct e1000_mac_info *mac = &hw->mac; 1187 u32 reg_data; 1188 s32 ret_val; 1189 u16 i, rar_count = mac->rar_entry_count; 1190 1191 DEBUGFUNC("e1000_init_hw_82571"); 1192 1193 e1000_initialize_hw_bits_82571(hw); 1194 1195 /* Initialize identification LED */ 1196 ret_val = mac->ops.id_led_init(hw); 1197 /* An error is not fatal and we should not stop init due to this */ 1198 if (ret_val) 1199 DEBUGOUT("Error initializing identification LED\n"); 1200 1201 /* Disabling VLAN filtering */ 1202 DEBUGOUT("Initializing the IEEE VLAN\n"); 1203 mac->ops.clear_vfta(hw); 1204 1205 /* Setup the receive address. 1206 * If, however, a locally administered address was assigned to the 1207 * 82571, we must reserve a RAR for it to work around an issue where 1208 * resetting one port will reload the MAC on the other port. 1209 */ 1210 if (e1000_get_laa_state_82571(hw)) 1211 rar_count--; 1212 e1000_init_rx_addrs_generic(hw, rar_count); 1213 1214 /* Zero out the Multicast HASH table */ 1215 DEBUGOUT("Zeroing the MTA\n"); 1216 for (i = 0; i < mac->mta_reg_count; i++) 1217 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1218 1219 /* Setup link and flow control */ 1220 ret_val = mac->ops.setup_link(hw); 1221 1222 /* Set the transmit descriptor write-back policy */ 1223 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0)); 1224 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | 1225 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC); 1226 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data); 1227 1228 /* ...for both queues. */ 1229 switch (mac->type) { 1230 case e1000_82573: 1231 e1000_enable_tx_pkt_filtering_generic(hw); 1232 /* fall through */ 1233 case e1000_82574: 1234 case e1000_82583: 1235 reg_data = E1000_READ_REG(hw, E1000_GCR); 1236 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1237 E1000_WRITE_REG(hw, E1000_GCR, reg_data); 1238 break; 1239 default: 1240 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1)); 1241 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | 1242 E1000_TXDCTL_FULL_TX_DESC_WB | 1243 E1000_TXDCTL_COUNT_DESC); 1244 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data); 1245 break; 1246 } 1247 1248 /* Clear all of the statistics registers (clear on read). It is 1249 * important that we do this after we have tried to establish link 1250 * because the symbol error count will increment wildly if there 1251 * is no link. 1252 */ 1253 e1000_clear_hw_cntrs_82571(hw); 1254 1255 return ret_val; 1256 } 1257 1258 /** 1259 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits 1260 * @hw: pointer to the HW structure 1261 * 1262 * Initializes required hardware-dependent bits needed for normal operation. 1263 **/ 1264 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) 1265 { 1266 u32 reg; 1267 1268 DEBUGFUNC("e1000_initialize_hw_bits_82571"); 1269 1270 /* Transmit Descriptor Control 0 */ 1271 reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 1272 reg |= (1 << 22); 1273 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 1274 1275 /* Transmit Descriptor Control 1 */ 1276 reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 1277 reg |= (1 << 22); 1278 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 1279 1280 /* Transmit Arbitration Control 0 */ 1281 reg = E1000_READ_REG(hw, E1000_TARC(0)); 1282 reg &= ~(0xF << 27); /* 30:27 */ 1283 switch (hw->mac.type) { 1284 case e1000_82571: 1285 case e1000_82572: 1286 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); 1287 break; 1288 case e1000_82574: 1289 case e1000_82583: 1290 reg |= (1 << 26); 1291 break; 1292 default: 1293 break; 1294 } 1295 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 1296 1297 /* Transmit Arbitration Control 1 */ 1298 reg = E1000_READ_REG(hw, E1000_TARC(1)); 1299 switch (hw->mac.type) { 1300 case e1000_82571: 1301 case e1000_82572: 1302 reg &= ~((1 << 29) | (1 << 30)); 1303 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); 1304 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 1305 reg &= ~(1 << 28); 1306 else 1307 reg |= (1 << 28); 1308 E1000_WRITE_REG(hw, E1000_TARC(1), reg); 1309 break; 1310 default: 1311 break; 1312 } 1313 1314 /* Device Control */ 1315 switch (hw->mac.type) { 1316 case e1000_82573: 1317 case e1000_82574: 1318 case e1000_82583: 1319 reg = E1000_READ_REG(hw, E1000_CTRL); 1320 reg &= ~(1 << 29); 1321 E1000_WRITE_REG(hw, E1000_CTRL, reg); 1322 break; 1323 default: 1324 break; 1325 } 1326 1327 /* Extended Device Control */ 1328 switch (hw->mac.type) { 1329 case e1000_82573: 1330 case e1000_82574: 1331 case e1000_82583: 1332 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1333 reg &= ~(1 << 23); 1334 reg |= (1 << 22); 1335 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1336 break; 1337 default: 1338 break; 1339 } 1340 1341 if (hw->mac.type == e1000_82571) { 1342 reg = E1000_READ_REG(hw, E1000_PBA_ECC); 1343 reg |= E1000_PBA_ECC_CORR_EN; 1344 E1000_WRITE_REG(hw, E1000_PBA_ECC, reg); 1345 } 1346 1347 /* Workaround for hardware errata. 1348 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572 1349 */ 1350 if ((hw->mac.type == e1000_82571) || 1351 (hw->mac.type == e1000_82572)) { 1352 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1353 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN; 1354 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1355 } 1356 1357 /* Disable IPv6 extension header parsing because some malformed 1358 * IPv6 headers can hang the Rx. 1359 */ 1360 if (hw->mac.type <= e1000_82573) { 1361 reg = E1000_READ_REG(hw, E1000_RFCTL); 1362 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); 1363 E1000_WRITE_REG(hw, E1000_RFCTL, reg); 1364 } 1365 1366 /* PCI-Ex Control Registers */ 1367 switch (hw->mac.type) { 1368 case e1000_82574: 1369 case e1000_82583: 1370 reg = E1000_READ_REG(hw, E1000_GCR); 1371 reg |= (1 << 22); 1372 E1000_WRITE_REG(hw, E1000_GCR, reg); 1373 1374 /* Workaround for hardware errata. 1375 * apply workaround for hardware errata documented in errata 1376 * docs Fixes issue where some error prone or unreliable PCIe 1377 * completions are occurring, particularly with ASPM enabled. 1378 * Without fix, issue can cause Tx timeouts. 1379 */ 1380 reg = E1000_READ_REG(hw, E1000_GCR2); 1381 reg |= 1; 1382 E1000_WRITE_REG(hw, E1000_GCR2, reg); 1383 break; 1384 default: 1385 break; 1386 } 1387 1388 return; 1389 } 1390 1391 /** 1392 * e1000_clear_vfta_82571 - Clear VLAN filter table 1393 * @hw: pointer to the HW structure 1394 * 1395 * Clears the register array which contains the VLAN filter table by 1396 * setting all the values to 0. 1397 **/ 1398 static void e1000_clear_vfta_82571(struct e1000_hw *hw) 1399 { 1400 u32 offset; 1401 u32 vfta_value = 0; 1402 u32 vfta_offset = 0; 1403 u32 vfta_bit_in_reg = 0; 1404 1405 DEBUGFUNC("e1000_clear_vfta_82571"); 1406 1407 switch (hw->mac.type) { 1408 case e1000_82573: 1409 case e1000_82574: 1410 case e1000_82583: 1411 if (hw->mng_cookie.vlan_id != 0) { 1412 /* The VFTA is a 4096b bit-field, each identifying 1413 * a single VLAN ID. The following operations 1414 * determine which 32b entry (i.e. offset) into the 1415 * array we want to set the VLAN ID (i.e. bit) of 1416 * the manageability unit. 1417 */ 1418 vfta_offset = (hw->mng_cookie.vlan_id >> 1419 E1000_VFTA_ENTRY_SHIFT) & 1420 E1000_VFTA_ENTRY_MASK; 1421 vfta_bit_in_reg = 1422 1 << (hw->mng_cookie.vlan_id & 1423 E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 1424 } 1425 break; 1426 default: 1427 break; 1428 } 1429 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 1430 /* If the offset we want to clear is the same offset of the 1431 * manageability VLAN ID, then clear all bits except that of 1432 * the manageability unit. 1433 */ 1434 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 1435 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value); 1436 E1000_WRITE_FLUSH(hw); 1437 } 1438 } 1439 1440 /** 1441 * e1000_check_mng_mode_82574 - Check manageability is enabled 1442 * @hw: pointer to the HW structure 1443 * 1444 * Reads the NVM Initialization Control Word 2 and returns TRUE 1445 * (>0) if any manageability is enabled, else FALSE (0). 1446 **/ 1447 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw) 1448 { 1449 u16 data; 1450 s32 ret_val; 1451 1452 DEBUGFUNC("e1000_check_mng_mode_82574"); 1453 1454 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data); 1455 if (ret_val) 1456 return FALSE; 1457 1458 return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0; 1459 } 1460 1461 /** 1462 * e1000_led_on_82574 - Turn LED on 1463 * @hw: pointer to the HW structure 1464 * 1465 * Turn LED on. 1466 **/ 1467 static s32 e1000_led_on_82574(struct e1000_hw *hw) 1468 { 1469 u32 ctrl; 1470 u32 i; 1471 1472 DEBUGFUNC("e1000_led_on_82574"); 1473 1474 ctrl = hw->mac.ledctl_mode2; 1475 if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) { 1476 /* If no link, then turn LED on by setting the invert bit 1477 * for each LED that's "on" (0x0E) in ledctl_mode2. 1478 */ 1479 for (i = 0; i < 4; i++) 1480 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1481 E1000_LEDCTL_MODE_LED_ON) 1482 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8)); 1483 } 1484 E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl); 1485 1486 return E1000_SUCCESS; 1487 } 1488 1489 /** 1490 * e1000_check_phy_82574 - check 82574 phy hung state 1491 * @hw: pointer to the HW structure 1492 * 1493 * Returns whether phy is hung or not 1494 **/ 1495 bool e1000_check_phy_82574(struct e1000_hw *hw) 1496 { 1497 u16 status_1kbt = 0; 1498 u16 receive_errors = 0; 1499 s32 ret_val; 1500 1501 DEBUGFUNC("e1000_check_phy_82574"); 1502 1503 /* Read PHY Receive Error counter first, if its is max - all F's then 1504 * read the Base1000T status register If both are max then PHY is hung. 1505 */ 1506 ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER, 1507 &receive_errors); 1508 if (ret_val) 1509 return FALSE; 1510 if (receive_errors == E1000_RECEIVE_ERROR_MAX) { 1511 ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS, 1512 &status_1kbt); 1513 if (ret_val) 1514 return FALSE; 1515 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) == 1516 E1000_IDLE_ERROR_COUNT_MASK) 1517 return TRUE; 1518 } 1519 1520 return FALSE; 1521 } 1522 1523 1524 /** 1525 * e1000_setup_link_82571 - Setup flow control and link settings 1526 * @hw: pointer to the HW structure 1527 * 1528 * Determines which flow control settings to use, then configures flow 1529 * control. Calls the appropriate media-specific link configuration 1530 * function. Assuming the adapter has a valid link partner, a valid link 1531 * should be established. Assumes the hardware has previously been reset 1532 * and the transmitter and receiver are not enabled. 1533 **/ 1534 static s32 e1000_setup_link_82571(struct e1000_hw *hw) 1535 { 1536 DEBUGFUNC("e1000_setup_link_82571"); 1537 1538 /* 82573 does not have a word in the NVM to determine 1539 * the default flow control setting, so we explicitly 1540 * set it to full. 1541 */ 1542 switch (hw->mac.type) { 1543 case e1000_82573: 1544 case e1000_82574: 1545 case e1000_82583: 1546 if (hw->fc.requested_mode == e1000_fc_default) 1547 hw->fc.requested_mode = e1000_fc_full; 1548 break; 1549 default: 1550 break; 1551 } 1552 1553 return e1000_setup_link_generic(hw); 1554 } 1555 1556 /** 1557 * e1000_setup_copper_link_82571 - Configure copper link settings 1558 * @hw: pointer to the HW structure 1559 * 1560 * Configures the link for auto-neg or forced speed and duplex. Then we check 1561 * for link, once link is established calls to configure collision distance 1562 * and flow control are called. 1563 **/ 1564 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) 1565 { 1566 u32 ctrl; 1567 s32 ret_val; 1568 1569 DEBUGFUNC("e1000_setup_copper_link_82571"); 1570 1571 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1572 ctrl |= E1000_CTRL_SLU; 1573 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1574 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1575 1576 switch (hw->phy.type) { 1577 case e1000_phy_m88: 1578 case e1000_phy_bm: 1579 ret_val = e1000_copper_link_setup_m88(hw); 1580 break; 1581 case e1000_phy_igp_2: 1582 ret_val = e1000_copper_link_setup_igp(hw); 1583 break; 1584 default: 1585 return -E1000_ERR_PHY; 1586 break; 1587 } 1588 1589 if (ret_val) 1590 return ret_val; 1591 1592 return e1000_setup_copper_link_generic(hw); 1593 } 1594 1595 /** 1596 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes 1597 * @hw: pointer to the HW structure 1598 * 1599 * Configures collision distance and flow control for fiber and serdes links. 1600 * Upon successful setup, poll for link. 1601 **/ 1602 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) 1603 { 1604 DEBUGFUNC("e1000_setup_fiber_serdes_link_82571"); 1605 1606 switch (hw->mac.type) { 1607 case e1000_82571: 1608 case e1000_82572: 1609 /* If SerDes loopback mode is entered, there is no form 1610 * of reset to take the adapter out of that mode. So we 1611 * have to explicitly take the adapter out of loopback 1612 * mode. This prevents drivers from twiddling their thumbs 1613 * if another tool failed to take it out of loopback mode. 1614 */ 1615 E1000_WRITE_REG(hw, E1000_SCTL, 1616 E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1617 break; 1618 default: 1619 break; 1620 } 1621 1622 return e1000_setup_fiber_serdes_link_generic(hw); 1623 } 1624 1625 /** 1626 * e1000_check_for_serdes_link_82571 - Check for link (Serdes) 1627 * @hw: pointer to the HW structure 1628 * 1629 * Reports the link state as up or down. 1630 * 1631 * If autonegotiation is supported by the link partner, the link state is 1632 * determined by the result of autonegotiation. This is the most likely case. 1633 * If autonegotiation is not supported by the link partner, and the link 1634 * has a valid signal, force the link up. 1635 * 1636 * The link state is represented internally here by 4 states: 1637 * 1638 * 1) down 1639 * 2) autoneg_progress 1640 * 3) autoneg_complete (the link successfully autonegotiated) 1641 * 4) forced_up (the link has been forced up, it did not autonegotiate) 1642 * 1643 **/ 1644 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) 1645 { 1646 struct e1000_mac_info *mac = &hw->mac; 1647 u32 rxcw; 1648 u32 ctrl; 1649 u32 status; 1650 u32 txcw; 1651 u32 i; 1652 s32 ret_val = E1000_SUCCESS; 1653 1654 DEBUGFUNC("e1000_check_for_serdes_link_82571"); 1655 1656 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1657 status = E1000_READ_REG(hw, E1000_STATUS); 1658 E1000_READ_REG(hw, E1000_RXCW); 1659 /* SYNCH bit and IV bit are sticky */ 1660 usec_delay(10); 1661 rxcw = E1000_READ_REG(hw, E1000_RXCW); 1662 1663 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) { 1664 /* Receiver is synchronized with no invalid bits. */ 1665 switch (mac->serdes_link_state) { 1666 case e1000_serdes_link_autoneg_complete: 1667 if (!(status & E1000_STATUS_LU)) { 1668 /* We have lost link, retry autoneg before 1669 * reporting link failure 1670 */ 1671 mac->serdes_link_state = 1672 e1000_serdes_link_autoneg_progress; 1673 mac->serdes_has_link = FALSE; 1674 DEBUGOUT("AN_UP -> AN_PROG\n"); 1675 } else { 1676 mac->serdes_has_link = TRUE; 1677 } 1678 break; 1679 1680 case e1000_serdes_link_forced_up: 1681 /* If we are receiving /C/ ordered sets, re-enable 1682 * auto-negotiation in the TXCW register and disable 1683 * forced link in the Device Control register in an 1684 * attempt to auto-negotiate with our link partner. 1685 */ 1686 if (rxcw & E1000_RXCW_C) { 1687 /* Enable autoneg, and unforce link up */ 1688 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1689 E1000_WRITE_REG(hw, E1000_CTRL, 1690 (ctrl & ~E1000_CTRL_SLU)); 1691 mac->serdes_link_state = 1692 e1000_serdes_link_autoneg_progress; 1693 mac->serdes_has_link = FALSE; 1694 DEBUGOUT("FORCED_UP -> AN_PROG\n"); 1695 } else { 1696 mac->serdes_has_link = TRUE; 1697 } 1698 break; 1699 1700 case e1000_serdes_link_autoneg_progress: 1701 if (rxcw & E1000_RXCW_C) { 1702 /* We received /C/ ordered sets, meaning the 1703 * link partner has autonegotiated, and we can 1704 * trust the Link Up (LU) status bit. 1705 */ 1706 if (status & E1000_STATUS_LU) { 1707 mac->serdes_link_state = 1708 e1000_serdes_link_autoneg_complete; 1709 DEBUGOUT("AN_PROG -> AN_UP\n"); 1710 mac->serdes_has_link = TRUE; 1711 } else { 1712 /* Autoneg completed, but failed. */ 1713 mac->serdes_link_state = 1714 e1000_serdes_link_down; 1715 DEBUGOUT("AN_PROG -> DOWN\n"); 1716 } 1717 } else { 1718 /* The link partner did not autoneg. 1719 * Force link up and full duplex, and change 1720 * state to forced. 1721 */ 1722 E1000_WRITE_REG(hw, E1000_TXCW, 1723 (mac->txcw & ~E1000_TXCW_ANE)); 1724 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 1725 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1726 1727 /* Configure Flow Control after link up. */ 1728 ret_val = 1729 e1000_config_fc_after_link_up_generic(hw); 1730 if (ret_val) { 1731 DEBUGOUT("Error config flow control\n"); 1732 break; 1733 } 1734 mac->serdes_link_state = 1735 e1000_serdes_link_forced_up; 1736 mac->serdes_has_link = TRUE; 1737 DEBUGOUT("AN_PROG -> FORCED_UP\n"); 1738 } 1739 break; 1740 1741 case e1000_serdes_link_down: 1742 default: 1743 /* The link was down but the receiver has now gained 1744 * valid sync, so lets see if we can bring the link 1745 * up. 1746 */ 1747 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1748 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & 1749 ~E1000_CTRL_SLU)); 1750 mac->serdes_link_state = 1751 e1000_serdes_link_autoneg_progress; 1752 mac->serdes_has_link = FALSE; 1753 DEBUGOUT("DOWN -> AN_PROG\n"); 1754 break; 1755 } 1756 } else { 1757 if (!(rxcw & E1000_RXCW_SYNCH)) { 1758 mac->serdes_has_link = FALSE; 1759 mac->serdes_link_state = e1000_serdes_link_down; 1760 DEBUGOUT("ANYSTATE -> DOWN\n"); 1761 } else { 1762 /* Check several times, if SYNCH bit and CONFIG 1763 * bit both are consistently 1 then simply ignore 1764 * the IV bit and restart Autoneg 1765 */ 1766 for (i = 0; i < AN_RETRY_COUNT; i++) { 1767 usec_delay(10); 1768 rxcw = E1000_READ_REG(hw, E1000_RXCW); 1769 if ((rxcw & E1000_RXCW_SYNCH) && 1770 (rxcw & E1000_RXCW_C)) 1771 continue; 1772 1773 if (rxcw & E1000_RXCW_IV) { 1774 mac->serdes_has_link = FALSE; 1775 mac->serdes_link_state = 1776 e1000_serdes_link_down; 1777 DEBUGOUT("ANYSTATE -> DOWN\n"); 1778 break; 1779 } 1780 } 1781 1782 if (i == AN_RETRY_COUNT) { 1783 txcw = E1000_READ_REG(hw, E1000_TXCW); 1784 txcw |= E1000_TXCW_ANE; 1785 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1786 mac->serdes_link_state = 1787 e1000_serdes_link_autoneg_progress; 1788 mac->serdes_has_link = FALSE; 1789 DEBUGOUT("ANYSTATE -> AN_PROG\n"); 1790 } 1791 } 1792 } 1793 1794 return ret_val; 1795 } 1796 1797 /** 1798 * e1000_valid_led_default_82571 - Verify a valid default LED config 1799 * @hw: pointer to the HW structure 1800 * @data: pointer to the NVM (EEPROM) 1801 * 1802 * Read the EEPROM for the current default LED configuration. If the 1803 * LED configuration is not valid, set to a valid LED configuration. 1804 **/ 1805 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) 1806 { 1807 s32 ret_val; 1808 1809 DEBUGFUNC("e1000_valid_led_default_82571"); 1810 1811 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1812 if (ret_val) { 1813 DEBUGOUT("NVM Read Error\n"); 1814 return ret_val; 1815 } 1816 1817 switch (hw->mac.type) { 1818 case e1000_82573: 1819 case e1000_82574: 1820 case e1000_82583: 1821 if (*data == ID_LED_RESERVED_F746) 1822 *data = ID_LED_DEFAULT_82573; 1823 break; 1824 default: 1825 if (*data == ID_LED_RESERVED_0000 || 1826 *data == ID_LED_RESERVED_FFFF) 1827 *data = ID_LED_DEFAULT; 1828 break; 1829 } 1830 1831 return E1000_SUCCESS; 1832 } 1833 1834 /** 1835 * e1000_get_laa_state_82571 - Get locally administered address state 1836 * @hw: pointer to the HW structure 1837 * 1838 * Retrieve and return the current locally administered address state. 1839 **/ 1840 bool e1000_get_laa_state_82571(struct e1000_hw *hw) 1841 { 1842 DEBUGFUNC("e1000_get_laa_state_82571"); 1843 1844 if (hw->mac.type != e1000_82571) 1845 return FALSE; 1846 1847 return hw->dev_spec._82571.laa_is_present; 1848 } 1849 1850 /** 1851 * e1000_set_laa_state_82571 - Set locally administered address state 1852 * @hw: pointer to the HW structure 1853 * @state: enable/disable locally administered address 1854 * 1855 * Enable/Disable the current locally administered address state. 1856 **/ 1857 void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state) 1858 { 1859 DEBUGFUNC("e1000_set_laa_state_82571"); 1860 1861 if (hw->mac.type != e1000_82571) 1862 return; 1863 1864 hw->dev_spec._82571.laa_is_present = state; 1865 1866 /* If workaround is activated... */ 1867 if (state) 1868 /* Hold a copy of the LAA in RAR[14] This is done so that 1869 * between the time RAR[0] gets clobbered and the time it 1870 * gets fixed, the actual LAA is in one of the RARs and no 1871 * incoming packets directed to this port are dropped. 1872 * Eventually the LAA will be in RAR[0] and RAR[14]. 1873 */ 1874 hw->mac.ops.rar_set(hw, hw->mac.addr, 1875 hw->mac.rar_entry_count - 1); 1876 return; 1877 } 1878 1879 /** 1880 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum 1881 * @hw: pointer to the HW structure 1882 * 1883 * Verifies that the EEPROM has completed the update. After updating the 1884 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If 1885 * the checksum fix is not implemented, we need to set the bit and update 1886 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, 1887 * we need to return bad checksum. 1888 **/ 1889 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) 1890 { 1891 struct e1000_nvm_info *nvm = &hw->nvm; 1892 s32 ret_val; 1893 u16 data; 1894 1895 DEBUGFUNC("e1000_fix_nvm_checksum_82571"); 1896 1897 if (nvm->type != e1000_nvm_flash_hw) 1898 return E1000_SUCCESS; 1899 1900 /* Check bit 4 of word 10h. If it is 0, firmware is done updating 1901 * 10h-12h. Checksum may need to be fixed. 1902 */ 1903 ret_val = nvm->ops.read(hw, 0x10, 1, &data); 1904 if (ret_val) 1905 return ret_val; 1906 1907 if (!(data & 0x10)) { 1908 /* Read 0x23 and check bit 15. This bit is a 1 1909 * when the checksum has already been fixed. If 1910 * the checksum is still wrong and this bit is a 1911 * 1, we need to return bad checksum. Otherwise, 1912 * we need to set this bit to a 1 and update the 1913 * checksum. 1914 */ 1915 ret_val = nvm->ops.read(hw, 0x23, 1, &data); 1916 if (ret_val) 1917 return ret_val; 1918 1919 if (!(data & 0x8000)) { 1920 data |= 0x8000; 1921 ret_val = nvm->ops.write(hw, 0x23, 1, &data); 1922 if (ret_val) 1923 return ret_val; 1924 ret_val = nvm->ops.update(hw); 1925 if (ret_val) 1926 return ret_val; 1927 } 1928 } 1929 1930 return E1000_SUCCESS; 1931 } 1932 1933 1934 /** 1935 * e1000_read_mac_addr_82571 - Read device MAC address 1936 * @hw: pointer to the HW structure 1937 **/ 1938 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw) 1939 { 1940 DEBUGFUNC("e1000_read_mac_addr_82571"); 1941 1942 if (hw->mac.type == e1000_82571) { 1943 s32 ret_val; 1944 1945 /* If there's an alternate MAC address place it in RAR0 1946 * so that it will override the Si installed default perm 1947 * address. 1948 */ 1949 ret_val = e1000_check_alt_mac_addr_generic(hw); 1950 if (ret_val) 1951 return ret_val; 1952 } 1953 1954 return e1000_read_mac_addr_generic(hw); 1955 } 1956 1957 /** 1958 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down 1959 * @hw: pointer to the HW structure 1960 * 1961 * In the case of a PHY power down to save power, or to turn off link during a 1962 * driver unload, or wake on lan is not enabled, remove the link. 1963 **/ 1964 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw) 1965 { 1966 struct e1000_phy_info *phy = &hw->phy; 1967 struct e1000_mac_info *mac = &hw->mac; 1968 1969 if (!phy->ops.check_reset_block) 1970 return; 1971 1972 /* If the management interface is not enabled, then power down */ 1973 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) 1974 e1000_power_down_phy_copper(hw); 1975 1976 return; 1977 } 1978 1979 /** 1980 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters 1981 * @hw: pointer to the HW structure 1982 * 1983 * Clears the hardware counters by reading the counter registers. 1984 **/ 1985 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) 1986 { 1987 DEBUGFUNC("e1000_clear_hw_cntrs_82571"); 1988 1989 e1000_clear_hw_cntrs_base_generic(hw); 1990 1991 E1000_READ_REG(hw, E1000_PRC64); 1992 E1000_READ_REG(hw, E1000_PRC127); 1993 E1000_READ_REG(hw, E1000_PRC255); 1994 E1000_READ_REG(hw, E1000_PRC511); 1995 E1000_READ_REG(hw, E1000_PRC1023); 1996 E1000_READ_REG(hw, E1000_PRC1522); 1997 E1000_READ_REG(hw, E1000_PTC64); 1998 E1000_READ_REG(hw, E1000_PTC127); 1999 E1000_READ_REG(hw, E1000_PTC255); 2000 E1000_READ_REG(hw, E1000_PTC511); 2001 E1000_READ_REG(hw, E1000_PTC1023); 2002 E1000_READ_REG(hw, E1000_PTC1522); 2003 2004 E1000_READ_REG(hw, E1000_ALGNERRC); 2005 E1000_READ_REG(hw, E1000_RXERRC); 2006 E1000_READ_REG(hw, E1000_TNCRS); 2007 E1000_READ_REG(hw, E1000_CEXTERR); 2008 E1000_READ_REG(hw, E1000_TSCTC); 2009 E1000_READ_REG(hw, E1000_TSCTFC); 2010 2011 E1000_READ_REG(hw, E1000_MGTPRC); 2012 E1000_READ_REG(hw, E1000_MGTPDC); 2013 E1000_READ_REG(hw, E1000_MGTPTC); 2014 2015 E1000_READ_REG(hw, E1000_IAC); 2016 E1000_READ_REG(hw, E1000_ICRXOC); 2017 2018 E1000_READ_REG(hw, E1000_ICRXPTC); 2019 E1000_READ_REG(hw, E1000_ICRXATC); 2020 E1000_READ_REG(hw, E1000_ICTXPTC); 2021 E1000_READ_REG(hw, E1000_ICTXATC); 2022 E1000_READ_REG(hw, E1000_ICTXQEC); 2023 E1000_READ_REG(hw, E1000_ICTXQMTC); 2024 E1000_READ_REG(hw, E1000_ICRXDMTC); 2025 } 2026