1 /****************************************************************************** 2 3 Copyright (c) 2001-2011, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD:$*/ 34 35 /* 36 * 82571EB Gigabit Ethernet Controller 37 * 82571EB Gigabit Ethernet Controller (Copper) 38 * 82571EB Gigabit Ethernet Controller (Fiber) 39 * 82571EB Dual Port Gigabit Mezzanine Adapter 40 * 82571EB Quad Port Gigabit Mezzanine Adapter 41 * 82571PT Gigabit PT Quad Port Server ExpressModule 42 * 82572EI Gigabit Ethernet Controller (Copper) 43 * 82572EI Gigabit Ethernet Controller (Fiber) 44 * 82572EI Gigabit Ethernet Controller 45 * 82573V Gigabit Ethernet Controller (Copper) 46 * 82573E Gigabit Ethernet Controller (Copper) 47 * 82573L Gigabit Ethernet Controller 48 * 82574L Gigabit Network Connection 49 * 82583V Gigabit Network Connection 50 */ 51 52 #include "e1000_api.h" 53 54 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw); 55 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw); 56 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw); 57 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw); 58 static void e1000_release_nvm_82571(struct e1000_hw *hw); 59 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, 60 u16 words, u16 *data); 61 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw); 62 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw); 63 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw); 64 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, 65 bool active); 66 static s32 e1000_reset_hw_82571(struct e1000_hw *hw); 67 static s32 e1000_init_hw_82571(struct e1000_hw *hw); 68 static void e1000_clear_vfta_82571(struct e1000_hw *hw); 69 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw); 70 static s32 e1000_led_on_82574(struct e1000_hw *hw); 71 static s32 e1000_setup_link_82571(struct e1000_hw *hw); 72 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); 73 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw); 74 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); 75 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data); 76 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); 77 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw); 78 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); 79 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); 80 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); 81 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw); 82 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw); 83 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw); 84 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw); 85 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, 86 bool active); 87 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, 88 bool active); 89 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); 90 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 91 u16 words, u16 *data); 92 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw); 93 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw); 94 95 /** 96 * e1000_init_phy_params_82571 - Init PHY func ptrs. 97 * @hw: pointer to the HW structure 98 **/ 99 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) 100 { 101 struct e1000_phy_info *phy = &hw->phy; 102 s32 ret_val; 103 104 DEBUGFUNC("e1000_init_phy_params_82571"); 105 106 if (hw->phy.media_type != e1000_media_type_copper) { 107 phy->type = e1000_phy_none; 108 return E1000_SUCCESS; 109 } 110 111 phy->addr = 1; 112 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 113 phy->reset_delay_us = 100; 114 115 phy->ops.check_reset_block = e1000_check_reset_block_generic; 116 phy->ops.reset = e1000_phy_hw_reset_generic; 117 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82571; 118 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 119 phy->ops.power_up = e1000_power_up_phy_copper; 120 phy->ops.power_down = e1000_power_down_phy_copper_82571; 121 122 switch (hw->mac.type) { 123 case e1000_82571: 124 case e1000_82572: 125 phy->type = e1000_phy_igp_2; 126 phy->ops.get_cfg_done = e1000_get_cfg_done_82571; 127 phy->ops.get_info = e1000_get_phy_info_igp; 128 phy->ops.check_polarity = e1000_check_polarity_igp; 129 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 130 phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 131 phy->ops.read_reg = e1000_read_phy_reg_igp; 132 phy->ops.write_reg = e1000_write_phy_reg_igp; 133 phy->ops.acquire = e1000_get_hw_semaphore_82571; 134 phy->ops.release = e1000_put_hw_semaphore_82571; 135 break; 136 case e1000_82573: 137 phy->type = e1000_phy_m88; 138 phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 139 phy->ops.get_info = e1000_get_phy_info_m88; 140 phy->ops.check_polarity = e1000_check_polarity_m88; 141 phy->ops.commit = e1000_phy_sw_reset_generic; 142 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 143 phy->ops.get_cable_length = e1000_get_cable_length_m88; 144 phy->ops.read_reg = e1000_read_phy_reg_m88; 145 phy->ops.write_reg = e1000_write_phy_reg_m88; 146 phy->ops.acquire = e1000_get_hw_semaphore_82571; 147 phy->ops.release = e1000_put_hw_semaphore_82571; 148 break; 149 case e1000_82574: 150 case e1000_82583: 151 phy->type = e1000_phy_bm; 152 phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 153 phy->ops.get_info = e1000_get_phy_info_m88; 154 phy->ops.check_polarity = e1000_check_polarity_m88; 155 phy->ops.commit = e1000_phy_sw_reset_generic; 156 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 157 phy->ops.get_cable_length = e1000_get_cable_length_m88; 158 phy->ops.read_reg = e1000_read_phy_reg_bm2; 159 phy->ops.write_reg = e1000_write_phy_reg_bm2; 160 phy->ops.acquire = e1000_get_hw_semaphore_82574; 161 phy->ops.release = e1000_put_hw_semaphore_82574; 162 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574; 163 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574; 164 break; 165 default: 166 return -E1000_ERR_PHY; 167 break; 168 } 169 170 /* This can only be done after all function pointers are setup. */ 171 ret_val = e1000_get_phy_id_82571(hw); 172 if (ret_val) { 173 DEBUGOUT("Error getting PHY ID\n"); 174 return ret_val; 175 } 176 177 /* Verify phy id */ 178 switch (hw->mac.type) { 179 case e1000_82571: 180 case e1000_82572: 181 if (phy->id != IGP01E1000_I_PHY_ID) 182 ret_val = -E1000_ERR_PHY; 183 break; 184 case e1000_82573: 185 if (phy->id != M88E1111_I_PHY_ID) 186 ret_val = -E1000_ERR_PHY; 187 break; 188 case e1000_82574: 189 case e1000_82583: 190 if (phy->id != BME1000_E_PHY_ID_R2) 191 ret_val = -E1000_ERR_PHY; 192 break; 193 default: 194 ret_val = -E1000_ERR_PHY; 195 break; 196 } 197 198 if (ret_val) 199 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); 200 201 return ret_val; 202 } 203 204 /** 205 * e1000_init_nvm_params_82571 - Init NVM func ptrs. 206 * @hw: pointer to the HW structure 207 **/ 208 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) 209 { 210 struct e1000_nvm_info *nvm = &hw->nvm; 211 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 212 u16 size; 213 214 DEBUGFUNC("e1000_init_nvm_params_82571"); 215 216 nvm->opcode_bits = 8; 217 nvm->delay_usec = 1; 218 switch (nvm->override) { 219 case e1000_nvm_override_spi_large: 220 nvm->page_size = 32; 221 nvm->address_bits = 16; 222 break; 223 case e1000_nvm_override_spi_small: 224 nvm->page_size = 8; 225 nvm->address_bits = 8; 226 break; 227 default: 228 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 229 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 230 break; 231 } 232 233 switch (hw->mac.type) { 234 case e1000_82573: 235 case e1000_82574: 236 case e1000_82583: 237 if (((eecd >> 15) & 0x3) == 0x3) { 238 nvm->type = e1000_nvm_flash_hw; 239 nvm->word_size = 2048; 240 /* 241 * Autonomous Flash update bit must be cleared due 242 * to Flash update issue. 243 */ 244 eecd &= ~E1000_EECD_AUPDEN; 245 E1000_WRITE_REG(hw, E1000_EECD, eecd); 246 break; 247 } 248 /* Fall Through */ 249 default: 250 nvm->type = e1000_nvm_eeprom_spi; 251 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 252 E1000_EECD_SIZE_EX_SHIFT); 253 /* 254 * Added to a constant, "size" becomes the left-shift value 255 * for setting word_size. 256 */ 257 size += NVM_WORD_SIZE_BASE_SHIFT; 258 259 /* EEPROM access above 16k is unsupported */ 260 if (size > 14) 261 size = 14; 262 nvm->word_size = 1 << size; 263 break; 264 } 265 266 /* Function Pointers */ 267 switch (hw->mac.type) { 268 case e1000_82574: 269 case e1000_82583: 270 nvm->ops.acquire = e1000_get_hw_semaphore_82574; 271 nvm->ops.release = e1000_put_hw_semaphore_82574; 272 break; 273 default: 274 nvm->ops.acquire = e1000_acquire_nvm_82571; 275 nvm->ops.release = e1000_release_nvm_82571; 276 break; 277 } 278 nvm->ops.read = e1000_read_nvm_eerd; 279 nvm->ops.update = e1000_update_nvm_checksum_82571; 280 nvm->ops.validate = e1000_validate_nvm_checksum_82571; 281 nvm->ops.valid_led_default = e1000_valid_led_default_82571; 282 nvm->ops.write = e1000_write_nvm_82571; 283 284 return E1000_SUCCESS; 285 } 286 287 /** 288 * e1000_init_mac_params_82571 - Init MAC func ptrs. 289 * @hw: pointer to the HW structure 290 **/ 291 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw) 292 { 293 struct e1000_mac_info *mac = &hw->mac; 294 u32 swsm = 0; 295 u32 swsm2 = 0; 296 bool force_clear_smbi = FALSE; 297 298 DEBUGFUNC("e1000_init_mac_params_82571"); 299 300 /* Set media type and media-dependent function pointers */ 301 switch (hw->device_id) { 302 case E1000_DEV_ID_82571EB_FIBER: 303 case E1000_DEV_ID_82572EI_FIBER: 304 case E1000_DEV_ID_82571EB_QUAD_FIBER: 305 hw->phy.media_type = e1000_media_type_fiber; 306 mac->ops.setup_physical_interface = 307 e1000_setup_fiber_serdes_link_82571; 308 mac->ops.check_for_link = e1000_check_for_fiber_link_generic; 309 mac->ops.get_link_up_info = 310 e1000_get_speed_and_duplex_fiber_serdes_generic; 311 break; 312 case E1000_DEV_ID_82571EB_SERDES: 313 case E1000_DEV_ID_82571EB_SERDES_DUAL: 314 case E1000_DEV_ID_82571EB_SERDES_QUAD: 315 case E1000_DEV_ID_82572EI_SERDES: 316 hw->phy.media_type = e1000_media_type_internal_serdes; 317 mac->ops.setup_physical_interface = 318 e1000_setup_fiber_serdes_link_82571; 319 mac->ops.check_for_link = e1000_check_for_serdes_link_82571; 320 mac->ops.get_link_up_info = 321 e1000_get_speed_and_duplex_fiber_serdes_generic; 322 break; 323 default: 324 hw->phy.media_type = e1000_media_type_copper; 325 mac->ops.setup_physical_interface = 326 e1000_setup_copper_link_82571; 327 mac->ops.check_for_link = e1000_check_for_copper_link_generic; 328 mac->ops.get_link_up_info = 329 e1000_get_speed_and_duplex_copper_generic; 330 break; 331 } 332 333 /* Set mta register count */ 334 mac->mta_reg_count = 128; 335 /* Set rar entry count */ 336 mac->rar_entry_count = E1000_RAR_ENTRIES; 337 /* Set if part includes ASF firmware */ 338 mac->asf_firmware_present = TRUE; 339 /* Adaptive IFS supported */ 340 mac->adaptive_ifs = TRUE; 341 342 /* Function pointers */ 343 344 /* bus type/speed/width */ 345 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 346 /* reset */ 347 mac->ops.reset_hw = e1000_reset_hw_82571; 348 /* hw initialization */ 349 mac->ops.init_hw = e1000_init_hw_82571; 350 /* link setup */ 351 mac->ops.setup_link = e1000_setup_link_82571; 352 /* multicast address update */ 353 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 354 /* writing VFTA */ 355 mac->ops.write_vfta = e1000_write_vfta_generic; 356 /* clearing VFTA */ 357 mac->ops.clear_vfta = e1000_clear_vfta_82571; 358 /* read mac address */ 359 mac->ops.read_mac_addr = e1000_read_mac_addr_82571; 360 /* ID LED init */ 361 mac->ops.id_led_init = e1000_id_led_init_generic; 362 /* setup LED */ 363 mac->ops.setup_led = e1000_setup_led_generic; 364 /* cleanup LED */ 365 mac->ops.cleanup_led = e1000_cleanup_led_generic; 366 /* turn off LED */ 367 mac->ops.led_off = e1000_led_off_generic; 368 /* clear hardware counters */ 369 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571; 370 371 /* MAC-specific function pointers */ 372 switch (hw->mac.type) { 373 case e1000_82573: 374 mac->ops.set_lan_id = e1000_set_lan_id_single_port; 375 mac->ops.check_mng_mode = e1000_check_mng_mode_generic; 376 mac->ops.led_on = e1000_led_on_generic; 377 mac->ops.blink_led = e1000_blink_led_generic; 378 379 /* FWSM register */ 380 mac->has_fwsm = TRUE; 381 /* 382 * ARC supported; valid only if manageability features are 383 * enabled. 384 */ 385 mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) & 386 E1000_FWSM_MODE_MASK); 387 break; 388 case e1000_82574: 389 case e1000_82583: 390 mac->ops.set_lan_id = e1000_set_lan_id_single_port; 391 mac->ops.check_mng_mode = e1000_check_mng_mode_82574; 392 mac->ops.led_on = e1000_led_on_82574; 393 break; 394 default: 395 mac->ops.check_mng_mode = e1000_check_mng_mode_generic; 396 mac->ops.led_on = e1000_led_on_generic; 397 mac->ops.blink_led = e1000_blink_led_generic; 398 399 /* FWSM register */ 400 mac->has_fwsm = TRUE; 401 break; 402 } 403 404 /* 405 * Ensure that the inter-port SWSM.SMBI lock bit is clear before 406 * first NVM or PHY acess. This should be done for single-port 407 * devices, and for one port only on dual-port devices so that 408 * for those devices we can still use the SMBI lock to synchronize 409 * inter-port accesses to the PHY & NVM. 410 */ 411 switch (hw->mac.type) { 412 case e1000_82571: 413 case e1000_82572: 414 swsm2 = E1000_READ_REG(hw, E1000_SWSM2); 415 416 if (!(swsm2 & E1000_SWSM2_LOCK)) { 417 /* Only do this for the first interface on this card */ 418 E1000_WRITE_REG(hw, E1000_SWSM2, swsm2 | 419 E1000_SWSM2_LOCK); 420 force_clear_smbi = TRUE; 421 } else { 422 force_clear_smbi = FALSE; 423 } 424 break; 425 default: 426 force_clear_smbi = TRUE; 427 break; 428 } 429 430 if (force_clear_smbi) { 431 /* Make sure SWSM.SMBI is clear */ 432 swsm = E1000_READ_REG(hw, E1000_SWSM); 433 if (swsm & E1000_SWSM_SMBI) { 434 /* This bit should not be set on a first interface, and 435 * indicates that the bootagent or EFI code has 436 * improperly left this bit enabled 437 */ 438 DEBUGOUT("Please update your 82571 Bootagent\n"); 439 } 440 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI); 441 } 442 443 /* 444 * Initialze device specific counter of SMBI acquisition 445 * timeouts. 446 */ 447 hw->dev_spec._82571.smb_counter = 0; 448 449 return E1000_SUCCESS; 450 } 451 452 /** 453 * e1000_init_function_pointers_82571 - Init func ptrs. 454 * @hw: pointer to the HW structure 455 * 456 * Called to initialize all function pointers and parameters. 457 **/ 458 void e1000_init_function_pointers_82571(struct e1000_hw *hw) 459 { 460 DEBUGFUNC("e1000_init_function_pointers_82571"); 461 462 hw->mac.ops.init_params = e1000_init_mac_params_82571; 463 hw->nvm.ops.init_params = e1000_init_nvm_params_82571; 464 hw->phy.ops.init_params = e1000_init_phy_params_82571; 465 } 466 467 /** 468 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision 469 * @hw: pointer to the HW structure 470 * 471 * Reads the PHY registers and stores the PHY ID and possibly the PHY 472 * revision in the hardware structure. 473 **/ 474 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) 475 { 476 struct e1000_phy_info *phy = &hw->phy; 477 s32 ret_val; 478 u16 phy_id = 0; 479 480 DEBUGFUNC("e1000_get_phy_id_82571"); 481 482 switch (hw->mac.type) { 483 case e1000_82571: 484 case e1000_82572: 485 /* 486 * The 82571 firmware may still be configuring the PHY. 487 * In this case, we cannot access the PHY until the 488 * configuration is done. So we explicitly set the 489 * PHY ID. 490 */ 491 phy->id = IGP01E1000_I_PHY_ID; 492 break; 493 case e1000_82573: 494 return e1000_get_phy_id(hw); 495 break; 496 case e1000_82574: 497 case e1000_82583: 498 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 499 if (ret_val) 500 return ret_val; 501 502 phy->id = (u32)(phy_id << 16); 503 usec_delay(20); 504 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 505 if (ret_val) 506 return ret_val; 507 508 phy->id |= (u32)(phy_id); 509 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 510 break; 511 default: 512 return -E1000_ERR_PHY; 513 break; 514 } 515 516 return E1000_SUCCESS; 517 } 518 519 /** 520 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore 521 * @hw: pointer to the HW structure 522 * 523 * Acquire the HW semaphore to access the PHY or NVM 524 **/ 525 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) 526 { 527 u32 swsm; 528 s32 sw_timeout = hw->nvm.word_size + 1; 529 s32 fw_timeout = hw->nvm.word_size + 1; 530 s32 i = 0; 531 532 DEBUGFUNC("e1000_get_hw_semaphore_82571"); 533 534 /* 535 * If we have timedout 3 times on trying to acquire 536 * the inter-port SMBI semaphore, there is old code 537 * operating on the other port, and it is not 538 * releasing SMBI. Modify the number of times that 539 * we try for the semaphore to interwork with this 540 * older code. 541 */ 542 if (hw->dev_spec._82571.smb_counter > 2) 543 sw_timeout = 1; 544 545 /* Get the SW semaphore */ 546 while (i < sw_timeout) { 547 swsm = E1000_READ_REG(hw, E1000_SWSM); 548 if (!(swsm & E1000_SWSM_SMBI)) 549 break; 550 551 usec_delay(50); 552 i++; 553 } 554 555 if (i == sw_timeout) { 556 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 557 hw->dev_spec._82571.smb_counter++; 558 } 559 /* Get the FW semaphore. */ 560 for (i = 0; i < fw_timeout; i++) { 561 swsm = E1000_READ_REG(hw, E1000_SWSM); 562 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 563 564 /* Semaphore acquired if bit latched */ 565 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 566 break; 567 568 usec_delay(50); 569 } 570 571 if (i == fw_timeout) { 572 /* Release semaphores */ 573 e1000_put_hw_semaphore_82571(hw); 574 DEBUGOUT("Driver can't access the NVM\n"); 575 return -E1000_ERR_NVM; 576 } 577 578 return E1000_SUCCESS; 579 } 580 581 /** 582 * e1000_put_hw_semaphore_82571 - Release hardware semaphore 583 * @hw: pointer to the HW structure 584 * 585 * Release hardware semaphore used to access the PHY or NVM 586 **/ 587 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) 588 { 589 u32 swsm; 590 591 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 592 593 swsm = E1000_READ_REG(hw, E1000_SWSM); 594 595 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 596 597 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 598 } 599 600 /** 601 * e1000_get_hw_semaphore_82573 - Acquire hardware semaphore 602 * @hw: pointer to the HW structure 603 * 604 * Acquire the HW semaphore during reset. 605 * 606 **/ 607 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw) 608 { 609 u32 extcnf_ctrl; 610 s32 i = 0; 611 612 DEBUGFUNC("e1000_get_hw_semaphore_82573"); 613 614 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 615 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 616 do { 617 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 618 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 619 620 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 621 break; 622 623 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 624 625 msec_delay(2); 626 i++; 627 } while (i < MDIO_OWNERSHIP_TIMEOUT); 628 629 if (i == MDIO_OWNERSHIP_TIMEOUT) { 630 /* Release semaphores */ 631 e1000_put_hw_semaphore_82573(hw); 632 DEBUGOUT("Driver can't access the PHY\n"); 633 return -E1000_ERR_PHY; 634 } 635 636 return E1000_SUCCESS; 637 } 638 639 /** 640 * e1000_put_hw_semaphore_82573 - Release hardware semaphore 641 * @hw: pointer to the HW structure 642 * 643 * Release hardware semaphore used during reset. 644 * 645 **/ 646 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw) 647 { 648 u32 extcnf_ctrl; 649 650 DEBUGFUNC("e1000_put_hw_semaphore_82573"); 651 652 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 653 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 654 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 655 } 656 657 /** 658 * e1000_get_hw_semaphore_82574 - Acquire hardware semaphore 659 * @hw: pointer to the HW structure 660 * 661 * Acquire the HW semaphore to access the PHY or NVM. 662 * 663 **/ 664 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw) 665 { 666 s32 ret_val; 667 668 DEBUGFUNC("e1000_get_hw_semaphore_82574"); 669 670 ret_val = e1000_get_hw_semaphore_82573(hw); 671 return ret_val; 672 } 673 674 /** 675 * e1000_put_hw_semaphore_82574 - Release hardware semaphore 676 * @hw: pointer to the HW structure 677 * 678 * Release hardware semaphore used to access the PHY or NVM 679 * 680 **/ 681 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw) 682 { 683 DEBUGFUNC("e1000_put_hw_semaphore_82574"); 684 685 e1000_put_hw_semaphore_82573(hw); 686 } 687 688 /** 689 * e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state 690 * @hw: pointer to the HW structure 691 * @active: TRUE to enable LPLU, FALSE to disable 692 * 693 * Sets the LPLU D0 state according to the active flag. 694 * LPLU will not be activated unless the 695 * device autonegotiation advertisement meets standards of 696 * either 10 or 10/100 or 10/100/1000 at all duplexes. 697 * This is a function pointer entry point only called by 698 * PHY setup routines. 699 **/ 700 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active) 701 { 702 u16 data = E1000_READ_REG(hw, E1000_POEMB); 703 704 DEBUGFUNC("e1000_set_d0_lplu_state_82574"); 705 706 if (active) 707 data |= E1000_PHY_CTRL_D0A_LPLU; 708 else 709 data &= ~E1000_PHY_CTRL_D0A_LPLU; 710 711 E1000_WRITE_REG(hw, E1000_POEMB, data); 712 return E1000_SUCCESS; 713 } 714 715 /** 716 * e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3 717 * @hw: pointer to the HW structure 718 * @active: boolean used to enable/disable lplu 719 * 720 * The low power link up (lplu) state is set to the power management level D3 721 * when active is TRUE, else clear lplu for D3. LPLU 722 * is used during Dx states where the power conservation is most important. 723 * During driver activity, SmartSpeed should be enabled so performance is 724 * maintained. 725 **/ 726 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active) 727 { 728 u16 data = E1000_READ_REG(hw, E1000_POEMB); 729 730 DEBUGFUNC("e1000_set_d3_lplu_state_82574"); 731 732 if (!active) { 733 data &= ~E1000_PHY_CTRL_NOND0A_LPLU; 734 } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 735 (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) || 736 (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) { 737 data |= E1000_PHY_CTRL_NOND0A_LPLU; 738 } 739 740 E1000_WRITE_REG(hw, E1000_POEMB, data); 741 return E1000_SUCCESS; 742 } 743 744 /** 745 * e1000_acquire_nvm_82571 - Request for access to the EEPROM 746 * @hw: pointer to the HW structure 747 * 748 * To gain access to the EEPROM, first we must obtain a hardware semaphore. 749 * Then for non-82573 hardware, set the EEPROM access request bit and wait 750 * for EEPROM access grant bit. If the access grant bit is not set, release 751 * hardware semaphore. 752 **/ 753 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) 754 { 755 s32 ret_val; 756 757 DEBUGFUNC("e1000_acquire_nvm_82571"); 758 759 ret_val = e1000_get_hw_semaphore_82571(hw); 760 if (ret_val) 761 return ret_val; 762 763 switch (hw->mac.type) { 764 case e1000_82573: 765 break; 766 default: 767 ret_val = e1000_acquire_nvm_generic(hw); 768 break; 769 } 770 771 if (ret_val) 772 e1000_put_hw_semaphore_82571(hw); 773 774 return ret_val; 775 } 776 777 /** 778 * e1000_release_nvm_82571 - Release exclusive access to EEPROM 779 * @hw: pointer to the HW structure 780 * 781 * Stop any current commands to the EEPROM and clear the EEPROM request bit. 782 **/ 783 static void e1000_release_nvm_82571(struct e1000_hw *hw) 784 { 785 DEBUGFUNC("e1000_release_nvm_82571"); 786 787 e1000_release_nvm_generic(hw); 788 e1000_put_hw_semaphore_82571(hw); 789 } 790 791 /** 792 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface 793 * @hw: pointer to the HW structure 794 * @offset: offset within the EEPROM to be written to 795 * @words: number of words to write 796 * @data: 16 bit word(s) to be written to the EEPROM 797 * 798 * For non-82573 silicon, write data to EEPROM at offset using SPI interface. 799 * 800 * If e1000_update_nvm_checksum is not called after this function, the 801 * EEPROM will most likely contain an invalid checksum. 802 **/ 803 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, 804 u16 *data) 805 { 806 s32 ret_val; 807 808 DEBUGFUNC("e1000_write_nvm_82571"); 809 810 switch (hw->mac.type) { 811 case e1000_82573: 812 case e1000_82574: 813 case e1000_82583: 814 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); 815 break; 816 case e1000_82571: 817 case e1000_82572: 818 ret_val = e1000_write_nvm_spi(hw, offset, words, data); 819 break; 820 default: 821 ret_val = -E1000_ERR_NVM; 822 break; 823 } 824 825 return ret_val; 826 } 827 828 /** 829 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum 830 * @hw: pointer to the HW structure 831 * 832 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 833 * up to the checksum. Then calculates the EEPROM checksum and writes the 834 * value to the EEPROM. 835 **/ 836 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) 837 { 838 u32 eecd; 839 s32 ret_val; 840 u16 i; 841 842 DEBUGFUNC("e1000_update_nvm_checksum_82571"); 843 844 ret_val = e1000_update_nvm_checksum_generic(hw); 845 if (ret_val) 846 return ret_val; 847 848 /* 849 * If our nvm is an EEPROM, then we're done 850 * otherwise, commit the checksum to the flash NVM. 851 */ 852 if (hw->nvm.type != e1000_nvm_flash_hw) 853 return E1000_SUCCESS; 854 855 /* Check for pending operations. */ 856 for (i = 0; i < E1000_FLASH_UPDATES; i++) { 857 msec_delay(1); 858 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) 859 break; 860 } 861 862 if (i == E1000_FLASH_UPDATES) 863 return -E1000_ERR_NVM; 864 865 /* Reset the firmware if using STM opcode. */ 866 if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) { 867 /* 868 * The enabling of and the actual reset must be done 869 * in two write cycles. 870 */ 871 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE); 872 E1000_WRITE_FLUSH(hw); 873 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET); 874 } 875 876 /* Commit the write to flash */ 877 eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD; 878 E1000_WRITE_REG(hw, E1000_EECD, eecd); 879 880 for (i = 0; i < E1000_FLASH_UPDATES; i++) { 881 msec_delay(1); 882 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) 883 break; 884 } 885 886 if (i == E1000_FLASH_UPDATES) 887 return -E1000_ERR_NVM; 888 889 return E1000_SUCCESS; 890 } 891 892 /** 893 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum 894 * @hw: pointer to the HW structure 895 * 896 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 897 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 898 **/ 899 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) 900 { 901 DEBUGFUNC("e1000_validate_nvm_checksum_82571"); 902 903 if (hw->nvm.type == e1000_nvm_flash_hw) 904 e1000_fix_nvm_checksum_82571(hw); 905 906 return e1000_validate_nvm_checksum_generic(hw); 907 } 908 909 /** 910 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon 911 * @hw: pointer to the HW structure 912 * @offset: offset within the EEPROM to be written to 913 * @words: number of words to write 914 * @data: 16 bit word(s) to be written to the EEPROM 915 * 916 * After checking for invalid values, poll the EEPROM to ensure the previous 917 * command has completed before trying to write the next word. After write 918 * poll for completion. 919 * 920 * If e1000_update_nvm_checksum is not called after this function, the 921 * EEPROM will most likely contain an invalid checksum. 922 **/ 923 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 924 u16 words, u16 *data) 925 { 926 struct e1000_nvm_info *nvm = &hw->nvm; 927 u32 i, eewr = 0; 928 s32 ret_val = E1000_SUCCESS; 929 930 DEBUGFUNC("e1000_write_nvm_eewr_82571"); 931 932 /* 933 * A check for invalid values: offset too large, too many words, 934 * and not enough words. 935 */ 936 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 937 (words == 0)) { 938 DEBUGOUT("nvm parameter(s) out of bounds\n"); 939 return -E1000_ERR_NVM; 940 } 941 942 for (i = 0; i < words; i++) { 943 eewr = (data[i] << E1000_NVM_RW_REG_DATA) | 944 ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | 945 E1000_NVM_RW_REG_START; 946 947 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 948 if (ret_val) 949 break; 950 951 E1000_WRITE_REG(hw, E1000_EEWR, eewr); 952 953 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 954 if (ret_val) 955 break; 956 } 957 958 return ret_val; 959 } 960 961 /** 962 * e1000_get_cfg_done_82571 - Poll for configuration done 963 * @hw: pointer to the HW structure 964 * 965 * Reads the management control register for the config done bit to be set. 966 **/ 967 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) 968 { 969 s32 timeout = PHY_CFG_TIMEOUT; 970 971 DEBUGFUNC("e1000_get_cfg_done_82571"); 972 973 while (timeout) { 974 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & 975 E1000_NVM_CFG_DONE_PORT_0) 976 break; 977 msec_delay(1); 978 timeout--; 979 } 980 if (!timeout) { 981 DEBUGOUT("MNG configuration cycle has not completed.\n"); 982 return -E1000_ERR_RESET; 983 } 984 985 return E1000_SUCCESS; 986 } 987 988 /** 989 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state 990 * @hw: pointer to the HW structure 991 * @active: TRUE to enable LPLU, FALSE to disable 992 * 993 * Sets the LPLU D0 state according to the active flag. When activating LPLU 994 * this function also disables smart speed and vice versa. LPLU will not be 995 * activated unless the device autonegotiation advertisement meets standards 996 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function 997 * pointer entry point only called by PHY setup routines. 998 **/ 999 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) 1000 { 1001 struct e1000_phy_info *phy = &hw->phy; 1002 s32 ret_val; 1003 u16 data; 1004 1005 DEBUGFUNC("e1000_set_d0_lplu_state_82571"); 1006 1007 if (!(phy->ops.read_reg)) 1008 return E1000_SUCCESS; 1009 1010 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 1011 if (ret_val) 1012 return ret_val; 1013 1014 if (active) { 1015 data |= IGP02E1000_PM_D0_LPLU; 1016 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1017 data); 1018 if (ret_val) 1019 return ret_val; 1020 1021 /* When LPLU is enabled, we should disable SmartSpeed */ 1022 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1023 &data); 1024 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1025 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1026 data); 1027 if (ret_val) 1028 return ret_val; 1029 } else { 1030 data &= ~IGP02E1000_PM_D0_LPLU; 1031 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1032 data); 1033 /* 1034 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 1035 * during Dx states where the power conservation is most 1036 * important. During driver activity we should enable 1037 * SmartSpeed, so performance is maintained. 1038 */ 1039 if (phy->smart_speed == e1000_smart_speed_on) { 1040 ret_val = phy->ops.read_reg(hw, 1041 IGP01E1000_PHY_PORT_CONFIG, 1042 &data); 1043 if (ret_val) 1044 return ret_val; 1045 1046 data |= IGP01E1000_PSCFR_SMART_SPEED; 1047 ret_val = phy->ops.write_reg(hw, 1048 IGP01E1000_PHY_PORT_CONFIG, 1049 data); 1050 if (ret_val) 1051 return ret_val; 1052 } else if (phy->smart_speed == e1000_smart_speed_off) { 1053 ret_val = phy->ops.read_reg(hw, 1054 IGP01E1000_PHY_PORT_CONFIG, 1055 &data); 1056 if (ret_val) 1057 return ret_val; 1058 1059 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1060 ret_val = phy->ops.write_reg(hw, 1061 IGP01E1000_PHY_PORT_CONFIG, 1062 data); 1063 if (ret_val) 1064 return ret_val; 1065 } 1066 } 1067 1068 return E1000_SUCCESS; 1069 } 1070 1071 /** 1072 * e1000_reset_hw_82571 - Reset hardware 1073 * @hw: pointer to the HW structure 1074 * 1075 * This resets the hardware into a known state. 1076 **/ 1077 static s32 e1000_reset_hw_82571(struct e1000_hw *hw) 1078 { 1079 u32 ctrl, ctrl_ext; 1080 s32 ret_val; 1081 1082 DEBUGFUNC("e1000_reset_hw_82571"); 1083 1084 /* 1085 * Prevent the PCI-E bus from sticking if there is no TLP connection 1086 * on the last TLP read/write transaction when MAC is reset. 1087 */ 1088 ret_val = e1000_disable_pcie_master_generic(hw); 1089 if (ret_val) 1090 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 1091 1092 DEBUGOUT("Masking off all interrupts\n"); 1093 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1094 1095 E1000_WRITE_REG(hw, E1000_RCTL, 0); 1096 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 1097 E1000_WRITE_FLUSH(hw); 1098 1099 msec_delay(10); 1100 1101 /* 1102 * Must acquire the MDIO ownership before MAC reset. 1103 * Ownership defaults to firmware after a reset. 1104 */ 1105 switch (hw->mac.type) { 1106 case e1000_82573: 1107 ret_val = e1000_get_hw_semaphore_82573(hw); 1108 break; 1109 case e1000_82574: 1110 case e1000_82583: 1111 ret_val = e1000_get_hw_semaphore_82574(hw); 1112 break; 1113 default: 1114 break; 1115 } 1116 if (ret_val) 1117 DEBUGOUT("Cannot acquire MDIO ownership\n"); 1118 1119 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1120 1121 DEBUGOUT("Issuing a global reset to MAC\n"); 1122 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 1123 1124 /* Must release MDIO ownership and mutex after MAC reset. */ 1125 switch (hw->mac.type) { 1126 case e1000_82574: 1127 case e1000_82583: 1128 e1000_put_hw_semaphore_82574(hw); 1129 break; 1130 default: 1131 break; 1132 } 1133 1134 if (hw->nvm.type == e1000_nvm_flash_hw) { 1135 usec_delay(10); 1136 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1137 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1138 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1139 E1000_WRITE_FLUSH(hw); 1140 } 1141 1142 ret_val = e1000_get_auto_rd_done_generic(hw); 1143 if (ret_val) 1144 /* We don't want to continue accessing MAC registers. */ 1145 return ret_val; 1146 1147 /* 1148 * Phy configuration from NVM just starts after EECD_AUTO_RD is set. 1149 * Need to wait for Phy configuration completion before accessing 1150 * NVM and Phy. 1151 */ 1152 1153 switch (hw->mac.type) { 1154 case e1000_82573: 1155 case e1000_82574: 1156 case e1000_82583: 1157 msec_delay(25); 1158 break; 1159 default: 1160 break; 1161 } 1162 1163 /* Clear any pending interrupt events. */ 1164 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1165 E1000_READ_REG(hw, E1000_ICR); 1166 1167 if (hw->mac.type == e1000_82571) { 1168 /* Install any alternate MAC address into RAR0 */ 1169 ret_val = e1000_check_alt_mac_addr_generic(hw); 1170 if (ret_val) 1171 return ret_val; 1172 1173 e1000_set_laa_state_82571(hw, TRUE); 1174 } 1175 1176 /* Reinitialize the 82571 serdes link state machine */ 1177 if (hw->phy.media_type == e1000_media_type_internal_serdes) 1178 hw->mac.serdes_link_state = e1000_serdes_link_down; 1179 1180 return E1000_SUCCESS; 1181 } 1182 1183 /** 1184 * e1000_init_hw_82571 - Initialize hardware 1185 * @hw: pointer to the HW structure 1186 * 1187 * This inits the hardware readying it for operation. 1188 **/ 1189 static s32 e1000_init_hw_82571(struct e1000_hw *hw) 1190 { 1191 struct e1000_mac_info *mac = &hw->mac; 1192 u32 reg_data; 1193 s32 ret_val; 1194 u16 i, rar_count = mac->rar_entry_count; 1195 1196 DEBUGFUNC("e1000_init_hw_82571"); 1197 1198 e1000_initialize_hw_bits_82571(hw); 1199 1200 /* Initialize identification LED */ 1201 ret_val = mac->ops.id_led_init(hw); 1202 if (ret_val) 1203 DEBUGOUT("Error initializing identification LED\n"); 1204 /* This is not fatal and we should not stop init due to this */ 1205 1206 /* Disabling VLAN filtering */ 1207 DEBUGOUT("Initializing the IEEE VLAN\n"); 1208 mac->ops.clear_vfta(hw); 1209 1210 /* Setup the receive address. */ 1211 /* 1212 * If, however, a locally administered address was assigned to the 1213 * 82571, we must reserve a RAR for it to work around an issue where 1214 * resetting one port will reload the MAC on the other port. 1215 */ 1216 if (e1000_get_laa_state_82571(hw)) 1217 rar_count--; 1218 e1000_init_rx_addrs_generic(hw, rar_count); 1219 1220 /* Zero out the Multicast HASH table */ 1221 DEBUGOUT("Zeroing the MTA\n"); 1222 for (i = 0; i < mac->mta_reg_count; i++) 1223 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1224 1225 /* Setup link and flow control */ 1226 ret_val = mac->ops.setup_link(hw); 1227 1228 /* Set the transmit descriptor write-back policy */ 1229 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0)); 1230 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 1231 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; 1232 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data); 1233 1234 /* ...for both queues. */ 1235 switch (mac->type) { 1236 case e1000_82573: 1237 e1000_enable_tx_pkt_filtering_generic(hw); 1238 /* fall through */ 1239 case e1000_82574: 1240 case e1000_82583: 1241 reg_data = E1000_READ_REG(hw, E1000_GCR); 1242 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1243 E1000_WRITE_REG(hw, E1000_GCR, reg_data); 1244 break; 1245 default: 1246 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1)); 1247 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 1248 E1000_TXDCTL_FULL_TX_DESC_WB | 1249 E1000_TXDCTL_COUNT_DESC; 1250 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data); 1251 break; 1252 } 1253 1254 /* 1255 * Clear all of the statistics registers (clear on read). It is 1256 * important that we do this after we have tried to establish link 1257 * because the symbol error count will increment wildly if there 1258 * is no link. 1259 */ 1260 e1000_clear_hw_cntrs_82571(hw); 1261 1262 return ret_val; 1263 } 1264 1265 /** 1266 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits 1267 * @hw: pointer to the HW structure 1268 * 1269 * Initializes required hardware-dependent bits needed for normal operation. 1270 **/ 1271 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) 1272 { 1273 u32 reg; 1274 1275 DEBUGFUNC("e1000_initialize_hw_bits_82571"); 1276 1277 /* Transmit Descriptor Control 0 */ 1278 reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 1279 reg |= (1 << 22); 1280 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 1281 1282 /* Transmit Descriptor Control 1 */ 1283 reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 1284 reg |= (1 << 22); 1285 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 1286 1287 /* Transmit Arbitration Control 0 */ 1288 reg = E1000_READ_REG(hw, E1000_TARC(0)); 1289 reg &= ~(0xF << 27); /* 30:27 */ 1290 switch (hw->mac.type) { 1291 case e1000_82571: 1292 case e1000_82572: 1293 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); 1294 break; 1295 case e1000_82574: 1296 case e1000_82583: 1297 reg |= (1 << 26); 1298 break; 1299 default: 1300 break; 1301 } 1302 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 1303 1304 /* Transmit Arbitration Control 1 */ 1305 reg = E1000_READ_REG(hw, E1000_TARC(1)); 1306 switch (hw->mac.type) { 1307 case e1000_82571: 1308 case e1000_82572: 1309 reg &= ~((1 << 29) | (1 << 30)); 1310 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); 1311 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 1312 reg &= ~(1 << 28); 1313 else 1314 reg |= (1 << 28); 1315 E1000_WRITE_REG(hw, E1000_TARC(1), reg); 1316 break; 1317 default: 1318 break; 1319 } 1320 1321 /* Device Control */ 1322 switch (hw->mac.type) { 1323 case e1000_82573: 1324 case e1000_82574: 1325 case e1000_82583: 1326 reg = E1000_READ_REG(hw, E1000_CTRL); 1327 reg &= ~(1 << 29); 1328 E1000_WRITE_REG(hw, E1000_CTRL, reg); 1329 break; 1330 default: 1331 break; 1332 } 1333 1334 /* Extended Device Control */ 1335 switch (hw->mac.type) { 1336 case e1000_82573: 1337 case e1000_82574: 1338 case e1000_82583: 1339 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1340 reg &= ~(1 << 23); 1341 reg |= (1 << 22); 1342 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1343 break; 1344 default: 1345 break; 1346 } 1347 1348 if (hw->mac.type == e1000_82571) { 1349 reg = E1000_READ_REG(hw, E1000_PBA_ECC); 1350 reg |= E1000_PBA_ECC_CORR_EN; 1351 E1000_WRITE_REG(hw, E1000_PBA_ECC, reg); 1352 } 1353 1354 /* 1355 * Workaround for hardware errata. 1356 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572 1357 */ 1358 if ((hw->mac.type == e1000_82571) || 1359 (hw->mac.type == e1000_82572)) { 1360 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1361 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN; 1362 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1363 } 1364 1365 /* 1366 * Disable IPv6 extension header parsing because some malformed 1367 * IPv6 headers can hang the Rx. 1368 */ 1369 if (hw->mac.type <= e1000_82573) { 1370 reg = E1000_READ_REG(hw, E1000_RFCTL); 1371 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); 1372 E1000_WRITE_REG(hw, E1000_RFCTL, reg); 1373 } 1374 1375 /* PCI-Ex Control Registers */ 1376 switch (hw->mac.type) { 1377 case e1000_82574: 1378 case e1000_82583: 1379 reg = E1000_READ_REG(hw, E1000_GCR); 1380 reg |= (1 << 22); 1381 E1000_WRITE_REG(hw, E1000_GCR, reg); 1382 1383 /* 1384 * Workaround for hardware errata. 1385 * apply workaround for hardware errata documented in errata 1386 * docs Fixes issue where some error prone or unreliable PCIe 1387 * completions are occurring, particularly with ASPM enabled. 1388 * Without fix, issue can cause Tx timeouts. 1389 */ 1390 reg = E1000_READ_REG(hw, E1000_GCR2); 1391 reg |= 1; 1392 E1000_WRITE_REG(hw, E1000_GCR2, reg); 1393 break; 1394 default: 1395 break; 1396 } 1397 1398 return; 1399 } 1400 1401 /** 1402 * e1000_clear_vfta_82571 - Clear VLAN filter table 1403 * @hw: pointer to the HW structure 1404 * 1405 * Clears the register array which contains the VLAN filter table by 1406 * setting all the values to 0. 1407 **/ 1408 static void e1000_clear_vfta_82571(struct e1000_hw *hw) 1409 { 1410 u32 offset; 1411 u32 vfta_value = 0; 1412 u32 vfta_offset = 0; 1413 u32 vfta_bit_in_reg = 0; 1414 1415 DEBUGFUNC("e1000_clear_vfta_82571"); 1416 1417 switch (hw->mac.type) { 1418 case e1000_82573: 1419 case e1000_82574: 1420 case e1000_82583: 1421 if (hw->mng_cookie.vlan_id != 0) { 1422 /* 1423 * The VFTA is a 4096b bit-field, each identifying 1424 * a single VLAN ID. The following operations 1425 * determine which 32b entry (i.e. offset) into the 1426 * array we want to set the VLAN ID (i.e. bit) of 1427 * the manageability unit. 1428 */ 1429 vfta_offset = (hw->mng_cookie.vlan_id >> 1430 E1000_VFTA_ENTRY_SHIFT) & 1431 E1000_VFTA_ENTRY_MASK; 1432 vfta_bit_in_reg = 1433 1 << (hw->mng_cookie.vlan_id & 1434 E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 1435 } 1436 break; 1437 default: 1438 break; 1439 } 1440 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 1441 /* 1442 * If the offset we want to clear is the same offset of the 1443 * manageability VLAN ID, then clear all bits except that of 1444 * the manageability unit. 1445 */ 1446 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 1447 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value); 1448 E1000_WRITE_FLUSH(hw); 1449 } 1450 } 1451 1452 /** 1453 * e1000_check_mng_mode_82574 - Check manageability is enabled 1454 * @hw: pointer to the HW structure 1455 * 1456 * Reads the NVM Initialization Control Word 2 and returns TRUE 1457 * (>0) if any manageability is enabled, else FALSE (0). 1458 **/ 1459 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw) 1460 { 1461 u16 data; 1462 1463 DEBUGFUNC("e1000_check_mng_mode_82574"); 1464 1465 hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data); 1466 return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0; 1467 } 1468 1469 /** 1470 * e1000_led_on_82574 - Turn LED on 1471 * @hw: pointer to the HW structure 1472 * 1473 * Turn LED on. 1474 **/ 1475 static s32 e1000_led_on_82574(struct e1000_hw *hw) 1476 { 1477 u32 ctrl; 1478 u32 i; 1479 1480 DEBUGFUNC("e1000_led_on_82574"); 1481 1482 ctrl = hw->mac.ledctl_mode2; 1483 if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) { 1484 /* 1485 * If no link, then turn LED on by setting the invert bit 1486 * for each LED that's "on" (0x0E) in ledctl_mode2. 1487 */ 1488 for (i = 0; i < 4; i++) 1489 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1490 E1000_LEDCTL_MODE_LED_ON) 1491 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8)); 1492 } 1493 E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl); 1494 1495 return E1000_SUCCESS; 1496 } 1497 1498 /** 1499 * e1000_check_phy_82574 - check 82574 phy hung state 1500 * @hw: pointer to the HW structure 1501 * 1502 * Returns whether phy is hung or not 1503 **/ 1504 bool e1000_check_phy_82574(struct e1000_hw *hw) 1505 { 1506 u16 status_1kbt = 0; 1507 u16 receive_errors = 0; 1508 s32 ret_val = E1000_SUCCESS; 1509 1510 DEBUGFUNC("e1000_check_phy_82574"); 1511 1512 /* 1513 * Read PHY Receive Error counter first, if its is max - all F's then 1514 * read the Base1000T status register If both are max then PHY is hung. 1515 */ 1516 ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER, 1517 &receive_errors); 1518 if (ret_val) 1519 return FALSE; 1520 if (receive_errors == E1000_RECEIVE_ERROR_MAX) { 1521 ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS, 1522 &status_1kbt); 1523 if (ret_val) 1524 return FALSE; 1525 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) == 1526 E1000_IDLE_ERROR_COUNT_MASK) 1527 return TRUE; 1528 } 1529 1530 return FALSE; 1531 } 1532 1533 1534 /** 1535 * e1000_setup_link_82571 - Setup flow control and link settings 1536 * @hw: pointer to the HW structure 1537 * 1538 * Determines which flow control settings to use, then configures flow 1539 * control. Calls the appropriate media-specific link configuration 1540 * function. Assuming the adapter has a valid link partner, a valid link 1541 * should be established. Assumes the hardware has previously been reset 1542 * and the transmitter and receiver are not enabled. 1543 **/ 1544 static s32 e1000_setup_link_82571(struct e1000_hw *hw) 1545 { 1546 DEBUGFUNC("e1000_setup_link_82571"); 1547 1548 /* 1549 * 82573 does not have a word in the NVM to determine 1550 * the default flow control setting, so we explicitly 1551 * set it to full. 1552 */ 1553 switch (hw->mac.type) { 1554 case e1000_82573: 1555 case e1000_82574: 1556 case e1000_82583: 1557 if (hw->fc.requested_mode == e1000_fc_default) 1558 hw->fc.requested_mode = e1000_fc_full; 1559 break; 1560 default: 1561 break; 1562 } 1563 1564 return e1000_setup_link_generic(hw); 1565 } 1566 1567 /** 1568 * e1000_setup_copper_link_82571 - Configure copper link settings 1569 * @hw: pointer to the HW structure 1570 * 1571 * Configures the link for auto-neg or forced speed and duplex. Then we check 1572 * for link, once link is established calls to configure collision distance 1573 * and flow control are called. 1574 **/ 1575 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) 1576 { 1577 u32 ctrl; 1578 s32 ret_val; 1579 1580 DEBUGFUNC("e1000_setup_copper_link_82571"); 1581 1582 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1583 ctrl |= E1000_CTRL_SLU; 1584 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1585 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1586 1587 switch (hw->phy.type) { 1588 case e1000_phy_m88: 1589 case e1000_phy_bm: 1590 ret_val = e1000_copper_link_setup_m88(hw); 1591 break; 1592 case e1000_phy_igp_2: 1593 ret_val = e1000_copper_link_setup_igp(hw); 1594 break; 1595 default: 1596 return -E1000_ERR_PHY; 1597 break; 1598 } 1599 1600 if (ret_val) 1601 return ret_val; 1602 1603 return e1000_setup_copper_link_generic(hw); 1604 } 1605 1606 /** 1607 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes 1608 * @hw: pointer to the HW structure 1609 * 1610 * Configures collision distance and flow control for fiber and serdes links. 1611 * Upon successful setup, poll for link. 1612 **/ 1613 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) 1614 { 1615 DEBUGFUNC("e1000_setup_fiber_serdes_link_82571"); 1616 1617 switch (hw->mac.type) { 1618 case e1000_82571: 1619 case e1000_82572: 1620 /* 1621 * If SerDes loopback mode is entered, there is no form 1622 * of reset to take the adapter out of that mode. So we 1623 * have to explicitly take the adapter out of loopback 1624 * mode. This prevents drivers from twiddling their thumbs 1625 * if another tool failed to take it out of loopback mode. 1626 */ 1627 E1000_WRITE_REG(hw, E1000_SCTL, 1628 E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1629 break; 1630 default: 1631 break; 1632 } 1633 1634 return e1000_setup_fiber_serdes_link_generic(hw); 1635 } 1636 1637 /** 1638 * e1000_check_for_serdes_link_82571 - Check for link (Serdes) 1639 * @hw: pointer to the HW structure 1640 * 1641 * Reports the link state as up or down. 1642 * 1643 * If autonegotiation is supported by the link partner, the link state is 1644 * determined by the result of autonegotiation. This is the most likely case. 1645 * If autonegotiation is not supported by the link partner, and the link 1646 * has a valid signal, force the link up. 1647 * 1648 * The link state is represented internally here by 4 states: 1649 * 1650 * 1) down 1651 * 2) autoneg_progress 1652 * 3) autoneg_complete (the link successfully autonegotiated) 1653 * 4) forced_up (the link has been forced up, it did not autonegotiate) 1654 * 1655 **/ 1656 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) 1657 { 1658 struct e1000_mac_info *mac = &hw->mac; 1659 u32 rxcw; 1660 u32 ctrl; 1661 u32 status; 1662 u32 txcw; 1663 u32 i; 1664 s32 ret_val = E1000_SUCCESS; 1665 1666 DEBUGFUNC("e1000_check_for_serdes_link_82571"); 1667 1668 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1669 status = E1000_READ_REG(hw, E1000_STATUS); 1670 rxcw = E1000_READ_REG(hw, E1000_RXCW); 1671 1672 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) { 1673 1674 /* Receiver is synchronized with no invalid bits. */ 1675 switch (mac->serdes_link_state) { 1676 case e1000_serdes_link_autoneg_complete: 1677 if (!(status & E1000_STATUS_LU)) { 1678 /* 1679 * We have lost link, retry autoneg before 1680 * reporting link failure 1681 */ 1682 mac->serdes_link_state = 1683 e1000_serdes_link_autoneg_progress; 1684 mac->serdes_has_link = FALSE; 1685 DEBUGOUT("AN_UP -> AN_PROG\n"); 1686 } else { 1687 mac->serdes_has_link = TRUE; 1688 } 1689 break; 1690 1691 case e1000_serdes_link_forced_up: 1692 /* 1693 * If we are receiving /C/ ordered sets, re-enable 1694 * auto-negotiation in the TXCW register and disable 1695 * forced link in the Device Control register in an 1696 * attempt to auto-negotiate with our link partner. 1697 * If the partner code word is null, stop forcing 1698 * and restart auto negotiation. 1699 */ 1700 if ((rxcw & E1000_RXCW_C) || !(rxcw & E1000_RXCW_CW)) { 1701 /* Enable autoneg, and unforce link up */ 1702 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1703 E1000_WRITE_REG(hw, E1000_CTRL, 1704 (ctrl & ~E1000_CTRL_SLU)); 1705 mac->serdes_link_state = 1706 e1000_serdes_link_autoneg_progress; 1707 mac->serdes_has_link = FALSE; 1708 DEBUGOUT("FORCED_UP -> AN_PROG\n"); 1709 } else { 1710 mac->serdes_has_link = TRUE; 1711 } 1712 break; 1713 1714 case e1000_serdes_link_autoneg_progress: 1715 if (rxcw & E1000_RXCW_C) { 1716 /* 1717 * We received /C/ ordered sets, meaning the 1718 * link partner has autonegotiated, and we can 1719 * trust the Link Up (LU) status bit. 1720 */ 1721 if (status & E1000_STATUS_LU) { 1722 mac->serdes_link_state = 1723 e1000_serdes_link_autoneg_complete; 1724 DEBUGOUT("AN_PROG -> AN_UP\n"); 1725 mac->serdes_has_link = TRUE; 1726 } else { 1727 /* Autoneg completed, but failed. */ 1728 mac->serdes_link_state = 1729 e1000_serdes_link_down; 1730 DEBUGOUT("AN_PROG -> DOWN\n"); 1731 } 1732 } else { 1733 /* 1734 * The link partner did not autoneg. 1735 * Force link up and full duplex, and change 1736 * state to forced. 1737 */ 1738 E1000_WRITE_REG(hw, E1000_TXCW, 1739 (mac->txcw & ~E1000_TXCW_ANE)); 1740 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 1741 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1742 1743 /* Configure Flow Control after link up. */ 1744 ret_val = 1745 e1000_config_fc_after_link_up_generic(hw); 1746 if (ret_val) { 1747 DEBUGOUT("Error config flow control\n"); 1748 break; 1749 } 1750 mac->serdes_link_state = 1751 e1000_serdes_link_forced_up; 1752 mac->serdes_has_link = TRUE; 1753 DEBUGOUT("AN_PROG -> FORCED_UP\n"); 1754 } 1755 break; 1756 1757 case e1000_serdes_link_down: 1758 default: 1759 /* 1760 * The link was down but the receiver has now gained 1761 * valid sync, so lets see if we can bring the link 1762 * up. 1763 */ 1764 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1765 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & 1766 ~E1000_CTRL_SLU)); 1767 mac->serdes_link_state = 1768 e1000_serdes_link_autoneg_progress; 1769 mac->serdes_has_link = FALSE; 1770 DEBUGOUT("DOWN -> AN_PROG\n"); 1771 break; 1772 } 1773 } else { 1774 if (!(rxcw & E1000_RXCW_SYNCH)) { 1775 mac->serdes_has_link = FALSE; 1776 mac->serdes_link_state = e1000_serdes_link_down; 1777 DEBUGOUT("ANYSTATE -> DOWN\n"); 1778 } else { 1779 /* 1780 * Check several times, if Sync and Config 1781 * both are consistently 1 then simply ignore 1782 * the Invalid bit and restart Autoneg 1783 */ 1784 for (i = 0; i < AN_RETRY_COUNT; i++) { 1785 usec_delay(10); 1786 rxcw = E1000_READ_REG(hw, E1000_RXCW); 1787 if ((rxcw & E1000_RXCW_IV) && 1788 !((rxcw & E1000_RXCW_SYNCH) && 1789 (rxcw & E1000_RXCW_C))) { 1790 mac->serdes_has_link = FALSE; 1791 mac->serdes_link_state = 1792 e1000_serdes_link_down; 1793 DEBUGOUT("ANYSTATE -> DOWN\n"); 1794 break; 1795 } 1796 } 1797 1798 if (i == AN_RETRY_COUNT) { 1799 txcw = E1000_READ_REG(hw, E1000_TXCW); 1800 txcw |= E1000_TXCW_ANE; 1801 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1802 mac->serdes_link_state = 1803 e1000_serdes_link_autoneg_progress; 1804 mac->serdes_has_link = FALSE; 1805 DEBUGOUT("ANYSTATE -> AN_PROG\n"); 1806 } 1807 } 1808 } 1809 1810 return ret_val; 1811 } 1812 1813 /** 1814 * e1000_valid_led_default_82571 - Verify a valid default LED config 1815 * @hw: pointer to the HW structure 1816 * @data: pointer to the NVM (EEPROM) 1817 * 1818 * Read the EEPROM for the current default LED configuration. If the 1819 * LED configuration is not valid, set to a valid LED configuration. 1820 **/ 1821 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) 1822 { 1823 s32 ret_val; 1824 1825 DEBUGFUNC("e1000_valid_led_default_82571"); 1826 1827 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1828 if (ret_val) { 1829 DEBUGOUT("NVM Read Error\n"); 1830 return ret_val; 1831 } 1832 1833 switch (hw->mac.type) { 1834 case e1000_82573: 1835 case e1000_82574: 1836 case e1000_82583: 1837 if (*data == ID_LED_RESERVED_F746) 1838 *data = ID_LED_DEFAULT_82573; 1839 break; 1840 default: 1841 if (*data == ID_LED_RESERVED_0000 || 1842 *data == ID_LED_RESERVED_FFFF) 1843 *data = ID_LED_DEFAULT; 1844 break; 1845 } 1846 1847 return E1000_SUCCESS; 1848 } 1849 1850 /** 1851 * e1000_get_laa_state_82571 - Get locally administered address state 1852 * @hw: pointer to the HW structure 1853 * 1854 * Retrieve and return the current locally administered address state. 1855 **/ 1856 bool e1000_get_laa_state_82571(struct e1000_hw *hw) 1857 { 1858 DEBUGFUNC("e1000_get_laa_state_82571"); 1859 1860 if (hw->mac.type != e1000_82571) 1861 return FALSE; 1862 1863 return hw->dev_spec._82571.laa_is_present; 1864 } 1865 1866 /** 1867 * e1000_set_laa_state_82571 - Set locally administered address state 1868 * @hw: pointer to the HW structure 1869 * @state: enable/disable locally administered address 1870 * 1871 * Enable/Disable the current locally administered address state. 1872 **/ 1873 void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state) 1874 { 1875 DEBUGFUNC("e1000_set_laa_state_82571"); 1876 1877 if (hw->mac.type != e1000_82571) 1878 return; 1879 1880 hw->dev_spec._82571.laa_is_present = state; 1881 1882 /* If workaround is activated... */ 1883 if (state) 1884 /* 1885 * Hold a copy of the LAA in RAR[14] This is done so that 1886 * between the time RAR[0] gets clobbered and the time it 1887 * gets fixed, the actual LAA is in one of the RARs and no 1888 * incoming packets directed to this port are dropped. 1889 * Eventually the LAA will be in RAR[0] and RAR[14]. 1890 */ 1891 e1000_rar_set_generic(hw, hw->mac.addr, 1892 hw->mac.rar_entry_count - 1); 1893 return; 1894 } 1895 1896 /** 1897 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum 1898 * @hw: pointer to the HW structure 1899 * 1900 * Verifies that the EEPROM has completed the update. After updating the 1901 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If 1902 * the checksum fix is not implemented, we need to set the bit and update 1903 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, 1904 * we need to return bad checksum. 1905 **/ 1906 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) 1907 { 1908 struct e1000_nvm_info *nvm = &hw->nvm; 1909 s32 ret_val; 1910 u16 data; 1911 1912 DEBUGFUNC("e1000_fix_nvm_checksum_82571"); 1913 1914 if (nvm->type != e1000_nvm_flash_hw) 1915 return E1000_SUCCESS; 1916 1917 /* 1918 * Check bit 4 of word 10h. If it is 0, firmware is done updating 1919 * 10h-12h. Checksum may need to be fixed. 1920 */ 1921 ret_val = nvm->ops.read(hw, 0x10, 1, &data); 1922 if (ret_val) 1923 return ret_val; 1924 1925 if (!(data & 0x10)) { 1926 /* 1927 * Read 0x23 and check bit 15. This bit is a 1 1928 * when the checksum has already been fixed. If 1929 * the checksum is still wrong and this bit is a 1930 * 1, we need to return bad checksum. Otherwise, 1931 * we need to set this bit to a 1 and update the 1932 * checksum. 1933 */ 1934 ret_val = nvm->ops.read(hw, 0x23, 1, &data); 1935 if (ret_val) 1936 return ret_val; 1937 1938 if (!(data & 0x8000)) { 1939 data |= 0x8000; 1940 ret_val = nvm->ops.write(hw, 0x23, 1, &data); 1941 if (ret_val) 1942 return ret_val; 1943 ret_val = nvm->ops.update(hw); 1944 } 1945 } 1946 1947 return E1000_SUCCESS; 1948 } 1949 1950 1951 /** 1952 * e1000_read_mac_addr_82571 - Read device MAC address 1953 * @hw: pointer to the HW structure 1954 **/ 1955 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw) 1956 { 1957 DEBUGFUNC("e1000_read_mac_addr_82571"); 1958 1959 if (hw->mac.type == e1000_82571) { 1960 s32 ret_val = E1000_SUCCESS; 1961 1962 /* 1963 * If there's an alternate MAC address place it in RAR0 1964 * so that it will override the Si installed default perm 1965 * address. 1966 */ 1967 ret_val = e1000_check_alt_mac_addr_generic(hw); 1968 if (ret_val) 1969 return ret_val; 1970 } 1971 1972 return e1000_read_mac_addr_generic(hw); 1973 } 1974 1975 /** 1976 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down 1977 * @hw: pointer to the HW structure 1978 * 1979 * In the case of a PHY power down to save power, or to turn off link during a 1980 * driver unload, or wake on lan is not enabled, remove the link. 1981 **/ 1982 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw) 1983 { 1984 struct e1000_phy_info *phy = &hw->phy; 1985 struct e1000_mac_info *mac = &hw->mac; 1986 1987 if (!phy->ops.check_reset_block) 1988 return; 1989 1990 /* If the management interface is not enabled, then power down */ 1991 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) 1992 e1000_power_down_phy_copper(hw); 1993 1994 return; 1995 } 1996 1997 /** 1998 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters 1999 * @hw: pointer to the HW structure 2000 * 2001 * Clears the hardware counters by reading the counter registers. 2002 **/ 2003 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) 2004 { 2005 DEBUGFUNC("e1000_clear_hw_cntrs_82571"); 2006 2007 e1000_clear_hw_cntrs_base_generic(hw); 2008 2009 E1000_READ_REG(hw, E1000_PRC64); 2010 E1000_READ_REG(hw, E1000_PRC127); 2011 E1000_READ_REG(hw, E1000_PRC255); 2012 E1000_READ_REG(hw, E1000_PRC511); 2013 E1000_READ_REG(hw, E1000_PRC1023); 2014 E1000_READ_REG(hw, E1000_PRC1522); 2015 E1000_READ_REG(hw, E1000_PTC64); 2016 E1000_READ_REG(hw, E1000_PTC127); 2017 E1000_READ_REG(hw, E1000_PTC255); 2018 E1000_READ_REG(hw, E1000_PTC511); 2019 E1000_READ_REG(hw, E1000_PTC1023); 2020 E1000_READ_REG(hw, E1000_PTC1522); 2021 2022 E1000_READ_REG(hw, E1000_ALGNERRC); 2023 E1000_READ_REG(hw, E1000_RXERRC); 2024 E1000_READ_REG(hw, E1000_TNCRS); 2025 E1000_READ_REG(hw, E1000_CEXTERR); 2026 E1000_READ_REG(hw, E1000_TSCTC); 2027 E1000_READ_REG(hw, E1000_TSCTFC); 2028 2029 E1000_READ_REG(hw, E1000_MGTPRC); 2030 E1000_READ_REG(hw, E1000_MGTPDC); 2031 E1000_READ_REG(hw, E1000_MGTPTC); 2032 2033 E1000_READ_REG(hw, E1000_IAC); 2034 E1000_READ_REG(hw, E1000_ICRXOC); 2035 2036 E1000_READ_REG(hw, E1000_ICRXPTC); 2037 E1000_READ_REG(hw, E1000_ICRXATC); 2038 E1000_READ_REG(hw, E1000_ICTXPTC); 2039 E1000_READ_REG(hw, E1000_ICTXATC); 2040 E1000_READ_REG(hw, E1000_ICTXQEC); 2041 E1000_READ_REG(hw, E1000_ICTXQMTC); 2042 E1000_READ_REG(hw, E1000_ICRXDMTC); 2043 } 2044