1 /****************************************************************************** 2 3 Copyright (c) 2001-2011, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 /* 36 * 82575EB Gigabit Network Connection 37 * 82575EB Gigabit Backplane Connection 38 * 82575GB Gigabit Network Connection 39 * 82576 Gigabit Network Connection 40 * 82576 Quad Port Gigabit Mezzanine Adapter 41 * 82580 Gigabit Network Connection 42 * I350 Gigabit Network Connection 43 */ 44 45 #include "e1000_api.h" 46 #include "e1000_i210.h" 47 48 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw); 49 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw); 50 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw); 51 static void e1000_release_phy_82575(struct e1000_hw *hw); 52 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw); 53 static void e1000_release_nvm_82575(struct e1000_hw *hw); 54 static s32 e1000_check_for_link_82575(struct e1000_hw *hw); 55 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw); 56 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 57 u16 *duplex); 58 static s32 e1000_init_hw_82575(struct e1000_hw *hw); 59 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw); 60 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 61 u16 *data); 62 static s32 e1000_reset_hw_82575(struct e1000_hw *hw); 63 static s32 e1000_reset_hw_82580(struct e1000_hw *hw); 64 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, 65 u32 offset, u16 *data); 66 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, 67 u32 offset, u16 data); 68 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, 69 bool active); 70 static s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, 71 bool active); 72 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, 73 bool active); 74 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw); 75 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw); 76 static s32 e1000_get_media_type_82575(struct e1000_hw *hw); 77 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw); 78 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data); 79 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, 80 u32 offset, u16 data); 81 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw); 82 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 83 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 84 u16 *speed, u16 *duplex); 85 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw); 86 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 87 static bool e1000_sgmii_active_82575(struct e1000_hw *hw); 88 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw); 89 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw); 90 static void e1000_config_collision_dist_82575(struct e1000_hw *hw); 91 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw); 92 static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw); 93 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw); 94 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw); 95 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw); 96 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw); 97 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw); 98 static s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, 99 u16 offset); 100 static s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, 101 u16 offset); 102 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw); 103 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw); 104 static void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value); 105 static void e1000_clear_vfta_i350(struct e1000_hw *hw); 106 107 static void e1000_i2c_start(struct e1000_hw *hw); 108 static void e1000_i2c_stop(struct e1000_hw *hw); 109 static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data); 110 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data); 111 static s32 e1000_get_i2c_ack(struct e1000_hw *hw); 112 static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data); 113 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data); 114 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl); 115 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl); 116 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data); 117 static bool e1000_get_i2c_data(u32 *i2cctl); 118 119 static const u16 e1000_82580_rxpbs_table[] = { 120 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 }; 121 #define E1000_82580_RXPBS_TABLE_SIZE \ 122 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16)) 123 124 125 /** 126 * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO 127 * @hw: pointer to the HW structure 128 * 129 * Called to determine if the I2C pins are being used for I2C or as an 130 * external MDIO interface since the two options are mutually exclusive. 131 **/ 132 static bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw) 133 { 134 u32 reg = 0; 135 bool ext_mdio = FALSE; 136 137 DEBUGFUNC("e1000_sgmii_uses_mdio_82575"); 138 139 switch (hw->mac.type) { 140 case e1000_82575: 141 case e1000_82576: 142 reg = E1000_READ_REG(hw, E1000_MDIC); 143 ext_mdio = !!(reg & E1000_MDIC_DEST); 144 break; 145 case e1000_82580: 146 case e1000_i350: 147 reg = E1000_READ_REG(hw, E1000_MDICNFG); 148 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO); 149 break; 150 default: 151 break; 152 } 153 return ext_mdio; 154 } 155 156 /** 157 * e1000_init_phy_params_82575 - Init PHY func ptrs. 158 * @hw: pointer to the HW structure 159 **/ 160 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw) 161 { 162 struct e1000_phy_info *phy = &hw->phy; 163 s32 ret_val = E1000_SUCCESS; 164 u32 ctrl_ext; 165 166 DEBUGFUNC("e1000_init_phy_params_82575"); 167 168 phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic; 169 phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic; 170 171 if (hw->phy.media_type != e1000_media_type_copper) { 172 phy->type = e1000_phy_none; 173 goto out; 174 } 175 176 phy->ops.power_up = e1000_power_up_phy_copper; 177 phy->ops.power_down = e1000_power_down_phy_copper_82575; 178 179 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 180 phy->reset_delay_us = 100; 181 182 phy->ops.acquire = e1000_acquire_phy_82575; 183 phy->ops.check_reset_block = e1000_check_reset_block_generic; 184 phy->ops.commit = e1000_phy_sw_reset_generic; 185 phy->ops.get_cfg_done = e1000_get_cfg_done_82575; 186 phy->ops.release = e1000_release_phy_82575; 187 188 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 189 190 if (e1000_sgmii_active_82575(hw)) { 191 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575; 192 ctrl_ext |= E1000_CTRL_I2C_ENA; 193 } else { 194 phy->ops.reset = e1000_phy_hw_reset_generic; 195 ctrl_ext &= ~E1000_CTRL_I2C_ENA; 196 } 197 198 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 199 e1000_reset_mdicnfg_82580(hw); 200 201 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) { 202 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575; 203 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575; 204 } else { 205 switch (hw->mac.type) { 206 case e1000_82580: 207 case e1000_i350: 208 phy->ops.read_reg = e1000_read_phy_reg_82580; 209 phy->ops.write_reg = e1000_write_phy_reg_82580; 210 break; 211 case e1000_i210: 212 case e1000_i211: 213 phy->ops.read_reg = e1000_read_phy_reg_gs40g; 214 phy->ops.write_reg = e1000_write_phy_reg_gs40g; 215 break; 216 default: 217 phy->ops.read_reg = e1000_read_phy_reg_igp; 218 phy->ops.write_reg = e1000_write_phy_reg_igp; 219 } 220 } 221 222 /* Set phy->phy_addr and phy->id. */ 223 ret_val = e1000_get_phy_id_82575(hw); 224 225 /* Verify phy id and set remaining function pointers */ 226 switch (phy->id) { 227 case I347AT4_E_PHY_ID: 228 case M88E1112_E_PHY_ID: 229 case M88E1340M_E_PHY_ID: 230 case M88E1111_I_PHY_ID: 231 phy->type = e1000_phy_m88; 232 phy->ops.check_polarity = e1000_check_polarity_m88; 233 phy->ops.get_info = e1000_get_phy_info_m88; 234 if (phy->id == I347AT4_E_PHY_ID || 235 phy->id == M88E1112_E_PHY_ID || 236 phy->id == M88E1340M_E_PHY_ID) 237 phy->ops.get_cable_length = 238 e1000_get_cable_length_m88_gen2; 239 else 240 phy->ops.get_cable_length = e1000_get_cable_length_m88; 241 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 242 break; 243 case IGP03E1000_E_PHY_ID: 244 case IGP04E1000_E_PHY_ID: 245 phy->type = e1000_phy_igp_3; 246 phy->ops.check_polarity = e1000_check_polarity_igp; 247 phy->ops.get_info = e1000_get_phy_info_igp; 248 phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 249 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 250 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575; 251 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 252 break; 253 case I82580_I_PHY_ID: 254 case I350_I_PHY_ID: 255 phy->type = e1000_phy_82580; 256 phy->ops.check_polarity = e1000_check_polarity_82577; 257 phy->ops.force_speed_duplex = 258 e1000_phy_force_speed_duplex_82577; 259 phy->ops.get_cable_length = e1000_get_cable_length_82577; 260 phy->ops.get_info = e1000_get_phy_info_82577; 261 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580; 262 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580; 263 break; 264 case I210_I_PHY_ID: 265 phy->type = e1000_phy_i210; 266 phy->ops.check_polarity = e1000_check_polarity_m88; 267 phy->ops.get_info = e1000_get_phy_info_m88; 268 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2; 269 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580; 270 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580; 271 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 272 break; 273 default: 274 ret_val = -E1000_ERR_PHY; 275 goto out; 276 } 277 278 out: 279 return ret_val; 280 } 281 282 /** 283 * e1000_init_nvm_params_82575 - Init NVM func ptrs. 284 * @hw: pointer to the HW structure 285 **/ 286 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw) 287 { 288 struct e1000_nvm_info *nvm = &hw->nvm; 289 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 290 u16 size; 291 292 DEBUGFUNC("e1000_init_nvm_params_82575"); 293 294 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 295 E1000_EECD_SIZE_EX_SHIFT); 296 /* 297 * Added to a constant, "size" becomes the left-shift value 298 * for setting word_size. 299 */ 300 size += NVM_WORD_SIZE_BASE_SHIFT; 301 302 /* Just in case size is out of range, cap it to the largest 303 * EEPROM size supported 304 */ 305 if (size > 15) 306 size = 15; 307 308 nvm->word_size = 1 << size; 309 if (hw->mac.type < e1000_i210) { 310 nvm->opcode_bits = 8; 311 nvm->delay_usec = 1; 312 313 switch (nvm->override) { 314 case e1000_nvm_override_spi_large: 315 nvm->page_size = 32; 316 nvm->address_bits = 16; 317 break; 318 case e1000_nvm_override_spi_small: 319 nvm->page_size = 8; 320 nvm->address_bits = 8; 321 break; 322 default: 323 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 324 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 325 16 : 8; 326 break; 327 } 328 if (nvm->word_size == (1 << 15)) 329 nvm->page_size = 128; 330 331 nvm->type = e1000_nvm_eeprom_spi; 332 } else { 333 nvm->type = e1000_nvm_flash_hw; 334 } 335 /* Function Pointers */ 336 nvm->ops.acquire = e1000_acquire_nvm_82575; 337 nvm->ops.release = e1000_release_nvm_82575; 338 if (nvm->word_size < (1 << 15)) 339 nvm->ops.read = e1000_read_nvm_eerd; 340 else 341 nvm->ops.read = e1000_read_nvm_spi; 342 343 nvm->ops.write = e1000_write_nvm_spi; 344 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 345 nvm->ops.update = e1000_update_nvm_checksum_generic; 346 nvm->ops.valid_led_default = e1000_valid_led_default_82575; 347 348 /* override generic family function pointers for specific descendants */ 349 switch (hw->mac.type) { 350 case e1000_82580: 351 nvm->ops.validate = e1000_validate_nvm_checksum_82580; 352 nvm->ops.update = e1000_update_nvm_checksum_82580; 353 break; 354 case e1000_i350: 355 nvm->ops.validate = e1000_validate_nvm_checksum_i350; 356 nvm->ops.update = e1000_update_nvm_checksum_i350; 357 break; 358 default: 359 break; 360 } 361 362 return E1000_SUCCESS; 363 } 364 365 /** 366 * e1000_init_mac_params_82575 - Init MAC func ptrs. 367 * @hw: pointer to the HW structure 368 **/ 369 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw) 370 { 371 struct e1000_mac_info *mac = &hw->mac; 372 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 373 374 DEBUGFUNC("e1000_init_mac_params_82575"); 375 376 /* Derives media type */ 377 e1000_get_media_type_82575(hw); 378 /* Set mta register count */ 379 mac->mta_reg_count = 128; 380 /* Set uta register count */ 381 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128; 382 /* Set rar entry count */ 383 mac->rar_entry_count = E1000_RAR_ENTRIES_82575; 384 if (mac->type == e1000_82576) 385 mac->rar_entry_count = E1000_RAR_ENTRIES_82576; 386 if (mac->type == e1000_82580) 387 mac->rar_entry_count = E1000_RAR_ENTRIES_82580; 388 if (mac->type == e1000_i350) { 389 mac->rar_entry_count = E1000_RAR_ENTRIES_I350; 390 /* Enable EEE default settings for i350 */ 391 dev_spec->eee_disable = FALSE; 392 } 393 394 /* Set if part includes ASF firmware */ 395 mac->asf_firmware_present = TRUE; 396 /* FWSM register */ 397 mac->has_fwsm = TRUE; 398 /* ARC supported; valid only if manageability features are enabled. */ 399 mac->arc_subsystem_valid = 400 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK); 401 402 /* Function pointers */ 403 404 /* bus type/speed/width */ 405 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 406 /* reset */ 407 if (mac->type >= e1000_82580) 408 mac->ops.reset_hw = e1000_reset_hw_82580; 409 else 410 mac->ops.reset_hw = e1000_reset_hw_82575; 411 /* hw initialization */ 412 mac->ops.init_hw = e1000_init_hw_82575; 413 /* link setup */ 414 mac->ops.setup_link = e1000_setup_link_generic; 415 /* physical interface link setup */ 416 mac->ops.setup_physical_interface = 417 (hw->phy.media_type == e1000_media_type_copper) 418 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575; 419 /* physical interface shutdown */ 420 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575; 421 /* physical interface power up */ 422 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575; 423 /* check for link */ 424 mac->ops.check_for_link = e1000_check_for_link_82575; 425 /* read mac address */ 426 mac->ops.read_mac_addr = e1000_read_mac_addr_82575; 427 /* configure collision distance */ 428 mac->ops.config_collision_dist = e1000_config_collision_dist_82575; 429 /* multicast address update */ 430 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 431 if (mac->type == e1000_i350) { 432 /* writing VFTA */ 433 mac->ops.write_vfta = e1000_write_vfta_i350; 434 /* clearing VFTA */ 435 mac->ops.clear_vfta = e1000_clear_vfta_i350; 436 } else { 437 /* writing VFTA */ 438 mac->ops.write_vfta = e1000_write_vfta_generic; 439 /* clearing VFTA */ 440 mac->ops.clear_vfta = e1000_clear_vfta_generic; 441 } 442 if (hw->mac.type >= e1000_82580) 443 mac->ops.validate_mdi_setting = 444 e1000_validate_mdi_setting_crossover_generic; 445 /* ID LED init */ 446 mac->ops.id_led_init = e1000_id_led_init_generic; 447 /* blink LED */ 448 mac->ops.blink_led = e1000_blink_led_generic; 449 /* setup LED */ 450 mac->ops.setup_led = e1000_setup_led_generic; 451 /* cleanup LED */ 452 mac->ops.cleanup_led = e1000_cleanup_led_generic; 453 /* turn on/off LED */ 454 mac->ops.led_on = e1000_led_on_generic; 455 mac->ops.led_off = e1000_led_off_generic; 456 /* clear hardware counters */ 457 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575; 458 /* link info */ 459 mac->ops.get_link_up_info = e1000_get_link_up_info_82575; 460 /* acquire SW_FW sync */ 461 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575; 462 mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575; 463 if (mac->type >= e1000_i210) { 464 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210; 465 mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210; 466 } 467 468 /* set lan id for port to determine which phy lock to use */ 469 hw->mac.ops.set_lan_id(hw); 470 471 return E1000_SUCCESS; 472 } 473 474 /** 475 * e1000_init_function_pointers_82575 - Init func ptrs. 476 * @hw: pointer to the HW structure 477 * 478 * Called to initialize all function pointers and parameters. 479 **/ 480 void e1000_init_function_pointers_82575(struct e1000_hw *hw) 481 { 482 DEBUGFUNC("e1000_init_function_pointers_82575"); 483 484 hw->mac.ops.init_params = e1000_init_mac_params_82575; 485 hw->nvm.ops.init_params = e1000_init_nvm_params_82575; 486 hw->phy.ops.init_params = e1000_init_phy_params_82575; 487 hw->mbx.ops.init_params = e1000_init_mbx_params_pf; 488 } 489 490 /** 491 * e1000_acquire_phy_82575 - Acquire rights to access PHY 492 * @hw: pointer to the HW structure 493 * 494 * Acquire access rights to the correct PHY. 495 **/ 496 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw) 497 { 498 u16 mask = E1000_SWFW_PHY0_SM; 499 500 DEBUGFUNC("e1000_acquire_phy_82575"); 501 502 if (hw->bus.func == E1000_FUNC_1) 503 mask = E1000_SWFW_PHY1_SM; 504 else if (hw->bus.func == E1000_FUNC_2) 505 mask = E1000_SWFW_PHY2_SM; 506 else if (hw->bus.func == E1000_FUNC_3) 507 mask = E1000_SWFW_PHY3_SM; 508 509 return hw->mac.ops.acquire_swfw_sync(hw, mask); 510 } 511 512 /** 513 * e1000_release_phy_82575 - Release rights to access PHY 514 * @hw: pointer to the HW structure 515 * 516 * A wrapper to release access rights to the correct PHY. 517 **/ 518 static void e1000_release_phy_82575(struct e1000_hw *hw) 519 { 520 u16 mask = E1000_SWFW_PHY0_SM; 521 522 DEBUGFUNC("e1000_release_phy_82575"); 523 524 if (hw->bus.func == E1000_FUNC_1) 525 mask = E1000_SWFW_PHY1_SM; 526 else if (hw->bus.func == E1000_FUNC_2) 527 mask = E1000_SWFW_PHY2_SM; 528 else if (hw->bus.func == E1000_FUNC_3) 529 mask = E1000_SWFW_PHY3_SM; 530 531 hw->mac.ops.release_swfw_sync(hw, mask); 532 } 533 534 /** 535 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii 536 * @hw: pointer to the HW structure 537 * @offset: register offset to be read 538 * @data: pointer to the read data 539 * 540 * Reads the PHY register at offset using the serial gigabit media independent 541 * interface and stores the retrieved information in data. 542 **/ 543 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 544 u16 *data) 545 { 546 s32 ret_val = -E1000_ERR_PARAM; 547 548 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575"); 549 550 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 551 DEBUGOUT1("PHY Address %u is out of range\n", offset); 552 goto out; 553 } 554 555 ret_val = hw->phy.ops.acquire(hw); 556 if (ret_val) 557 goto out; 558 559 ret_val = e1000_read_phy_reg_i2c(hw, offset, data); 560 561 hw->phy.ops.release(hw); 562 563 out: 564 return ret_val; 565 } 566 567 /** 568 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii 569 * @hw: pointer to the HW structure 570 * @offset: register offset to write to 571 * @data: data to write at register offset 572 * 573 * Writes the data to PHY register at the offset using the serial gigabit 574 * media independent interface. 575 **/ 576 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 577 u16 data) 578 { 579 s32 ret_val = -E1000_ERR_PARAM; 580 581 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575"); 582 583 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 584 DEBUGOUT1("PHY Address %d is out of range\n", offset); 585 goto out; 586 } 587 588 ret_val = hw->phy.ops.acquire(hw); 589 if (ret_val) 590 goto out; 591 592 ret_val = e1000_write_phy_reg_i2c(hw, offset, data); 593 594 hw->phy.ops.release(hw); 595 596 out: 597 return ret_val; 598 } 599 600 /** 601 * e1000_get_phy_id_82575 - Retrieve PHY addr and id 602 * @hw: pointer to the HW structure 603 * 604 * Retrieves the PHY address and ID for both PHY's which do and do not use 605 * sgmi interface. 606 **/ 607 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw) 608 { 609 struct e1000_phy_info *phy = &hw->phy; 610 s32 ret_val = E1000_SUCCESS; 611 u16 phy_id; 612 u32 ctrl_ext; 613 u32 mdic; 614 615 DEBUGFUNC("e1000_get_phy_id_82575"); 616 617 /* 618 * For SGMII PHYs, we try the list of possible addresses until 619 * we find one that works. For non-SGMII PHYs 620 * (e.g. integrated copper PHYs), an address of 1 should 621 * work. The result of this function should mean phy->phy_addr 622 * and phy->id are set correctly. 623 */ 624 if (!e1000_sgmii_active_82575(hw)) { 625 phy->addr = 1; 626 ret_val = e1000_get_phy_id(hw); 627 goto out; 628 } 629 630 if (e1000_sgmii_uses_mdio_82575(hw)) { 631 switch (hw->mac.type) { 632 case e1000_82575: 633 case e1000_82576: 634 mdic = E1000_READ_REG(hw, E1000_MDIC); 635 mdic &= E1000_MDIC_PHY_MASK; 636 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT; 637 break; 638 case e1000_82580: 639 case e1000_i350: 640 mdic = E1000_READ_REG(hw, E1000_MDICNFG); 641 mdic &= E1000_MDICNFG_PHY_MASK; 642 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT; 643 break; 644 default: 645 ret_val = -E1000_ERR_PHY; 646 goto out; 647 break; 648 } 649 ret_val = e1000_get_phy_id(hw); 650 goto out; 651 } 652 653 /* Power on sgmii phy if it is disabled */ 654 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 655 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 656 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); 657 E1000_WRITE_FLUSH(hw); 658 msec_delay(300); 659 660 /* 661 * The address field in the I2CCMD register is 3 bits and 0 is invalid. 662 * Therefore, we need to test 1-7 663 */ 664 for (phy->addr = 1; phy->addr < 8; phy->addr++) { 665 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); 666 if (ret_val == E1000_SUCCESS) { 667 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n", 668 phy_id, phy->addr); 669 /* 670 * At the time of this writing, The M88 part is 671 * the only supported SGMII PHY product. 672 */ 673 if (phy_id == M88_VENDOR) 674 break; 675 } else { 676 DEBUGOUT1("PHY address %u was unreadable\n", 677 phy->addr); 678 } 679 } 680 681 /* A valid PHY type couldn't be found. */ 682 if (phy->addr == 8) { 683 phy->addr = 0; 684 ret_val = -E1000_ERR_PHY; 685 } else { 686 ret_val = e1000_get_phy_id(hw); 687 } 688 689 /* restore previous sfp cage power state */ 690 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 691 692 out: 693 return ret_val; 694 } 695 696 /** 697 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset 698 * @hw: pointer to the HW structure 699 * 700 * Resets the PHY using the serial gigabit media independent interface. 701 **/ 702 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) 703 { 704 s32 ret_val = E1000_SUCCESS; 705 706 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575"); 707 708 /* 709 * This isn't a TRUE "hard" reset, but is the only reset 710 * available to us at this time. 711 */ 712 713 DEBUGOUT("Soft resetting SGMII attached PHY...\n"); 714 715 if (!(hw->phy.ops.write_reg)) 716 goto out; 717 718 /* 719 * SFP documentation requires the following to configure the SPF module 720 * to work on SGMII. No further documentation is given. 721 */ 722 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); 723 if (ret_val) 724 goto out; 725 726 ret_val = hw->phy.ops.commit(hw); 727 728 out: 729 return ret_val; 730 } 731 732 /** 733 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state 734 * @hw: pointer to the HW structure 735 * @active: TRUE to enable LPLU, FALSE to disable 736 * 737 * Sets the LPLU D0 state according to the active flag. When 738 * activating LPLU this function also disables smart speed 739 * and vice versa. LPLU will not be activated unless the 740 * device autonegotiation advertisement meets standards of 741 * either 10 or 10/100 or 10/100/1000 at all duplexes. 742 * This is a function pointer entry point only called by 743 * PHY setup routines. 744 **/ 745 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) 746 { 747 struct e1000_phy_info *phy = &hw->phy; 748 s32 ret_val = E1000_SUCCESS; 749 u16 data; 750 751 DEBUGFUNC("e1000_set_d0_lplu_state_82575"); 752 753 if (!(hw->phy.ops.read_reg)) 754 goto out; 755 756 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 757 if (ret_val) 758 goto out; 759 760 if (active) { 761 data |= IGP02E1000_PM_D0_LPLU; 762 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 763 data); 764 if (ret_val) 765 goto out; 766 767 /* When LPLU is enabled, we should disable SmartSpeed */ 768 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 769 &data); 770 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 771 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 772 data); 773 if (ret_val) 774 goto out; 775 } else { 776 data &= ~IGP02E1000_PM_D0_LPLU; 777 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 778 data); 779 /* 780 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 781 * during Dx states where the power conservation is most 782 * important. During driver activity we should enable 783 * SmartSpeed, so performance is maintained. 784 */ 785 if (phy->smart_speed == e1000_smart_speed_on) { 786 ret_val = phy->ops.read_reg(hw, 787 IGP01E1000_PHY_PORT_CONFIG, 788 &data); 789 if (ret_val) 790 goto out; 791 792 data |= IGP01E1000_PSCFR_SMART_SPEED; 793 ret_val = phy->ops.write_reg(hw, 794 IGP01E1000_PHY_PORT_CONFIG, 795 data); 796 if (ret_val) 797 goto out; 798 } else if (phy->smart_speed == e1000_smart_speed_off) { 799 ret_val = phy->ops.read_reg(hw, 800 IGP01E1000_PHY_PORT_CONFIG, 801 &data); 802 if (ret_val) 803 goto out; 804 805 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 806 ret_val = phy->ops.write_reg(hw, 807 IGP01E1000_PHY_PORT_CONFIG, 808 data); 809 if (ret_val) 810 goto out; 811 } 812 } 813 814 out: 815 return ret_val; 816 } 817 818 /** 819 * e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state 820 * @hw: pointer to the HW structure 821 * @active: TRUE to enable LPLU, FALSE to disable 822 * 823 * Sets the LPLU D0 state according to the active flag. When 824 * activating LPLU this function also disables smart speed 825 * and vice versa. LPLU will not be activated unless the 826 * device autonegotiation advertisement meets standards of 827 * either 10 or 10/100 or 10/100/1000 at all duplexes. 828 * This is a function pointer entry point only called by 829 * PHY setup routines. 830 **/ 831 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active) 832 { 833 struct e1000_phy_info *phy = &hw->phy; 834 s32 ret_val = E1000_SUCCESS; 835 u32 data; 836 837 DEBUGFUNC("e1000_set_d0_lplu_state_82580"); 838 839 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); 840 841 if (active) { 842 data |= E1000_82580_PM_D0_LPLU; 843 844 /* When LPLU is enabled, we should disable SmartSpeed */ 845 data &= ~E1000_82580_PM_SPD; 846 } else { 847 data &= ~E1000_82580_PM_D0_LPLU; 848 849 /* 850 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 851 * during Dx states where the power conservation is most 852 * important. During driver activity we should enable 853 * SmartSpeed, so performance is maintained. 854 */ 855 if (phy->smart_speed == e1000_smart_speed_on) 856 data |= E1000_82580_PM_SPD; 857 else if (phy->smart_speed == e1000_smart_speed_off) 858 data &= ~E1000_82580_PM_SPD; 859 } 860 861 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data); 862 return ret_val; 863 } 864 865 /** 866 * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3 867 * @hw: pointer to the HW structure 868 * @active: boolean used to enable/disable lplu 869 * 870 * Success returns 0, Failure returns 1 871 * 872 * The low power link up (lplu) state is set to the power management level D3 873 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3 874 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 875 * is used during Dx states where the power conservation is most important. 876 * During driver activity, SmartSpeed should be enabled so performance is 877 * maintained. 878 **/ 879 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active) 880 { 881 struct e1000_phy_info *phy = &hw->phy; 882 s32 ret_val = E1000_SUCCESS; 883 u32 data; 884 885 DEBUGFUNC("e1000_set_d3_lplu_state_82580"); 886 887 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); 888 889 if (!active) { 890 data &= ~E1000_82580_PM_D3_LPLU; 891 /* 892 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 893 * during Dx states where the power conservation is most 894 * important. During driver activity we should enable 895 * SmartSpeed, so performance is maintained. 896 */ 897 if (phy->smart_speed == e1000_smart_speed_on) 898 data |= E1000_82580_PM_SPD; 899 else if (phy->smart_speed == e1000_smart_speed_off) 900 data &= ~E1000_82580_PM_SPD; 901 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 902 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 903 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 904 data |= E1000_82580_PM_D3_LPLU; 905 /* When LPLU is enabled, we should disable SmartSpeed */ 906 data &= ~E1000_82580_PM_SPD; 907 } 908 909 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data); 910 return ret_val; 911 } 912 913 /** 914 * e1000_acquire_nvm_82575 - Request for access to EEPROM 915 * @hw: pointer to the HW structure 916 * 917 * Acquire the necessary semaphores for exclusive access to the EEPROM. 918 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 919 * Return successful if access grant bit set, else clear the request for 920 * EEPROM access and return -E1000_ERR_NVM (-1). 921 **/ 922 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw) 923 { 924 s32 ret_val; 925 926 DEBUGFUNC("e1000_acquire_nvm_82575"); 927 928 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 929 if (ret_val) 930 goto out; 931 932 /* 933 * Check if there is some access 934 * error this access may hook on 935 */ 936 if (hw->mac.type == e1000_i350) { 937 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 938 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT | 939 E1000_EECD_TIMEOUT)) { 940 /* Clear all access error flags */ 941 E1000_WRITE_REG(hw, E1000_EECD, eecd | 942 E1000_EECD_ERROR_CLR); 943 DEBUGOUT("Nvm bit banging access error detected and cleared.\n"); 944 } 945 } 946 if (hw->mac.type == e1000_82580) { 947 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 948 if (eecd & E1000_EECD_BLOCKED) { 949 /* Clear access error flag */ 950 E1000_WRITE_REG(hw, E1000_EECD, eecd | 951 E1000_EECD_BLOCKED); 952 DEBUGOUT("Nvm bit banging access error detected and cleared.\n"); 953 } 954 } 955 956 957 ret_val = e1000_acquire_nvm_generic(hw); 958 if (ret_val) 959 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 960 961 out: 962 return ret_val; 963 } 964 965 /** 966 * e1000_release_nvm_82575 - Release exclusive access to EEPROM 967 * @hw: pointer to the HW structure 968 * 969 * Stop any current commands to the EEPROM and clear the EEPROM request bit, 970 * then release the semaphores acquired. 971 **/ 972 static void e1000_release_nvm_82575(struct e1000_hw *hw) 973 { 974 DEBUGFUNC("e1000_release_nvm_82575"); 975 976 e1000_release_nvm_generic(hw); 977 978 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 979 } 980 981 /** 982 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore 983 * @hw: pointer to the HW structure 984 * @mask: specifies which semaphore to acquire 985 * 986 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 987 * will also specify which port we're acquiring the lock for. 988 **/ 989 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 990 { 991 u32 swfw_sync; 992 u32 swmask = mask; 993 u32 fwmask = mask << 16; 994 s32 ret_val = E1000_SUCCESS; 995 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */ 996 997 DEBUGFUNC("e1000_acquire_swfw_sync_82575"); 998 999 while (i < timeout) { 1000 if (e1000_get_hw_semaphore_generic(hw)) { 1001 ret_val = -E1000_ERR_SWFW_SYNC; 1002 goto out; 1003 } 1004 1005 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 1006 if (!(swfw_sync & (fwmask | swmask))) 1007 break; 1008 1009 /* 1010 * Firmware currently using resource (fwmask) 1011 * or other software thread using resource (swmask) 1012 */ 1013 e1000_put_hw_semaphore_generic(hw); 1014 msec_delay_irq(5); 1015 i++; 1016 } 1017 1018 if (i == timeout) { 1019 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 1020 ret_val = -E1000_ERR_SWFW_SYNC; 1021 goto out; 1022 } 1023 1024 swfw_sync |= swmask; 1025 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 1026 1027 e1000_put_hw_semaphore_generic(hw); 1028 1029 out: 1030 return ret_val; 1031 } 1032 1033 /** 1034 * e1000_release_swfw_sync_82575 - Release SW/FW semaphore 1035 * @hw: pointer to the HW structure 1036 * @mask: specifies which semaphore to acquire 1037 * 1038 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 1039 * will also specify which port we're releasing the lock for. 1040 **/ 1041 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 1042 { 1043 u32 swfw_sync; 1044 1045 DEBUGFUNC("e1000_release_swfw_sync_82575"); 1046 1047 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS) 1048 ; /* Empty */ 1049 1050 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 1051 swfw_sync &= ~mask; 1052 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 1053 1054 e1000_put_hw_semaphore_generic(hw); 1055 } 1056 1057 /** 1058 * e1000_get_cfg_done_82575 - Read config done bit 1059 * @hw: pointer to the HW structure 1060 * 1061 * Read the management control register for the config done bit for 1062 * completion status. NOTE: silicon which is EEPROM-less will fail trying 1063 * to read the config done bit, so an error is *ONLY* logged and returns 1064 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon 1065 * would not be able to be reset or change link. 1066 **/ 1067 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw) 1068 { 1069 s32 timeout = PHY_CFG_TIMEOUT; 1070 s32 ret_val = E1000_SUCCESS; 1071 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 1072 1073 DEBUGFUNC("e1000_get_cfg_done_82575"); 1074 1075 if (hw->bus.func == E1000_FUNC_1) 1076 mask = E1000_NVM_CFG_DONE_PORT_1; 1077 else if (hw->bus.func == E1000_FUNC_2) 1078 mask = E1000_NVM_CFG_DONE_PORT_2; 1079 else if (hw->bus.func == E1000_FUNC_3) 1080 mask = E1000_NVM_CFG_DONE_PORT_3; 1081 while (timeout) { 1082 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) 1083 break; 1084 msec_delay(1); 1085 timeout--; 1086 } 1087 if (!timeout) 1088 DEBUGOUT("MNG configuration cycle has not completed.\n"); 1089 1090 /* If EEPROM is not marked present, init the PHY manually */ 1091 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) && 1092 (hw->phy.type == e1000_phy_igp_3)) 1093 e1000_phy_init_script_igp3(hw); 1094 1095 return ret_val; 1096 } 1097 1098 /** 1099 * e1000_get_link_up_info_82575 - Get link speed/duplex info 1100 * @hw: pointer to the HW structure 1101 * @speed: stores the current speed 1102 * @duplex: stores the current duplex 1103 * 1104 * This is a wrapper function, if using the serial gigabit media independent 1105 * interface, use PCS to retrieve the link speed and duplex information. 1106 * Otherwise, use the generic function to get the link speed and duplex info. 1107 **/ 1108 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 1109 u16 *duplex) 1110 { 1111 s32 ret_val; 1112 1113 DEBUGFUNC("e1000_get_link_up_info_82575"); 1114 1115 if (hw->phy.media_type != e1000_media_type_copper) 1116 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed, 1117 duplex); 1118 else 1119 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, 1120 duplex); 1121 1122 return ret_val; 1123 } 1124 1125 /** 1126 * e1000_check_for_link_82575 - Check for link 1127 * @hw: pointer to the HW structure 1128 * 1129 * If sgmii is enabled, then use the pcs register to determine link, otherwise 1130 * use the generic interface for determining link. 1131 **/ 1132 static s32 e1000_check_for_link_82575(struct e1000_hw *hw) 1133 { 1134 s32 ret_val; 1135 u16 speed, duplex; 1136 1137 DEBUGFUNC("e1000_check_for_link_82575"); 1138 1139 if (hw->phy.media_type != e1000_media_type_copper) { 1140 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed, 1141 &duplex); 1142 /* 1143 * Use this flag to determine if link needs to be checked or 1144 * not. If we have link clear the flag so that we do not 1145 * continue to check for link. 1146 */ 1147 hw->mac.get_link_status = !hw->mac.serdes_has_link; 1148 1149 /* 1150 * Configure Flow Control now that Auto-Neg has completed. 1151 * First, we need to restore the desired flow control 1152 * settings because we may have had to re-autoneg with a 1153 * different link partner. 1154 */ 1155 ret_val = e1000_config_fc_after_link_up_generic(hw); 1156 if (ret_val) 1157 DEBUGOUT("Error configuring flow control\n"); 1158 } else { 1159 ret_val = e1000_check_for_copper_link_generic(hw); 1160 } 1161 1162 return ret_val; 1163 } 1164 1165 /** 1166 * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown 1167 * @hw: pointer to the HW structure 1168 **/ 1169 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw) 1170 { 1171 u32 reg; 1172 1173 DEBUGFUNC("e1000_power_up_serdes_link_82575"); 1174 1175 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1176 !e1000_sgmii_active_82575(hw)) 1177 return; 1178 1179 /* Enable PCS to turn on link */ 1180 reg = E1000_READ_REG(hw, E1000_PCS_CFG0); 1181 reg |= E1000_PCS_CFG_PCS_EN; 1182 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg); 1183 1184 /* Power up the laser */ 1185 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1186 reg &= ~E1000_CTRL_EXT_SDP3_DATA; 1187 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1188 1189 /* flush the write to verify completion */ 1190 E1000_WRITE_FLUSH(hw); 1191 msec_delay(1); 1192 } 1193 1194 /** 1195 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex 1196 * @hw: pointer to the HW structure 1197 * @speed: stores the current speed 1198 * @duplex: stores the current duplex 1199 * 1200 * Using the physical coding sub-layer (PCS), retrieve the current speed and 1201 * duplex, then store the values in the pointers provided. 1202 **/ 1203 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 1204 u16 *speed, u16 *duplex) 1205 { 1206 struct e1000_mac_info *mac = &hw->mac; 1207 u32 pcs; 1208 1209 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575"); 1210 1211 /* 1212 * Read the PCS Status register for link state. For non-copper mode, 1213 * the status register is not accurate. The PCS status register is 1214 * used instead. 1215 */ 1216 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT); 1217 1218 /* 1219 * The link up bit determines when link is up on autoneg. 1220 */ 1221 if (pcs & E1000_PCS_LSTS_LINK_OK) { 1222 mac->serdes_has_link = TRUE; 1223 1224 /* Detect and store PCS speed */ 1225 if (pcs & E1000_PCS_LSTS_SPEED_1000) 1226 *speed = SPEED_1000; 1227 else if (pcs & E1000_PCS_LSTS_SPEED_100) 1228 *speed = SPEED_100; 1229 else 1230 *speed = SPEED_10; 1231 1232 /* Detect and store PCS duplex */ 1233 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) 1234 *duplex = FULL_DUPLEX; 1235 else 1236 *duplex = HALF_DUPLEX; 1237 } else { 1238 mac->serdes_has_link = FALSE; 1239 *speed = 0; 1240 *duplex = 0; 1241 } 1242 1243 return E1000_SUCCESS; 1244 } 1245 1246 /** 1247 * e1000_shutdown_serdes_link_82575 - Remove link during power down 1248 * @hw: pointer to the HW structure 1249 * 1250 * In the case of serdes shut down sfp and PCS on driver unload 1251 * when management pass thru is not enabled. 1252 **/ 1253 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw) 1254 { 1255 u32 reg; 1256 1257 DEBUGFUNC("e1000_shutdown_serdes_link_82575"); 1258 1259 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1260 !e1000_sgmii_active_82575(hw)) 1261 return; 1262 1263 if (!e1000_enable_mng_pass_thru(hw)) { 1264 /* Disable PCS to turn off link */ 1265 reg = E1000_READ_REG(hw, E1000_PCS_CFG0); 1266 reg &= ~E1000_PCS_CFG_PCS_EN; 1267 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg); 1268 1269 /* shutdown the laser */ 1270 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1271 reg |= E1000_CTRL_EXT_SDP3_DATA; 1272 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1273 1274 /* flush the write to verify completion */ 1275 E1000_WRITE_FLUSH(hw); 1276 msec_delay(1); 1277 } 1278 1279 return; 1280 } 1281 1282 /** 1283 * e1000_reset_hw_82575 - Reset hardware 1284 * @hw: pointer to the HW structure 1285 * 1286 * This resets the hardware into a known state. 1287 **/ 1288 static s32 e1000_reset_hw_82575(struct e1000_hw *hw) 1289 { 1290 u32 ctrl; 1291 s32 ret_val; 1292 1293 DEBUGFUNC("e1000_reset_hw_82575"); 1294 1295 /* 1296 * Prevent the PCI-E bus from sticking if there is no TLP connection 1297 * on the last TLP read/write transaction when MAC is reset. 1298 */ 1299 ret_val = e1000_disable_pcie_master_generic(hw); 1300 if (ret_val) 1301 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 1302 1303 /* set the completion timeout for interface */ 1304 ret_val = e1000_set_pcie_completion_timeout(hw); 1305 if (ret_val) 1306 DEBUGOUT("PCI-E Set completion timeout has failed.\n"); 1307 1308 DEBUGOUT("Masking off all interrupts\n"); 1309 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1310 1311 E1000_WRITE_REG(hw, E1000_RCTL, 0); 1312 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 1313 E1000_WRITE_FLUSH(hw); 1314 1315 msec_delay(10); 1316 1317 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1318 1319 DEBUGOUT("Issuing a global reset to MAC\n"); 1320 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 1321 1322 ret_val = e1000_get_auto_rd_done_generic(hw); 1323 if (ret_val) { 1324 /* 1325 * When auto config read does not complete, do not 1326 * return with an error. This can happen in situations 1327 * where there is no eeprom and prevents getting link. 1328 */ 1329 DEBUGOUT("Auto Read Done did not complete\n"); 1330 } 1331 1332 /* If EEPROM is not present, run manual init scripts */ 1333 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES)) 1334 e1000_reset_init_script_82575(hw); 1335 1336 /* Clear any pending interrupt events. */ 1337 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1338 E1000_READ_REG(hw, E1000_ICR); 1339 1340 /* Install any alternate MAC address into RAR0 */ 1341 ret_val = e1000_check_alt_mac_addr_generic(hw); 1342 1343 return ret_val; 1344 } 1345 1346 /** 1347 * e1000_init_hw_82575 - Initialize hardware 1348 * @hw: pointer to the HW structure 1349 * 1350 * This inits the hardware readying it for operation. 1351 **/ 1352 static s32 e1000_init_hw_82575(struct e1000_hw *hw) 1353 { 1354 struct e1000_mac_info *mac = &hw->mac; 1355 s32 ret_val; 1356 u16 i, rar_count = mac->rar_entry_count; 1357 1358 DEBUGFUNC("e1000_init_hw_82575"); 1359 1360 /* Initialize identification LED */ 1361 ret_val = mac->ops.id_led_init(hw); 1362 if (ret_val) { 1363 DEBUGOUT("Error initializing identification LED\n"); 1364 /* This is not fatal and we should not stop init due to this */ 1365 } 1366 1367 /* Disabling VLAN filtering */ 1368 DEBUGOUT("Initializing the IEEE VLAN\n"); 1369 mac->ops.clear_vfta(hw); 1370 1371 /* Setup the receive address */ 1372 e1000_init_rx_addrs_generic(hw, rar_count); 1373 1374 /* Zero out the Multicast HASH table */ 1375 DEBUGOUT("Zeroing the MTA\n"); 1376 for (i = 0; i < mac->mta_reg_count; i++) 1377 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1378 1379 /* Zero out the Unicast HASH table */ 1380 DEBUGOUT("Zeroing the UTA\n"); 1381 for (i = 0; i < mac->uta_reg_count; i++) 1382 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0); 1383 1384 /* Setup link and flow control */ 1385 ret_val = mac->ops.setup_link(hw); 1386 1387 /* Set the default MTU size */ 1388 hw->dev_spec._82575.mtu = 1500; 1389 1390 /* 1391 * Clear all of the statistics registers (clear on read). It is 1392 * important that we do this after we have tried to establish link 1393 * because the symbol error count will increment wildly if there 1394 * is no link. 1395 */ 1396 e1000_clear_hw_cntrs_82575(hw); 1397 1398 return ret_val; 1399 } 1400 1401 /** 1402 * e1000_setup_copper_link_82575 - Configure copper link settings 1403 * @hw: pointer to the HW structure 1404 * 1405 * Configures the link for auto-neg or forced speed and duplex. Then we check 1406 * for link, once link is established calls to configure collision distance 1407 * and flow control are called. 1408 **/ 1409 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw) 1410 { 1411 u32 ctrl; 1412 s32 ret_val; 1413 u32 phpm_reg; 1414 1415 DEBUGFUNC("e1000_setup_copper_link_82575"); 1416 1417 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1418 ctrl |= E1000_CTRL_SLU; 1419 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1420 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1421 1422 /* Clear Go Link Disconnect bit */ 1423 if (hw->mac.type >= e1000_82580) { 1424 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); 1425 phpm_reg &= ~E1000_82580_PM_GO_LINKD; 1426 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg); 1427 } 1428 1429 ret_val = e1000_setup_serdes_link_82575(hw); 1430 if (ret_val) 1431 goto out; 1432 1433 if (e1000_sgmii_active_82575(hw)) { 1434 /* allow time for SFP cage time to power up phy */ 1435 msec_delay(300); 1436 1437 ret_val = hw->phy.ops.reset(hw); 1438 if (ret_val) { 1439 DEBUGOUT("Error resetting the PHY.\n"); 1440 goto out; 1441 } 1442 } 1443 switch (hw->phy.type) { 1444 case e1000_phy_i210: 1445 case e1000_phy_m88: 1446 if (hw->phy.id == I347AT4_E_PHY_ID || 1447 hw->phy.id == M88E1112_E_PHY_ID || 1448 hw->phy.id == M88E1340M_E_PHY_ID) 1449 ret_val = e1000_copper_link_setup_m88_gen2(hw); 1450 else 1451 ret_val = e1000_copper_link_setup_m88(hw); 1452 break; 1453 case e1000_phy_igp_3: 1454 ret_val = e1000_copper_link_setup_igp(hw); 1455 break; 1456 case e1000_phy_82580: 1457 ret_val = e1000_copper_link_setup_82577(hw); 1458 break; 1459 default: 1460 ret_val = -E1000_ERR_PHY; 1461 break; 1462 } 1463 1464 if (ret_val) 1465 goto out; 1466 1467 ret_val = e1000_setup_copper_link_generic(hw); 1468 out: 1469 return ret_val; 1470 } 1471 1472 /** 1473 * e1000_setup_serdes_link_82575 - Setup link for serdes 1474 * @hw: pointer to the HW structure 1475 * 1476 * Configure the physical coding sub-layer (PCS) link. The PCS link is 1477 * used on copper connections where the serialized gigabit media independent 1478 * interface (sgmii), or serdes fiber is being used. Configures the link 1479 * for auto-negotiation or forces speed/duplex. 1480 **/ 1481 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw) 1482 { 1483 u32 ctrl_ext, ctrl_reg, reg, anadv_reg; 1484 bool pcs_autoneg; 1485 s32 ret_val = E1000_SUCCESS; 1486 u16 data; 1487 1488 DEBUGFUNC("e1000_setup_serdes_link_82575"); 1489 1490 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1491 !e1000_sgmii_active_82575(hw)) 1492 return ret_val; 1493 1494 /* 1495 * On the 82575, SerDes loopback mode persists until it is 1496 * explicitly turned off or a power cycle is performed. A read to 1497 * the register does not indicate its status. Therefore, we ensure 1498 * loopback mode is disabled during initialization. 1499 */ 1500 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1501 1502 /* power on the sfp cage if present */ 1503 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1504 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 1505 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1506 1507 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL); 1508 ctrl_reg |= E1000_CTRL_SLU; 1509 1510 /* set both sw defined pins on 82575/82576*/ 1511 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) 1512 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 1513 1514 reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 1515 1516 /* default pcs_autoneg to the same setting as mac autoneg */ 1517 pcs_autoneg = hw->mac.autoneg; 1518 1519 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 1520 case E1000_CTRL_EXT_LINK_MODE_SGMII: 1521 /* sgmii mode lets the phy handle forcing speed/duplex */ 1522 pcs_autoneg = TRUE; 1523 /* autoneg time out should be disabled for SGMII mode */ 1524 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); 1525 break; 1526 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 1527 /* disable PCS autoneg and support parallel detect only */ 1528 pcs_autoneg = FALSE; 1529 /* fall through to default case */ 1530 default: 1531 if (hw->mac.type == e1000_82575 || 1532 hw->mac.type == e1000_82576) { 1533 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data); 1534 if (ret_val) { 1535 DEBUGOUT("NVM Read Error\n"); 1536 return ret_val; 1537 } 1538 1539 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT) 1540 pcs_autoneg = FALSE; 1541 } 1542 1543 /* 1544 * non-SGMII modes only supports a speed of 1000/Full for the 1545 * link so it is best to just force the MAC and let the pcs 1546 * link either autoneg or be forced to 1000/Full 1547 */ 1548 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD | 1549 E1000_CTRL_FD | E1000_CTRL_FRCDPX; 1550 1551 /* set speed of 1000/Full if speed/duplex is forced */ 1552 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; 1553 break; 1554 } 1555 1556 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg); 1557 1558 /* 1559 * New SerDes mode allows for forcing speed or autonegotiating speed 1560 * at 1gb. Autoneg should be default set by most drivers. This is the 1561 * mode that will be compatible with older link partners and switches. 1562 * However, both are supported by the hardware and some drivers/tools. 1563 */ 1564 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | 1565 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); 1566 1567 if (pcs_autoneg) { 1568 /* Set PCS register for autoneg */ 1569 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ 1570 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ 1571 1572 /* Disable force flow control for autoneg */ 1573 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL; 1574 1575 /* Configure flow control advertisement for autoneg */ 1576 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV); 1577 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE); 1578 1579 switch (hw->fc.requested_mode) { 1580 case e1000_fc_full: 1581 case e1000_fc_rx_pause: 1582 anadv_reg |= E1000_TXCW_ASM_DIR; 1583 anadv_reg |= E1000_TXCW_PAUSE; 1584 break; 1585 case e1000_fc_tx_pause: 1586 anadv_reg |= E1000_TXCW_ASM_DIR; 1587 break; 1588 default: 1589 break; 1590 } 1591 1592 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg); 1593 1594 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg); 1595 } else { 1596 /* Set PCS register for forced link */ 1597 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ 1598 1599 /* Force flow control for forced link */ 1600 reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1601 1602 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg); 1603 } 1604 1605 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg); 1606 1607 if (!pcs_autoneg && !e1000_sgmii_active_82575(hw)) 1608 e1000_force_mac_fc_generic(hw); 1609 1610 return ret_val; 1611 } 1612 1613 /** 1614 * e1000_get_media_type_82575 - derives current media type. 1615 * @hw: pointer to the HW structure 1616 * 1617 * The media type is chosen reflecting few settings. 1618 * The following are taken into account: 1619 * - link mode set in the current port Init Control Word #3 1620 * - current link mode settings in CSR register 1621 * - MDIO vs. I2C PHY control interface chosen 1622 * - SFP module media type 1623 **/ 1624 static s32 e1000_get_media_type_82575(struct e1000_hw *hw) 1625 { 1626 u32 lan_id = 0; 1627 s32 ret_val = E1000_ERR_CONFIG; 1628 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1629 u32 ctrl_ext = 0; 1630 u32 current_link_mode = 0; 1631 u16 init_ctrl_wd_3 = 0; 1632 u8 init_ctrl_wd_3_offset = 0; 1633 u8 init_ctrl_wd_3_bit_offset = 0; 1634 1635 /* Set internal phy as default */ 1636 dev_spec->sgmii_active = FALSE; 1637 dev_spec->module_plugged = FALSE; 1638 1639 /* 1640 * Check if NVM access method is attached already. 1641 * If it is then Init Control Word #3 is considered 1642 * otherwise runtime CSR register content is taken. 1643 */ 1644 1645 /* Get CSR setting */ 1646 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1647 1648 /* Get link mode setting */ 1649 if ((hw->nvm.ops.read) && (hw->nvm.ops.read != e1000_null_read_nvm)) { 1650 /* Take link mode from EEPROM */ 1651 1652 /* 1653 * Get LAN port ID to derive its 1654 * adequate Init Control Word #3 1655 */ 1656 lan_id = ((E1000_READ_REG(hw, E1000_STATUS) & 1657 E1000_STATUS_LAN_ID_MASK) >> E1000_STATUS_LAN_ID_OFFSET); 1658 /* 1659 * Derive Init Control Word #3 offset 1660 * and mask to pick up link mode setting. 1661 */ 1662 if (hw->mac.type < e1000_82580) { 1663 init_ctrl_wd_3_offset = lan_id ? 1664 NVM_INIT_CONTROL3_PORT_A : NVM_INIT_CONTROL3_PORT_B; 1665 init_ctrl_wd_3_bit_offset = NVM_WORD24_LNK_MODE_OFFSET; 1666 } else { 1667 init_ctrl_wd_3_offset = 1668 NVM_82580_LAN_FUNC_OFFSET(lan_id) + 1669 NVM_INIT_CONTROL3_PORT_A; 1670 init_ctrl_wd_3_bit_offset = 1671 NVM_WORD24_82580_LNK_MODE_OFFSET; 1672 } 1673 /* Read Init Control Word #3*/ 1674 hw->nvm.ops.read(hw, init_ctrl_wd_3_offset, 1, &init_ctrl_wd_3); 1675 1676 /* 1677 * Align link mode bits to 1678 * their CTRL_EXT location. 1679 */ 1680 current_link_mode = init_ctrl_wd_3; 1681 current_link_mode <<= (E1000_CTRL_EXT_LINK_MODE_OFFSET - 1682 init_ctrl_wd_3_bit_offset); 1683 current_link_mode &= E1000_CTRL_EXT_LINK_MODE_MASK; 1684 1685 /* 1686 * Switch to CSR for all but internal PHY. 1687 */ 1688 if (current_link_mode != E1000_CTRL_EXT_LINK_MODE_GMII) 1689 /* Take link mode from CSR */ 1690 current_link_mode = ctrl_ext & 1691 E1000_CTRL_EXT_LINK_MODE_MASK; 1692 } else { 1693 /* Take link mode from CSR */ 1694 current_link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK; 1695 } 1696 1697 switch (current_link_mode) { 1698 1699 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 1700 hw->phy.media_type = e1000_media_type_internal_serdes; 1701 current_link_mode = E1000_CTRL_EXT_LINK_MODE_1000BASE_KX; 1702 break; 1703 case E1000_CTRL_EXT_LINK_MODE_GMII: 1704 hw->phy.media_type = e1000_media_type_copper; 1705 current_link_mode = E1000_CTRL_EXT_LINK_MODE_GMII; 1706 break; 1707 case E1000_CTRL_EXT_LINK_MODE_SGMII: 1708 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 1709 /* Get phy control interface type set (MDIO vs. I2C)*/ 1710 if (e1000_sgmii_uses_mdio_82575(hw)) { 1711 hw->phy.media_type = e1000_media_type_copper; 1712 dev_spec->sgmii_active = TRUE; 1713 current_link_mode = E1000_CTRL_EXT_LINK_MODE_SGMII; 1714 } else { 1715 ret_val = e1000_set_sfp_media_type_82575(hw); 1716 if (ret_val != E1000_SUCCESS) 1717 goto out; 1718 if (hw->phy.media_type == 1719 e1000_media_type_internal_serdes) { 1720 /* Keep Link Mode as SGMII for 100BaseFX */ 1721 if (!dev_spec->eth_flags.e100_base_fx) { 1722 current_link_mode = 1723 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1724 } 1725 } else if (hw->phy.media_type == 1726 e1000_media_type_copper) { 1727 current_link_mode = 1728 E1000_CTRL_EXT_LINK_MODE_SGMII; 1729 } 1730 } 1731 break; 1732 default: 1733 DEBUGOUT("Link mode mask doesn't fit bit field size\n"); 1734 goto out; 1735 } 1736 /* 1737 * Do not change current link mode setting 1738 * if media type is fibre or has not been 1739 * recognized. 1740 */ 1741 if ((hw->phy.media_type != e1000_media_type_unknown) && 1742 (hw->phy.media_type != e1000_media_type_fiber)) { 1743 /* Update link mode */ 1744 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 1745 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | 1746 current_link_mode); 1747 } 1748 1749 ret_val = E1000_SUCCESS; 1750 out: 1751 /* 1752 * If media type was not identified then return media type 1753 * defined by the CTRL_EXT settings. 1754 */ 1755 if (hw->phy.media_type == e1000_media_type_unknown) { 1756 if (current_link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) 1757 hw->phy.media_type = e1000_media_type_copper; 1758 else 1759 hw->phy.media_type = e1000_media_type_internal_serdes; 1760 } 1761 1762 return ret_val; 1763 } 1764 1765 /** 1766 * e1000_set_sfp_media_type_82575 - derives SFP module media type. 1767 * @hw: pointer to the HW structure 1768 * 1769 * The media type is chosen based on SFP module. 1770 * compatibility flags retrieved from SFP ID EEPROM. 1771 **/ 1772 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw) 1773 { 1774 s32 ret_val = E1000_ERR_CONFIG; 1775 u32 ctrl_ext = 0; 1776 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1777 struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags; 1778 u8 tranceiver_type = 0; 1779 s32 timeout = 3; 1780 1781 /* Turn I2C interface ON and power on sfp cage */ 1782 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1783 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 1784 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA); 1785 1786 E1000_WRITE_FLUSH(hw); 1787 1788 /* Read SFP module data */ 1789 while (timeout) { 1790 ret_val = e1000_read_sfp_data_byte(hw, 1791 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET), 1792 &tranceiver_type); 1793 if (ret_val == E1000_SUCCESS) 1794 break; 1795 msec_delay(100); 1796 timeout--; 1797 } 1798 if (ret_val != E1000_SUCCESS) 1799 goto out; 1800 ret_val = e1000_read_sfp_data_byte(hw, 1801 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET), 1802 (u8 *)eth_flags); 1803 if (ret_val != E1000_SUCCESS) 1804 goto out; 1805 /* 1806 * Check if there is some SFP 1807 * module plugged and powered 1808 */ 1809 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) || 1810 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) { 1811 dev_spec->module_plugged = TRUE; 1812 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) { 1813 hw->phy.media_type = e1000_media_type_internal_serdes; 1814 } else if (eth_flags->e100_base_fx) { 1815 dev_spec->sgmii_active = TRUE; 1816 hw->phy.media_type = e1000_media_type_internal_serdes; 1817 } else if (eth_flags->e1000_base_t) { 1818 dev_spec->sgmii_active = TRUE; 1819 hw->phy.media_type = e1000_media_type_copper; 1820 } else { 1821 hw->phy.media_type = e1000_media_type_unknown; 1822 DEBUGOUT("PHY module has not been recognized\n"); 1823 goto out; 1824 } 1825 } else { 1826 hw->phy.media_type = e1000_media_type_unknown; 1827 } 1828 ret_val = E1000_SUCCESS; 1829 out: 1830 /* Restore I2C interface setting */ 1831 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1832 return ret_val; 1833 } 1834 1835 /** 1836 * e1000_valid_led_default_82575 - Verify a valid default LED config 1837 * @hw: pointer to the HW structure 1838 * @data: pointer to the NVM (EEPROM) 1839 * 1840 * Read the EEPROM for the current default LED configuration. If the 1841 * LED configuration is not valid, set to a valid LED configuration. 1842 **/ 1843 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data) 1844 { 1845 s32 ret_val; 1846 1847 DEBUGFUNC("e1000_valid_led_default_82575"); 1848 1849 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1850 if (ret_val) { 1851 DEBUGOUT("NVM Read Error\n"); 1852 goto out; 1853 } 1854 1855 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) { 1856 switch (hw->phy.media_type) { 1857 case e1000_media_type_internal_serdes: 1858 *data = ID_LED_DEFAULT_82575_SERDES; 1859 break; 1860 case e1000_media_type_copper: 1861 default: 1862 *data = ID_LED_DEFAULT; 1863 break; 1864 } 1865 } 1866 out: 1867 return ret_val; 1868 } 1869 1870 /** 1871 * e1000_sgmii_active_82575 - Return sgmii state 1872 * @hw: pointer to the HW structure 1873 * 1874 * 82575 silicon has a serialized gigabit media independent interface (sgmii) 1875 * which can be enabled for use in the embedded applications. Simply 1876 * return the current state of the sgmii interface. 1877 **/ 1878 static bool e1000_sgmii_active_82575(struct e1000_hw *hw) 1879 { 1880 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1881 return dev_spec->sgmii_active; 1882 } 1883 1884 /** 1885 * e1000_reset_init_script_82575 - Inits HW defaults after reset 1886 * @hw: pointer to the HW structure 1887 * 1888 * Inits recommended HW defaults after a reset when there is no EEPROM 1889 * detected. This is only for the 82575. 1890 **/ 1891 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw) 1892 { 1893 DEBUGFUNC("e1000_reset_init_script_82575"); 1894 1895 if (hw->mac.type == e1000_82575) { 1896 DEBUGOUT("Running reset init script for 82575\n"); 1897 /* SerDes configuration via SERDESCTRL */ 1898 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C); 1899 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78); 1900 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23); 1901 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15); 1902 1903 /* CCM configuration via CCMCTL register */ 1904 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00); 1905 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00); 1906 1907 /* PCIe lanes configuration */ 1908 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC); 1909 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF); 1910 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05); 1911 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81); 1912 1913 /* PCIe PLL Configuration */ 1914 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47); 1915 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00); 1916 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00); 1917 } 1918 1919 return E1000_SUCCESS; 1920 } 1921 1922 /** 1923 * e1000_read_mac_addr_82575 - Read device MAC address 1924 * @hw: pointer to the HW structure 1925 **/ 1926 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw) 1927 { 1928 s32 ret_val = E1000_SUCCESS; 1929 1930 DEBUGFUNC("e1000_read_mac_addr_82575"); 1931 1932 /* 1933 * If there's an alternate MAC address place it in RAR0 1934 * so that it will override the Si installed default perm 1935 * address. 1936 */ 1937 ret_val = e1000_check_alt_mac_addr_generic(hw); 1938 if (ret_val) 1939 goto out; 1940 1941 ret_val = e1000_read_mac_addr_generic(hw); 1942 1943 out: 1944 return ret_val; 1945 } 1946 1947 /** 1948 * e1000_config_collision_dist_82575 - Configure collision distance 1949 * @hw: pointer to the HW structure 1950 * 1951 * Configures the collision distance to the default value and is used 1952 * during link setup. 1953 **/ 1954 static void e1000_config_collision_dist_82575(struct e1000_hw *hw) 1955 { 1956 u32 tctl_ext; 1957 1958 DEBUGFUNC("e1000_config_collision_dist_82575"); 1959 1960 tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT); 1961 1962 tctl_ext &= ~E1000_TCTL_EXT_COLD; 1963 tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT; 1964 1965 E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext); 1966 E1000_WRITE_FLUSH(hw); 1967 } 1968 1969 /** 1970 * e1000_power_down_phy_copper_82575 - Remove link during PHY power down 1971 * @hw: pointer to the HW structure 1972 * 1973 * In the case of a PHY power down to save power, or to turn off link during a 1974 * driver unload, or wake on lan is not enabled, remove the link. 1975 **/ 1976 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw) 1977 { 1978 struct e1000_phy_info *phy = &hw->phy; 1979 1980 if (!(phy->ops.check_reset_block)) 1981 return; 1982 1983 /* If the management interface is not enabled, then power down */ 1984 if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw))) 1985 e1000_power_down_phy_copper(hw); 1986 1987 return; 1988 } 1989 1990 /** 1991 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters 1992 * @hw: pointer to the HW structure 1993 * 1994 * Clears the hardware counters by reading the counter registers. 1995 **/ 1996 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw) 1997 { 1998 DEBUGFUNC("e1000_clear_hw_cntrs_82575"); 1999 2000 e1000_clear_hw_cntrs_base_generic(hw); 2001 2002 E1000_READ_REG(hw, E1000_PRC64); 2003 E1000_READ_REG(hw, E1000_PRC127); 2004 E1000_READ_REG(hw, E1000_PRC255); 2005 E1000_READ_REG(hw, E1000_PRC511); 2006 E1000_READ_REG(hw, E1000_PRC1023); 2007 E1000_READ_REG(hw, E1000_PRC1522); 2008 E1000_READ_REG(hw, E1000_PTC64); 2009 E1000_READ_REG(hw, E1000_PTC127); 2010 E1000_READ_REG(hw, E1000_PTC255); 2011 E1000_READ_REG(hw, E1000_PTC511); 2012 E1000_READ_REG(hw, E1000_PTC1023); 2013 E1000_READ_REG(hw, E1000_PTC1522); 2014 2015 E1000_READ_REG(hw, E1000_ALGNERRC); 2016 E1000_READ_REG(hw, E1000_RXERRC); 2017 E1000_READ_REG(hw, E1000_TNCRS); 2018 E1000_READ_REG(hw, E1000_CEXTERR); 2019 E1000_READ_REG(hw, E1000_TSCTC); 2020 E1000_READ_REG(hw, E1000_TSCTFC); 2021 2022 E1000_READ_REG(hw, E1000_MGTPRC); 2023 E1000_READ_REG(hw, E1000_MGTPDC); 2024 E1000_READ_REG(hw, E1000_MGTPTC); 2025 2026 E1000_READ_REG(hw, E1000_IAC); 2027 E1000_READ_REG(hw, E1000_ICRXOC); 2028 2029 E1000_READ_REG(hw, E1000_ICRXPTC); 2030 E1000_READ_REG(hw, E1000_ICRXATC); 2031 E1000_READ_REG(hw, E1000_ICTXPTC); 2032 E1000_READ_REG(hw, E1000_ICTXATC); 2033 E1000_READ_REG(hw, E1000_ICTXQEC); 2034 E1000_READ_REG(hw, E1000_ICTXQMTC); 2035 E1000_READ_REG(hw, E1000_ICRXDMTC); 2036 2037 E1000_READ_REG(hw, E1000_CBTMPC); 2038 E1000_READ_REG(hw, E1000_HTDPMC); 2039 E1000_READ_REG(hw, E1000_CBRMPC); 2040 E1000_READ_REG(hw, E1000_RPTHC); 2041 E1000_READ_REG(hw, E1000_HGPTC); 2042 E1000_READ_REG(hw, E1000_HTCBDPC); 2043 E1000_READ_REG(hw, E1000_HGORCL); 2044 E1000_READ_REG(hw, E1000_HGORCH); 2045 E1000_READ_REG(hw, E1000_HGOTCL); 2046 E1000_READ_REG(hw, E1000_HGOTCH); 2047 E1000_READ_REG(hw, E1000_LENERRS); 2048 2049 /* This register should not be read in copper configurations */ 2050 if ((hw->phy.media_type == e1000_media_type_internal_serdes) || 2051 e1000_sgmii_active_82575(hw)) 2052 E1000_READ_REG(hw, E1000_SCVPC); 2053 } 2054 2055 /** 2056 * e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable 2057 * @hw: pointer to the HW structure 2058 * 2059 * After rx enable if managability is enabled then there is likely some 2060 * bad data at the start of the fifo and possibly in the DMA fifo. This 2061 * function clears the fifos and flushes any packets that came in as rx was 2062 * being enabled. 2063 **/ 2064 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw) 2065 { 2066 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; 2067 int i, ms_wait; 2068 2069 DEBUGFUNC("e1000_rx_fifo_workaround_82575"); 2070 if (hw->mac.type != e1000_82575 || 2071 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN)) 2072 return; 2073 2074 /* Disable all Rx queues */ 2075 for (i = 0; i < 4; i++) { 2076 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i)); 2077 E1000_WRITE_REG(hw, E1000_RXDCTL(i), 2078 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); 2079 } 2080 /* Poll all queues to verify they have shut down */ 2081 for (ms_wait = 0; ms_wait < 10; ms_wait++) { 2082 msec_delay(1); 2083 rx_enabled = 0; 2084 for (i = 0; i < 4; i++) 2085 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i)); 2086 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) 2087 break; 2088 } 2089 2090 if (ms_wait == 10) 2091 DEBUGOUT("Queue disable timed out after 10ms\n"); 2092 2093 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all 2094 * incoming packets are rejected. Set enable and wait 2ms so that 2095 * any packet that was coming in as RCTL.EN was set is flushed 2096 */ 2097 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 2098 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); 2099 2100 rlpml = E1000_READ_REG(hw, E1000_RLPML); 2101 E1000_WRITE_REG(hw, E1000_RLPML, 0); 2102 2103 rctl = E1000_READ_REG(hw, E1000_RCTL); 2104 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); 2105 temp_rctl |= E1000_RCTL_LPE; 2106 2107 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl); 2108 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN); 2109 E1000_WRITE_FLUSH(hw); 2110 msec_delay(2); 2111 2112 /* Enable Rx queues that were previously enabled and restore our 2113 * previous state 2114 */ 2115 for (i = 0; i < 4; i++) 2116 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]); 2117 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2118 E1000_WRITE_FLUSH(hw); 2119 2120 E1000_WRITE_REG(hw, E1000_RLPML, rlpml); 2121 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 2122 2123 /* Flush receive errors generated by workaround */ 2124 E1000_READ_REG(hw, E1000_ROC); 2125 E1000_READ_REG(hw, E1000_RNBC); 2126 E1000_READ_REG(hw, E1000_MPC); 2127 } 2128 2129 /** 2130 * e1000_set_pcie_completion_timeout - set pci-e completion timeout 2131 * @hw: pointer to the HW structure 2132 * 2133 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, 2134 * however the hardware default for these parts is 500us to 1ms which is less 2135 * than the 10ms recommended by the pci-e spec. To address this we need to 2136 * increase the value to either 10ms to 200ms for capability version 1 config, 2137 * or 16ms to 55ms for version 2. 2138 **/ 2139 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw) 2140 { 2141 u32 gcr = E1000_READ_REG(hw, E1000_GCR); 2142 s32 ret_val = E1000_SUCCESS; 2143 u16 pcie_devctl2; 2144 2145 /* only take action if timeout value is defaulted to 0 */ 2146 if (gcr & E1000_GCR_CMPL_TMOUT_MASK) 2147 goto out; 2148 2149 /* 2150 * if capababilities version is type 1 we can write the 2151 * timeout of 10ms to 200ms through the GCR register 2152 */ 2153 if (!(gcr & E1000_GCR_CAP_VER2)) { 2154 gcr |= E1000_GCR_CMPL_TMOUT_10ms; 2155 goto out; 2156 } 2157 2158 /* 2159 * for version 2 capabilities we need to write the config space 2160 * directly in order to set the completion timeout value for 2161 * 16ms to 55ms 2162 */ 2163 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 2164 &pcie_devctl2); 2165 if (ret_val) 2166 goto out; 2167 2168 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 2169 2170 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 2171 &pcie_devctl2); 2172 out: 2173 /* disable completion timeout resend */ 2174 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; 2175 2176 E1000_WRITE_REG(hw, E1000_GCR, gcr); 2177 return ret_val; 2178 } 2179 2180 /** 2181 * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing 2182 * @hw: pointer to the hardware struct 2183 * @enable: state to enter, either enabled or disabled 2184 * @pf: Physical Function pool - do not set anti-spoofing for the PF 2185 * 2186 * enables/disables L2 switch anti-spoofing functionality. 2187 **/ 2188 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf) 2189 { 2190 u32 dtxswc; 2191 2192 switch (hw->mac.type) { 2193 case e1000_82576: 2194 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC); 2195 if (enable) { 2196 dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK | 2197 E1000_DTXSWC_VLAN_SPOOF_MASK); 2198 /* The PF can spoof - it has to in order to 2199 * support emulation mode NICs */ 2200 dtxswc ^= (1 << pf | 1 << (pf + 2201 E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 2202 } else { 2203 dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK | 2204 E1000_DTXSWC_VLAN_SPOOF_MASK); 2205 } 2206 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc); 2207 break; 2208 case e1000_i350: 2209 dtxswc = E1000_READ_REG(hw, E1000_TXSWC); 2210 if (enable) { 2211 dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK | 2212 E1000_DTXSWC_VLAN_SPOOF_MASK); 2213 /* The PF can spoof - it has to in order to 2214 * support emulation mode NICs 2215 */ 2216 dtxswc ^= (1 << pf | 1 << (pf + 2217 E1000_DTXSWC_VLAN_SPOOF_SHIFT)); 2218 } else { 2219 dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK | 2220 E1000_DTXSWC_VLAN_SPOOF_MASK); 2221 } 2222 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc); 2223 default: 2224 break; 2225 } 2226 } 2227 2228 /** 2229 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback 2230 * @hw: pointer to the hardware struct 2231 * @enable: state to enter, either enabled or disabled 2232 * 2233 * enables/disables L2 switch loopback functionality. 2234 **/ 2235 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable) 2236 { 2237 u32 dtxswc; 2238 2239 switch (hw->mac.type) { 2240 case e1000_82576: 2241 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC); 2242 if (enable) 2243 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2244 else 2245 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2246 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc); 2247 break; 2248 case e1000_i350: 2249 dtxswc = E1000_READ_REG(hw, E1000_TXSWC); 2250 if (enable) 2251 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2252 else 2253 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2254 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc); 2255 break; 2256 default: 2257 /* Currently no other hardware supports loopback */ 2258 break; 2259 } 2260 2261 2262 } 2263 2264 /** 2265 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication 2266 * @hw: pointer to the hardware struct 2267 * @enable: state to enter, either enabled or disabled 2268 * 2269 * enables/disables replication of packets across multiple pools. 2270 **/ 2271 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) 2272 { 2273 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL); 2274 2275 if (enable) 2276 vt_ctl |= E1000_VT_CTL_VM_REPL_EN; 2277 else 2278 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN; 2279 2280 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl); 2281 } 2282 2283 /** 2284 * e1000_read_phy_reg_82580 - Read 82580 MDI control register 2285 * @hw: pointer to the HW structure 2286 * @offset: register offset to be read 2287 * @data: pointer to the read data 2288 * 2289 * Reads the MDI control register in the PHY at offset and stores the 2290 * information read to data. 2291 **/ 2292 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data) 2293 { 2294 s32 ret_val; 2295 2296 DEBUGFUNC("e1000_read_phy_reg_82580"); 2297 2298 ret_val = hw->phy.ops.acquire(hw); 2299 if (ret_val) 2300 goto out; 2301 2302 ret_val = e1000_read_phy_reg_mdic(hw, offset, data); 2303 2304 hw->phy.ops.release(hw); 2305 2306 out: 2307 return ret_val; 2308 } 2309 2310 /** 2311 * e1000_write_phy_reg_82580 - Write 82580 MDI control register 2312 * @hw: pointer to the HW structure 2313 * @offset: register offset to write to 2314 * @data: data to write to register at offset 2315 * 2316 * Writes data to MDI control register in the PHY at offset. 2317 **/ 2318 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data) 2319 { 2320 s32 ret_val; 2321 2322 DEBUGFUNC("e1000_write_phy_reg_82580"); 2323 2324 ret_val = hw->phy.ops.acquire(hw); 2325 if (ret_val) 2326 goto out; 2327 2328 ret_val = e1000_write_phy_reg_mdic(hw, offset, data); 2329 2330 hw->phy.ops.release(hw); 2331 2332 out: 2333 return ret_val; 2334 } 2335 2336 /** 2337 * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits 2338 * @hw: pointer to the HW structure 2339 * 2340 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on 2341 * the values found in the EEPROM. This addresses an issue in which these 2342 * bits are not restored from EEPROM after reset. 2343 **/ 2344 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw) 2345 { 2346 s32 ret_val = E1000_SUCCESS; 2347 u32 mdicnfg; 2348 u16 nvm_data = 0; 2349 2350 DEBUGFUNC("e1000_reset_mdicnfg_82580"); 2351 2352 if (hw->mac.type != e1000_82580) 2353 goto out; 2354 if (!e1000_sgmii_active_82575(hw)) 2355 goto out; 2356 2357 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2358 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2359 &nvm_data); 2360 if (ret_val) { 2361 DEBUGOUT("NVM Read Error\n"); 2362 goto out; 2363 } 2364 2365 mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG); 2366 if (nvm_data & NVM_WORD24_EXT_MDIO) 2367 mdicnfg |= E1000_MDICNFG_EXT_MDIO; 2368 if (nvm_data & NVM_WORD24_COM_MDIO) 2369 mdicnfg |= E1000_MDICNFG_COM_MDIO; 2370 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg); 2371 out: 2372 return ret_val; 2373 } 2374 2375 /** 2376 * e1000_reset_hw_82580 - Reset hardware 2377 * @hw: pointer to the HW structure 2378 * 2379 * This resets function or entire device (all ports, etc.) 2380 * to a known state. 2381 **/ 2382 static s32 e1000_reset_hw_82580(struct e1000_hw *hw) 2383 { 2384 s32 ret_val = E1000_SUCCESS; 2385 /* BH SW mailbox bit in SW_FW_SYNC */ 2386 u16 swmbsw_mask = E1000_SW_SYNCH_MB; 2387 u32 ctrl; 2388 bool global_device_reset = hw->dev_spec._82575.global_device_reset; 2389 2390 DEBUGFUNC("e1000_reset_hw_82580"); 2391 2392 hw->dev_spec._82575.global_device_reset = FALSE; 2393 2394 /* Get current control state. */ 2395 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2396 2397 /* 2398 * Prevent the PCI-E bus from sticking if there is no TLP connection 2399 * on the last TLP read/write transaction when MAC is reset. 2400 */ 2401 ret_val = e1000_disable_pcie_master_generic(hw); 2402 if (ret_val) 2403 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 2404 2405 DEBUGOUT("Masking off all interrupts\n"); 2406 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 2407 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2408 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 2409 E1000_WRITE_FLUSH(hw); 2410 2411 msec_delay(10); 2412 2413 /* Determine whether or not a global dev reset is requested */ 2414 if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw, 2415 swmbsw_mask)) 2416 global_device_reset = FALSE; 2417 2418 if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) & 2419 E1000_STAT_DEV_RST_SET)) 2420 ctrl |= E1000_CTRL_DEV_RST; 2421 else 2422 ctrl |= E1000_CTRL_RST; 2423 2424 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2425 E1000_WRITE_FLUSH(hw); 2426 2427 /* Add delay to insure DEV_RST has time to complete */ 2428 if (global_device_reset) 2429 msec_delay(5); 2430 2431 ret_val = e1000_get_auto_rd_done_generic(hw); 2432 if (ret_val) { 2433 /* 2434 * When auto config read does not complete, do not 2435 * return with an error. This can happen in situations 2436 * where there is no eeprom and prevents getting link. 2437 */ 2438 DEBUGOUT("Auto Read Done did not complete\n"); 2439 } 2440 2441 /* If EEPROM is not present, run manual init scripts */ 2442 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES)) 2443 e1000_reset_init_script_82575(hw); 2444 2445 /* clear global device reset status bit */ 2446 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET); 2447 2448 /* Clear any pending interrupt events. */ 2449 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 2450 E1000_READ_REG(hw, E1000_ICR); 2451 2452 ret_val = e1000_reset_mdicnfg_82580(hw); 2453 if (ret_val) 2454 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n"); 2455 2456 /* Install any alternate MAC address into RAR0 */ 2457 ret_val = e1000_check_alt_mac_addr_generic(hw); 2458 2459 /* Release semaphore */ 2460 if (global_device_reset) 2461 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask); 2462 2463 return ret_val; 2464 } 2465 2466 /** 2467 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size 2468 * @data: data received by reading RXPBS register 2469 * 2470 * The 82580 uses a table based approach for packet buffer allocation sizes. 2471 * This function converts the retrieved value into the correct table value 2472 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 2473 * 0x0 36 72 144 1 2 4 8 16 2474 * 0x8 35 70 140 rsv rsv rsv rsv rsv 2475 */ 2476 u16 e1000_rxpbs_adjust_82580(u32 data) 2477 { 2478 u16 ret_val = 0; 2479 2480 if (data < E1000_82580_RXPBS_TABLE_SIZE) 2481 ret_val = e1000_82580_rxpbs_table[data]; 2482 2483 return ret_val; 2484 } 2485 2486 /** 2487 * e1000_validate_nvm_checksum_with_offset - Validate EEPROM 2488 * checksum 2489 * @hw: pointer to the HW structure 2490 * @offset: offset in words of the checksum protected region 2491 * 2492 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 2493 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 2494 **/ 2495 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) 2496 { 2497 s32 ret_val = E1000_SUCCESS; 2498 u16 checksum = 0; 2499 u16 i, nvm_data; 2500 2501 DEBUGFUNC("e1000_validate_nvm_checksum_with_offset"); 2502 2503 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) { 2504 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 2505 if (ret_val) { 2506 DEBUGOUT("NVM Read Error\n"); 2507 goto out; 2508 } 2509 checksum += nvm_data; 2510 } 2511 2512 if (checksum != (u16) NVM_SUM) { 2513 DEBUGOUT("NVM Checksum Invalid\n"); 2514 ret_val = -E1000_ERR_NVM; 2515 goto out; 2516 } 2517 2518 out: 2519 return ret_val; 2520 } 2521 2522 /** 2523 * e1000_update_nvm_checksum_with_offset - Update EEPROM 2524 * checksum 2525 * @hw: pointer to the HW structure 2526 * @offset: offset in words of the checksum protected region 2527 * 2528 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 2529 * up to the checksum. Then calculates the EEPROM checksum and writes the 2530 * value to the EEPROM. 2531 **/ 2532 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) 2533 { 2534 s32 ret_val; 2535 u16 checksum = 0; 2536 u16 i, nvm_data; 2537 2538 DEBUGFUNC("e1000_update_nvm_checksum_with_offset"); 2539 2540 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) { 2541 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 2542 if (ret_val) { 2543 DEBUGOUT("NVM Read Error while updating checksum.\n"); 2544 goto out; 2545 } 2546 checksum += nvm_data; 2547 } 2548 checksum = (u16) NVM_SUM - checksum; 2549 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1, 2550 &checksum); 2551 if (ret_val) 2552 DEBUGOUT("NVM Write Error while updating checksum.\n"); 2553 2554 out: 2555 return ret_val; 2556 } 2557 2558 /** 2559 * e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum 2560 * @hw: pointer to the HW structure 2561 * 2562 * Calculates the EEPROM section checksum by reading/adding each word of 2563 * the EEPROM and then verifies that the sum of the EEPROM is 2564 * equal to 0xBABA. 2565 **/ 2566 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw) 2567 { 2568 s32 ret_val = E1000_SUCCESS; 2569 u16 eeprom_regions_count = 1; 2570 u16 j, nvm_data; 2571 u16 nvm_offset; 2572 2573 DEBUGFUNC("e1000_validate_nvm_checksum_82580"); 2574 2575 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); 2576 if (ret_val) { 2577 DEBUGOUT("NVM Read Error\n"); 2578 goto out; 2579 } 2580 2581 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) { 2582 /* if chekcsums compatibility bit is set validate checksums 2583 * for all 4 ports. */ 2584 eeprom_regions_count = 4; 2585 } 2586 2587 for (j = 0; j < eeprom_regions_count; j++) { 2588 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2589 ret_val = e1000_validate_nvm_checksum_with_offset(hw, 2590 nvm_offset); 2591 if (ret_val != E1000_SUCCESS) 2592 goto out; 2593 } 2594 2595 out: 2596 return ret_val; 2597 } 2598 2599 /** 2600 * e1000_update_nvm_checksum_82580 - Update EEPROM checksum 2601 * @hw: pointer to the HW structure 2602 * 2603 * Updates the EEPROM section checksums for all 4 ports by reading/adding 2604 * each word of the EEPROM up to the checksum. Then calculates the EEPROM 2605 * checksum and writes the value to the EEPROM. 2606 **/ 2607 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw) 2608 { 2609 s32 ret_val; 2610 u16 j, nvm_data; 2611 u16 nvm_offset; 2612 2613 DEBUGFUNC("e1000_update_nvm_checksum_82580"); 2614 2615 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); 2616 if (ret_val) { 2617 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n"); 2618 goto out; 2619 } 2620 2621 if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) { 2622 /* set compatibility bit to validate checksums appropriately */ 2623 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK; 2624 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1, 2625 &nvm_data); 2626 if (ret_val) { 2627 DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n"); 2628 goto out; 2629 } 2630 } 2631 2632 for (j = 0; j < 4; j++) { 2633 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2634 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset); 2635 if (ret_val) 2636 goto out; 2637 } 2638 2639 out: 2640 return ret_val; 2641 } 2642 2643 /** 2644 * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum 2645 * @hw: pointer to the HW structure 2646 * 2647 * Calculates the EEPROM section checksum by reading/adding each word of 2648 * the EEPROM and then verifies that the sum of the EEPROM is 2649 * equal to 0xBABA. 2650 **/ 2651 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw) 2652 { 2653 s32 ret_val = E1000_SUCCESS; 2654 u16 j; 2655 u16 nvm_offset; 2656 2657 DEBUGFUNC("e1000_validate_nvm_checksum_i350"); 2658 2659 for (j = 0; j < 4; j++) { 2660 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2661 ret_val = e1000_validate_nvm_checksum_with_offset(hw, 2662 nvm_offset); 2663 if (ret_val != E1000_SUCCESS) 2664 goto out; 2665 } 2666 2667 out: 2668 return ret_val; 2669 } 2670 2671 /** 2672 * e1000_update_nvm_checksum_i350 - Update EEPROM checksum 2673 * @hw: pointer to the HW structure 2674 * 2675 * Updates the EEPROM section checksums for all 4 ports by reading/adding 2676 * each word of the EEPROM up to the checksum. Then calculates the EEPROM 2677 * checksum and writes the value to the EEPROM. 2678 **/ 2679 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw) 2680 { 2681 s32 ret_val = E1000_SUCCESS; 2682 u16 j; 2683 u16 nvm_offset; 2684 2685 DEBUGFUNC("e1000_update_nvm_checksum_i350"); 2686 2687 for (j = 0; j < 4; j++) { 2688 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2689 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset); 2690 if (ret_val != E1000_SUCCESS) 2691 goto out; 2692 } 2693 2694 out: 2695 return ret_val; 2696 } 2697 2698 /** 2699 * e1000_set_eee_i350 - Enable/disable EEE support 2700 * @hw: pointer to the HW structure 2701 * 2702 * Enable/disable EEE based on setting in dev_spec structure. 2703 * 2704 **/ 2705 s32 e1000_set_eee_i350(struct e1000_hw *hw) 2706 { 2707 s32 ret_val = E1000_SUCCESS; 2708 u32 ipcnfg, eeer; 2709 2710 DEBUGFUNC("e1000_set_eee_i350"); 2711 2712 if ((hw->mac.type < e1000_i350) || 2713 (hw->phy.media_type != e1000_media_type_copper)) 2714 goto out; 2715 ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG); 2716 eeer = E1000_READ_REG(hw, E1000_EEER); 2717 2718 /* enable or disable per user setting */ 2719 if (!(hw->dev_spec._82575.eee_disable)) { 2720 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); 2721 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 2722 E1000_EEER_LPI_FC); 2723 2724 /* keep the LPI clock running before EEE is enabled */ 2725 if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) { 2726 u32 eee_su; 2727 eee_su = E1000_READ_REG(hw, E1000_EEE_SU); 2728 eee_su &= ~E1000_EEE_SU_LPI_CLK_STP; 2729 E1000_WRITE_REG(hw, E1000_EEE_SU, eee_su); 2730 } 2731 2732 } else { 2733 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); 2734 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 2735 E1000_EEER_LPI_FC); 2736 } 2737 E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg); 2738 E1000_WRITE_REG(hw, E1000_EEER, eeer); 2739 E1000_READ_REG(hw, E1000_IPCNFG); 2740 E1000_READ_REG(hw, E1000_EEER); 2741 out: 2742 2743 return ret_val; 2744 } 2745 2746 /* Due to a hw errata, if the host tries to configure the VFTA register 2747 * while performing queries from the BMC or DMA, then the VFTA in some 2748 * cases won't be written. 2749 */ 2750 2751 /** 2752 * e1000_clear_vfta_i350 - Clear VLAN filter table 2753 * @hw: pointer to the HW structure 2754 * 2755 * Clears the register array which contains the VLAN filter table by 2756 * setting all the values to 0. 2757 **/ 2758 void e1000_clear_vfta_i350(struct e1000_hw *hw) 2759 { 2760 u32 offset; 2761 int i; 2762 2763 DEBUGFUNC("e1000_clear_vfta_350"); 2764 2765 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 2766 for (i = 0; i < 10; i++) 2767 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 2768 2769 E1000_WRITE_FLUSH(hw); 2770 } 2771 } 2772 2773 /** 2774 * e1000_write_vfta_i350 - Write value to VLAN filter table 2775 * @hw: pointer to the HW structure 2776 * @offset: register offset in VLAN filter table 2777 * @value: register value written to VLAN filter table 2778 * 2779 * Writes value at the given offset in the register array which stores 2780 * the VLAN filter table. 2781 **/ 2782 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value) 2783 { 2784 int i; 2785 2786 DEBUGFUNC("e1000_write_vfta_350"); 2787 2788 for (i = 0; i < 10; i++) 2789 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 2790 2791 E1000_WRITE_FLUSH(hw); 2792 } 2793 2794 2795 /** 2796 * e1000_set_i2c_bb - Enable I2C bit-bang 2797 * @hw: pointer to the HW structure 2798 * 2799 * Enable I2C bit-bang interface 2800 * 2801 **/ 2802 s32 e1000_set_i2c_bb(struct e1000_hw *hw) 2803 { 2804 s32 ret_val = E1000_SUCCESS; 2805 u32 ctrl_ext, i2cparams; 2806 2807 DEBUGFUNC("e1000_set_i2c_bb"); 2808 2809 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 2810 ctrl_ext |= E1000_CTRL_I2C_ENA; 2811 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 2812 E1000_WRITE_FLUSH(hw); 2813 2814 i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS); 2815 i2cparams |= E1000_I2CBB_EN; 2816 i2cparams |= E1000_I2C_DATA_OE_N; 2817 i2cparams |= E1000_I2C_CLK_OE_N; 2818 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams); 2819 E1000_WRITE_FLUSH(hw); 2820 2821 return ret_val; 2822 } 2823 2824 /** 2825 * e1000_read_i2c_byte_generic - Reads 8 bit word over I2C 2826 * @hw: pointer to hardware structure 2827 * @byte_offset: byte offset to read 2828 * @dev_addr: device address 2829 * @data: value read 2830 * 2831 * Performs byte read operation over I2C interface at 2832 * a specified device address. 2833 **/ 2834 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset, 2835 u8 dev_addr, u8 *data) 2836 { 2837 s32 status = E1000_SUCCESS; 2838 u32 max_retry = 10; 2839 u32 retry = 1; 2840 u16 swfw_mask = 0; 2841 2842 bool nack = TRUE; 2843 2844 DEBUGFUNC("e1000_read_i2c_byte_generic"); 2845 2846 swfw_mask = E1000_SWFW_PHY0_SM; 2847 2848 do { 2849 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) 2850 != E1000_SUCCESS) { 2851 status = E1000_ERR_SWFW_SYNC; 2852 goto read_byte_out; 2853 } 2854 2855 e1000_i2c_start(hw); 2856 2857 /* Device Address and write indication */ 2858 status = e1000_clock_out_i2c_byte(hw, dev_addr); 2859 if (status != E1000_SUCCESS) 2860 goto fail; 2861 2862 status = e1000_get_i2c_ack(hw); 2863 if (status != E1000_SUCCESS) 2864 goto fail; 2865 2866 status = e1000_clock_out_i2c_byte(hw, byte_offset); 2867 if (status != E1000_SUCCESS) 2868 goto fail; 2869 2870 status = e1000_get_i2c_ack(hw); 2871 if (status != E1000_SUCCESS) 2872 goto fail; 2873 2874 e1000_i2c_start(hw); 2875 2876 /* Device Address and read indication */ 2877 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 2878 if (status != E1000_SUCCESS) 2879 goto fail; 2880 2881 status = e1000_get_i2c_ack(hw); 2882 if (status != E1000_SUCCESS) 2883 goto fail; 2884 2885 status = e1000_clock_in_i2c_byte(hw, data); 2886 if (status != E1000_SUCCESS) 2887 goto fail; 2888 2889 status = e1000_clock_out_i2c_bit(hw, nack); 2890 if (status != E1000_SUCCESS) 2891 goto fail; 2892 2893 e1000_i2c_stop(hw); 2894 break; 2895 2896 fail: 2897 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2898 msec_delay(100); 2899 e1000_i2c_bus_clear(hw); 2900 retry++; 2901 if (retry < max_retry) 2902 DEBUGOUT("I2C byte read error - Retrying.\n"); 2903 else 2904 DEBUGOUT("I2C byte read error.\n"); 2905 2906 } while (retry < max_retry); 2907 2908 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2909 2910 read_byte_out: 2911 2912 return status; 2913 } 2914 2915 /** 2916 * e1000_write_i2c_byte_generic - Writes 8 bit word over I2C 2917 * @hw: pointer to hardware structure 2918 * @byte_offset: byte offset to write 2919 * @dev_addr: device address 2920 * @data: value to write 2921 * 2922 * Performs byte write operation over I2C interface at 2923 * a specified device address. 2924 **/ 2925 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset, 2926 u8 dev_addr, u8 data) 2927 { 2928 s32 status = E1000_SUCCESS; 2929 u32 max_retry = 1; 2930 u32 retry = 0; 2931 u16 swfw_mask = 0; 2932 2933 DEBUGFUNC("e1000_write_i2c_byte_generic"); 2934 2935 swfw_mask = E1000_SWFW_PHY0_SM; 2936 2937 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) { 2938 status = E1000_ERR_SWFW_SYNC; 2939 goto write_byte_out; 2940 } 2941 2942 do { 2943 e1000_i2c_start(hw); 2944 2945 status = e1000_clock_out_i2c_byte(hw, dev_addr); 2946 if (status != E1000_SUCCESS) 2947 goto fail; 2948 2949 status = e1000_get_i2c_ack(hw); 2950 if (status != E1000_SUCCESS) 2951 goto fail; 2952 2953 status = e1000_clock_out_i2c_byte(hw, byte_offset); 2954 if (status != E1000_SUCCESS) 2955 goto fail; 2956 2957 status = e1000_get_i2c_ack(hw); 2958 if (status != E1000_SUCCESS) 2959 goto fail; 2960 2961 status = e1000_clock_out_i2c_byte(hw, data); 2962 if (status != E1000_SUCCESS) 2963 goto fail; 2964 2965 status = e1000_get_i2c_ack(hw); 2966 if (status != E1000_SUCCESS) 2967 goto fail; 2968 2969 e1000_i2c_stop(hw); 2970 break; 2971 2972 fail: 2973 e1000_i2c_bus_clear(hw); 2974 retry++; 2975 if (retry < max_retry) 2976 DEBUGOUT("I2C byte write error - Retrying.\n"); 2977 else 2978 DEBUGOUT("I2C byte write error.\n"); 2979 } while (retry < max_retry); 2980 2981 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2982 2983 write_byte_out: 2984 2985 return status; 2986 } 2987 2988 /** 2989 * e1000_i2c_start - Sets I2C start condition 2990 * @hw: pointer to hardware structure 2991 * 2992 * Sets I2C start condition (High -> Low on SDA while SCL is High) 2993 **/ 2994 static void e1000_i2c_start(struct e1000_hw *hw) 2995 { 2996 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 2997 2998 DEBUGFUNC("e1000_i2c_start"); 2999 3000 /* Start condition must begin with data and clock high */ 3001 e1000_set_i2c_data(hw, &i2cctl, 1); 3002 e1000_raise_i2c_clk(hw, &i2cctl); 3003 3004 /* Setup time for start condition (4.7us) */ 3005 usec_delay(E1000_I2C_T_SU_STA); 3006 3007 e1000_set_i2c_data(hw, &i2cctl, 0); 3008 3009 /* Hold time for start condition (4us) */ 3010 usec_delay(E1000_I2C_T_HD_STA); 3011 3012 e1000_lower_i2c_clk(hw, &i2cctl); 3013 3014 /* Minimum low period of clock is 4.7 us */ 3015 usec_delay(E1000_I2C_T_LOW); 3016 3017 } 3018 3019 /** 3020 * e1000_i2c_stop - Sets I2C stop condition 3021 * @hw: pointer to hardware structure 3022 * 3023 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 3024 **/ 3025 static void e1000_i2c_stop(struct e1000_hw *hw) 3026 { 3027 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3028 3029 DEBUGFUNC("e1000_i2c_stop"); 3030 3031 /* Stop condition must begin with data low and clock high */ 3032 e1000_set_i2c_data(hw, &i2cctl, 0); 3033 e1000_raise_i2c_clk(hw, &i2cctl); 3034 3035 /* Setup time for stop condition (4us) */ 3036 usec_delay(E1000_I2C_T_SU_STO); 3037 3038 e1000_set_i2c_data(hw, &i2cctl, 1); 3039 3040 /* bus free time between stop and start (4.7us)*/ 3041 usec_delay(E1000_I2C_T_BUF); 3042 } 3043 3044 /** 3045 * e1000_clock_in_i2c_byte - Clocks in one byte via I2C 3046 * @hw: pointer to hardware structure 3047 * @data: data byte to clock in 3048 * 3049 * Clocks in one byte data via I2C data/clock 3050 **/ 3051 static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data) 3052 { 3053 s32 i; 3054 bool bit = 0; 3055 3056 DEBUGFUNC("e1000_clock_in_i2c_byte"); 3057 3058 *data = 0; 3059 for (i = 7; i >= 0; i--) { 3060 e1000_clock_in_i2c_bit(hw, &bit); 3061 *data |= bit << i; 3062 } 3063 3064 return E1000_SUCCESS; 3065 } 3066 3067 /** 3068 * e1000_clock_out_i2c_byte - Clocks out one byte via I2C 3069 * @hw: pointer to hardware structure 3070 * @data: data byte clocked out 3071 * 3072 * Clocks out one byte data via I2C data/clock 3073 **/ 3074 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data) 3075 { 3076 s32 status = E1000_SUCCESS; 3077 s32 i; 3078 u32 i2cctl; 3079 bool bit = 0; 3080 3081 DEBUGFUNC("e1000_clock_out_i2c_byte"); 3082 3083 for (i = 7; i >= 0; i--) { 3084 bit = (data >> i) & 0x1; 3085 status = e1000_clock_out_i2c_bit(hw, bit); 3086 3087 if (status != E1000_SUCCESS) 3088 break; 3089 } 3090 3091 /* Release SDA line (set high) */ 3092 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3093 3094 i2cctl |= E1000_I2C_DATA_OE_N; 3095 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl); 3096 E1000_WRITE_FLUSH(hw); 3097 3098 return status; 3099 } 3100 3101 /** 3102 * e1000_get_i2c_ack - Polls for I2C ACK 3103 * @hw: pointer to hardware structure 3104 * 3105 * Clocks in/out one bit via I2C data/clock 3106 **/ 3107 static s32 e1000_get_i2c_ack(struct e1000_hw *hw) 3108 { 3109 s32 status = E1000_SUCCESS; 3110 u32 i = 0; 3111 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3112 u32 timeout = 10; 3113 bool ack = TRUE; 3114 3115 DEBUGFUNC("e1000_get_i2c_ack"); 3116 3117 e1000_raise_i2c_clk(hw, &i2cctl); 3118 3119 /* Minimum high period of clock is 4us */ 3120 usec_delay(E1000_I2C_T_HIGH); 3121 3122 /* Wait until SCL returns high */ 3123 for (i = 0; i < timeout; i++) { 3124 usec_delay(1); 3125 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3126 if (i2cctl & E1000_I2C_CLK_IN) 3127 break; 3128 } 3129 if (!(i2cctl & E1000_I2C_CLK_IN)) 3130 return E1000_ERR_I2C; 3131 3132 ack = e1000_get_i2c_data(&i2cctl); 3133 if (ack) { 3134 DEBUGOUT("I2C ack was not received.\n"); 3135 status = E1000_ERR_I2C; 3136 } 3137 3138 e1000_lower_i2c_clk(hw, &i2cctl); 3139 3140 /* Minimum low period of clock is 4.7 us */ 3141 usec_delay(E1000_I2C_T_LOW); 3142 3143 return status; 3144 } 3145 3146 /** 3147 * e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 3148 * @hw: pointer to hardware structure 3149 * @data: read data value 3150 * 3151 * Clocks in one bit via I2C data/clock 3152 **/ 3153 static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data) 3154 { 3155 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3156 3157 DEBUGFUNC("e1000_clock_in_i2c_bit"); 3158 3159 e1000_raise_i2c_clk(hw, &i2cctl); 3160 3161 /* Minimum high period of clock is 4us */ 3162 usec_delay(E1000_I2C_T_HIGH); 3163 3164 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3165 *data = e1000_get_i2c_data(&i2cctl); 3166 3167 e1000_lower_i2c_clk(hw, &i2cctl); 3168 3169 /* Minimum low period of clock is 4.7 us */ 3170 usec_delay(E1000_I2C_T_LOW); 3171 3172 return E1000_SUCCESS; 3173 } 3174 3175 /** 3176 * e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 3177 * @hw: pointer to hardware structure 3178 * @data: data value to write 3179 * 3180 * Clocks out one bit via I2C data/clock 3181 **/ 3182 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data) 3183 { 3184 s32 status; 3185 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3186 3187 DEBUGFUNC("e1000_clock_out_i2c_bit"); 3188 3189 status = e1000_set_i2c_data(hw, &i2cctl, data); 3190 if (status == E1000_SUCCESS) { 3191 e1000_raise_i2c_clk(hw, &i2cctl); 3192 3193 /* Minimum high period of clock is 4us */ 3194 usec_delay(E1000_I2C_T_HIGH); 3195 3196 e1000_lower_i2c_clk(hw, &i2cctl); 3197 3198 /* Minimum low period of clock is 4.7 us. 3199 * This also takes care of the data hold time. 3200 */ 3201 usec_delay(E1000_I2C_T_LOW); 3202 } else { 3203 status = E1000_ERR_I2C; 3204 DEBUGOUT1("I2C data was not set to %X\n", data); 3205 } 3206 3207 return status; 3208 } 3209 /** 3210 * e1000_raise_i2c_clk - Raises the I2C SCL clock 3211 * @hw: pointer to hardware structure 3212 * @i2cctl: Current value of I2CCTL register 3213 * 3214 * Raises the I2C clock line '0'->'1' 3215 **/ 3216 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl) 3217 { 3218 DEBUGFUNC("e1000_raise_i2c_clk"); 3219 3220 *i2cctl |= E1000_I2C_CLK_OUT; 3221 *i2cctl &= ~E1000_I2C_CLK_OE_N; 3222 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl); 3223 E1000_WRITE_FLUSH(hw); 3224 3225 /* SCL rise time (1000ns) */ 3226 usec_delay(E1000_I2C_T_RISE); 3227 } 3228 3229 /** 3230 * e1000_lower_i2c_clk - Lowers the I2C SCL clock 3231 * @hw: pointer to hardware structure 3232 * @i2cctl: Current value of I2CCTL register 3233 * 3234 * Lowers the I2C clock line '1'->'0' 3235 **/ 3236 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl) 3237 { 3238 3239 DEBUGFUNC("e1000_lower_i2c_clk"); 3240 3241 *i2cctl &= ~E1000_I2C_CLK_OUT; 3242 *i2cctl &= ~E1000_I2C_CLK_OE_N; 3243 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl); 3244 E1000_WRITE_FLUSH(hw); 3245 3246 /* SCL fall time (300ns) */ 3247 usec_delay(E1000_I2C_T_FALL); 3248 } 3249 3250 /** 3251 * e1000_set_i2c_data - Sets the I2C data bit 3252 * @hw: pointer to hardware structure 3253 * @i2cctl: Current value of I2CCTL register 3254 * @data: I2C data value (0 or 1) to set 3255 * 3256 * Sets the I2C data bit 3257 **/ 3258 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data) 3259 { 3260 s32 status = E1000_SUCCESS; 3261 3262 DEBUGFUNC("e1000_set_i2c_data"); 3263 3264 if (data) 3265 *i2cctl |= E1000_I2C_DATA_OUT; 3266 else 3267 *i2cctl &= ~E1000_I2C_DATA_OUT; 3268 3269 *i2cctl &= ~E1000_I2C_DATA_OE_N; 3270 *i2cctl |= E1000_I2C_CLK_OE_N; 3271 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl); 3272 E1000_WRITE_FLUSH(hw); 3273 3274 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 3275 usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA); 3276 3277 *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3278 if (data != e1000_get_i2c_data(i2cctl)) { 3279 status = E1000_ERR_I2C; 3280 DEBUGOUT1("Error - I2C data was not set to %X.\n", data); 3281 } 3282 3283 return status; 3284 } 3285 3286 /** 3287 * e1000_get_i2c_data - Reads the I2C SDA data bit 3288 * @hw: pointer to hardware structure 3289 * @i2cctl: Current value of I2CCTL register 3290 * 3291 * Returns the I2C data bit value 3292 **/ 3293 static bool e1000_get_i2c_data(u32 *i2cctl) 3294 { 3295 bool data; 3296 3297 DEBUGFUNC("e1000_get_i2c_data"); 3298 3299 if (*i2cctl & E1000_I2C_DATA_IN) 3300 data = 1; 3301 else 3302 data = 0; 3303 3304 return data; 3305 } 3306 3307 /** 3308 * e1000_i2c_bus_clear - Clears the I2C bus 3309 * @hw: pointer to hardware structure 3310 * 3311 * Clears the I2C bus by sending nine clock pulses. 3312 * Used when data line is stuck low. 3313 **/ 3314 void e1000_i2c_bus_clear(struct e1000_hw *hw) 3315 { 3316 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3317 u32 i; 3318 3319 DEBUGFUNC("e1000_i2c_bus_clear"); 3320 3321 e1000_i2c_start(hw); 3322 3323 e1000_set_i2c_data(hw, &i2cctl, 1); 3324 3325 for (i = 0; i < 9; i++) { 3326 e1000_raise_i2c_clk(hw, &i2cctl); 3327 3328 /* Min high period of clock is 4us */ 3329 usec_delay(E1000_I2C_T_HIGH); 3330 3331 e1000_lower_i2c_clk(hw, &i2cctl); 3332 3333 /* Min low period of clock is 4.7us*/ 3334 usec_delay(E1000_I2C_T_LOW); 3335 } 3336 3337 e1000_i2c_start(hw); 3338 3339 /* Put the i2c bus back to default state */ 3340 e1000_i2c_stop(hw); 3341 } 3342 3343