1 /****************************************************************************** 2 3 Copyright (c) 2001-2014, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD:$*/ 34 35 #ifndef _E1000_DEFINES_H_ 36 #define _E1000_DEFINES_H_ 37 38 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 39 #define REQ_TX_DESCRIPTOR_MULTIPLE 8 40 #define REQ_RX_DESCRIPTOR_MULTIPLE 8 41 42 /* Definitions for power management and wakeup registers */ 43 /* Wake Up Control */ 44 #define E1000_WUC_APME 0x00000001 /* APM Enable */ 45 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ 46 #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ 47 #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ 48 #define E1000_WUC_LSCWE 0x00000010 /* Link Status wake up enable */ 49 #define E1000_WUC_PPROXYE 0x00000010 /* Protocol Proxy Enable */ 50 #define E1000_WUC_LSCWO 0x00000020 /* Link Status wake up override */ 51 #define E1000_WUC_SPM 0x80000000 /* Enable SPM */ 52 #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */ 53 #define E1000_WUC_FLX6_PHY 0x4000 /* Flexible Filter 6 Enable */ 54 #define E1000_WUC_FLX7_PHY 0x8000 /* Flexible Filter 7 Enable */ 55 56 /* Wake Up Filter Control */ 57 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 58 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 59 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 60 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 61 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 62 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 63 #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ 64 #define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ 65 #define E1000_WUFC_IGNORE_TCO_PHY 0x00000800 /* Ignore WakeOn TCO packets */ 66 #define E1000_WUFC_FLX0_PHY 0x00001000 /* Flexible Filter 0 Enable */ 67 #define E1000_WUFC_FLX1_PHY 0x00002000 /* Flexible Filter 1 Enable */ 68 #define E1000_WUFC_FLX2_PHY 0x00004000 /* Flexible Filter 2 Enable */ 69 #define E1000_WUFC_FLX3_PHY 0x00008000 /* Flexible Filter 3 Enable */ 70 #define E1000_WUFC_FLX4_PHY 0x00000200 /* Flexible Filter 4 Enable */ 71 #define E1000_WUFC_FLX5_PHY 0x00000400 /* Flexible Filter 5 Enable */ 72 #define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */ 73 #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ 74 #define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ 75 #define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ 76 #define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ 77 #define E1000_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */ 78 #define E1000_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */ 79 #define E1000_WUFC_FLX6 0x00400000 /* Flexible Filter 6 Enable */ 80 #define E1000_WUFC_FLX7 0x00800000 /* Flexible Filter 7 Enable */ 81 #define E1000_WUFC_ALL_FILTERS_PHY_4 0x0000F0FF /* wakeup filters mask */ 82 #define E1000_WUFC_FLX_OFFSET_PHY 12 /* Flexible Filters bits offset */ 83 #define E1000_WUFC_FLX_FILTERS_PHY_4 0x0000F000 /* 4 flexible filters mask */ 84 #define E1000_WUFC_ALL_FILTERS_PHY_6 0x0000F6FF /* 6 wakeup filters mask */ 85 #define E1000_WUFC_FLX_FILTERS_PHY_6 0x0000F600 /* 6 flexible filters mask */ 86 #define E1000_WUFC_FW_RST 0x80000000 /* Wake on FW Reset Enable */ 87 #define E1000_WUFC_ALL_FILTERS 0x000F00FF /* all wakeup filters mask */ 88 #define E1000_WUFC_ALL_FILTERS_6 0x003F00FF /* Mask all 6 wu filters */ 89 #define E1000_WUFC_ALL_FILTERS_8 0x00FF00FF /* Mask all 8 wu filters */ 90 #define E1000_WUFC_FLX_OFFSET 16 /* Flexible Filters bits offset */ 91 #define E1000_WUFC_FLX_FILTERS 0x000F0000 /* 4 flexible filters mask */ 92 #define E1000_WUFC_FLX_FILTERS_6 0x003F0000 /* 6 flexible filters mask */ 93 #define E1000_WUFC_FLX_FILTERS_8 0x00FF0000 /* 8 flexible filters mask */ 94 /* 95 * For 82576 to utilize Extended filter masks in addition to 96 * existing (filter) masks 97 */ 98 #define E1000_WUFC_EXT_FLX_FILTERS 0x00300000 /* Ext. FLX filter mask */ 99 100 /* Wake Up Status */ 101 #define E1000_WUS_LNKC E1000_WUFC_LNKC 102 #define E1000_WUS_MAG E1000_WUFC_MAG 103 #define E1000_WUS_EX E1000_WUFC_EX 104 #define E1000_WUS_MC E1000_WUFC_MC 105 #define E1000_WUS_BC E1000_WUFC_BC 106 #define E1000_WUS_ARP E1000_WUFC_ARP 107 #define E1000_WUS_IPV4 E1000_WUFC_IPV4 108 #define E1000_WUS_IPV6 E1000_WUFC_IPV6 109 #define E1000_WUS_FLX0_PHY E1000_WUFC_FLX0_PHY 110 #define E1000_WUS_FLX1_PHY E1000_WUFC_FLX1_PHY 111 #define E1000_WUS_FLX2_PHY E1000_WUFC_FLX2_PHY 112 #define E1000_WUS_FLX3_PHY E1000_WUFC_FLX3_PHY 113 #define E1000_WUS_FLX_FILTERS_PHY_4 E1000_WUFC_FLX_FILTERS_PHY_4 114 #define E1000_WUS_FLX0 E1000_WUFC_FLX0 115 #define E1000_WUS_FLX1 E1000_WUFC_FLX1 116 #define E1000_WUS_FLX2 E1000_WUFC_FLX2 117 #define E1000_WUS_FLX3 E1000_WUFC_FLX3 118 #define E1000_WUS_FLX4 E1000_WUFC_FLX4 119 #define E1000_WUS_FLX5 E1000_WUFC_FLX5 120 #define E1000_WUS_FLX6 E1000_WUFC_FLX6 121 #define E1000_WUS_FLX7 E1000_WUFC_FLX7 122 #define E1000_WUS_FLX4_PHY E1000_WUFC_FLX4_PHY 123 #define E1000_WUS_FLX5_PHY E1000_WUFC_FLX5_PHY 124 #define E1000_WUS_FLX6_PHY 0x0400 125 #define E1000_WUS_FLX7_PHY 0x0800 126 #define E1000_WUS_FLX_FILTERS E1000_WUFC_FLX_FILTERS 127 #define E1000_WUS_FLX_FILTERS_6 E1000_WUFC_FLX_FILTERS_6 128 #define E1000_WUS_FLX_FILTERS_8 E1000_WUFC_FLX_FILTERS_8 129 #define E1000_WUS_FLX_FILTERS_PHY_6 E1000_WUFC_FLX_FILTERS_PHY_6 130 131 /* Wake Up Packet Length */ 132 #define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */ 133 134 /* Four Flexible Filters are supported */ 135 #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4 136 /* Six Flexible Filters are supported */ 137 #define E1000_FLEXIBLE_FILTER_COUNT_MAX_6 6 138 /* Eight Flexible Filters are supported */ 139 #define E1000_FLEXIBLE_FILTER_COUNT_MAX_8 8 140 /* Two Extended Flexible Filters are supported (82576) */ 141 #define E1000_EXT_FLEXIBLE_FILTER_COUNT_MAX 2 142 #define E1000_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */ 143 #define E1000_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */ 144 145 /* Each Flexible Filter is at most 128 (0x80) bytes in length */ 146 #define E1000_FLEXIBLE_FILTER_SIZE_MAX 128 147 148 #define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX 149 #define E1000_FFLT_SIZE_6 E1000_FLEXIBLE_FILTER_COUNT_MAX_6 150 #define E1000_FFLT_SIZE_8 E1000_FLEXIBLE_FILTER_COUNT_MAX_8 151 #define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX 152 #define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX 153 154 /* Extended Device Control */ 155 #define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */ 156 #define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */ 157 #define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN 158 #define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */ 159 #define E1000_CTRL_EXT_LPCD 0x00000004 /* LCD Power Cycle Done */ 160 #define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */ 161 /* Reserved (bits 4,5) in >= 82575 */ 162 #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* SW Definable Pin 4 data */ 163 #define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* SW Definable Pin 5 data */ 164 #define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA 165 #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* SW Definable Pin 6 data */ 166 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* SW Definable Pin 3 data */ 167 /* SDP 4/5 (bits 8,9) are reserved in >= 82575 */ 168 #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ 169 #define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */ 170 #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ 171 #define E1000_CTRL_EXT_SDP3_DIR 0x00000800 /* Direction of SDP3 0=in 1=out */ 172 #define E1000_CTRL_EXT_FORCE_SMBUS 0x00000800 /* Force SMBus mode */ 173 #define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */ 174 #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ 175 #define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */ 176 /* Physical Func Reset Done Indication */ 177 #define E1000_CTRL_EXT_PFRSTD 0x00004000 178 #define E1000_CTRL_EXT_SDLPE 0X00040000 /* SerDes Low Power Enable */ 179 #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ 180 #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 181 #define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clk Gating */ 182 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 183 /* Offset of the link mode field in Ctrl Ext register */ 184 #define E1000_CTRL_EXT_LINK_MODE_OFFSET 22 185 #define E1000_CTRL_EXT_LINK_MODE_82580_MASK 0x01C00000 /*82580 bit 24:22*/ 186 #define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000 187 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 188 #define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 189 #define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000 190 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 191 #define E1000_CTRL_EXT_LINK_MODE_PCIX_SERDES 0x00800000 192 #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 193 #define E1000_CTRL_EXT_EIAME 0x01000000 194 #define E1000_CTRL_EXT_IRCA 0x00000001 195 #define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000 196 #define E1000_CTRL_EXT_WR_WMARK_256 0x00000000 197 #define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 198 #define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 199 #define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 200 #define E1000_CTRL_EXT_CANC 0x04000000 /* Int delay cancellation */ 201 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Drv loaded bit for FW */ 202 /* IAME enable bit (27) was removed in >= 82575 */ 203 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */ 204 /* packet buffer parity error detection enabled */ 205 #define E1000_CRTL_EXT_PB_PAREN 0x01000000 206 /* descriptor FIFO parity error detection enable */ 207 #define E1000_CTRL_EXT_DF_PAREN 0x02000000 208 #define E1000_CTRL_EXT_GHOST_PAREN 0x40000000 209 #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ 210 #define E1000_CTRL_EXT_LSECCK 0x00001000 211 #define E1000_CTRL_EXT_PHYPDEN 0x00100000 212 #define E1000_I2CCMD_REG_ADDR_SHIFT 16 213 #define E1000_I2CCMD_REG_ADDR 0x00FF0000 214 #define E1000_I2CCMD_PHY_ADDR_SHIFT 24 215 #define E1000_I2CCMD_PHY_ADDR 0x07000000 216 #define E1000_I2CCMD_OPCODE_READ 0x08000000 217 #define E1000_I2CCMD_OPCODE_WRITE 0x00000000 218 #define E1000_I2CCMD_RESET 0x10000000 219 #define E1000_I2CCMD_READY 0x20000000 220 #define E1000_I2CCMD_INTERRUPT_ENA 0x40000000 221 #define E1000_I2CCMD_ERROR 0x80000000 222 #define E1000_I2CCMD_SFP_DATA_ADDR(a) (0x0000 + (a)) 223 #define E1000_I2CCMD_SFP_DIAG_ADDR(a) (0x0100 + (a)) 224 #define E1000_MAX_SGMII_PHY_REG_ADDR 255 225 #define E1000_I2CCMD_PHY_TIMEOUT 200 226 #define E1000_IVAR_VALID 0x80 227 #define E1000_GPIE_NSICR 0x00000001 228 #define E1000_GPIE_MSIX_MODE 0x00000010 229 #define E1000_GPIE_EIAME 0x40000000 230 #define E1000_GPIE_PBA 0x80000000 231 232 /* Receive Descriptor bit definitions */ 233 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 234 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 235 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 236 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 237 #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 238 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 239 #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 240 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 241 #define E1000_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */ 242 #define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */ 243 #define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 244 #define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ 245 #define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ 246 #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ 247 #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ 248 #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ 249 #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ 250 #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ 251 #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ 252 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ 253 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 254 #define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 255 #define E1000_RXD_SPC_PRI_SHIFT 13 256 #define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ 257 #define E1000_RXD_SPC_CFI_SHIFT 12 258 259 #define E1000_RXDEXT_STATERR_TST 0x00000100 /* Time Stamp taken */ 260 #define E1000_RXDEXT_STATERR_LB 0x00040000 261 #define E1000_RXDEXT_STATERR_CE 0x01000000 262 #define E1000_RXDEXT_STATERR_SE 0x02000000 263 #define E1000_RXDEXT_STATERR_SEQ 0x04000000 264 #define E1000_RXDEXT_STATERR_CXE 0x10000000 265 #define E1000_RXDEXT_STATERR_TCPE 0x20000000 266 #define E1000_RXDEXT_STATERR_IPE 0x40000000 267 #define E1000_RXDEXT_STATERR_RXE 0x80000000 268 269 #define E1000_RXDEXT_LSECH 0x01000000 270 #define E1000_RXDEXT_LSECE_MASK 0x60000000 271 #define E1000_RXDEXT_LSECE_NO_ERROR 0x00000000 272 #define E1000_RXDEXT_LSECE_NO_SA_MATCH 0x20000000 273 #define E1000_RXDEXT_LSECE_REPLAY_DETECT 0x40000000 274 #define E1000_RXDEXT_LSECE_BAD_SIG 0x60000000 275 276 /* mask to determine if packets should be dropped due to frame errors */ 277 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \ 278 E1000_RXD_ERR_CE | \ 279 E1000_RXD_ERR_SE | \ 280 E1000_RXD_ERR_SEQ | \ 281 E1000_RXD_ERR_CXE | \ 282 E1000_RXD_ERR_RXE) 283 284 /* Same mask, but for extended and packet split descriptors */ 285 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ 286 E1000_RXDEXT_STATERR_CE | \ 287 E1000_RXDEXT_STATERR_SE | \ 288 E1000_RXDEXT_STATERR_SEQ | \ 289 E1000_RXDEXT_STATERR_CXE | \ 290 E1000_RXDEXT_STATERR_RXE) 291 292 /* Packet Types as indicated in the Adv/Ext receive descriptor. */ 293 #define E1000_RXD_PKTTYPE_MASK 0x000F0000 294 #define E1000_RXD_PKTTYPE_PTP 0x000E0000 295 296 #define E1000_MRQC_ENABLE_MASK 0x00000007 297 #define E1000_MRQC_ENABLE_RSS_2Q 0x00000001 298 #define E1000_MRQC_ENABLE_RSS_INT 0x00000004 299 #define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 300 #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 301 #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 302 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 303 #define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000 304 #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 305 #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 306 307 #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 308 #define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF 309 310 /* Management Control */ 311 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 312 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 313 #define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */ 314 #define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */ 315 #define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */ 316 #define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */ 317 #define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */ 318 #define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */ 319 #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ 320 /* Enable Neighbor Discovery Filtering */ 321 #define E1000_MANC_NEIGHBOR_EN 0x00004000 322 #define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */ 323 #define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ 324 #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 325 #define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ 326 #define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */ 327 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 328 /* Enable MAC address filtering */ 329 #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 330 /* Enable MNG packets to host memory */ 331 #define E1000_MANC_EN_MNG2HOST 0x00200000 332 /* Enable IP address filtering */ 333 #define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 334 #define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Ena checksum filtering */ 335 #define E1000_MANC_BR_EN 0x01000000 /* Ena broadcast filtering */ 336 #define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ 337 #define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ 338 #define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ 339 #define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */ 340 #define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */ 341 #define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */ 342 #define E1000_MANC_MPROXYE 0x40000000 /* Mngment Proxy Enable */ 343 #define E1000_MANC_EN_BMC2OS 0x10000000 /* OS2BMC is enabld or not */ 344 345 #define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ 346 #define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ 347 348 #define E1000_MANC2H_PORT_623 0x00000020 /* Port 0x26f */ 349 #define E1000_MANC2H_PORT_664 0x00000040 /* Port 0x298 */ 350 #define E1000_MDEF_PORT_623 0x00000800 /* Port 0x26f */ 351 #define E1000_MDEF_PORT_664 0x00000400 /* Port 0x298 */ 352 353 /* Receive Control */ 354 #define E1000_RCTL_RST 0x00000001 /* Software reset */ 355 #define E1000_RCTL_EN 0x00000002 /* enable */ 356 #define E1000_RCTL_SBP 0x00000004 /* store bad packet */ 357 #define E1000_RCTL_UPE 0x00000008 /* unicast promisc enable */ 358 #define E1000_RCTL_MPE 0x00000010 /* multicast promisc enable */ 359 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 360 #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ 361 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 362 #define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ 363 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 364 #define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */ 365 #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ 366 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */ 367 #define E1000_RCTL_RDMTS_QUAT 0x00000100 /* Rx desc min thresh size */ 368 #define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* Rx desc min thresh size */ 369 #define E1000_RCTL_RDMTS_HEX 0x00010000 370 #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 371 #define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */ 372 #define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */ 373 #define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */ 374 #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ 375 #define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */ 376 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 377 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ 378 #define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */ 379 #define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */ 380 #define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */ 381 #define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */ 382 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ 383 #define E1000_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */ 384 #define E1000_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */ 385 #define E1000_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */ 386 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ 387 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ 388 #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ 389 #define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ 390 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 391 #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ 392 #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 393 #define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */ 394 #define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */ 395 396 /* Use byte values for the following shift parameters 397 * Usage: 398 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & 399 * E1000_PSRCTL_BSIZE0_MASK) | 400 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & 401 * E1000_PSRCTL_BSIZE1_MASK) | 402 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & 403 * E1000_PSRCTL_BSIZE2_MASK) | 404 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; 405 * E1000_PSRCTL_BSIZE3_MASK)) 406 * where value0 = [128..16256], default=256 407 * value1 = [1024..64512], default=4096 408 * value2 = [0..64512], default=4096 409 * value3 = [0..64512], default=0 410 */ 411 412 #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F 413 #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 414 #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 415 #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 416 417 #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ 418 #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ 419 #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ 420 #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ 421 422 /* SWFW_SYNC Definitions */ 423 #define E1000_SWFW_EEP_SM 0x01 424 #define E1000_SWFW_PHY0_SM 0x02 425 #define E1000_SWFW_PHY1_SM 0x04 426 #define E1000_SWFW_CSR_SM 0x08 427 #define E1000_SWFW_PHY2_SM 0x20 428 #define E1000_SWFW_PHY3_SM 0x40 429 #define E1000_SWFW_SW_MNG_SM 0x400 430 431 /* FACTPS Definitions */ 432 #define E1000_FACTPS_LFS 0x40000000 /* LAN Function Select */ 433 /* Device Control */ 434 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 435 #define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ 436 #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ 437 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */ 438 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 439 #define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ 440 #define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ 441 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 442 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 443 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 444 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 445 #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ 446 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 447 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 448 #define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ 449 #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 450 #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 451 #define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */ 452 /* Defined polarity of Dock/Undock indication in SDP[0] */ 453 #define E1000_CTRL_D_UD_POLARITY 0x00004000 454 /* Reset both PHY ports, through PHYRST_N pin */ 455 #define E1000_CTRL_FORCE_PHY_RESET 0x00008000 456 /* enable link status from external LINK_0 and LINK_1 pins */ 457 #define E1000_CTRL_EXT_LINK_EN 0x00010000 458 #define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */ 459 #define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */ 460 #define E1000_CTRL_MEHE 0x00080000 /* Memory Error Handling Enable */ 461 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 462 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 463 #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ 464 #define E1000_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */ 465 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 /* PHY PM enable */ 466 #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ 467 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ 468 #define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */ 469 #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ 470 #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ 471 #define E1000_CTRL_RST 0x04000000 /* Global reset */ 472 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 473 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 474 #define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ 475 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 476 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 477 #define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to ME */ 478 #define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */ 479 480 /* 481 * Bit definitions for the Management Data IO (MDIO) and Management Data 482 * Clock (MDC) pins in the Device Control Register. 483 */ 484 #define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0 485 #define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0 486 #define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 487 #define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2 488 #define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 489 #define E1000_CTRL_MDC E1000_CTRL_SWDPIN3 490 #define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR 491 #define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA 492 493 #define E1000_CONNSW_ENRGSRC 0x4 494 #define E1000_CONNSW_PHYSD 0x400 495 #define E1000_CONNSW_PHY_PDN 0x800 496 #define E1000_CONNSW_SERDESD 0x200 497 #define E1000_CONNSW_AUTOSENSE_CONF 0x2 498 #define E1000_CONNSW_AUTOSENSE_EN 0x1 499 #define E1000_PCS_CFG_PCS_EN 8 500 #define E1000_PCS_LCTL_FLV_LINK_UP 1 501 #define E1000_PCS_LCTL_FSV_10 0 502 #define E1000_PCS_LCTL_FSV_100 2 503 #define E1000_PCS_LCTL_FSV_1000 4 504 #define E1000_PCS_LCTL_FDV_FULL 8 505 #define E1000_PCS_LCTL_FSD 0x10 506 #define E1000_PCS_LCTL_FORCE_LINK 0x20 507 #define E1000_PCS_LCTL_LOW_LINK_LATCH 0x40 508 #define E1000_PCS_LCTL_FORCE_FCTRL 0x80 509 #define E1000_PCS_LCTL_AN_ENABLE 0x10000 510 #define E1000_PCS_LCTL_AN_RESTART 0x20000 511 #define E1000_PCS_LCTL_AN_TIMEOUT 0x40000 512 #define E1000_PCS_LCTL_AN_SGMII_BYPASS 0x80000 513 #define E1000_PCS_LCTL_AN_SGMII_TRIGGER 0x100000 514 #define E1000_PCS_LCTL_FAST_LINK_TIMER 0x1000000 515 #define E1000_PCS_LCTL_LINK_OK_FIX 0x2000000 516 #define E1000_PCS_LCTL_CRS_ON_NI 0x4000000 517 #define E1000_ENABLE_SERDES_LOOPBACK 0x0410 518 519 #define E1000_PCS_LSTS_LINK_OK 1 520 #define E1000_PCS_LSTS_SPEED_10 0 521 #define E1000_PCS_LSTS_SPEED_100 2 522 #define E1000_PCS_LSTS_SPEED_1000 4 523 #define E1000_PCS_LSTS_DUPLEX_FULL 8 524 #define E1000_PCS_LSTS_SYNK_OK 0x10 525 #define E1000_PCS_LSTS_AN_COMPLETE 0x10000 526 #define E1000_PCS_LSTS_AN_PAGE_RX 0x20000 527 #define E1000_PCS_LSTS_AN_TIMED_OUT 0x40000 528 #define E1000_PCS_LSTS_AN_REMOTE_FAULT 0x80000 529 #define E1000_PCS_LSTS_AN_ERROR_RWS 0x100000 530 531 /* Device Status */ 532 #define E1000_STATUS_FD 0x00000001 /* Duplex 0=half 1=full */ 533 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 534 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 535 #define E1000_STATUS_FUNC_SHIFT 2 536 #define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ 537 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ 538 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 539 #define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */ 540 #define E1000_STATUS_SPEED_MASK 0x000000C0 541 #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 542 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 543 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 544 #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Compltn by NVM */ 545 #define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ 546 #define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */ 547 /* Change in Dock/Undock state clear on write '0'. */ 548 #define E1000_STATUS_DOCK_CI 0x00000800 549 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */ 550 #define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ 551 #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ 552 #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ 553 #define E1000_STATUS_2P5_SKU 0x00001000 /* Val of 2.5GBE SKU strap */ 554 #define E1000_STATUS_2P5_SKU_OVER 0x00002000 /* Val of 2.5GBE SKU Over */ 555 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ 556 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ 557 #define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disbld */ 558 #define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */ 559 #define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */ 560 #define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */ 561 /* BMC external code execution disabled */ 562 #define E1000_STATUS_BMC_LITE 0x01000000 563 #define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */ 564 #define E1000_STATUS_FUSE_8 0x04000000 565 #define E1000_STATUS_FUSE_9 0x08000000 566 #define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disbld on port 0 */ 567 #define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disbld on port 1 */ 568 569 /* Constants used to interpret the masked PCI-X bus speed. */ 570 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus spd 50-66MHz */ 571 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus spd 66-100MHz */ 572 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus spd 100-133MHz*/ 573 574 #define SPEED_10 10 575 #define SPEED_100 100 576 #define SPEED_1000 1000 577 #define SPEED_2500 2500 578 #define HALF_DUPLEX 1 579 #define FULL_DUPLEX 2 580 581 #define PHY_FORCE_TIME 20 582 583 #define ADVERTISE_10_HALF 0x0001 584 #define ADVERTISE_10_FULL 0x0002 585 #define ADVERTISE_100_HALF 0x0004 586 #define ADVERTISE_100_FULL 0x0008 587 #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ 588 #define ADVERTISE_1000_FULL 0x0020 589 590 /* 1000/H is not supported, nor spec-compliant. */ 591 #define E1000_ALL_SPEED_DUPLEX ( \ 592 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \ 593 ADVERTISE_100_FULL | ADVERTISE_1000_FULL) 594 #define E1000_ALL_NOT_GIG ( \ 595 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \ 596 ADVERTISE_100_FULL) 597 #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) 598 #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) 599 #define E1000_ALL_FULL_DUPLEX ( \ 600 ADVERTISE_10_FULL | ADVERTISE_100_FULL | ADVERTISE_1000_FULL) 601 #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) 602 603 #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX 604 605 /* LED Control */ 606 #define E1000_PHY_LED0_MODE_MASK 0x00000007 607 #define E1000_PHY_LED0_IVRT 0x00000008 608 #define E1000_PHY_LED0_BLINK 0x00000010 609 #define E1000_PHY_LED0_MASK 0x0000001F 610 611 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F 612 #define E1000_LEDCTL_LED0_MODE_SHIFT 0 613 #define E1000_LEDCTL_LED0_BLINK_RATE 0x00000020 614 #define E1000_LEDCTL_LED0_IVRT 0x00000040 615 #define E1000_LEDCTL_LED0_BLINK 0x00000080 616 #define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00 617 #define E1000_LEDCTL_LED1_MODE_SHIFT 8 618 #define E1000_LEDCTL_LED1_BLINK_RATE 0x00002000 619 #define E1000_LEDCTL_LED1_IVRT 0x00004000 620 #define E1000_LEDCTL_LED1_BLINK 0x00008000 621 #define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000 622 #define E1000_LEDCTL_LED2_MODE_SHIFT 16 623 #define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000 624 #define E1000_LEDCTL_LED2_IVRT 0x00400000 625 #define E1000_LEDCTL_LED2_BLINK 0x00800000 626 #define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000 627 #define E1000_LEDCTL_LED3_MODE_SHIFT 24 628 #define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000 629 #define E1000_LEDCTL_LED3_IVRT 0x40000000 630 #define E1000_LEDCTL_LED3_BLINK 0x80000000 631 632 #define E1000_LEDCTL_MODE_LINK_10_1000 0x0 633 #define E1000_LEDCTL_MODE_LINK_100_1000 0x1 634 #define E1000_LEDCTL_MODE_LINK_UP 0x2 635 #define E1000_LEDCTL_MODE_ACTIVITY 0x3 636 #define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4 637 #define E1000_LEDCTL_MODE_LINK_10 0x5 638 #define E1000_LEDCTL_MODE_LINK_100 0x6 639 #define E1000_LEDCTL_MODE_LINK_1000 0x7 640 #define E1000_LEDCTL_MODE_PCIX_MODE 0x8 641 #define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9 642 #define E1000_LEDCTL_MODE_COLLISION 0xA 643 #define E1000_LEDCTL_MODE_BUS_SPEED 0xB 644 #define E1000_LEDCTL_MODE_BUS_SIZE 0xC 645 #define E1000_LEDCTL_MODE_PAUSED 0xD 646 #define E1000_LEDCTL_MODE_LED_ON 0xE 647 #define E1000_LEDCTL_MODE_LED_OFF 0xF 648 649 /* Transmit Descriptor bit definitions */ 650 #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ 651 #define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ 652 #define E1000_TXD_POPTS_SHIFT 8 /* POPTS shift */ 653 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 654 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 655 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 656 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 657 #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 658 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 659 #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 660 #define E1000_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */ 661 #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 662 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 663 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 664 #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 665 #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 666 #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 667 #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 668 #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 669 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 670 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 671 /* Extended desc bits for Linksec and timesync */ 672 #define E1000_TXD_CMD_LINKSEC 0x10000000 /* Apply LinkSec on packet */ 673 #define E1000_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */ 674 675 /* Transmit Control */ 676 #define E1000_TCTL_RST 0x00000001 /* software reset */ 677 #define E1000_TCTL_EN 0x00000002 /* enable Tx */ 678 #define E1000_TCTL_BCE 0x00000004 /* busy check enable */ 679 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ 680 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ 681 #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 682 #define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */ 683 #define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ 684 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 685 #define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ 686 #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ 687 688 /* Transmit Arbitration Count */ 689 #define E1000_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */ 690 691 /* SerDes Control */ 692 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 693 #define E1000_SCTL_ENABLE_SERDES_LOOPBACK 0x0410 694 695 /* Receive Checksum Control */ 696 #define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */ 697 #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ 698 #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 699 #define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */ 700 #define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */ 701 #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 702 #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 703 704 /* Header split receive */ 705 #define E1000_RFCTL_ISCSI_DIS 0x00000001 706 #define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E 707 #define E1000_RFCTL_ISCSI_DWC_SHIFT 1 708 #define E1000_RFCTL_NFSW_DIS 0x00000040 709 #define E1000_RFCTL_NFSR_DIS 0x00000080 710 #define E1000_RFCTL_NFS_VER_MASK 0x00000300 711 #define E1000_RFCTL_NFS_VER_SHIFT 8 712 #define E1000_RFCTL_IPV6_DIS 0x00000400 713 #define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800 714 #define E1000_RFCTL_ACK_DIS 0x00001000 715 #define E1000_RFCTL_ACKD_DIS 0x00002000 716 #define E1000_RFCTL_IPFRSP_DIS 0x00004000 717 #define E1000_RFCTL_EXTEN 0x00008000 718 #define E1000_RFCTL_IPV6_EX_DIS 0x00010000 719 #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 720 #define E1000_RFCTL_LEF 0x00040000 721 722 /* Collision related configuration parameters */ 723 #define E1000_COLLISION_THRESHOLD 15 724 #define E1000_CT_SHIFT 4 725 #define E1000_COLLISION_DISTANCE 63 726 #define E1000_COLD_SHIFT 12 727 728 /* Default values for the transmit IPG register */ 729 #ifndef NO_82542_SUPPORT 730 #define DEFAULT_82542_TIPG_IPGT 10 731 #endif 732 #define DEFAULT_82543_TIPG_IPGT_FIBER 9 733 #define DEFAULT_82543_TIPG_IPGT_COPPER 8 734 735 #define E1000_TIPG_IPGT_MASK 0x000003FF 736 #define E1000_TIPG_IPGR1_MASK 0x000FFC00 737 #define E1000_TIPG_IPGR2_MASK 0x3FF00000 738 739 #ifndef NO_82542_SUPPORT 740 #define DEFAULT_82542_TIPG_IPGR1 2 741 #endif 742 #define DEFAULT_82543_TIPG_IPGR1 8 743 #define E1000_TIPG_IPGR1_SHIFT 10 744 745 #ifndef NO_82542_SUPPORT 746 #define DEFAULT_82542_TIPG_IPGR2 10 747 #endif 748 #define DEFAULT_82543_TIPG_IPGR2 6 749 #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 750 #define E1000_TIPG_IPGR2_SHIFT 20 751 752 /* Ethertype field values */ 753 #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ 754 755 #define ETHERNET_FCS_SIZE 4 756 #define MAX_JUMBO_FRAME_SIZE 0x3F00 757 #define E1000_TX_PTR_GAP 0x1F 758 759 /* Extended Configuration Control and Size */ 760 #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 761 #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 762 #define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008 763 #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 764 #define E1000_EXTCNF_CTRL_GATE_PHY_CFG 0x00000080 765 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000 766 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16 767 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 768 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 769 770 #define E1000_PHY_CTRL_SPD_EN 0x00000001 771 #define E1000_PHY_CTRL_D0A_LPLU 0x00000002 772 #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 773 #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 774 #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 775 776 #define E1000_KABGTXD_BGSQLBIAS 0x00050000 777 778 /* Low Power IDLE Control */ 779 #define E1000_LPIC_LPIET_SHIFT 24 /* Low Power Idle Entry Time */ 780 781 /* PBA constants */ 782 #define E1000_PBA_6K 0x0006 /* 6KB */ 783 #define E1000_PBA_8K 0x0008 /* 8KB */ 784 #define E1000_PBA_10K 0x000A /* 10KB */ 785 #define E1000_PBA_12K 0x000C /* 12KB */ 786 #define E1000_PBA_14K 0x000E /* 14KB */ 787 #define E1000_PBA_16K 0x0010 /* 16KB */ 788 #define E1000_PBA_18K 0x0012 789 #define E1000_PBA_20K 0x0014 790 #define E1000_PBA_22K 0x0016 791 #define E1000_PBA_24K 0x0018 792 #define E1000_PBA_26K 0x001A 793 #define E1000_PBA_30K 0x001E 794 #define E1000_PBA_32K 0x0020 795 #define E1000_PBA_34K 0x0022 796 #define E1000_PBA_35K 0x0023 797 #define E1000_PBA_38K 0x0026 798 #define E1000_PBA_40K 0x0028 799 #define E1000_PBA_48K 0x0030 /* 48KB */ 800 #define E1000_PBA_64K 0x0040 /* 64KB */ 801 802 #define E1000_PBA_RXA_MASK 0xFFFF 803 804 #define E1000_PBS_16K E1000_PBA_16K 805 #define E1000_PBS_24K E1000_PBA_24K 806 807 /* Uncorrectable/correctable ECC Error counts and enable bits */ 808 #define E1000_PBECCSTS_CORR_ERR_CNT_MASK 0x000000FF 809 #define E1000_PBECCSTS_UNCORR_ERR_CNT_MASK 0x0000FF00 810 #define E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT 8 811 #define E1000_PBECCSTS_ECC_ENABLE 0x00010000 812 813 #define IFS_MAX 80 814 #define IFS_MIN 40 815 #define IFS_RATIO 4 816 #define IFS_STEP 10 817 #define MIN_NUM_XMITS 1000 818 819 /* SW Semaphore Register */ 820 #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 821 #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 822 #define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ 823 #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ 824 825 #define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */ 826 827 /* Interrupt Cause Read */ 828 #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ 829 #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ 830 #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ 831 #define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */ 832 #define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */ 833 #define E1000_ICR_RXO 0x00000040 /* Rx overrun */ 834 #define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */ 835 #define E1000_ICR_VMMB 0x00000100 /* VM MB event */ 836 #define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ 837 #define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */ 838 #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ 839 #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ 840 #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ 841 #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ 842 #define E1000_ICR_TXD_LOW 0x00008000 843 #define E1000_ICR_SRPD 0x00010000 844 #define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */ 845 #define E1000_ICR_MNG 0x00040000 /* Manageability event */ 846 #define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */ 847 #define E1000_ICR_ECCER 0x00400000 /* Uncorrectable ECC Error */ 848 #define E1000_ICR_TS 0x00080000 /* Time Sync Interrupt */ 849 #define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */ 850 #define E1000_ICR_ECCER 0x00400000 /* Uncorrectable ECC Error */ 851 /* If this bit asserted, the driver should claim the interrupt */ 852 #define E1000_ICR_INT_ASSERTED 0x80000000 853 #define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* Q0 Rx desc FIFO parity error */ 854 #define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* Q0 Tx desc FIFO parity error */ 855 #define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity err */ 856 #define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */ 857 #define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* Q1 Rx desc FIFO parity error */ 858 #define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* Q1 Tx desc FIFO parity error */ 859 #define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */ 860 /* FW changed the status of DISSW bit in the FWSM */ 861 #define E1000_ICR_DSW 0x00000020 862 /* LAN connected device generates an interrupt */ 863 #define E1000_ICR_PHYINT 0x00001000 864 #define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */ 865 #define E1000_ICR_EPRST 0x00100000 /* ME hardware reset occurs */ 866 #define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */ 867 #define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */ 868 #define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */ 869 #define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */ 870 #define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */ 871 #define E1000_ICR_FER 0x00400000 /* Fatal Error */ 872 873 #define E1000_ICR_THS 0x00800000 /* ICR.THS: Thermal Sensor Event*/ 874 #define E1000_ICR_MDDET 0x10000000 /* Malicious Driver Detect */ 875 876 #define E1000_ITR_MASK 0x000FFFFF /* ITR value bitfield */ 877 #define E1000_ITR_MULT 256 /* ITR mulitplier in nsec */ 878 879 /* PBA ECC Register */ 880 #define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */ 881 #define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */ 882 #define E1000_PBA_ECC_CORR_EN 0x00000001 /* Enable ECC error correction */ 883 #define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */ 884 #define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 on ECC error */ 885 886 /* Extended Interrupt Cause Read */ 887 #define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */ 888 #define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */ 889 #define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */ 890 #define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */ 891 #define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */ 892 #define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */ 893 #define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */ 894 #define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */ 895 #define E1000_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ 896 #define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ 897 /* TCP Timer */ 898 #define E1000_TCPTIMER_KS 0x00000100 /* KickStart */ 899 #define E1000_TCPTIMER_COUNT_ENABLE 0x00000200 /* Count Enable */ 900 #define E1000_TCPTIMER_COUNT_FINISH 0x00000400 /* Count finish */ 901 #define E1000_TCPTIMER_LOOP 0x00000800 /* Loop */ 902 903 /* This defines the bits that are set in the Interrupt Mask 904 * Set/Read Register. Each bit is documented below: 905 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 906 * o RXSEQ = Receive Sequence Error 907 */ 908 #define POLL_IMS_ENABLE_MASK ( \ 909 E1000_IMS_RXDMT0 | \ 910 E1000_IMS_RXSEQ) 911 912 /* 913 * This defines the bits that are set in the Interrupt Mask 914 * Set/Read Register. Each bit is documented below: 915 * o RXT0 = Receiver Timer Interrupt (ring 0) 916 * o TXDW = Transmit Descriptor Written Back 917 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 918 * o RXSEQ = Receive Sequence Error 919 * o LSC = Link Status Change 920 */ 921 #define IMS_ENABLE_MASK ( \ 922 E1000_IMS_RXT0 | \ 923 E1000_IMS_TXDW | \ 924 E1000_IMS_RXDMT0 | \ 925 E1000_IMS_RXSEQ | \ 926 E1000_IMS_LSC) 927 928 /* Interrupt Mask Set */ 929 #define E1000_IMS_TXDW E1000_ICR_TXDW /* Tx desc written back */ 930 #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 931 #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ 932 #define E1000_IMS_VMMB E1000_ICR_VMMB /* Mail box activity */ 933 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ 934 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ 935 #define E1000_IMS_RXO E1000_ICR_RXO /* Rx overrun */ 936 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */ 937 #define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ 938 #define E1000_IMS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */ 939 #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 940 #define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 941 #define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 942 #define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 943 #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW 944 #define E1000_IMS_SRPD E1000_ICR_SRPD 945 #define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */ 946 #define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */ 947 #define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */ 948 #define E1000_IMS_ECCER E1000_ICR_ECCER /* Uncorrectable ECC Error */ 949 #define E1000_IMS_TS E1000_ICR_TS /* Time Sync Interrupt */ 950 #define E1000_IMS_DRSTA E1000_ICR_DRSTA /* Device Reset Asserted */ 951 /* Q0 Rx desc FIFO parity error */ 952 #define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 953 /* Q0 Tx desc FIFO parity error */ 954 #define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 955 /* host arb read buffer parity error */ 956 #define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR 957 /* packet buffer parity error */ 958 #define E1000_IMS_PB_PAR E1000_ICR_PB_PAR 959 /* Q1 Rx desc FIFO parity error */ 960 #define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 961 /* Q1 Tx desc FIFO parity error */ 962 #define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 963 #define E1000_IMS_DSW E1000_ICR_DSW 964 #define E1000_IMS_PHYINT E1000_ICR_PHYINT 965 #define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ 966 #define E1000_IMS_EPRST E1000_ICR_EPRST 967 #define E1000_IMS_ECCER E1000_ICR_ECCER /* Uncorrectable ECC Error */ 968 #define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */ 969 #define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */ 970 #define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */ 971 #define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */ 972 #define E1000_IMS_OTHER E1000_ICR_OTHER /* Other Interrupts */ 973 #define E1000_IMS_FER E1000_ICR_FER /* Fatal Error */ 974 975 #define E1000_IMS_THS E1000_ICR_THS /* ICR.TS: Thermal Sensor Event*/ 976 #define E1000_IMS_MDDET E1000_ICR_MDDET /* Malicious Driver Detect */ 977 /* Extended Interrupt Mask Set */ 978 #define E1000_EIMS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */ 979 #define E1000_EIMS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */ 980 #define E1000_EIMS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */ 981 #define E1000_EIMS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */ 982 #define E1000_EIMS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */ 983 #define E1000_EIMS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */ 984 #define E1000_EIMS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */ 985 #define E1000_EIMS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */ 986 #define E1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */ 987 #define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */ 988 989 /* Interrupt Cause Set */ 990 #define E1000_ICS_TXDW E1000_ICR_TXDW /* Tx desc written back */ 991 #define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 992 #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 993 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ 994 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ 995 #define E1000_ICS_RXO E1000_ICR_RXO /* Rx overrun */ 996 #define E1000_ICS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */ 997 #define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ 998 #define E1000_ICS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */ 999 #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 1000 #define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 1001 #define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 1002 #define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 1003 #define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW 1004 #define E1000_ICS_SRPD E1000_ICR_SRPD 1005 #define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */ 1006 #define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */ 1007 #define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */ 1008 #define E1000_ICS_DRSTA E1000_ICR_DRSTA /* Device Reset Aserted */ 1009 /* Q0 Rx desc FIFO parity error */ 1010 #define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 1011 /* Q0 Tx desc FIFO parity error */ 1012 #define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 1013 /* host arb read buffer parity error */ 1014 #define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR 1015 /* packet buffer parity error */ 1016 #define E1000_ICS_PB_PAR E1000_ICR_PB_PAR 1017 /* Q1 Rx desc FIFO parity error */ 1018 #define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 1019 /* Q1 Tx desc FIFO parity error */ 1020 #define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 1021 #define E1000_ICS_DSW E1000_ICR_DSW 1022 #define E1000_ICS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ 1023 #define E1000_ICS_PHYINT E1000_ICR_PHYINT 1024 #define E1000_ICS_EPRST E1000_ICR_EPRST 1025 1026 /* Extended Interrupt Cause Set */ 1027 #define E1000_EICS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */ 1028 #define E1000_EICS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */ 1029 #define E1000_EICS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */ 1030 #define E1000_EICS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */ 1031 #define E1000_EICS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */ 1032 #define E1000_EICS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */ 1033 #define E1000_EICS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */ 1034 #define E1000_EICS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */ 1035 #define E1000_EICS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */ 1036 #define E1000_EICS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */ 1037 1038 #define E1000_EITR_ITR_INT_MASK 0x0000FFFF 1039 /* E1000_EITR_CNT_IGNR is only for 82576 and newer */ 1040 #define E1000_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */ 1041 #define E1000_EITR_INTERVAL 0x00007FFC 1042 1043 /* Transmit Descriptor Control */ 1044 #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ 1045 #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ 1046 #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ 1047 #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ 1048 #define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */ 1049 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ 1050 #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */ 1051 /* Enable the counting of descriptors still to be processed. */ 1052 #define E1000_TXDCTL_COUNT_DESC 0x00400000 1053 1054 /* Flow Control Constants */ 1055 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 1056 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 1057 #define FLOW_CONTROL_TYPE 0x8808 1058 1059 /* 802.1q VLAN Packet Size */ 1060 #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */ 1061 #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 1062 1063 /* Receive Address 1064 * Number of high/low register pairs in the RAR. The RAR (Receive Address 1065 * Registers) holds the directed and multicast addresses that we monitor. 1066 * Technically, we have 16 spots. However, we reserve one of these spots 1067 * (RAR[15]) for our directed address used by controllers with 1068 * manageability enabled, allowing us room for 15 multicast addresses. 1069 */ 1070 #define E1000_RAR_ENTRIES 15 1071 #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ 1072 #define E1000_RAL_MAC_ADDR_LEN 4 1073 #define E1000_RAH_MAC_ADDR_LEN 2 1074 #define E1000_RAH_QUEUE_MASK_82575 0x000C0000 1075 #define E1000_RAH_POOL_MASK 0x03FC0000 1076 #define E1000_RAH_POOL_SHIFT 18 1077 #define E1000_RAH_POOL_1 0x00040000 1078 1079 /* Error Codes */ 1080 #define E1000_SUCCESS 0 1081 #define E1000_ERR_NVM 1 1082 #define E1000_ERR_PHY 2 1083 #define E1000_ERR_CONFIG 3 1084 #define E1000_ERR_PARAM 4 1085 #define E1000_ERR_MAC_INIT 5 1086 #define E1000_ERR_PHY_TYPE 6 1087 #define E1000_ERR_RESET 9 1088 #define E1000_ERR_MASTER_REQUESTS_PENDING 10 1089 #define E1000_ERR_HOST_INTERFACE_COMMAND 11 1090 #define E1000_BLK_PHY_RESET 12 1091 #define E1000_ERR_SWFW_SYNC 13 1092 #define E1000_NOT_IMPLEMENTED 14 1093 #define E1000_ERR_MBX 15 1094 #define E1000_ERR_INVALID_ARGUMENT 16 1095 #define E1000_ERR_NO_SPACE 17 1096 #define E1000_ERR_NVM_PBA_SECTION 18 1097 #define E1000_ERR_I2C 19 1098 #define E1000_ERR_INVM_VALUE_NOT_FOUND 20 1099 1100 /* Loop limit on how long we wait for auto-negotiation to complete */ 1101 #define FIBER_LINK_UP_LIMIT 50 1102 #define COPPER_LINK_UP_LIMIT 10 1103 #define PHY_AUTO_NEG_LIMIT 45 1104 #define PHY_FORCE_LIMIT 20 1105 /* Number of 100 microseconds we wait for PCI Express master disable */ 1106 #define MASTER_DISABLE_TIMEOUT 800 1107 /* Number of milliseconds we wait for PHY configuration done after MAC reset */ 1108 #define PHY_CFG_TIMEOUT 100 1109 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ 1110 #define MDIO_OWNERSHIP_TIMEOUT 10 1111 /* Number of milliseconds for NVM auto read done after MAC reset. */ 1112 #define AUTO_READ_DONE_TIMEOUT 10 1113 1114 /* Flow Control */ 1115 #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ 1116 #define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */ 1117 #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ 1118 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 1119 1120 /* Transmit Configuration Word */ 1121 #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ 1122 #define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */ 1123 #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ 1124 #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ 1125 #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ 1126 #define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */ 1127 #define E1000_TXCW_NP 0x00008000 /* TXCW next page */ 1128 #define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */ 1129 #define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */ 1130 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ 1131 1132 /* Receive Configuration Word */ 1133 #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ 1134 #define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */ 1135 #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ 1136 #define E1000_RXCW_CC 0x10000000 /* Receive config change */ 1137 #define E1000_RXCW_C 0x20000000 /* Receive config */ 1138 #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ 1139 #define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */ 1140 1141 #define E1000_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */ 1142 #define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */ 1143 1144 #define E1000_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */ 1145 #define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */ 1146 #define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00 1147 #define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02 1148 #define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 1149 #define E1000_TSYNCRXCTL_TYPE_ALL 0x08 1150 #define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A 1151 #define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */ 1152 #define E1000_TSYNCRXCTL_SYSCFI 0x00000020 /* Sys clock frequency */ 1153 1154 #define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF 1155 #define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00 1156 #define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01 1157 #define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE 0x02 1158 #define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03 1159 #define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04 1160 1161 #define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK 0x00000F00 1162 #define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE 0x0000 1163 #define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE 0x0100 1164 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE 0x0200 1165 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE 0x0300 1166 #define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE 0x0800 1167 #define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE 0x0900 1168 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00 1169 #define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE 0x0B00 1170 #define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE 0x0C00 1171 #define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00 1172 1173 #define E1000_RXMTRL_PTP_V1_SYNC_MESSAGE 0x00000000 1174 #define E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE 0x00010000 1175 1176 #define E1000_RXMTRL_PTP_V2_SYNC_MESSAGE 0x00000000 1177 #define E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE 0x01000000 1178 1179 #define E1000_TIMINCA_16NS_SHIFT 24 1180 #define E1000_TIMINCA_INCPERIOD_SHIFT 24 1181 #define E1000_TIMINCA_INCVALUE_MASK 0x00FFFFFF 1182 1183 #define E1000_TSICR_TXTS 0x00000002 1184 #define E1000_TSIM_TXTS 0x00000002 1185 /* TUPLE Filtering Configuration */ 1186 #define E1000_TTQF_DISABLE_MASK 0xF0008000 /* TTQF Disable Mask */ 1187 #define E1000_TTQF_QUEUE_ENABLE 0x100 /* TTQF Queue Enable Bit */ 1188 #define E1000_TTQF_PROTOCOL_MASK 0xFF /* TTQF Protocol Mask */ 1189 /* TTQF TCP Bit, shift with E1000_TTQF_PROTOCOL SHIFT */ 1190 #define E1000_TTQF_PROTOCOL_TCP 0x0 1191 /* TTQF UDP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */ 1192 #define E1000_TTQF_PROTOCOL_UDP 0x1 1193 /* TTQF SCTP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */ 1194 #define E1000_TTQF_PROTOCOL_SCTP 0x2 1195 #define E1000_TTQF_PROTOCOL_SHIFT 5 /* TTQF Protocol Shift */ 1196 #define E1000_TTQF_QUEUE_SHIFT 16 /* TTQF Queue Shfit */ 1197 #define E1000_TTQF_RX_QUEUE_MASK 0x70000 /* TTQF Queue Mask */ 1198 #define E1000_TTQF_MASK_ENABLE 0x10000000 /* TTQF Mask Enable Bit */ 1199 #define E1000_IMIR_CLEAR_MASK 0xF001FFFF /* IMIR Reg Clear Mask */ 1200 #define E1000_IMIR_PORT_BYPASS 0x20000 /* IMIR Port Bypass Bit */ 1201 #define E1000_IMIR_PRIORITY_SHIFT 29 /* IMIR Priority Shift */ 1202 #define E1000_IMIREXT_CLEAR_MASK 0x7FFFF /* IMIREXT Reg Clear Mask */ 1203 1204 #define E1000_MDICNFG_EXT_MDIO 0x80000000 /* MDI ext/int destination */ 1205 #define E1000_MDICNFG_COM_MDIO 0x40000000 /* MDI shared w/ lan 0 */ 1206 #define E1000_MDICNFG_PHY_MASK 0x03E00000 1207 #define E1000_MDICNFG_PHY_SHIFT 21 1208 1209 #define E1000_MEDIA_PORT_COPPER 1 1210 #define E1000_MEDIA_PORT_OTHER 2 1211 #define E1000_M88E1112_AUTO_COPPER_SGMII 0x2 1212 #define E1000_M88E1112_AUTO_COPPER_BASEX 0x3 1213 #define E1000_M88E1112_STATUS_LINK 0x0004 /* Interface Link Bit */ 1214 #define E1000_M88E1112_MAC_CTRL_1 0x10 1215 #define E1000_M88E1112_MAC_CTRL_1_MODE_MASK 0x0380 /* Mode Select */ 1216 #define E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT 7 1217 #define E1000_M88E1112_PAGE_ADDR 0x16 1218 #define E1000_M88E1112_STATUS 0x01 1219 1220 #define E1000_THSTAT_LOW_EVENT 0x20000000 /* Low thermal threshold */ 1221 #define E1000_THSTAT_MID_EVENT 0x00200000 /* Mid thermal threshold */ 1222 #define E1000_THSTAT_HIGH_EVENT 0x00002000 /* High thermal threshold */ 1223 #define E1000_THSTAT_PWR_DOWN 0x00000001 /* Power Down Event */ 1224 #define E1000_THSTAT_LINK_THROTTLE 0x00000002 /* Link Spd Throttle Event */ 1225 1226 /* I350 EEE defines */ 1227 #define E1000_IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Ena 1G AN */ 1228 #define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* IPCNFG EEE Ena 100M AN */ 1229 #define E1000_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */ 1230 #define E1000_EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */ 1231 #define E1000_EEER_LPI_FC 0x00040000 /* EEER Ena on Flow Cntrl */ 1232 /* EEE status */ 1233 #define E1000_EEER_EEE_NEG 0x20000000 /* EEE capability nego */ 1234 #define E1000_EEER_RX_LPI_STATUS 0x40000000 /* Rx in LPI state */ 1235 #define E1000_EEER_TX_LPI_STATUS 0x80000000 /* Tx in LPI state */ 1236 #define E1000_EEE_LP_ADV_ADDR_I350 0x040F /* EEE LP Advertisement */ 1237 #define E1000_M88E1543_PAGE_ADDR 0x16 /* Page Offset Register */ 1238 #define E1000_M88E1543_EEE_CTRL_1 0x0 1239 #define E1000_M88E1543_EEE_CTRL_1_MS 0x0001 /* EEE Master/Slave */ 1240 #define E1000_EEE_ADV_DEV_I354 7 1241 #define E1000_EEE_ADV_ADDR_I354 60 1242 #define E1000_EEE_ADV_100_SUPPORTED (1 << 1) /* 100BaseTx EEE Supported */ 1243 #define E1000_EEE_ADV_1000_SUPPORTED (1 << 2) /* 1000BaseT EEE Supported */ 1244 #define E1000_PCS_STATUS_DEV_I354 3 1245 #define E1000_PCS_STATUS_ADDR_I354 1 1246 #define E1000_PCS_STATUS_TX_LPI_IND 0x0200 /* Tx in LPI state */ 1247 #define E1000_PCS_STATUS_RX_LPI_RCVD 0x0400 1248 #define E1000_PCS_STATUS_TX_LPI_RCVD 0x0800 1249 #define E1000_M88E1512_CFG_REG_1 0x0010 1250 #define E1000_M88E1512_CFG_REG_2 0x0011 1251 #define E1000_M88E1512_CFG_REG_3 0x0007 1252 #define E1000_M88E1512_MODE 0x0014 1253 #define E1000_EEE_SU_LPI_CLK_STP 0x00800000 /* EEE LPI Clock Stop */ 1254 #define E1000_EEE_LP_ADV_DEV_I210 7 /* EEE LP Adv Device */ 1255 #define E1000_EEE_LP_ADV_ADDR_I210 61 /* EEE LP Adv Register */ 1256 /* PCI Express Control */ 1257 #define E1000_GCR_RXD_NO_SNOOP 0x00000001 1258 #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 1259 #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004 1260 #define E1000_GCR_TXD_NO_SNOOP 0x00000008 1261 #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 1262 #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 1263 #define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000 1264 #define E1000_GCR_CMPL_TMOUT_10ms 0x00001000 1265 #define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000 1266 #define E1000_GCR_CAP_VER2 0x00040000 1267 1268 #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ 1269 E1000_GCR_RXDSCW_NO_SNOOP | \ 1270 E1000_GCR_RXDSCR_NO_SNOOP | \ 1271 E1000_GCR_TXD_NO_SNOOP | \ 1272 E1000_GCR_TXDSCW_NO_SNOOP | \ 1273 E1000_GCR_TXDSCR_NO_SNOOP) 1274 1275 #define E1000_MMDAC_FUNC_DATA 0x4000 /* Data, no post increment */ 1276 1277 /* mPHY address control and data registers */ 1278 #define E1000_MPHY_ADDR_CTL 0x0024 /* Address Control Reg */ 1279 #define E1000_MPHY_ADDR_CTL_OFFSET_MASK 0xFFFF0000 1280 #define E1000_MPHY_DATA 0x0E10 /* Data Register */ 1281 1282 /* AFE CSR Offset for PCS CLK */ 1283 #define E1000_MPHY_PCS_CLK_REG_OFFSET 0x0004 1284 /* Override for near end digital loopback. */ 1285 #define E1000_MPHY_PCS_CLK_REG_DIGINELBEN 0x10 1286 1287 /* PHY Control Register */ 1288 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ 1289 #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ 1290 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 1291 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 1292 #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ 1293 #define MII_CR_POWER_DOWN 0x0800 /* Power down */ 1294 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 1295 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ 1296 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 1297 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 1298 #define MII_CR_SPEED_1000 0x0040 1299 #define MII_CR_SPEED_100 0x2000 1300 #define MII_CR_SPEED_10 0x0000 1301 1302 /* PHY Status Register */ 1303 #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ 1304 #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ 1305 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 1306 #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ 1307 #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ 1308 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 1309 #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ 1310 #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ 1311 #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ 1312 #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ 1313 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ 1314 #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ 1315 #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ 1316 #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ 1317 #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ 1318 1319 /* Autoneg Advertisement Register */ 1320 #define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ 1321 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 1322 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 1323 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 1324 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 1325 #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ 1326 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ 1327 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ 1328 #define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ 1329 #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 1330 1331 /* Link Partner Ability Register (Base Page) */ 1332 #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ 1333 #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP 10T Half Dplx Capable */ 1334 #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP 10T Full Dplx Capable */ 1335 #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP 100TX Half Dplx Capable */ 1336 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP 100TX Full Dplx Capable */ 1337 #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ 1338 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ 1339 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asym Pause Direction bit */ 1340 #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP detected Remote Fault */ 1341 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP rx'd link code word */ 1342 #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 1343 1344 /* Autoneg Expansion Register */ 1345 #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ 1346 #define NWAY_ER_PAGE_RXD 0x0002 /* LP 10T Half Dplx Capable */ 1347 #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP 10T Full Dplx Capable */ 1348 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP 100TX Half Dplx Capable */ 1349 #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP 100TX Full Dplx Capable */ 1350 1351 /* 1000BASE-T Control Register */ 1352 #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ 1353 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 1354 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 1355 /* 1=Repeater/switch device port 0=DTE device */ 1356 #define CR_1000T_REPEATER_DTE 0x0400 1357 /* 1=Configure PHY as Master 0=Configure PHY as Slave */ 1358 #define CR_1000T_MS_VALUE 0x0800 1359 /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */ 1360 #define CR_1000T_MS_ENABLE 0x1000 1361 #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ 1362 #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ 1363 #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ 1364 #define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ 1365 #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ 1366 1367 /* 1000BASE-T Status Register */ 1368 #define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle err since last rd */ 1369 #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asym pause direction bit */ 1370 #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ 1371 #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ 1372 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 1373 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 1374 #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local Tx Master, 0=Slave */ 1375 #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ 1376 1377 #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5 1378 1379 /* PHY 1000 MII Register/Bit Definitions */ 1380 /* PHY Registers defined by IEEE */ 1381 #define PHY_CONTROL 0x00 /* Control Register */ 1382 #define PHY_STATUS 0x01 /* Status Register */ 1383 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 1384 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 1385 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 1386 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 1387 #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ 1388 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */ 1389 #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ 1390 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 1391 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 1392 #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ 1393 1394 #define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */ 1395 1396 /* NVM Control */ 1397 #define E1000_EECD_SK 0x00000001 /* NVM Clock */ 1398 #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ 1399 #define E1000_EECD_DI 0x00000004 /* NVM Data In */ 1400 #define E1000_EECD_DO 0x00000008 /* NVM Data Out */ 1401 #define E1000_EECD_FWE_MASK 0x00000030 1402 #define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */ 1403 #define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */ 1404 #define E1000_EECD_FWE_SHIFT 4 1405 #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ 1406 #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ 1407 #define E1000_EECD_PRES 0x00000100 /* NVM Present */ 1408 #define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ 1409 #define E1000_EECD_BLOCKED 0x00008000 /* Bit banging access blocked flag */ 1410 #define E1000_EECD_ABORT 0x00010000 /* NVM operation aborted flag */ 1411 #define E1000_EECD_TIMEOUT 0x00020000 /* NVM read operation timeout flag */ 1412 #define E1000_EECD_ERROR_CLR 0x00040000 /* NVM error status clear bit */ 1413 /* NVM Addressing bits based on type 0=small, 1=large */ 1414 #define E1000_EECD_ADDR_BITS 0x00000400 1415 #define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */ 1416 #ifndef E1000_NVM_GRANT_ATTEMPTS 1417 #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ 1418 #endif 1419 #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ 1420 #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ 1421 #define E1000_EECD_SIZE_EX_SHIFT 11 1422 #define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */ 1423 #define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */ 1424 #define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */ 1425 #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ 1426 #define E1000_EECD_AUPDEN 0x00100000 /* Ena Auto FLASH update */ 1427 #define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */ 1428 #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ 1429 #define E1000_EECD_SECVAL_SHIFT 22 1430 #define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) 1431 #define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */ 1432 #define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done */ 1433 #define E1000_EECD_FLASH_DETECTED_I210 0x00080000 /* FLASH detected */ 1434 #define E1000_EECD_SEC1VAL_I210 0x02000000 /* Sector One Valid */ 1435 #define E1000_FLUDONE_ATTEMPTS 20000 1436 #define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */ 1437 #define E1000_I210_FIFO_SEL_RX 0x00 1438 #define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i)) 1439 #define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0) 1440 #define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06 1441 #define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01 1442 1443 #define E1000_I210_FLASH_SECTOR_SIZE 0x1000 /* 4KB FLASH sector unit size */ 1444 /* Secure FLASH mode requires removing MSb */ 1445 #define E1000_I210_FW_PTR_MASK 0x7FFF 1446 /* Firmware code revision field word offset*/ 1447 #define E1000_I210_FW_VER_OFFSET 328 1448 1449 #define E1000_NVM_SWDPIN0 0x0001 /* SWDPIN 0 NVM Value */ 1450 #define E1000_NVM_LED_LOGIC 0x0020 /* Led Logic Word */ 1451 #define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write regs */ 1452 #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 1453 #define E1000_NVM_RW_REG_START 1 /* Start operation */ 1454 #define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 1455 #define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ 1456 #define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */ 1457 #define E1000_FLASH_UPDATES 2000 1458 1459 /* NVM Word Offsets */ 1460 #define NVM_COMPAT 0x0003 1461 #define NVM_ID_LED_SETTINGS 0x0004 1462 #define NVM_VERSION 0x0005 1463 #define NVM_SERDES_AMPLITUDE 0x0006 /* SERDES output amplitude */ 1464 #define NVM_PHY_CLASS_WORD 0x0007 1465 #define E1000_I210_NVM_FW_MODULE_PTR 0x0010 1466 #define E1000_I350_NVM_FW_MODULE_PTR 0x0051 1467 #define NVM_FUTURE_INIT_WORD1 0x0019 1468 #define NVM_COMPAT_VALID_CSUM 0x0001 1469 #define NVM_FUTURE_INIT_WORD1_VALID_CSUM 0x0040 1470 #define NVM_ETRACK_WORD 0x0042 1471 #define NVM_ETRACK_HIWORD 0x0043 1472 #define NVM_COMB_VER_OFF 0x0083 1473 #define NVM_COMB_VER_PTR 0x003d 1474 1475 /* NVM version defines */ 1476 #define NVM_MAJOR_MASK 0xF000 1477 #define NVM_MINOR_MASK 0x0FF0 1478 #define NVM_IMAGE_ID_MASK 0x000F 1479 #define NVM_COMB_VER_MASK 0x00FF 1480 #define NVM_MAJOR_SHIFT 12 1481 #define NVM_MINOR_SHIFT 4 1482 #define NVM_COMB_VER_SHFT 8 1483 #define NVM_VER_INVALID 0xFFFF 1484 #define NVM_ETRACK_SHIFT 16 1485 #define NVM_ETRACK_VALID 0x8000 1486 #define NVM_NEW_DEC_MASK 0x0F00 1487 #define NVM_HEX_CONV 16 1488 #define NVM_HEX_TENS 10 1489 1490 /* FW version defines */ 1491 /* Offset of "Loader patch ptr" in Firmware Header */ 1492 #define E1000_I350_NVM_FW_LOADER_PATCH_PTR_OFFSET 0x01 1493 /* Patch generation hour & minutes */ 1494 #define E1000_I350_NVM_FW_VER_WORD1_OFFSET 0x04 1495 /* Patch generation month & day */ 1496 #define E1000_I350_NVM_FW_VER_WORD2_OFFSET 0x05 1497 /* Patch generation year */ 1498 #define E1000_I350_NVM_FW_VER_WORD3_OFFSET 0x06 1499 /* Patch major & minor numbers */ 1500 #define E1000_I350_NVM_FW_VER_WORD4_OFFSET 0x07 1501 1502 #define NVM_MAC_ADDR 0x0000 1503 #define NVM_SUB_DEV_ID 0x000B 1504 #define NVM_SUB_VEN_ID 0x000C 1505 #define NVM_DEV_ID 0x000D 1506 #define NVM_VEN_ID 0x000E 1507 #define NVM_INIT_CTRL_2 0x000F 1508 #define NVM_INIT_CTRL_4 0x0013 1509 #define NVM_LED_1_CFG 0x001C 1510 #define NVM_LED_0_2_CFG 0x001F 1511 1512 #define NVM_INIT_CONTROL1_REG 0x000A 1513 #define NVM_COMPAT_VALID_CSUM 0x0001 1514 #define NVM_FUTURE_INIT_WORD1_VALID_CSUM 0x0040 1515 1516 #define NVM_INIT_CONTROL2_REG 0x000F 1517 #define NVM_SWDEF_PINS_CTRL_PORT_1 0x0010 1518 #define NVM_INIT_CONTROL3_PORT_B 0x0014 1519 #define NVM_INIT_3GIO_3 0x001A 1520 #define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020 1521 #define NVM_INIT_CONTROL3_PORT_A 0x0024 1522 #define NVM_CFG 0x0012 1523 #define NVM_FLASH_VERSION 0x0032 1524 #define NVM_ALT_MAC_ADDR_PTR 0x0037 1525 #define NVM_CHECKSUM_REG 0x003F 1526 #define NVM_COMPATIBILITY_REG_3 0x0003 1527 #define NVM_COMPATIBILITY_BIT_MASK 0x8000 1528 1529 #define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */ 1530 #define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */ 1531 #define E1000_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */ 1532 #define E1000_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */ 1533 1534 #define NVM_82580_LAN_FUNC_OFFSET(a) ((a) ? (0x40 + (0x40 * (a))) : 0) 1535 1536 /* Mask bits for fields in Word 0x24 of the NVM */ 1537 #define NVM_WORD24_COM_MDIO 0x0008 /* MDIO interface shared */ 1538 #define NVM_WORD24_EXT_MDIO 0x0004 /* MDIO accesses routed extrnl */ 1539 /* Offset of Link Mode bits for 82575/82576 */ 1540 #define NVM_WORD24_LNK_MODE_OFFSET 8 1541 /* Offset of Link Mode bits for 82580 up */ 1542 #define NVM_WORD24_82580_LNK_MODE_OFFSET 4 1543 1544 1545 /* Mask bits for fields in Word 0x0f of the NVM */ 1546 #define NVM_WORD0F_PAUSE_MASK 0x3000 1547 #define NVM_WORD0F_PAUSE 0x1000 1548 #define NVM_WORD0F_ASM_DIR 0x2000 1549 #define NVM_WORD0F_ANE 0x0800 1550 #define NVM_WORD0F_SWPDIO_EXT_MASK 0x00F0 1551 #define NVM_WORD0F_LPLU 0x0001 1552 1553 /* Mask bits for fields in Word 0x1a of the NVM */ 1554 #define NVM_WORD1A_ASPM_MASK 0x000C 1555 1556 /* Mask bits for fields in Word 0x03 of the EEPROM */ 1557 #define NVM_COMPAT_LOM 0x0800 1558 1559 /* length of string needed to store PBA number */ 1560 #define E1000_PBANUM_LENGTH 11 1561 1562 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ 1563 #define NVM_SUM 0xBABA 1564 1565 #define NVM_MAC_ADDR_OFFSET 0 1566 /* PBA (printed board assembly) number words */ 1567 #define NVM_PBA_OFFSET_0 8 1568 #define NVM_PBA_OFFSET_1 9 1569 #define NVM_PBA_PTR_GUARD 0xFAFA 1570 #define NVM_RESERVED_WORD 0xFFFF 1571 #define NVM_PHY_CLASS_A 0x8000 1572 #define NVM_SERDES_AMPLITUDE_MASK 0x000F 1573 #define NVM_SIZE_MASK 0x1C00 1574 #define NVM_SIZE_SHIFT 10 1575 #define NVM_WORD_SIZE_BASE_SHIFT 6 1576 #define NVM_SWDPIO_EXT_SHIFT 4 1577 1578 /* NVM Commands - Microwire */ 1579 #define NVM_READ_OPCODE_MICROWIRE 0x6 /* NVM read opcode */ 1580 #define NVM_WRITE_OPCODE_MICROWIRE 0x5 /* NVM write opcode */ 1581 #define NVM_ERASE_OPCODE_MICROWIRE 0x7 /* NVM erase opcode */ 1582 #define NVM_EWEN_OPCODE_MICROWIRE 0x13 /* NVM erase/write enable */ 1583 #define NVM_EWDS_OPCODE_MICROWIRE 0x10 /* NVM erase/write disable */ 1584 1585 /* NVM Commands - SPI */ 1586 #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 1587 #define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ 1588 #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ 1589 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 1590 #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ 1591 #define NVM_WRDI_OPCODE_SPI 0x04 /* NVM reset Write Enable latch */ 1592 #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ 1593 #define NVM_WRSR_OPCODE_SPI 0x01 /* NVM write Status register */ 1594 1595 /* SPI NVM Status Register */ 1596 #define NVM_STATUS_RDY_SPI 0x01 1597 #define NVM_STATUS_WEN_SPI 0x02 1598 #define NVM_STATUS_BP0_SPI 0x04 1599 #define NVM_STATUS_BP1_SPI 0x08 1600 #define NVM_STATUS_WPEN_SPI 0x80 1601 1602 /* Word definitions for ID LED Settings */ 1603 #define ID_LED_RESERVED_0000 0x0000 1604 #define ID_LED_RESERVED_FFFF 0xFFFF 1605 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 1606 (ID_LED_OFF1_OFF2 << 8) | \ 1607 (ID_LED_DEF1_DEF2 << 4) | \ 1608 (ID_LED_DEF1_DEF2)) 1609 #define ID_LED_DEF1_DEF2 0x1 1610 #define ID_LED_DEF1_ON2 0x2 1611 #define ID_LED_DEF1_OFF2 0x3 1612 #define ID_LED_ON1_DEF2 0x4 1613 #define ID_LED_ON1_ON2 0x5 1614 #define ID_LED_ON1_OFF2 0x6 1615 #define ID_LED_OFF1_DEF2 0x7 1616 #define ID_LED_OFF1_ON2 0x8 1617 #define ID_LED_OFF1_OFF2 0x9 1618 1619 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF 1620 #define IGP_ACTIVITY_LED_ENABLE 0x0300 1621 #define IGP_LED3_MODE 0x07000000 1622 1623 /* PCI/PCI-X/PCI-EX Config space */ 1624 #define PCIX_COMMAND_REGISTER 0xE6 1625 #define PCIX_STATUS_REGISTER_LO 0xE8 1626 #define PCIX_STATUS_REGISTER_HI 0xEA 1627 #define PCI_HEADER_TYPE_REGISTER 0x0E 1628 #define PCIE_LINK_STATUS 0x12 1629 #define PCIE_DEVICE_CONTROL2 0x28 1630 1631 #define PCIX_COMMAND_MMRBC_MASK 0x000C 1632 #define PCIX_COMMAND_MMRBC_SHIFT 0x2 1633 #define PCIX_STATUS_HI_MMRBC_MASK 0x0060 1634 #define PCIX_STATUS_HI_MMRBC_SHIFT 0x5 1635 #define PCIX_STATUS_HI_MMRBC_4K 0x3 1636 #define PCIX_STATUS_HI_MMRBC_2K 0x2 1637 #define PCIX_STATUS_LO_FUNC_MASK 0x7 1638 #define PCI_HEADER_TYPE_MULTIFUNC 0x80 1639 #define PCIE_LINK_WIDTH_MASK 0x3F0 1640 #define PCIE_LINK_WIDTH_SHIFT 4 1641 #define PCIE_LINK_SPEED_MASK 0x0F 1642 #define PCIE_LINK_SPEED_2500 0x01 1643 #define PCIE_LINK_SPEED_5000 0x02 1644 #define PCIE_DEVICE_CONTROL2_16ms 0x0005 1645 1646 #ifndef ETH_ADDR_LEN 1647 #define ETH_ADDR_LEN 6 1648 #endif 1649 1650 #define PHY_REVISION_MASK 0xFFFFFFF0 1651 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 1652 #define MAX_PHY_MULTI_PAGE_REG 0xF 1653 1654 /* Bit definitions for valid PHY IDs. 1655 * I = Integrated 1656 * E = External 1657 */ 1658 #define M88E1000_E_PHY_ID 0x01410C50 1659 #define M88E1000_I_PHY_ID 0x01410C30 1660 #define M88E1011_I_PHY_ID 0x01410C20 1661 #define IGP01E1000_I_PHY_ID 0x02A80380 1662 #define M88E1011_I_REV_4 0x04 1663 #define M88E1111_I_PHY_ID 0x01410CC0 1664 #define M88E1543_E_PHY_ID 0x01410EA0 1665 #define M88E1512_E_PHY_ID 0x01410DD0 1666 #define M88E1112_E_PHY_ID 0x01410C90 1667 #define I347AT4_E_PHY_ID 0x01410DC0 1668 #define M88E1340M_E_PHY_ID 0x01410DF0 1669 #define GG82563_E_PHY_ID 0x01410CA0 1670 #define IGP03E1000_E_PHY_ID 0x02A80390 1671 #define IFE_E_PHY_ID 0x02A80330 1672 #define IFE_PLUS_E_PHY_ID 0x02A80320 1673 #define IFE_C_E_PHY_ID 0x02A80310 1674 #define BME1000_E_PHY_ID 0x01410CB0 1675 #define BME1000_E_PHY_ID_R2 0x01410CB1 1676 #define I82577_E_PHY_ID 0x01540050 1677 #define I82578_E_PHY_ID 0x004DD040 1678 #define I82579_E_PHY_ID 0x01540090 1679 #define I217_E_PHY_ID 0x015400A0 1680 #define I82580_I_PHY_ID 0x015403A0 1681 #define I350_I_PHY_ID 0x015403B0 1682 #define I210_I_PHY_ID 0x01410C00 1683 #define IGP04E1000_E_PHY_ID 0x02A80391 1684 #define M88_VENDOR 0x0141 1685 1686 /* M88E1000 Specific Registers */ 1687 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Reg */ 1688 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Reg */ 1689 #define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Reg */ 1690 #define M88E1000_INT_STATUS 0x13 /* Interrupt Status Reg */ 1691 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Cntrl */ 1692 #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ 1693 1694 #define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */ 1695 #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for pg number setting */ 1696 #define M88E1000_PHY_GEN_CONTROL 0x1E /* meaning depends on reg 29 */ 1697 #define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */ 1698 #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ 1699 1700 /* M88E1000 PHY Specific Control Register */ 1701 #define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ 1702 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reverse enabled */ 1703 #define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ 1704 /* 1=CLK125 low, 0=CLK125 toggling */ 1705 #define M88E1000_PSCR_CLK125_DISABLE 0x0010 1706 /* MDI Crossover Mode bits 6:5 Manual MDI configuration */ 1707 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 1708 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 1709 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ 1710 #define M88E1000_PSCR_AUTO_X_1000T 0x0040 1711 /* Auto crossover enabled all speeds */ 1712 #define M88E1000_PSCR_AUTO_X_MODE 0x0060 1713 /* 1714 * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold 1715 * 0=Normal 10BASE-T Rx Threshold 1716 */ 1717 #define M88E1000_PSCR_EN_10BT_EXT_DIST 0x0080 1718 /* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */ 1719 #define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100 1720 #define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */ 1721 #define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ 1722 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Tx */ 1723 1724 /* M88E1000 PHY Specific Status Register */ 1725 #define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */ 1726 #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ 1727 #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ 1728 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ 1729 /* 0 = <50M 1730 * 1 = 50-80M 1731 * 2 = 80-110M 1732 * 3 = 110-140M 1733 * 4 = >140M 1734 */ 1735 #define M88E1000_PSSR_CABLE_LENGTH 0x0380 1736 #define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ 1737 #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ 1738 #define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */ 1739 #define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ 1740 #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 1741 #define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */ 1742 #define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */ 1743 #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 1744 1745 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 1746 1747 /* M88E1000 Extended PHY Specific Control Register */ 1748 #define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */ 1749 /* 1750 * 1 = Lost lock detect enabled. 1751 * Will assert lost lock and bring 1752 * link down if idle not seen 1753 * within 1ms in 1000BASE-T 1754 */ 1755 #define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 1756 /* Number of times we will attempt to autonegotiate before downshifting if we 1757 * are the master 1758 */ 1759 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 1760 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 1761 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400 1762 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800 1763 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00 1764 /* Number of times we will attempt to autonegotiate before downshifting if we 1765 * are the slave 1766 */ 1767 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 1768 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000 1769 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 1770 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200 1771 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300 1772 #define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */ 1773 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 1774 #define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ 1775 1776 /* M88E1111 Specific Registers */ 1777 #define M88E1111_PHY_PAGE_SELECT1 0x16 /* for registers 0-28 */ 1778 #define M88E1111_PHY_PAGE_SELECT2 0x1D /* for registers 30-31 */ 1779 1780 /* M88E1111 page select register mask */ 1781 #define M88E1111_PHY_PAGE_SELECT_MASK1 0xFF 1782 #define M88E1111_PHY_PAGE_SELECT_MASK2 0x3F 1783 1784 #if !defined(NO_DH89XXCC_SUPPORT) || defined(SPRINGVILLE_HW) 1785 /* Intel I347AT4 Registers */ 1786 #define I347AT4_PCDL 0x10 /* PHY Cable Diagnostics Length */ 1787 #define I347AT4_PCDC 0x15 /* PHY Cable Diagnostics Control */ 1788 #define I347AT4_PAGE_SELECT 0x16 1789 1790 /* I347AT4 Extended PHY Specific Control Register */ 1791 1792 /* Number of times we will attempt to autonegotiate before downshifting if we 1793 * are the master 1794 */ 1795 #define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800 1796 #define I347AT4_PSCR_DOWNSHIFT_MASK 0x7000 1797 #define I347AT4_PSCR_DOWNSHIFT_1X 0x0000 1798 #define I347AT4_PSCR_DOWNSHIFT_2X 0x1000 1799 #define I347AT4_PSCR_DOWNSHIFT_3X 0x2000 1800 #define I347AT4_PSCR_DOWNSHIFT_4X 0x3000 1801 #define I347AT4_PSCR_DOWNSHIFT_5X 0x4000 1802 #define I347AT4_PSCR_DOWNSHIFT_6X 0x5000 1803 #define I347AT4_PSCR_DOWNSHIFT_7X 0x6000 1804 #define I347AT4_PSCR_DOWNSHIFT_8X 0x7000 1805 1806 /* I347AT4 PHY Cable Diagnostics Control */ 1807 #define I347AT4_PCDC_CABLE_LENGTH_UNIT 0x0400 /* 0=cm 1=meters */ 1808 1809 /* M88E1112 only registers */ 1810 #define M88E1112_VCT_DSP_DISTANCE 0x001A 1811 #endif /* !defined(NO_DH89XXCC_SUPPORT) || defined(SPRINGVILLE_HW) */ 1812 1813 /* M88EC018 Rev 2 specific DownShift settings */ 1814 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 1815 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000 1816 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200 1817 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400 1818 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600 1819 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 1820 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00 1821 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00 1822 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00 1823 1824 #define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020 1825 #define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C 1826 1827 /* BME1000 PHY Specific Control Register */ 1828 #define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */ 1829 1830 /* Bits... 1831 * 15-5: page 1832 * 4-0: register offset 1833 */ 1834 #define GG82563_PAGE_SHIFT 5 1835 #define GG82563_REG(page, reg) \ 1836 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) 1837 #define GG82563_MIN_ALT_REG 30 1838 1839 /* GG82563 Specific Registers */ 1840 #define GG82563_PHY_SPEC_CTRL GG82563_REG(0, 16) /* PHY Spec Cntrl */ 1841 #define GG82563_PHY_SPEC_STATUS GG82563_REG(0, 17) /* PHY Spec Status */ 1842 #define GG82563_PHY_INT_ENABLE GG82563_REG(0, 18) /* Interrupt Ena */ 1843 #define GG82563_PHY_SPEC_STATUS_2 GG82563_REG(0, 19) /* PHY Spec Stat2 */ 1844 #define GG82563_PHY_RX_ERR_CNTR GG82563_REG(0, 21) /* Rx Err Counter */ 1845 #define GG82563_PHY_PAGE_SELECT GG82563_REG(0, 22) /* Page Select */ 1846 #define GG82563_PHY_SPEC_CTRL_2 GG82563_REG(0, 26) /* PHY Spec Cntrl2 */ 1847 #define GG82563_PHY_PAGE_SELECT_ALT GG82563_REG(0, 29) /* Alt Page Select */ 1848 /* Test Clock Control (use reg. 29 to select) */ 1849 #define GG82563_PHY_TEST_CLK_CTRL GG82563_REG(0, 30) 1850 1851 /* MAC Specific Control Register */ 1852 #define GG82563_PHY_MAC_SPEC_CTRL GG82563_REG(2, 21) 1853 #define GG82563_PHY_MAC_SPEC_CTRL_2 GG82563_REG(2, 26) /* MAC Spec Ctrl 2 */ 1854 1855 #define GG82563_PHY_DSP_DISTANCE GG82563_REG(5, 26) /* DSP Distance */ 1856 1857 /* Page 193 - Port Control Registers */ 1858 /* Kumeran Mode Control */ 1859 #define GG82563_PHY_KMRN_MODE_CTRL GG82563_REG(193, 16) 1860 #define GG82563_PHY_PORT_RESET GG82563_REG(193, 17) /* Port Reset */ 1861 #define GG82563_PHY_REVISION_ID GG82563_REG(193, 18) /* Revision ID */ 1862 #define GG82563_PHY_DEVICE_ID GG82563_REG(193, 19) /* Device ID */ 1863 #define GG82563_PHY_PWR_MGMT_CTRL GG82563_REG(193, 20) /* Pwr Mgt Ctrl */ 1864 /* Rate Adaptation Control */ 1865 #define GG82563_PHY_RATE_ADAPT_CTRL GG82563_REG(193, 25) 1866 1867 /* Page 194 - KMRN Registers */ 1868 /* FIFO's Control/Status */ 1869 #define GG82563_PHY_KMRN_FIFO_CTRL_STAT GG82563_REG(194, 16) 1870 #define GG82563_PHY_KMRN_CTRL GG82563_REG(194, 17) /* Control */ 1871 #define GG82563_PHY_INBAND_CTRL GG82563_REG(194, 18) /* Inband Ctrl */ 1872 #define GG82563_PHY_KMRN_DIAGNOSTIC GG82563_REG(194, 19) /* Diagnostic */ 1873 #define GG82563_PHY_ACK_TIMEOUTS GG82563_REG(194, 20) /* Ack Timeouts */ 1874 #define GG82563_PHY_ADV_ABILITY GG82563_REG(194, 21) /* Adver Ability */ 1875 /* Link Partner Advertised Ability */ 1876 #define GG82563_PHY_LINK_PARTNER_ADV_ABILITY GG82563_REG(194, 23) 1877 #define GG82563_PHY_ADV_NEXT_PAGE GG82563_REG(194, 24) /* Adver Next Pg */ 1878 /* Link Partner Advertised Next page */ 1879 #define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE GG82563_REG(194, 25) 1880 #define GG82563_PHY_KMRN_MISC GG82563_REG(194, 26) /* Misc. */ 1881 1882 /* MDI Control */ 1883 #define E1000_MDIC_DATA_MASK 0x0000FFFF 1884 #define E1000_MDIC_REG_MASK 0x001F0000 1885 #define E1000_MDIC_REG_SHIFT 16 1886 #define E1000_MDIC_PHY_MASK 0x03E00000 1887 #define E1000_MDIC_PHY_SHIFT 21 1888 #define E1000_MDIC_OP_WRITE 0x04000000 1889 #define E1000_MDIC_OP_READ 0x08000000 1890 #define E1000_MDIC_READY 0x10000000 1891 #define E1000_MDIC_INT_EN 0x20000000 1892 #define E1000_MDIC_ERROR 0x40000000 1893 #define E1000_MDIC_DEST 0x80000000 1894 1895 /* SerDes Control */ 1896 #define E1000_GEN_CTL_READY 0x80000000 1897 #define E1000_GEN_CTL_ADDRESS_SHIFT 8 1898 #define E1000_GEN_POLL_TIMEOUT 640 1899 1900 /* LinkSec register fields */ 1901 #define E1000_LSECTXCAP_SUM_MASK 0x00FF0000 1902 #define E1000_LSECTXCAP_SUM_SHIFT 16 1903 #define E1000_LSECRXCAP_SUM_MASK 0x00FF0000 1904 #define E1000_LSECRXCAP_SUM_SHIFT 16 1905 1906 #define E1000_LSECTXCTRL_EN_MASK 0x00000003 1907 #define E1000_LSECTXCTRL_DISABLE 0x0 1908 #define E1000_LSECTXCTRL_AUTH 0x1 1909 #define E1000_LSECTXCTRL_AUTH_ENCRYPT 0x2 1910 #define E1000_LSECTXCTRL_AISCI 0x00000020 1911 #define E1000_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00 1912 #define E1000_LSECTXCTRL_RSV_MASK 0x000000D8 1913 1914 #define E1000_LSECRXCTRL_EN_MASK 0x0000000C 1915 #define E1000_LSECRXCTRL_EN_SHIFT 2 1916 #define E1000_LSECRXCTRL_DISABLE 0x0 1917 #define E1000_LSECRXCTRL_CHECK 0x1 1918 #define E1000_LSECRXCTRL_STRICT 0x2 1919 #define E1000_LSECRXCTRL_DROP 0x3 1920 #define E1000_LSECRXCTRL_PLSH 0x00000040 1921 #define E1000_LSECRXCTRL_RP 0x00000080 1922 #define E1000_LSECRXCTRL_RSV_MASK 0xFFFFFF33 1923 1924 /* Tx Rate-Scheduler Config fields */ 1925 #define E1000_RTTBCNRC_RS_ENA 0x80000000 1926 #define E1000_RTTBCNRC_RF_DEC_MASK 0x00003FFF 1927 #define E1000_RTTBCNRC_RF_INT_SHIFT 14 1928 #define E1000_RTTBCNRC_RF_INT_MASK \ 1929 (E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT) 1930 1931 /* DMA Coalescing register fields */ 1932 /* DMA Coalescing Watchdog Timer */ 1933 #define E1000_DMACR_DMACWT_MASK 0x00003FFF 1934 /* DMA Coalescing Rx Threshold */ 1935 #define E1000_DMACR_DMACTHR_MASK 0x00FF0000 1936 #define E1000_DMACR_DMACTHR_SHIFT 16 1937 /* Lx when no PCIe transactions */ 1938 #define E1000_DMACR_DMAC_LX_MASK 0x30000000 1939 #define E1000_DMACR_DMAC_LX_SHIFT 28 1940 #define E1000_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */ 1941 /* DMA Coalescing BMC-to-OS Watchdog Enable */ 1942 #define E1000_DMACR_DC_BMC2OSW_EN 0x00008000 1943 1944 /* DMA Coalescing Transmit Threshold */ 1945 #define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF 1946 1947 #define E1000_DMCTLX_TTLX_MASK 0x00000FFF /* Time to LX request */ 1948 1949 /* Rx Traffic Rate Threshold */ 1950 #define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF 1951 /* Rx packet rate in current window */ 1952 #define E1000_DMCRTRH_LRPRCW 0x80000000 1953 1954 /* DMA Coal Rx Traffic Current Count */ 1955 #define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF 1956 1957 /* Flow ctrl Rx Threshold High val */ 1958 #define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0 1959 #define E1000_FCRTC_RTH_COAL_SHIFT 4 1960 /* Lx power decision based on DMA coal */ 1961 #define E1000_PCIEMISC_LX_DECISION 0x00000080 1962 1963 #define E1000_RXPBS_CFG_TS_EN 0x80000000 /* Timestamp in Rx buffer */ 1964 #define E1000_RXPBS_SIZE_I210_MASK 0x0000003F /* Rx packet buffer size */ 1965 #define E1000_TXPB0S_SIZE_I210_MASK 0x0000003F /* Tx packet buffer 0 size */ 1966 #define I210_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */ 1967 #define I210_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */ 1968 1969 1970 /* Proxy Filter Control */ 1971 #define E1000_PROXYFC_D0 0x00000001 /* Enable offload in D0 */ 1972 #define E1000_PROXYFC_EX 0x00000004 /* Directed exact proxy */ 1973 #define E1000_PROXYFC_MC 0x00000008 /* Directed MC Proxy */ 1974 #define E1000_PROXYFC_BC 0x00000010 /* Broadcast Proxy Enable */ 1975 #define E1000_PROXYFC_ARP_DIRECTED 0x00000020 /* Directed ARP Proxy Ena */ 1976 #define E1000_PROXYFC_IPV4 0x00000040 /* Directed IPv4 Enable */ 1977 #define E1000_PROXYFC_IPV6 0x00000080 /* Directed IPv6 Enable */ 1978 #define E1000_PROXYFC_NS 0x00000200 /* IPv6 Neighbor Solicitation */ 1979 #define E1000_PROXYFC_ARP 0x00000800 /* ARP Request Proxy Ena */ 1980 /* Proxy Status */ 1981 #define E1000_PROXYS_CLEAR 0xFFFFFFFF /* Clear */ 1982 1983 /* Firmware Status */ 1984 #define E1000_FWSTS_FWRI 0x80000000 /* FW Reset Indication */ 1985 /* VF Control */ 1986 #define E1000_VTCTRL_RST 0x04000000 /* Reset VF */ 1987 1988 #define E1000_STATUS_LAN_ID_MASK 0x00000000C /* Mask for Lan ID field */ 1989 /* Lan ID bit field offset in status register */ 1990 #define E1000_STATUS_LAN_ID_OFFSET 2 1991 #define E1000_VFTA_ENTRIES 128 1992 #ifndef E1000_UNUSEDARG 1993 #define E1000_UNUSEDARG 1994 #endif /* E1000_UNUSEDARG */ 1995 #ifndef ERROR_REPORT 1996 #define ERROR_REPORT(fmt) do { } while (0) 1997 #endif /* ERROR_REPORT */ 1998 #endif /* _E1000_DEFINES_H_ */ 1999