1 /****************************************************************************** 2 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #ifndef _E1000_HW_H_ 36 #define _E1000_HW_H_ 37 38 #include "e1000_osdep.h" 39 #include "e1000_regs.h" 40 #include "e1000_defines.h" 41 42 struct e1000_hw; 43 44 #define E1000_DEV_ID_82542 0x1000 45 #define E1000_DEV_ID_82543GC_FIBER 0x1001 46 #define E1000_DEV_ID_82543GC_COPPER 0x1004 47 #define E1000_DEV_ID_82544EI_COPPER 0x1008 48 #define E1000_DEV_ID_82544EI_FIBER 0x1009 49 #define E1000_DEV_ID_82544GC_COPPER 0x100C 50 #define E1000_DEV_ID_82544GC_LOM 0x100D 51 #define E1000_DEV_ID_82540EM 0x100E 52 #define E1000_DEV_ID_82540EM_LOM 0x1015 53 #define E1000_DEV_ID_82540EP_LOM 0x1016 54 #define E1000_DEV_ID_82540EP 0x1017 55 #define E1000_DEV_ID_82540EP_LP 0x101E 56 #define E1000_DEV_ID_82545EM_COPPER 0x100F 57 #define E1000_DEV_ID_82545EM_FIBER 0x1011 58 #define E1000_DEV_ID_82545GM_COPPER 0x1026 59 #define E1000_DEV_ID_82545GM_FIBER 0x1027 60 #define E1000_DEV_ID_82545GM_SERDES 0x1028 61 #define E1000_DEV_ID_82546EB_COPPER 0x1010 62 #define E1000_DEV_ID_82546EB_FIBER 0x1012 63 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 64 #define E1000_DEV_ID_82546GB_COPPER 0x1079 65 #define E1000_DEV_ID_82546GB_FIBER 0x107A 66 #define E1000_DEV_ID_82546GB_SERDES 0x107B 67 #define E1000_DEV_ID_82546GB_PCIE 0x108A 68 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 69 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 70 #define E1000_DEV_ID_82541EI 0x1013 71 #define E1000_DEV_ID_82541EI_MOBILE 0x1018 72 #define E1000_DEV_ID_82541ER_LOM 0x1014 73 #define E1000_DEV_ID_82541ER 0x1078 74 #define E1000_DEV_ID_82541GI 0x1076 75 #define E1000_DEV_ID_82541GI_LF 0x107C 76 #define E1000_DEV_ID_82541GI_MOBILE 0x1077 77 #define E1000_DEV_ID_82547EI 0x1019 78 #define E1000_DEV_ID_82547EI_MOBILE 0x101A 79 #define E1000_DEV_ID_82547GI 0x1075 80 #define E1000_DEV_ID_82571EB_COPPER 0x105E 81 #define E1000_DEV_ID_82571EB_FIBER 0x105F 82 #define E1000_DEV_ID_82571EB_SERDES 0x1060 83 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 84 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 85 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 86 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 87 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 88 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 89 #define E1000_DEV_ID_82571EB_QUAD_COPPER_BP 0x10A0 90 #define E1000_DEV_ID_82572EI_COPPER 0x107D 91 #define E1000_DEV_ID_82572EI_FIBER 0x107E 92 #define E1000_DEV_ID_82572EI_SERDES 0x107F 93 #define E1000_DEV_ID_82572EI 0x10B9 94 #define E1000_DEV_ID_82573E 0x108B 95 #define E1000_DEV_ID_82573E_IAMT 0x108C 96 #define E1000_DEV_ID_82573L 0x109A 97 #define E1000_DEV_ID_82574L 0x10D3 98 #define E1000_DEV_ID_82574LA 0x10F6 99 #define E1000_DEV_ID_82583V 0x150C 100 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 101 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 102 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 103 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 104 #define E1000_DEV_ID_ICH8_82567V_3 0x1501 105 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 106 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 107 #define E1000_DEV_ID_ICH8_IGP_C 0x104B 108 #define E1000_DEV_ID_ICH8_IFE 0x104C 109 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 110 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 111 #define E1000_DEV_ID_ICH8_IGP_M 0x104D 112 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF 113 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 114 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 115 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 116 #define E1000_DEV_ID_ICH9_BM 0x10E5 117 #define E1000_DEV_ID_ICH9_IGP_C 0x294C 118 #define E1000_DEV_ID_ICH9_IFE 0x10C0 119 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 120 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 121 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 122 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 123 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 124 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 125 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 126 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525 127 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 128 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 129 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 130 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 131 #define E1000_DEV_ID_PCH2_LV_LM 0x1502 132 #define E1000_DEV_ID_PCH2_LV_V 0x1503 133 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A 134 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B 135 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A 136 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559 137 #define E1000_DEV_ID_PCH_I218_LM2 0x15A0 138 #define E1000_DEV_ID_PCH_I218_V2 0x15A1 139 #define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */ 140 #define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */ 141 #define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* Sunrise Point PCH */ 142 #define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* Sunrise Point PCH */ 143 #define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* Sunrise Point-H PCH */ 144 #define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* Sunrise Point-H PCH */ 145 #define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LEWISBURG PCH */ 146 #define E1000_DEV_ID_PCH_SPT_I219_LM4 0x15D7 147 #define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8 148 #define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3 149 #define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6 150 151 #define E1000_DEV_ID_82576 0x10C9 152 #define E1000_DEV_ID_82576_FIBER 0x10E6 153 #define E1000_DEV_ID_82576_SERDES 0x10E7 154 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 155 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526 156 #define E1000_DEV_ID_82576_NS 0x150A 157 #define E1000_DEV_ID_82576_NS_SERDES 0x1518 158 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D 159 #define E1000_DEV_ID_82576_VF 0x10CA 160 #define E1000_DEV_ID_82576_VF_HV 0x152D 161 #define E1000_DEV_ID_I350_VF 0x1520 162 #define E1000_DEV_ID_I350_VF_HV 0x152F 163 #define E1000_DEV_ID_82575EB_COPPER 0x10A7 164 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 165 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 166 #define E1000_DEV_ID_82580_COPPER 0x150E 167 #define E1000_DEV_ID_82580_FIBER 0x150F 168 #define E1000_DEV_ID_82580_SERDES 0x1510 169 #define E1000_DEV_ID_82580_SGMII 0x1511 170 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 171 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527 172 #define E1000_DEV_ID_I350_COPPER 0x1521 173 #define E1000_DEV_ID_I350_FIBER 0x1522 174 #define E1000_DEV_ID_I350_SERDES 0x1523 175 #define E1000_DEV_ID_I350_SGMII 0x1524 176 #define E1000_DEV_ID_I350_DA4 0x1546 177 #define E1000_DEV_ID_I210_COPPER 0x1533 178 #define E1000_DEV_ID_I210_COPPER_OEM1 0x1534 179 #define E1000_DEV_ID_I210_COPPER_IT 0x1535 180 #define E1000_DEV_ID_I210_FIBER 0x1536 181 #define E1000_DEV_ID_I210_SERDES 0x1537 182 #define E1000_DEV_ID_I210_SGMII 0x1538 183 #define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B 184 #define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C 185 #define E1000_DEV_ID_I211_COPPER 0x1539 186 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40 187 #define E1000_DEV_ID_I354_SGMII 0x1F41 188 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45 189 #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438 190 #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A 191 #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C 192 #define E1000_DEV_ID_DH89XXCC_SFP 0x0440 193 194 #define E1000_REVISION_0 0 195 #define E1000_REVISION_1 1 196 #define E1000_REVISION_2 2 197 #define E1000_REVISION_3 3 198 #define E1000_REVISION_4 4 199 200 #define E1000_FUNC_0 0 201 #define E1000_FUNC_1 1 202 #define E1000_FUNC_2 2 203 #define E1000_FUNC_3 3 204 205 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 206 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 207 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6 208 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9 209 210 enum e1000_mac_type { 211 e1000_undefined = 0, 212 e1000_82542, 213 e1000_82543, 214 e1000_82544, 215 e1000_82540, 216 e1000_82545, 217 e1000_82545_rev_3, 218 e1000_82546, 219 e1000_82546_rev_3, 220 e1000_82541, 221 e1000_82541_rev_2, 222 e1000_82547, 223 e1000_82547_rev_2, 224 e1000_82571, 225 e1000_82572, 226 e1000_82573, 227 e1000_82574, 228 e1000_82583, 229 e1000_80003es2lan, 230 e1000_ich8lan, 231 e1000_ich9lan, 232 e1000_ich10lan, 233 e1000_pchlan, 234 e1000_pch2lan, 235 e1000_pch_lpt, 236 e1000_pch_spt, 237 e1000_82575, 238 e1000_82576, 239 e1000_82580, 240 e1000_i350, 241 e1000_i354, 242 e1000_i210, 243 e1000_i211, 244 e1000_vfadapt, 245 e1000_vfadapt_i350, 246 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ 247 }; 248 249 enum e1000_media_type { 250 e1000_media_type_unknown = 0, 251 e1000_media_type_copper = 1, 252 e1000_media_type_fiber = 2, 253 e1000_media_type_internal_serdes = 3, 254 e1000_num_media_types 255 }; 256 257 enum e1000_nvm_type { 258 e1000_nvm_unknown = 0, 259 e1000_nvm_none, 260 e1000_nvm_eeprom_spi, 261 e1000_nvm_eeprom_microwire, 262 e1000_nvm_flash_hw, 263 e1000_nvm_invm, 264 e1000_nvm_flash_sw 265 }; 266 267 enum e1000_nvm_override { 268 e1000_nvm_override_none = 0, 269 e1000_nvm_override_spi_small, 270 e1000_nvm_override_spi_large, 271 e1000_nvm_override_microwire_small, 272 e1000_nvm_override_microwire_large 273 }; 274 275 enum e1000_phy_type { 276 e1000_phy_unknown = 0, 277 e1000_phy_none, 278 e1000_phy_m88, 279 e1000_phy_igp, 280 e1000_phy_igp_2, 281 e1000_phy_gg82563, 282 e1000_phy_igp_3, 283 e1000_phy_ife, 284 e1000_phy_bm, 285 e1000_phy_82578, 286 e1000_phy_82577, 287 e1000_phy_82579, 288 e1000_phy_i217, 289 e1000_phy_82580, 290 e1000_phy_vf, 291 e1000_phy_i210, 292 }; 293 294 enum e1000_bus_type { 295 e1000_bus_type_unknown = 0, 296 e1000_bus_type_pci, 297 e1000_bus_type_pcix, 298 e1000_bus_type_pci_express, 299 e1000_bus_type_reserved 300 }; 301 302 enum e1000_bus_speed { 303 e1000_bus_speed_unknown = 0, 304 e1000_bus_speed_33, 305 e1000_bus_speed_66, 306 e1000_bus_speed_100, 307 e1000_bus_speed_120, 308 e1000_bus_speed_133, 309 e1000_bus_speed_2500, 310 e1000_bus_speed_5000, 311 e1000_bus_speed_reserved 312 }; 313 314 enum e1000_bus_width { 315 e1000_bus_width_unknown = 0, 316 e1000_bus_width_pcie_x1, 317 e1000_bus_width_pcie_x2, 318 e1000_bus_width_pcie_x4 = 4, 319 e1000_bus_width_pcie_x8 = 8, 320 e1000_bus_width_32, 321 e1000_bus_width_64, 322 e1000_bus_width_reserved 323 }; 324 325 enum e1000_1000t_rx_status { 326 e1000_1000t_rx_status_not_ok = 0, 327 e1000_1000t_rx_status_ok, 328 e1000_1000t_rx_status_undefined = 0xFF 329 }; 330 331 enum e1000_rev_polarity { 332 e1000_rev_polarity_normal = 0, 333 e1000_rev_polarity_reversed, 334 e1000_rev_polarity_undefined = 0xFF 335 }; 336 337 enum e1000_fc_mode { 338 e1000_fc_none = 0, 339 e1000_fc_rx_pause, 340 e1000_fc_tx_pause, 341 e1000_fc_full, 342 e1000_fc_default = 0xFF 343 }; 344 345 enum e1000_ffe_config { 346 e1000_ffe_config_enabled = 0, 347 e1000_ffe_config_active, 348 e1000_ffe_config_blocked 349 }; 350 351 enum e1000_dsp_config { 352 e1000_dsp_config_disabled = 0, 353 e1000_dsp_config_enabled, 354 e1000_dsp_config_activated, 355 e1000_dsp_config_undefined = 0xFF 356 }; 357 358 enum e1000_ms_type { 359 e1000_ms_hw_default = 0, 360 e1000_ms_force_master, 361 e1000_ms_force_slave, 362 e1000_ms_auto 363 }; 364 365 enum e1000_smart_speed { 366 e1000_smart_speed_default = 0, 367 e1000_smart_speed_on, 368 e1000_smart_speed_off 369 }; 370 371 enum e1000_serdes_link_state { 372 e1000_serdes_link_down = 0, 373 e1000_serdes_link_autoneg_progress, 374 e1000_serdes_link_autoneg_complete, 375 e1000_serdes_link_forced_up 376 }; 377 378 #define __le16 u16 379 #define __le32 u32 380 #define __le64 u64 381 /* Receive Descriptor */ 382 struct e1000_rx_desc { 383 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 384 __le16 length; /* Length of data DMAed into data buffer */ 385 __le16 csum; /* Packet checksum */ 386 u8 status; /* Descriptor status */ 387 u8 errors; /* Descriptor Errors */ 388 __le16 special; 389 }; 390 391 /* Receive Descriptor - Extended */ 392 union e1000_rx_desc_extended { 393 struct { 394 __le64 buffer_addr; 395 __le64 reserved; 396 } read; 397 struct { 398 struct { 399 __le32 mrq; /* Multiple Rx Queues */ 400 union { 401 __le32 rss; /* RSS Hash */ 402 struct { 403 __le16 ip_id; /* IP id */ 404 __le16 csum; /* Packet Checksum */ 405 } csum_ip; 406 } hi_dword; 407 } lower; 408 struct { 409 __le32 status_error; /* ext status/error */ 410 __le16 length; 411 __le16 vlan; /* VLAN tag */ 412 } upper; 413 } wb; /* writeback */ 414 }; 415 416 #define MAX_PS_BUFFERS 4 417 418 /* Number of packet split data buffers (not including the header buffer) */ 419 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) 420 421 /* Receive Descriptor - Packet Split */ 422 union e1000_rx_desc_packet_split { 423 struct { 424 /* one buffer for protocol header(s), three data buffers */ 425 __le64 buffer_addr[MAX_PS_BUFFERS]; 426 } read; 427 struct { 428 struct { 429 __le32 mrq; /* Multiple Rx Queues */ 430 union { 431 __le32 rss; /* RSS Hash */ 432 struct { 433 __le16 ip_id; /* IP id */ 434 __le16 csum; /* Packet Checksum */ 435 } csum_ip; 436 } hi_dword; 437 } lower; 438 struct { 439 __le32 status_error; /* ext status/error */ 440 __le16 length0; /* length of buffer 0 */ 441 __le16 vlan; /* VLAN tag */ 442 } middle; 443 struct { 444 __le16 header_status; 445 /* length of buffers 1-3 */ 446 __le16 length[PS_PAGE_BUFFERS]; 447 } upper; 448 __le64 reserved; 449 } wb; /* writeback */ 450 }; 451 452 /* Transmit Descriptor */ 453 struct e1000_tx_desc { 454 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 455 union { 456 __le32 data; 457 struct { 458 __le16 length; /* Data buffer length */ 459 u8 cso; /* Checksum offset */ 460 u8 cmd; /* Descriptor control */ 461 } flags; 462 } lower; 463 union { 464 __le32 data; 465 struct { 466 u8 status; /* Descriptor status */ 467 u8 css; /* Checksum start */ 468 __le16 special; 469 } fields; 470 } upper; 471 }; 472 473 /* Offload Context Descriptor */ 474 struct e1000_context_desc { 475 union { 476 __le32 ip_config; 477 struct { 478 u8 ipcss; /* IP checksum start */ 479 u8 ipcso; /* IP checksum offset */ 480 __le16 ipcse; /* IP checksum end */ 481 } ip_fields; 482 } lower_setup; 483 union { 484 __le32 tcp_config; 485 struct { 486 u8 tucss; /* TCP checksum start */ 487 u8 tucso; /* TCP checksum offset */ 488 __le16 tucse; /* TCP checksum end */ 489 } tcp_fields; 490 } upper_setup; 491 __le32 cmd_and_length; 492 union { 493 __le32 data; 494 struct { 495 u8 status; /* Descriptor status */ 496 u8 hdr_len; /* Header length */ 497 __le16 mss; /* Maximum segment size */ 498 } fields; 499 } tcp_seg_setup; 500 }; 501 502 /* Offload data descriptor */ 503 struct e1000_data_desc { 504 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 505 union { 506 __le32 data; 507 struct { 508 __le16 length; /* Data buffer length */ 509 u8 typ_len_ext; 510 u8 cmd; 511 } flags; 512 } lower; 513 union { 514 __le32 data; 515 struct { 516 u8 status; /* Descriptor status */ 517 u8 popts; /* Packet Options */ 518 __le16 special; 519 } fields; 520 } upper; 521 }; 522 523 /* Statistics counters collected by the MAC */ 524 struct e1000_hw_stats { 525 u64 crcerrs; 526 u64 algnerrc; 527 u64 symerrs; 528 u64 rxerrc; 529 u64 mpc; 530 u64 scc; 531 u64 ecol; 532 u64 mcc; 533 u64 latecol; 534 u64 colc; 535 u64 dc; 536 u64 tncrs; 537 u64 sec; 538 u64 cexterr; 539 u64 rlec; 540 u64 xonrxc; 541 u64 xontxc; 542 u64 xoffrxc; 543 u64 xofftxc; 544 u64 fcruc; 545 u64 prc64; 546 u64 prc127; 547 u64 prc255; 548 u64 prc511; 549 u64 prc1023; 550 u64 prc1522; 551 u64 gprc; 552 u64 bprc; 553 u64 mprc; 554 u64 gptc; 555 u64 gorc; 556 u64 gotc; 557 u64 rnbc; 558 u64 ruc; 559 u64 rfc; 560 u64 roc; 561 u64 rjc; 562 u64 mgprc; 563 u64 mgpdc; 564 u64 mgptc; 565 u64 tor; 566 u64 tot; 567 u64 tpr; 568 u64 tpt; 569 u64 ptc64; 570 u64 ptc127; 571 u64 ptc255; 572 u64 ptc511; 573 u64 ptc1023; 574 u64 ptc1522; 575 u64 mptc; 576 u64 bptc; 577 u64 tsctc; 578 u64 tsctfc; 579 u64 iac; 580 u64 icrxptc; 581 u64 icrxatc; 582 u64 ictxptc; 583 u64 ictxatc; 584 u64 ictxqec; 585 u64 ictxqmtc; 586 u64 icrxdmtc; 587 u64 icrxoc; 588 u64 cbtmpc; 589 u64 htdpmc; 590 u64 cbrdpc; 591 u64 cbrmpc; 592 u64 rpthc; 593 u64 hgptc; 594 u64 htcbdpc; 595 u64 hgorc; 596 u64 hgotc; 597 u64 lenerrs; 598 u64 scvpc; 599 u64 hrmpc; 600 u64 doosync; 601 u64 o2bgptc; 602 u64 o2bspc; 603 u64 b2ospc; 604 u64 b2ogprc; 605 }; 606 607 struct e1000_vf_stats { 608 u64 base_gprc; 609 u64 base_gptc; 610 u64 base_gorc; 611 u64 base_gotc; 612 u64 base_mprc; 613 u64 base_gotlbc; 614 u64 base_gptlbc; 615 u64 base_gorlbc; 616 u64 base_gprlbc; 617 618 u32 last_gprc; 619 u32 last_gptc; 620 u32 last_gorc; 621 u32 last_gotc; 622 u32 last_mprc; 623 u32 last_gotlbc; 624 u32 last_gptlbc; 625 u32 last_gorlbc; 626 u32 last_gprlbc; 627 628 u64 gprc; 629 u64 gptc; 630 u64 gorc; 631 u64 gotc; 632 u64 mprc; 633 u64 gotlbc; 634 u64 gptlbc; 635 u64 gorlbc; 636 u64 gprlbc; 637 }; 638 639 struct e1000_phy_stats { 640 u32 idle_errors; 641 u32 receive_errors; 642 }; 643 644 struct e1000_host_mng_dhcp_cookie { 645 u32 signature; 646 u8 status; 647 u8 reserved0; 648 u16 vlan_id; 649 u32 reserved1; 650 u16 reserved2; 651 u8 reserved3; 652 u8 checksum; 653 }; 654 655 /* Host Interface "Rev 1" */ 656 struct e1000_host_command_header { 657 u8 command_id; 658 u8 command_length; 659 u8 command_options; 660 u8 checksum; 661 }; 662 663 #define E1000_HI_MAX_DATA_LENGTH 252 664 struct e1000_host_command_info { 665 struct e1000_host_command_header command_header; 666 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 667 }; 668 669 /* Host Interface "Rev 2" */ 670 struct e1000_host_mng_command_header { 671 u8 command_id; 672 u8 checksum; 673 u16 reserved1; 674 u16 reserved2; 675 u16 command_length; 676 }; 677 678 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 679 struct e1000_host_mng_command_info { 680 struct e1000_host_mng_command_header command_header; 681 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 682 }; 683 684 #include "e1000_mac.h" 685 #include "e1000_phy.h" 686 #include "e1000_nvm.h" 687 #include "e1000_manage.h" 688 #include "e1000_mbx.h" 689 690 /* Function pointers for the MAC. */ 691 struct e1000_mac_operations { 692 s32 (*init_params)(struct e1000_hw *); 693 s32 (*id_led_init)(struct e1000_hw *); 694 s32 (*blink_led)(struct e1000_hw *); 695 bool (*check_mng_mode)(struct e1000_hw *); 696 s32 (*check_for_link)(struct e1000_hw *); 697 s32 (*cleanup_led)(struct e1000_hw *); 698 void (*clear_hw_cntrs)(struct e1000_hw *); 699 void (*clear_vfta)(struct e1000_hw *); 700 s32 (*get_bus_info)(struct e1000_hw *); 701 void (*set_lan_id)(struct e1000_hw *); 702 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 703 s32 (*led_on)(struct e1000_hw *); 704 s32 (*led_off)(struct e1000_hw *); 705 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 706 s32 (*reset_hw)(struct e1000_hw *); 707 s32 (*init_hw)(struct e1000_hw *); 708 void (*shutdown_serdes)(struct e1000_hw *); 709 void (*power_up_serdes)(struct e1000_hw *); 710 s32 (*setup_link)(struct e1000_hw *); 711 s32 (*setup_physical_interface)(struct e1000_hw *); 712 s32 (*setup_led)(struct e1000_hw *); 713 void (*write_vfta)(struct e1000_hw *, u32, u32); 714 void (*config_collision_dist)(struct e1000_hw *); 715 int (*rar_set)(struct e1000_hw *, u8*, u32); 716 s32 (*read_mac_addr)(struct e1000_hw *); 717 s32 (*validate_mdi_setting)(struct e1000_hw *); 718 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16); 719 void (*release_swfw_sync)(struct e1000_hw *, u16); 720 s32 (*set_obff_timer)(struct e1000_hw *, u32); 721 }; 722 723 /* When to use various PHY register access functions: 724 * 725 * Func Caller 726 * Function Does Does When to use 727 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 728 * X_reg L,P,A n/a for simple PHY reg accesses 729 * X_reg_locked P,A L for multiple accesses of different regs 730 * on different pages 731 * X_reg_page A L,P for multiple accesses of different regs 732 * on the same page 733 * 734 * Where X=[read|write], L=locking, P=sets page, A=register access 735 * 736 */ 737 struct e1000_phy_operations { 738 s32 (*init_params)(struct e1000_hw *); 739 s32 (*acquire)(struct e1000_hw *); 740 s32 (*cfg_on_link_up)(struct e1000_hw *); 741 s32 (*check_polarity)(struct e1000_hw *); 742 s32 (*check_reset_block)(struct e1000_hw *); 743 s32 (*commit)(struct e1000_hw *); 744 s32 (*force_speed_duplex)(struct e1000_hw *); 745 s32 (*get_cfg_done)(struct e1000_hw *hw); 746 s32 (*get_cable_length)(struct e1000_hw *); 747 s32 (*get_info)(struct e1000_hw *); 748 s32 (*set_page)(struct e1000_hw *, u16); 749 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 750 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 751 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *); 752 void (*release)(struct e1000_hw *); 753 s32 (*reset)(struct e1000_hw *); 754 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 755 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 756 s32 (*write_reg)(struct e1000_hw *, u32, u16); 757 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 758 s32 (*write_reg_page)(struct e1000_hw *, u32, u16); 759 void (*power_up)(struct e1000_hw *); 760 void (*power_down)(struct e1000_hw *); 761 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *); 762 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8); 763 }; 764 765 /* Function pointers for the NVM. */ 766 struct e1000_nvm_operations { 767 s32 (*init_params)(struct e1000_hw *); 768 s32 (*acquire)(struct e1000_hw *); 769 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 770 void (*release)(struct e1000_hw *); 771 void (*reload)(struct e1000_hw *); 772 s32 (*update)(struct e1000_hw *); 773 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 774 s32 (*validate)(struct e1000_hw *); 775 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 776 }; 777 778 struct e1000_mac_info { 779 struct e1000_mac_operations ops; 780 u8 addr[ETH_ADDR_LEN]; 781 u8 perm_addr[ETH_ADDR_LEN]; 782 783 enum e1000_mac_type type; 784 785 u32 collision_delta; 786 u32 ledctl_default; 787 u32 ledctl_mode1; 788 u32 ledctl_mode2; 789 u32 mc_filter_type; 790 u32 tx_packet_delta; 791 u32 txcw; 792 793 u16 current_ifs_val; 794 u16 ifs_max_val; 795 u16 ifs_min_val; 796 u16 ifs_ratio; 797 u16 ifs_step_size; 798 u16 mta_reg_count; 799 u16 uta_reg_count; 800 801 /* Maximum size of the MTA register table in all supported adapters */ 802 #define MAX_MTA_REG 128 803 u32 mta_shadow[MAX_MTA_REG]; 804 u16 rar_entry_count; 805 806 u8 forced_speed_duplex; 807 808 bool adaptive_ifs; 809 bool has_fwsm; 810 bool arc_subsystem_valid; 811 bool asf_firmware_present; 812 bool autoneg; 813 bool autoneg_failed; 814 bool get_link_status; 815 bool in_ifs_mode; 816 bool report_tx_early; 817 enum e1000_serdes_link_state serdes_link_state; 818 bool serdes_has_link; 819 bool tx_pkt_filtering; 820 u32 max_frame_size; 821 }; 822 823 struct e1000_phy_info { 824 struct e1000_phy_operations ops; 825 enum e1000_phy_type type; 826 827 enum e1000_1000t_rx_status local_rx; 828 enum e1000_1000t_rx_status remote_rx; 829 enum e1000_ms_type ms_type; 830 enum e1000_ms_type original_ms_type; 831 enum e1000_rev_polarity cable_polarity; 832 enum e1000_smart_speed smart_speed; 833 834 u32 addr; 835 u32 id; 836 u32 reset_delay_us; /* in usec */ 837 u32 revision; 838 839 enum e1000_media_type media_type; 840 841 u16 autoneg_advertised; 842 u16 autoneg_mask; 843 u16 cable_length; 844 u16 max_cable_length; 845 u16 min_cable_length; 846 847 u8 mdix; 848 849 bool disable_polarity_correction; 850 bool is_mdix; 851 bool polarity_correction; 852 bool speed_downgraded; 853 bool autoneg_wait_to_complete; 854 }; 855 856 struct e1000_nvm_info { 857 struct e1000_nvm_operations ops; 858 enum e1000_nvm_type type; 859 enum e1000_nvm_override override; 860 861 u32 flash_bank_size; 862 u32 flash_base_addr; 863 864 u16 word_size; 865 u16 delay_usec; 866 u16 address_bits; 867 u16 opcode_bits; 868 u16 page_size; 869 }; 870 871 struct e1000_bus_info { 872 enum e1000_bus_type type; 873 enum e1000_bus_speed speed; 874 enum e1000_bus_width width; 875 876 u16 func; 877 u16 pci_cmd_word; 878 }; 879 880 struct e1000_fc_info { 881 u32 high_water; /* Flow control high-water mark */ 882 u32 low_water; /* Flow control low-water mark */ 883 u16 pause_time; /* Flow control pause timer */ 884 u16 refresh_time; /* Flow control refresh timer */ 885 bool send_xon; /* Flow control send XON */ 886 bool strict_ieee; /* Strict IEEE mode */ 887 enum e1000_fc_mode current_mode; /* FC mode in effect */ 888 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 889 }; 890 891 struct e1000_dev_spec_82541 { 892 enum e1000_dsp_config dsp_config; 893 enum e1000_ffe_config ffe_config; 894 u16 spd_default; 895 bool phy_init_script; 896 }; 897 898 struct e1000_dev_spec_82542 { 899 bool dma_fairness; 900 }; 901 902 struct e1000_dev_spec_82543 { 903 u32 tbi_compatibility; 904 bool dma_fairness; 905 bool init_phy_disabled; 906 }; 907 908 struct e1000_dev_spec_82571 { 909 bool laa_is_present; 910 u32 smb_counter; 911 }; 912 913 struct e1000_dev_spec_80003es2lan { 914 bool mdic_wa_enable; 915 }; 916 917 struct e1000_shadow_ram { 918 u16 value; 919 bool modified; 920 }; 921 922 struct e1000_mbx_operations { 923 s32 (*init_params)(struct e1000_hw *hw); 924 s32 (*read)(struct e1000_hw *, u32 *, u16, u16); 925 s32 (*write)(struct e1000_hw *, u32 *, u16, u16); 926 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16); 927 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16); 928 s32 (*check_for_msg)(struct e1000_hw *, u16); 929 s32 (*check_for_ack)(struct e1000_hw *, u16); 930 s32 (*check_for_rst)(struct e1000_hw *, u16); 931 }; 932 933 struct e1000_mbx_stats { 934 u32 msgs_tx; 935 u32 msgs_rx; 936 937 u32 acks; 938 u32 reqs; 939 u32 rsts; 940 }; 941 942 struct e1000_mbx_info { 943 struct e1000_mbx_operations ops; 944 struct e1000_mbx_stats stats; 945 u32 timeout; 946 u32 usec_delay; 947 u16 size; 948 }; 949 950 struct e1000_dev_spec_82575 { 951 bool sgmii_active; 952 bool global_device_reset; 953 bool eee_disable; 954 bool module_plugged; 955 bool clear_semaphore_once; 956 u32 mtu; 957 struct sfp_e1000_flags eth_flags; 958 u8 media_port; 959 bool media_changed; 960 }; 961 962 #define E1000_SHADOW_RAM_WORDS 2048 963 964 /* I218 PHY Ultra Low Power (ULP) states */ 965 enum e1000_ulp_state { 966 e1000_ulp_state_unknown, 967 e1000_ulp_state_off, 968 e1000_ulp_state_on, 969 }; 970 971 struct e1000_dev_spec_ich8lan { 972 bool kmrn_lock_loss_workaround_enabled; 973 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; 974 bool nvm_k1_enabled; 975 bool eee_disable; 976 u16 eee_lp_ability; 977 enum e1000_ulp_state ulp_state; 978 }; 979 980 struct e1000_dev_spec_vf { 981 u32 vf_number; 982 u32 v2p_mailbox; 983 }; 984 985 struct e1000_hw { 986 void *back; 987 988 u8 *hw_addr; 989 u8 *flash_address; 990 unsigned long io_base; 991 992 struct e1000_mac_info mac; 993 struct e1000_fc_info fc; 994 struct e1000_phy_info phy; 995 struct e1000_nvm_info nvm; 996 struct e1000_bus_info bus; 997 struct e1000_mbx_info mbx; 998 struct e1000_host_mng_dhcp_cookie mng_cookie; 999 1000 union { 1001 struct e1000_dev_spec_82541 _82541; 1002 struct e1000_dev_spec_82542 _82542; 1003 struct e1000_dev_spec_82543 _82543; 1004 struct e1000_dev_spec_82571 _82571; 1005 struct e1000_dev_spec_80003es2lan _80003es2lan; 1006 struct e1000_dev_spec_ich8lan ich8lan; 1007 struct e1000_dev_spec_82575 _82575; 1008 struct e1000_dev_spec_vf vf; 1009 } dev_spec; 1010 1011 u16 device_id; 1012 u16 subsystem_vendor_id; 1013 u16 subsystem_device_id; 1014 u16 vendor_id; 1015 1016 u8 revision_id; 1017 }; 1018 1019 #include "e1000_82541.h" 1020 #include "e1000_82543.h" 1021 #include "e1000_82571.h" 1022 #include "e1000_80003es2lan.h" 1023 #include "e1000_ich8lan.h" 1024 #include "e1000_82575.h" 1025 #include "e1000_i210.h" 1026 1027 /* These functions must be implemented by drivers */ 1028 void e1000_pci_clear_mwi(struct e1000_hw *hw); 1029 void e1000_pci_set_mwi(struct e1000_hw *hw); 1030 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1031 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1032 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1033 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1034 1035 #endif 1036