1 /****************************************************************************** 2 3 Copyright (c) 2001-2012, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD:$*/ 34 35 #ifndef _E1000_HW_H_ 36 #define _E1000_HW_H_ 37 38 #include "e1000_osdep.h" 39 #include "e1000_regs.h" 40 #include "e1000_defines.h" 41 42 struct e1000_hw; 43 44 #ifndef NO_82542_SUPPORT 45 #define E1000_DEV_ID_82542 0x1000 46 #endif 47 #define E1000_DEV_ID_82543GC_FIBER 0x1001 48 #define E1000_DEV_ID_82543GC_COPPER 0x1004 49 #define E1000_DEV_ID_82544EI_COPPER 0x1008 50 #define E1000_DEV_ID_82544EI_FIBER 0x1009 51 #define E1000_DEV_ID_82544GC_COPPER 0x100C 52 #define E1000_DEV_ID_82544GC_LOM 0x100D 53 #define E1000_DEV_ID_82540EM 0x100E 54 #define E1000_DEV_ID_82540EM_LOM 0x1015 55 #define E1000_DEV_ID_82540EP_LOM 0x1016 56 #define E1000_DEV_ID_82540EP 0x1017 57 #define E1000_DEV_ID_82540EP_LP 0x101E 58 #define E1000_DEV_ID_82545EM_COPPER 0x100F 59 #define E1000_DEV_ID_82545EM_FIBER 0x1011 60 #define E1000_DEV_ID_82545GM_COPPER 0x1026 61 #define E1000_DEV_ID_82545GM_FIBER 0x1027 62 #define E1000_DEV_ID_82545GM_SERDES 0x1028 63 #define E1000_DEV_ID_82546EB_COPPER 0x1010 64 #define E1000_DEV_ID_82546EB_FIBER 0x1012 65 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 66 #define E1000_DEV_ID_82546GB_COPPER 0x1079 67 #define E1000_DEV_ID_82546GB_FIBER 0x107A 68 #define E1000_DEV_ID_82546GB_SERDES 0x107B 69 #define E1000_DEV_ID_82546GB_PCIE 0x108A 70 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 71 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 72 #define E1000_DEV_ID_82541EI 0x1013 73 #define E1000_DEV_ID_82541EI_MOBILE 0x1018 74 #define E1000_DEV_ID_82541ER_LOM 0x1014 75 #define E1000_DEV_ID_82541ER 0x1078 76 #define E1000_DEV_ID_82541GI 0x1076 77 #define E1000_DEV_ID_82541GI_LF 0x107C 78 #define E1000_DEV_ID_82541GI_MOBILE 0x1077 79 #define E1000_DEV_ID_82547EI 0x1019 80 #define E1000_DEV_ID_82547EI_MOBILE 0x101A 81 #define E1000_DEV_ID_82547GI 0x1075 82 #define E1000_DEV_ID_82571EB_COPPER 0x105E 83 #define E1000_DEV_ID_82571EB_FIBER 0x105F 84 #define E1000_DEV_ID_82571EB_SERDES 0x1060 85 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 86 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 87 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 88 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 89 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 90 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 91 #define E1000_DEV_ID_82571EB_QUAD_COPPER_BP 0x10A0 92 #define E1000_DEV_ID_82572EI_COPPER 0x107D 93 #define E1000_DEV_ID_82572EI_FIBER 0x107E 94 #define E1000_DEV_ID_82572EI_SERDES 0x107F 95 #define E1000_DEV_ID_82572EI 0x10B9 96 #define E1000_DEV_ID_82573E 0x108B 97 #define E1000_DEV_ID_82573E_IAMT 0x108C 98 #define E1000_DEV_ID_82573L 0x109A 99 #define E1000_DEV_ID_82574L 0x10D3 100 #define E1000_DEV_ID_82574LA 0x10F6 101 #define E1000_DEV_ID_82583V 0x150C 102 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 103 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 104 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 105 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 106 #define E1000_DEV_ID_ICH8_82567V_3 0x1501 107 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 108 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 109 #define E1000_DEV_ID_ICH8_IGP_C 0x104B 110 #define E1000_DEV_ID_ICH8_IFE 0x104C 111 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 112 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 113 #define E1000_DEV_ID_ICH8_IGP_M 0x104D 114 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF 115 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 116 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 117 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 118 #define E1000_DEV_ID_ICH9_BM 0x10E5 119 #define E1000_DEV_ID_ICH9_IGP_C 0x294C 120 #define E1000_DEV_ID_ICH9_IFE 0x10C0 121 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 122 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 123 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 124 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 125 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 126 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 127 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 128 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525 129 130 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 131 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 132 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 133 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 134 #define E1000_DEV_ID_PCH2_LV_LM 0x1502 135 #define E1000_DEV_ID_PCH2_LV_V 0x1503 136 137 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A 138 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B 139 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A 140 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559 141 142 #define E1000_DEV_ID_82576 0x10C9 143 #define E1000_DEV_ID_82576_FIBER 0x10E6 144 #define E1000_DEV_ID_82576_SERDES 0x10E7 145 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 146 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526 147 #define E1000_DEV_ID_82576_NS 0x150A 148 #define E1000_DEV_ID_82576_NS_SERDES 0x1518 149 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D 150 #define E1000_DEV_ID_82576_VF 0x10CA 151 #define E1000_DEV_ID_82576_VF_HV 0x152D 152 #define E1000_DEV_ID_I350_VF 0x1520 153 #define E1000_DEV_ID_I350_VF_HV 0x152F 154 #define E1000_DEV_ID_82575EB_COPPER 0x10A7 155 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 156 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 157 #define E1000_DEV_ID_82580_COPPER 0x150E 158 #define E1000_DEV_ID_82580_FIBER 0x150F 159 #define E1000_DEV_ID_82580_SERDES 0x1510 160 #define E1000_DEV_ID_82580_SGMII 0x1511 161 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 162 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527 163 #define E1000_DEV_ID_I350_COPPER 0x1521 164 #define E1000_DEV_ID_I350_FIBER 0x1522 165 #define E1000_DEV_ID_I350_SERDES 0x1523 166 #define E1000_DEV_ID_I350_SGMII 0x1524 167 #define E1000_DEV_ID_I350_DA4 0x1546 168 #define E1000_DEV_ID_I210_COPPER 0x1533 169 #define E1000_DEV_ID_I210_COPPER_OEM1 0x1534 170 #define E1000_DEV_ID_I210_COPPER_IT 0x1535 171 #define E1000_DEV_ID_I210_FIBER 0x1536 172 #define E1000_DEV_ID_I210_SERDES 0x1537 173 #define E1000_DEV_ID_I210_SGMII 0x1538 174 #define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B 175 #define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C 176 #define E1000_DEV_ID_I211_COPPER 0x1539 177 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40 178 #define E1000_DEV_ID_I354_SGMII 0x1F41 179 #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438 180 #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A 181 #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C 182 #define E1000_DEV_ID_DH89XXCC_SFP 0x0440 183 184 #define E1000_REVISION_0 0 185 #define E1000_REVISION_1 1 186 #define E1000_REVISION_2 2 187 #define E1000_REVISION_3 3 188 #define E1000_REVISION_4 4 189 190 #define E1000_FUNC_0 0 191 #define E1000_FUNC_1 1 192 #define E1000_FUNC_2 2 193 #define E1000_FUNC_3 3 194 195 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 196 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 197 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6 198 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9 199 200 enum e1000_mac_type { 201 e1000_undefined = 0, 202 #ifndef NO_82542_SUPPORT 203 e1000_82542, 204 #endif 205 e1000_82543, 206 e1000_82544, 207 e1000_82540, 208 e1000_82545, 209 e1000_82545_rev_3, 210 e1000_82546, 211 e1000_82546_rev_3, 212 e1000_82541, 213 e1000_82541_rev_2, 214 e1000_82547, 215 e1000_82547_rev_2, 216 e1000_82571, 217 e1000_82572, 218 e1000_82573, 219 e1000_82574, 220 e1000_82583, 221 e1000_80003es2lan, 222 e1000_ich8lan, 223 e1000_ich9lan, 224 e1000_ich10lan, 225 e1000_pchlan, 226 e1000_pch2lan, 227 e1000_pch_lpt, 228 e1000_82575, 229 e1000_82576, 230 e1000_82580, 231 e1000_i350, 232 e1000_i354, 233 e1000_i210, 234 e1000_i211, 235 e1000_vfadapt, 236 e1000_vfadapt_i350, 237 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ 238 }; 239 240 enum e1000_media_type { 241 e1000_media_type_unknown = 0, 242 e1000_media_type_copper = 1, 243 e1000_media_type_fiber = 2, 244 e1000_media_type_internal_serdes = 3, 245 e1000_num_media_types 246 }; 247 248 enum e1000_nvm_type { 249 e1000_nvm_unknown = 0, 250 e1000_nvm_none, 251 e1000_nvm_eeprom_spi, 252 e1000_nvm_eeprom_microwire, 253 e1000_nvm_flash_hw, 254 e1000_nvm_invm, 255 e1000_nvm_flash_sw 256 }; 257 258 enum e1000_nvm_override { 259 e1000_nvm_override_none = 0, 260 e1000_nvm_override_spi_small, 261 e1000_nvm_override_spi_large, 262 e1000_nvm_override_microwire_small, 263 e1000_nvm_override_microwire_large 264 }; 265 266 enum e1000_phy_type { 267 e1000_phy_unknown = 0, 268 e1000_phy_none, 269 e1000_phy_m88, 270 e1000_phy_igp, 271 e1000_phy_igp_2, 272 e1000_phy_gg82563, 273 e1000_phy_igp_3, 274 e1000_phy_ife, 275 e1000_phy_bm, 276 e1000_phy_82578, 277 e1000_phy_82577, 278 e1000_phy_82579, 279 e1000_phy_i217, 280 e1000_phy_82580, 281 e1000_phy_vf, 282 e1000_phy_i210, 283 }; 284 285 enum e1000_bus_type { 286 e1000_bus_type_unknown = 0, 287 e1000_bus_type_pci, 288 e1000_bus_type_pcix, 289 e1000_bus_type_pci_express, 290 e1000_bus_type_reserved 291 }; 292 293 enum e1000_bus_speed { 294 e1000_bus_speed_unknown = 0, 295 e1000_bus_speed_33, 296 e1000_bus_speed_66, 297 e1000_bus_speed_100, 298 e1000_bus_speed_120, 299 e1000_bus_speed_133, 300 e1000_bus_speed_2500, 301 e1000_bus_speed_5000, 302 e1000_bus_speed_reserved 303 }; 304 305 enum e1000_bus_width { 306 e1000_bus_width_unknown = 0, 307 e1000_bus_width_pcie_x1, 308 e1000_bus_width_pcie_x2, 309 e1000_bus_width_pcie_x4 = 4, 310 e1000_bus_width_pcie_x8 = 8, 311 e1000_bus_width_32, 312 e1000_bus_width_64, 313 e1000_bus_width_reserved 314 }; 315 316 enum e1000_1000t_rx_status { 317 e1000_1000t_rx_status_not_ok = 0, 318 e1000_1000t_rx_status_ok, 319 e1000_1000t_rx_status_undefined = 0xFF 320 }; 321 322 enum e1000_rev_polarity { 323 e1000_rev_polarity_normal = 0, 324 e1000_rev_polarity_reversed, 325 e1000_rev_polarity_undefined = 0xFF 326 }; 327 328 enum e1000_fc_mode { 329 e1000_fc_none = 0, 330 e1000_fc_rx_pause, 331 e1000_fc_tx_pause, 332 e1000_fc_full, 333 e1000_fc_default = 0xFF 334 }; 335 336 enum e1000_ffe_config { 337 e1000_ffe_config_enabled = 0, 338 e1000_ffe_config_active, 339 e1000_ffe_config_blocked 340 }; 341 342 enum e1000_dsp_config { 343 e1000_dsp_config_disabled = 0, 344 e1000_dsp_config_enabled, 345 e1000_dsp_config_activated, 346 e1000_dsp_config_undefined = 0xFF 347 }; 348 349 enum e1000_ms_type { 350 e1000_ms_hw_default = 0, 351 e1000_ms_force_master, 352 e1000_ms_force_slave, 353 e1000_ms_auto 354 }; 355 356 enum e1000_smart_speed { 357 e1000_smart_speed_default = 0, 358 e1000_smart_speed_on, 359 e1000_smart_speed_off 360 }; 361 362 enum e1000_serdes_link_state { 363 e1000_serdes_link_down = 0, 364 e1000_serdes_link_autoneg_progress, 365 e1000_serdes_link_autoneg_complete, 366 e1000_serdes_link_forced_up 367 }; 368 369 #define __le16 u16 370 #define __le32 u32 371 #define __le64 u64 372 /* Receive Descriptor */ 373 struct e1000_rx_desc { 374 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 375 __le16 length; /* Length of data DMAed into data buffer */ 376 __le16 csum; /* Packet checksum */ 377 u8 status; /* Descriptor status */ 378 u8 errors; /* Descriptor Errors */ 379 __le16 special; 380 }; 381 382 /* Receive Descriptor - Extended */ 383 union e1000_rx_desc_extended { 384 struct { 385 __le64 buffer_addr; 386 __le64 reserved; 387 } read; 388 struct { 389 struct { 390 __le32 mrq; /* Multiple Rx Queues */ 391 union { 392 __le32 rss; /* RSS Hash */ 393 struct { 394 __le16 ip_id; /* IP id */ 395 __le16 csum; /* Packet Checksum */ 396 } csum_ip; 397 } hi_dword; 398 } lower; 399 struct { 400 __le32 status_error; /* ext status/error */ 401 __le16 length; 402 __le16 vlan; /* VLAN tag */ 403 } upper; 404 } wb; /* writeback */ 405 }; 406 407 #define MAX_PS_BUFFERS 4 408 /* Receive Descriptor - Packet Split */ 409 union e1000_rx_desc_packet_split { 410 struct { 411 /* one buffer for protocol header(s), three data buffers */ 412 __le64 buffer_addr[MAX_PS_BUFFERS]; 413 } read; 414 struct { 415 struct { 416 __le32 mrq; /* Multiple Rx Queues */ 417 union { 418 __le32 rss; /* RSS Hash */ 419 struct { 420 __le16 ip_id; /* IP id */ 421 __le16 csum; /* Packet Checksum */ 422 } csum_ip; 423 } hi_dword; 424 } lower; 425 struct { 426 __le32 status_error; /* ext status/error */ 427 __le16 length0; /* length of buffer 0 */ 428 __le16 vlan; /* VLAN tag */ 429 } middle; 430 struct { 431 __le16 header_status; 432 __le16 length[3]; /* length of buffers 1-3 */ 433 } upper; 434 __le64 reserved; 435 } wb; /* writeback */ 436 }; 437 438 /* Transmit Descriptor */ 439 struct e1000_tx_desc { 440 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 441 union { 442 __le32 data; 443 struct { 444 __le16 length; /* Data buffer length */ 445 u8 cso; /* Checksum offset */ 446 u8 cmd; /* Descriptor control */ 447 } flags; 448 } lower; 449 union { 450 __le32 data; 451 struct { 452 u8 status; /* Descriptor status */ 453 u8 css; /* Checksum start */ 454 __le16 special; 455 } fields; 456 } upper; 457 }; 458 459 /* Offload Context Descriptor */ 460 struct e1000_context_desc { 461 union { 462 __le32 ip_config; 463 struct { 464 u8 ipcss; /* IP checksum start */ 465 u8 ipcso; /* IP checksum offset */ 466 __le16 ipcse; /* IP checksum end */ 467 } ip_fields; 468 } lower_setup; 469 union { 470 __le32 tcp_config; 471 struct { 472 u8 tucss; /* TCP checksum start */ 473 u8 tucso; /* TCP checksum offset */ 474 __le16 tucse; /* TCP checksum end */ 475 } tcp_fields; 476 } upper_setup; 477 __le32 cmd_and_length; 478 union { 479 __le32 data; 480 struct { 481 u8 status; /* Descriptor status */ 482 u8 hdr_len; /* Header length */ 483 __le16 mss; /* Maximum segment size */ 484 } fields; 485 } tcp_seg_setup; 486 }; 487 488 /* Offload data descriptor */ 489 struct e1000_data_desc { 490 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 491 union { 492 __le32 data; 493 struct { 494 __le16 length; /* Data buffer length */ 495 u8 typ_len_ext; 496 u8 cmd; 497 } flags; 498 } lower; 499 union { 500 __le32 data; 501 struct { 502 u8 status; /* Descriptor status */ 503 u8 popts; /* Packet Options */ 504 __le16 special; 505 } fields; 506 } upper; 507 }; 508 509 /* Statistics counters collected by the MAC */ 510 struct e1000_hw_stats { 511 u64 crcerrs; 512 u64 algnerrc; 513 u64 symerrs; 514 u64 rxerrc; 515 u64 mpc; 516 u64 scc; 517 u64 ecol; 518 u64 mcc; 519 u64 latecol; 520 u64 colc; 521 u64 dc; 522 u64 tncrs; 523 u64 sec; 524 u64 cexterr; 525 u64 rlec; 526 u64 xonrxc; 527 u64 xontxc; 528 u64 xoffrxc; 529 u64 xofftxc; 530 u64 fcruc; 531 u64 prc64; 532 u64 prc127; 533 u64 prc255; 534 u64 prc511; 535 u64 prc1023; 536 u64 prc1522; 537 u64 gprc; 538 u64 bprc; 539 u64 mprc; 540 u64 gptc; 541 u64 gorc; 542 u64 gotc; 543 u64 rnbc; 544 u64 ruc; 545 u64 rfc; 546 u64 roc; 547 u64 rjc; 548 u64 mgprc; 549 u64 mgpdc; 550 u64 mgptc; 551 u64 tor; 552 u64 tot; 553 u64 tpr; 554 u64 tpt; 555 u64 ptc64; 556 u64 ptc127; 557 u64 ptc255; 558 u64 ptc511; 559 u64 ptc1023; 560 u64 ptc1522; 561 u64 mptc; 562 u64 bptc; 563 u64 tsctc; 564 u64 tsctfc; 565 u64 iac; 566 u64 icrxptc; 567 u64 icrxatc; 568 u64 ictxptc; 569 u64 ictxatc; 570 u64 ictxqec; 571 u64 ictxqmtc; 572 u64 icrxdmtc; 573 u64 icrxoc; 574 u64 cbtmpc; 575 u64 htdpmc; 576 u64 cbrdpc; 577 u64 cbrmpc; 578 u64 rpthc; 579 u64 hgptc; 580 u64 htcbdpc; 581 u64 hgorc; 582 u64 hgotc; 583 u64 lenerrs; 584 u64 scvpc; 585 u64 hrmpc; 586 u64 doosync; 587 u64 o2bgptc; 588 u64 o2bspc; 589 u64 b2ospc; 590 u64 b2ogprc; 591 }; 592 593 struct e1000_vf_stats { 594 u64 base_gprc; 595 u64 base_gptc; 596 u64 base_gorc; 597 u64 base_gotc; 598 u64 base_mprc; 599 u64 base_gotlbc; 600 u64 base_gptlbc; 601 u64 base_gorlbc; 602 u64 base_gprlbc; 603 604 u32 last_gprc; 605 u32 last_gptc; 606 u32 last_gorc; 607 u32 last_gotc; 608 u32 last_mprc; 609 u32 last_gotlbc; 610 u32 last_gptlbc; 611 u32 last_gorlbc; 612 u32 last_gprlbc; 613 614 u64 gprc; 615 u64 gptc; 616 u64 gorc; 617 u64 gotc; 618 u64 mprc; 619 u64 gotlbc; 620 u64 gptlbc; 621 u64 gorlbc; 622 u64 gprlbc; 623 }; 624 625 struct e1000_phy_stats { 626 u32 idle_errors; 627 u32 receive_errors; 628 }; 629 630 struct e1000_host_mng_dhcp_cookie { 631 u32 signature; 632 u8 status; 633 u8 reserved0; 634 u16 vlan_id; 635 u32 reserved1; 636 u16 reserved2; 637 u8 reserved3; 638 u8 checksum; 639 }; 640 641 /* Host Interface "Rev 1" */ 642 struct e1000_host_command_header { 643 u8 command_id; 644 u8 command_length; 645 u8 command_options; 646 u8 checksum; 647 }; 648 649 #define E1000_HI_MAX_DATA_LENGTH 252 650 struct e1000_host_command_info { 651 struct e1000_host_command_header command_header; 652 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 653 }; 654 655 /* Host Interface "Rev 2" */ 656 struct e1000_host_mng_command_header { 657 u8 command_id; 658 u8 checksum; 659 u16 reserved1; 660 u16 reserved2; 661 u16 command_length; 662 }; 663 664 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 665 struct e1000_host_mng_command_info { 666 struct e1000_host_mng_command_header command_header; 667 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 668 }; 669 670 #include "e1000_mac.h" 671 #include "e1000_phy.h" 672 #include "e1000_nvm.h" 673 #include "e1000_manage.h" 674 #include "e1000_mbx.h" 675 676 /* Function pointers for the MAC. */ 677 struct e1000_mac_operations { 678 s32 (*init_params)(struct e1000_hw *); 679 s32 (*id_led_init)(struct e1000_hw *); 680 s32 (*blink_led)(struct e1000_hw *); 681 bool (*check_mng_mode)(struct e1000_hw *); 682 s32 (*check_for_link)(struct e1000_hw *); 683 s32 (*cleanup_led)(struct e1000_hw *); 684 void (*clear_hw_cntrs)(struct e1000_hw *); 685 void (*clear_vfta)(struct e1000_hw *); 686 s32 (*get_bus_info)(struct e1000_hw *); 687 void (*set_lan_id)(struct e1000_hw *); 688 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 689 s32 (*led_on)(struct e1000_hw *); 690 s32 (*led_off)(struct e1000_hw *); 691 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 692 s32 (*reset_hw)(struct e1000_hw *); 693 s32 (*init_hw)(struct e1000_hw *); 694 void (*shutdown_serdes)(struct e1000_hw *); 695 void (*power_up_serdes)(struct e1000_hw *); 696 s32 (*setup_link)(struct e1000_hw *); 697 s32 (*setup_physical_interface)(struct e1000_hw *); 698 s32 (*setup_led)(struct e1000_hw *); 699 void (*write_vfta)(struct e1000_hw *, u32, u32); 700 void (*config_collision_dist)(struct e1000_hw *); 701 void (*rar_set)(struct e1000_hw *, u8*, u32); 702 s32 (*read_mac_addr)(struct e1000_hw *); 703 s32 (*validate_mdi_setting)(struct e1000_hw *); 704 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16); 705 void (*release_swfw_sync)(struct e1000_hw *, u16); 706 s32 (*set_obff_timer)(struct e1000_hw *, u32); 707 }; 708 709 /* When to use various PHY register access functions: 710 * 711 * Func Caller 712 * Function Does Does When to use 713 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 714 * X_reg L,P,A n/a for simple PHY reg accesses 715 * X_reg_locked P,A L for multiple accesses of different regs 716 * on different pages 717 * X_reg_page A L,P for multiple accesses of different regs 718 * on the same page 719 * 720 * Where X=[read|write], L=locking, P=sets page, A=register access 721 * 722 */ 723 struct e1000_phy_operations { 724 s32 (*init_params)(struct e1000_hw *); 725 s32 (*acquire)(struct e1000_hw *); 726 s32 (*cfg_on_link_up)(struct e1000_hw *); 727 s32 (*check_polarity)(struct e1000_hw *); 728 s32 (*check_reset_block)(struct e1000_hw *); 729 s32 (*commit)(struct e1000_hw *); 730 s32 (*force_speed_duplex)(struct e1000_hw *); 731 s32 (*get_cfg_done)(struct e1000_hw *hw); 732 s32 (*get_cable_length)(struct e1000_hw *); 733 s32 (*get_info)(struct e1000_hw *); 734 s32 (*set_page)(struct e1000_hw *, u16); 735 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 736 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 737 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *); 738 void (*release)(struct e1000_hw *); 739 s32 (*reset)(struct e1000_hw *); 740 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 741 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 742 s32 (*write_reg)(struct e1000_hw *, u32, u16); 743 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 744 s32 (*write_reg_page)(struct e1000_hw *, u32, u16); 745 void (*power_up)(struct e1000_hw *); 746 void (*power_down)(struct e1000_hw *); 747 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *); 748 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8); 749 }; 750 751 /* Function pointers for the NVM. */ 752 struct e1000_nvm_operations { 753 s32 (*init_params)(struct e1000_hw *); 754 s32 (*acquire)(struct e1000_hw *); 755 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 756 void (*release)(struct e1000_hw *); 757 void (*reload)(struct e1000_hw *); 758 s32 (*update)(struct e1000_hw *); 759 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 760 s32 (*validate)(struct e1000_hw *); 761 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 762 }; 763 764 struct e1000_mac_info { 765 struct e1000_mac_operations ops; 766 u8 addr[ETH_ADDR_LEN]; 767 u8 perm_addr[ETH_ADDR_LEN]; 768 769 enum e1000_mac_type type; 770 771 u32 collision_delta; 772 u32 ledctl_default; 773 u32 ledctl_mode1; 774 u32 ledctl_mode2; 775 u32 mc_filter_type; 776 u32 tx_packet_delta; 777 u32 txcw; 778 779 u16 current_ifs_val; 780 u16 ifs_max_val; 781 u16 ifs_min_val; 782 u16 ifs_ratio; 783 u16 ifs_step_size; 784 u16 mta_reg_count; 785 u16 uta_reg_count; 786 787 /* Maximum size of the MTA register table in all supported adapters */ 788 #define MAX_MTA_REG 128 789 u32 mta_shadow[MAX_MTA_REG]; 790 u16 rar_entry_count; 791 792 u8 forced_speed_duplex; 793 794 bool adaptive_ifs; 795 bool has_fwsm; 796 bool arc_subsystem_valid; 797 bool asf_firmware_present; 798 bool autoneg; 799 bool autoneg_failed; 800 bool get_link_status; 801 bool in_ifs_mode; 802 #ifndef NO_82542_SUPPORT 803 bool report_tx_early; 804 #endif 805 enum e1000_serdes_link_state serdes_link_state; 806 bool serdes_has_link; 807 bool tx_pkt_filtering; 808 u32 max_frame_size; 809 }; 810 811 struct e1000_phy_info { 812 struct e1000_phy_operations ops; 813 enum e1000_phy_type type; 814 815 enum e1000_1000t_rx_status local_rx; 816 enum e1000_1000t_rx_status remote_rx; 817 enum e1000_ms_type ms_type; 818 enum e1000_ms_type original_ms_type; 819 enum e1000_rev_polarity cable_polarity; 820 enum e1000_smart_speed smart_speed; 821 822 u32 addr; 823 u32 id; 824 u32 reset_delay_us; /* in usec */ 825 u32 revision; 826 827 enum e1000_media_type media_type; 828 829 u16 autoneg_advertised; 830 u16 autoneg_mask; 831 u16 cable_length; 832 u16 max_cable_length; 833 u16 min_cable_length; 834 835 u8 mdix; 836 837 bool disable_polarity_correction; 838 bool is_mdix; 839 bool polarity_correction; 840 bool speed_downgraded; 841 bool autoneg_wait_to_complete; 842 }; 843 844 struct e1000_nvm_info { 845 struct e1000_nvm_operations ops; 846 enum e1000_nvm_type type; 847 enum e1000_nvm_override override; 848 849 u32 flash_bank_size; 850 u32 flash_base_addr; 851 852 u16 word_size; 853 u16 delay_usec; 854 u16 address_bits; 855 u16 opcode_bits; 856 u16 page_size; 857 }; 858 859 struct e1000_bus_info { 860 enum e1000_bus_type type; 861 enum e1000_bus_speed speed; 862 enum e1000_bus_width width; 863 864 u16 func; 865 u16 pci_cmd_word; 866 }; 867 868 struct e1000_fc_info { 869 u32 high_water; /* Flow control high-water mark */ 870 u32 low_water; /* Flow control low-water mark */ 871 u16 pause_time; /* Flow control pause timer */ 872 u16 refresh_time; /* Flow control refresh timer */ 873 bool send_xon; /* Flow control send XON */ 874 bool strict_ieee; /* Strict IEEE mode */ 875 enum e1000_fc_mode current_mode; /* FC mode in effect */ 876 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 877 }; 878 879 struct e1000_dev_spec_82541 { 880 enum e1000_dsp_config dsp_config; 881 enum e1000_ffe_config ffe_config; 882 u16 spd_default; 883 bool phy_init_script; 884 }; 885 886 #ifndef NO_82542_SUPPORT 887 struct e1000_dev_spec_82542 { 888 bool dma_fairness; 889 }; 890 891 #endif /* NO_82542_SUPPORT */ 892 struct e1000_dev_spec_82543 { 893 u32 tbi_compatibility; 894 bool dma_fairness; 895 bool init_phy_disabled; 896 }; 897 898 struct e1000_dev_spec_82571 { 899 bool laa_is_present; 900 u32 smb_counter; 901 }; 902 903 struct e1000_dev_spec_80003es2lan { 904 bool mdic_wa_enable; 905 }; 906 907 struct e1000_shadow_ram { 908 u16 value; 909 bool modified; 910 }; 911 912 struct e1000_mbx_operations { 913 s32 (*init_params)(struct e1000_hw *hw); 914 s32 (*read)(struct e1000_hw *, u32 *, u16, u16); 915 s32 (*write)(struct e1000_hw *, u32 *, u16, u16); 916 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16); 917 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16); 918 s32 (*check_for_msg)(struct e1000_hw *, u16); 919 s32 (*check_for_ack)(struct e1000_hw *, u16); 920 s32 (*check_for_rst)(struct e1000_hw *, u16); 921 }; 922 923 struct e1000_mbx_stats { 924 u32 msgs_tx; 925 u32 msgs_rx; 926 927 u32 acks; 928 u32 reqs; 929 u32 rsts; 930 }; 931 932 struct e1000_mbx_info { 933 struct e1000_mbx_operations ops; 934 struct e1000_mbx_stats stats; 935 u32 timeout; 936 u32 usec_delay; 937 u16 size; 938 }; 939 940 struct e1000_dev_spec_82575 { 941 bool sgmii_active; 942 bool global_device_reset; 943 bool eee_disable; 944 bool module_plugged; 945 bool clear_semaphore_once; 946 u32 mtu; 947 struct sfp_e1000_flags eth_flags; 948 u8 media_port; 949 bool media_changed; 950 }; 951 952 #define E1000_SHADOW_RAM_WORDS 2048 953 954 struct e1000_dev_spec_ich8lan { 955 bool kmrn_lock_loss_workaround_enabled; 956 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; 957 bool nvm_k1_enabled; 958 bool eee_disable; 959 u16 eee_lp_ability; 960 }; 961 962 struct e1000_dev_spec_vf { 963 u32 vf_number; 964 u32 v2p_mailbox; 965 }; 966 967 struct e1000_hw { 968 void *back; 969 970 u8 *hw_addr; 971 u8 *flash_address; 972 unsigned long io_base; 973 974 struct e1000_mac_info mac; 975 struct e1000_fc_info fc; 976 struct e1000_phy_info phy; 977 struct e1000_nvm_info nvm; 978 struct e1000_bus_info bus; 979 struct e1000_mbx_info mbx; 980 struct e1000_host_mng_dhcp_cookie mng_cookie; 981 982 union { 983 struct e1000_dev_spec_82541 _82541; 984 #ifndef NO_82542_SUPPORT 985 struct e1000_dev_spec_82542 _82542; 986 #endif 987 struct e1000_dev_spec_82543 _82543; 988 struct e1000_dev_spec_82571 _82571; 989 struct e1000_dev_spec_80003es2lan _80003es2lan; 990 struct e1000_dev_spec_ich8lan ich8lan; 991 struct e1000_dev_spec_82575 _82575; 992 struct e1000_dev_spec_vf vf; 993 } dev_spec; 994 995 u16 device_id; 996 u16 subsystem_vendor_id; 997 u16 subsystem_device_id; 998 u16 vendor_id; 999 1000 u8 revision_id; 1001 }; 1002 1003 #include "e1000_82541.h" 1004 #include "e1000_82543.h" 1005 #include "e1000_82571.h" 1006 #include "e1000_80003es2lan.h" 1007 #include "e1000_ich8lan.h" 1008 #include "e1000_82575.h" 1009 #include "e1000_i210.h" 1010 1011 /* These functions must be implemented by drivers */ 1012 #ifndef NO_82542_SUPPORT 1013 void e1000_pci_clear_mwi(struct e1000_hw *hw); 1014 void e1000_pci_set_mwi(struct e1000_hw *hw); 1015 #endif 1016 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1017 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1018 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1019 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1020 1021 #endif 1022