1 /****************************************************************************** 2 3 Copyright (c) 2001-2016, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #ifndef _E1000_HW_H_ 36 #define _E1000_HW_H_ 37 38 #include "e1000_osdep.h" 39 #include "e1000_regs.h" 40 #include "e1000_defines.h" 41 42 struct e1000_hw; 43 44 #define E1000_DEV_ID_82542 0x1000 45 #define E1000_DEV_ID_82543GC_FIBER 0x1001 46 #define E1000_DEV_ID_82543GC_COPPER 0x1004 47 #define E1000_DEV_ID_82544EI_COPPER 0x1008 48 #define E1000_DEV_ID_82544EI_FIBER 0x1009 49 #define E1000_DEV_ID_82544GC_COPPER 0x100C 50 #define E1000_DEV_ID_82544GC_LOM 0x100D 51 #define E1000_DEV_ID_82540EM 0x100E 52 #define E1000_DEV_ID_82540EM_LOM 0x1015 53 #define E1000_DEV_ID_82540EP_LOM 0x1016 54 #define E1000_DEV_ID_82540EP 0x1017 55 #define E1000_DEV_ID_82540EP_LP 0x101E 56 #define E1000_DEV_ID_82545EM_COPPER 0x100F 57 #define E1000_DEV_ID_82545EM_FIBER 0x1011 58 #define E1000_DEV_ID_82545GM_COPPER 0x1026 59 #define E1000_DEV_ID_82545GM_FIBER 0x1027 60 #define E1000_DEV_ID_82545GM_SERDES 0x1028 61 #define E1000_DEV_ID_82546EB_COPPER 0x1010 62 #define E1000_DEV_ID_82546EB_FIBER 0x1012 63 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 64 #define E1000_DEV_ID_82546GB_COPPER 0x1079 65 #define E1000_DEV_ID_82546GB_FIBER 0x107A 66 #define E1000_DEV_ID_82546GB_SERDES 0x107B 67 #define E1000_DEV_ID_82546GB_PCIE 0x108A 68 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 69 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 70 #define E1000_DEV_ID_82541EI 0x1013 71 #define E1000_DEV_ID_82541EI_MOBILE 0x1018 72 #define E1000_DEV_ID_82541ER_LOM 0x1014 73 #define E1000_DEV_ID_82541ER 0x1078 74 #define E1000_DEV_ID_82541GI 0x1076 75 #define E1000_DEV_ID_82541GI_LF 0x107C 76 #define E1000_DEV_ID_82541GI_MOBILE 0x1077 77 #define E1000_DEV_ID_82547EI 0x1019 78 #define E1000_DEV_ID_82547EI_MOBILE 0x101A 79 #define E1000_DEV_ID_82547GI 0x1075 80 #define E1000_DEV_ID_82571EB_COPPER 0x105E 81 #define E1000_DEV_ID_82571EB_FIBER 0x105F 82 #define E1000_DEV_ID_82571EB_SERDES 0x1060 83 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 84 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 85 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 86 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 87 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 88 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 89 #define E1000_DEV_ID_82571EB_QUAD_COPPER_BP 0x10A0 90 #define E1000_DEV_ID_82572EI_COPPER 0x107D 91 #define E1000_DEV_ID_82572EI_FIBER 0x107E 92 #define E1000_DEV_ID_82572EI_SERDES 0x107F 93 #define E1000_DEV_ID_82572EI 0x10B9 94 #define E1000_DEV_ID_82573E 0x108B 95 #define E1000_DEV_ID_82573E_IAMT 0x108C 96 #define E1000_DEV_ID_82573L 0x109A 97 #define E1000_DEV_ID_82574L 0x10D3 98 #define E1000_DEV_ID_82574LA 0x10F6 99 #define E1000_DEV_ID_82583V 0x150C 100 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 101 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 102 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 103 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 104 #define E1000_DEV_ID_ICH8_82567V_3 0x1501 105 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 106 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 107 #define E1000_DEV_ID_ICH8_IGP_C 0x104B 108 #define E1000_DEV_ID_ICH8_IFE 0x104C 109 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 110 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 111 #define E1000_DEV_ID_ICH8_IGP_M 0x104D 112 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF 113 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 114 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 115 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 116 #define E1000_DEV_ID_ICH9_BM 0x10E5 117 #define E1000_DEV_ID_ICH9_IGP_C 0x294C 118 #define E1000_DEV_ID_ICH9_IFE 0x10C0 119 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 120 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 121 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 122 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 123 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 124 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 125 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 126 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525 127 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 128 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 129 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 130 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 131 #define E1000_DEV_ID_PCH2_LV_LM 0x1502 132 #define E1000_DEV_ID_PCH2_LV_V 0x1503 133 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A 134 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B 135 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A 136 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559 137 #define E1000_DEV_ID_PCH_I218_LM2 0x15A0 138 #define E1000_DEV_ID_PCH_I218_V2 0x15A1 139 #define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */ 140 #define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */ 141 #define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* Sunrise Point PCH */ 142 #define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* Sunrise Point PCH */ 143 #define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* Sunrise Point-H PCH */ 144 #define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* Sunrise Point-H PCH */ 145 #define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LEWISBURG PCH */ 146 #define E1000_DEV_ID_PCH_SPT_I219_LM4 0x15D7 147 #define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8 148 #define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3 149 #define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6 150 #define E1000_DEV_ID_PCH_CNP_I219_LM6 0x15BD 151 #define E1000_DEV_ID_PCH_CNP_I219_V6 0x15BE 152 #define E1000_DEV_ID_PCH_CNP_I219_LM7 0x15BB 153 #define E1000_DEV_ID_PCH_CNP_I219_V7 0x15BC 154 #define E1000_DEV_ID_82576 0x10C9 155 #define E1000_DEV_ID_82576_FIBER 0x10E6 156 #define E1000_DEV_ID_82576_SERDES 0x10E7 157 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 158 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526 159 #define E1000_DEV_ID_82576_NS 0x150A 160 #define E1000_DEV_ID_82576_NS_SERDES 0x1518 161 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D 162 #define E1000_DEV_ID_82576_VF 0x10CA 163 #define E1000_DEV_ID_82576_VF_HV 0x152D 164 #define E1000_DEV_ID_I350_VF 0x1520 165 #define E1000_DEV_ID_I350_VF_HV 0x152F 166 #define E1000_DEV_ID_82575EB_COPPER 0x10A7 167 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 168 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 169 #define E1000_DEV_ID_82580_COPPER 0x150E 170 #define E1000_DEV_ID_82580_FIBER 0x150F 171 #define E1000_DEV_ID_82580_SERDES 0x1510 172 #define E1000_DEV_ID_82580_SGMII 0x1511 173 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 174 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527 175 #define E1000_DEV_ID_I350_COPPER 0x1521 176 #define E1000_DEV_ID_I350_FIBER 0x1522 177 #define E1000_DEV_ID_I350_SERDES 0x1523 178 #define E1000_DEV_ID_I350_SGMII 0x1524 179 #define E1000_DEV_ID_I350_DA4 0x1546 180 #define E1000_DEV_ID_I210_COPPER 0x1533 181 #define E1000_DEV_ID_I210_COPPER_OEM1 0x1534 182 #define E1000_DEV_ID_I210_COPPER_IT 0x1535 183 #define E1000_DEV_ID_I210_FIBER 0x1536 184 #define E1000_DEV_ID_I210_SERDES 0x1537 185 #define E1000_DEV_ID_I210_SGMII 0x1538 186 #define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B 187 #define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C 188 #define E1000_DEV_ID_I211_COPPER 0x1539 189 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40 190 #define E1000_DEV_ID_I354_SGMII 0x1F41 191 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45 192 #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438 193 #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A 194 #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C 195 #define E1000_DEV_ID_DH89XXCC_SFP 0x0440 196 197 #define E1000_REVISION_0 0 198 #define E1000_REVISION_1 1 199 #define E1000_REVISION_2 2 200 #define E1000_REVISION_3 3 201 #define E1000_REVISION_4 4 202 203 #define E1000_FUNC_0 0 204 #define E1000_FUNC_1 1 205 #define E1000_FUNC_2 2 206 #define E1000_FUNC_3 3 207 208 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 209 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 210 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6 211 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9 212 213 enum e1000_mac_type { 214 e1000_undefined = 0, 215 e1000_82542, 216 e1000_82543, 217 e1000_82544, 218 e1000_82540, 219 e1000_82545, 220 e1000_82545_rev_3, 221 e1000_82546, 222 e1000_82546_rev_3, 223 e1000_82541, 224 e1000_82541_rev_2, 225 e1000_82547, 226 e1000_82547_rev_2, 227 e1000_82571, 228 e1000_82572, 229 e1000_82573, 230 e1000_82574, 231 e1000_82583, 232 e1000_80003es2lan, 233 e1000_ich8lan, 234 e1000_ich9lan, 235 e1000_ich10lan, 236 e1000_pchlan, 237 e1000_pch2lan, 238 e1000_pch_lpt, 239 e1000_pch_spt, 240 e1000_pch_cnp, 241 e1000_82575, 242 e1000_82576, 243 e1000_82580, 244 e1000_i350, 245 e1000_i354, 246 e1000_i210, 247 e1000_i211, 248 e1000_vfadapt, 249 e1000_vfadapt_i350, 250 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ 251 }; 252 253 enum e1000_media_type { 254 e1000_media_type_unknown = 0, 255 e1000_media_type_copper = 1, 256 e1000_media_type_fiber = 2, 257 e1000_media_type_internal_serdes = 3, 258 e1000_num_media_types 259 }; 260 261 enum e1000_nvm_type { 262 e1000_nvm_unknown = 0, 263 e1000_nvm_none, 264 e1000_nvm_eeprom_spi, 265 e1000_nvm_eeprom_microwire, 266 e1000_nvm_flash_hw, 267 e1000_nvm_invm, 268 e1000_nvm_flash_sw 269 }; 270 271 enum e1000_nvm_override { 272 e1000_nvm_override_none = 0, 273 e1000_nvm_override_spi_small, 274 e1000_nvm_override_spi_large, 275 e1000_nvm_override_microwire_small, 276 e1000_nvm_override_microwire_large 277 }; 278 279 enum e1000_phy_type { 280 e1000_phy_unknown = 0, 281 e1000_phy_none, 282 e1000_phy_m88, 283 e1000_phy_igp, 284 e1000_phy_igp_2, 285 e1000_phy_gg82563, 286 e1000_phy_igp_3, 287 e1000_phy_ife, 288 e1000_phy_bm, 289 e1000_phy_82578, 290 e1000_phy_82577, 291 e1000_phy_82579, 292 e1000_phy_i217, 293 e1000_phy_82580, 294 e1000_phy_vf, 295 e1000_phy_i210, 296 }; 297 298 enum e1000_bus_type { 299 e1000_bus_type_unknown = 0, 300 e1000_bus_type_pci, 301 e1000_bus_type_pcix, 302 e1000_bus_type_pci_express, 303 e1000_bus_type_reserved 304 }; 305 306 enum e1000_bus_speed { 307 e1000_bus_speed_unknown = 0, 308 e1000_bus_speed_33, 309 e1000_bus_speed_66, 310 e1000_bus_speed_100, 311 e1000_bus_speed_120, 312 e1000_bus_speed_133, 313 e1000_bus_speed_2500, 314 e1000_bus_speed_5000, 315 e1000_bus_speed_reserved 316 }; 317 318 enum e1000_bus_width { 319 e1000_bus_width_unknown = 0, 320 e1000_bus_width_pcie_x1, 321 e1000_bus_width_pcie_x2, 322 e1000_bus_width_pcie_x4 = 4, 323 e1000_bus_width_pcie_x8 = 8, 324 e1000_bus_width_32, 325 e1000_bus_width_64, 326 e1000_bus_width_reserved 327 }; 328 329 enum e1000_1000t_rx_status { 330 e1000_1000t_rx_status_not_ok = 0, 331 e1000_1000t_rx_status_ok, 332 e1000_1000t_rx_status_undefined = 0xFF 333 }; 334 335 enum e1000_rev_polarity { 336 e1000_rev_polarity_normal = 0, 337 e1000_rev_polarity_reversed, 338 e1000_rev_polarity_undefined = 0xFF 339 }; 340 341 enum e1000_fc_mode { 342 e1000_fc_none = 0, 343 e1000_fc_rx_pause, 344 e1000_fc_tx_pause, 345 e1000_fc_full, 346 e1000_fc_default = 0xFF 347 }; 348 349 enum e1000_ffe_config { 350 e1000_ffe_config_enabled = 0, 351 e1000_ffe_config_active, 352 e1000_ffe_config_blocked 353 }; 354 355 enum e1000_dsp_config { 356 e1000_dsp_config_disabled = 0, 357 e1000_dsp_config_enabled, 358 e1000_dsp_config_activated, 359 e1000_dsp_config_undefined = 0xFF 360 }; 361 362 enum e1000_ms_type { 363 e1000_ms_hw_default = 0, 364 e1000_ms_force_master, 365 e1000_ms_force_slave, 366 e1000_ms_auto 367 }; 368 369 enum e1000_smart_speed { 370 e1000_smart_speed_default = 0, 371 e1000_smart_speed_on, 372 e1000_smart_speed_off 373 }; 374 375 enum e1000_serdes_link_state { 376 e1000_serdes_link_down = 0, 377 e1000_serdes_link_autoneg_progress, 378 e1000_serdes_link_autoneg_complete, 379 e1000_serdes_link_forced_up 380 }; 381 382 #define __le16 u16 383 #define __le32 u32 384 #define __le64 u64 385 /* Receive Descriptor */ 386 struct e1000_rx_desc { 387 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 388 __le16 length; /* Length of data DMAed into data buffer */ 389 __le16 csum; /* Packet checksum */ 390 u8 status; /* Descriptor status */ 391 u8 errors; /* Descriptor Errors */ 392 __le16 special; 393 }; 394 395 /* Receive Descriptor - Extended */ 396 union e1000_rx_desc_extended { 397 struct { 398 __le64 buffer_addr; 399 __le64 reserved; 400 } read; 401 struct { 402 struct { 403 __le32 mrq; /* Multiple Rx Queues */ 404 union { 405 __le32 rss; /* RSS Hash */ 406 struct { 407 __le16 ip_id; /* IP id */ 408 __le16 csum; /* Packet Checksum */ 409 } csum_ip; 410 } hi_dword; 411 } lower; 412 struct { 413 __le32 status_error; /* ext status/error */ 414 __le16 length; 415 __le16 vlan; /* VLAN tag */ 416 } upper; 417 } wb; /* writeback */ 418 }; 419 420 #define MAX_PS_BUFFERS 4 421 422 /* Number of packet split data buffers (not including the header buffer) */ 423 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) 424 425 /* Receive Descriptor - Packet Split */ 426 union e1000_rx_desc_packet_split { 427 struct { 428 /* one buffer for protocol header(s), three data buffers */ 429 __le64 buffer_addr[MAX_PS_BUFFERS]; 430 } read; 431 struct { 432 struct { 433 __le32 mrq; /* Multiple Rx Queues */ 434 union { 435 __le32 rss; /* RSS Hash */ 436 struct { 437 __le16 ip_id; /* IP id */ 438 __le16 csum; /* Packet Checksum */ 439 } csum_ip; 440 } hi_dword; 441 } lower; 442 struct { 443 __le32 status_error; /* ext status/error */ 444 __le16 length0; /* length of buffer 0 */ 445 __le16 vlan; /* VLAN tag */ 446 } middle; 447 struct { 448 __le16 header_status; 449 /* length of buffers 1-3 */ 450 __le16 length[PS_PAGE_BUFFERS]; 451 } upper; 452 __le64 reserved; 453 } wb; /* writeback */ 454 }; 455 456 /* Transmit Descriptor */ 457 struct e1000_tx_desc { 458 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 459 union { 460 __le32 data; 461 struct { 462 __le16 length; /* Data buffer length */ 463 u8 cso; /* Checksum offset */ 464 u8 cmd; /* Descriptor control */ 465 } flags; 466 } lower; 467 union { 468 __le32 data; 469 struct { 470 u8 status; /* Descriptor status */ 471 u8 css; /* Checksum start */ 472 __le16 special; 473 } fields; 474 } upper; 475 }; 476 477 /* Offload Context Descriptor */ 478 struct e1000_context_desc { 479 union { 480 __le32 ip_config; 481 struct { 482 u8 ipcss; /* IP checksum start */ 483 u8 ipcso; /* IP checksum offset */ 484 __le16 ipcse; /* IP checksum end */ 485 } ip_fields; 486 } lower_setup; 487 union { 488 __le32 tcp_config; 489 struct { 490 u8 tucss; /* TCP checksum start */ 491 u8 tucso; /* TCP checksum offset */ 492 __le16 tucse; /* TCP checksum end */ 493 } tcp_fields; 494 } upper_setup; 495 __le32 cmd_and_length; 496 union { 497 __le32 data; 498 struct { 499 u8 status; /* Descriptor status */ 500 u8 hdr_len; /* Header length */ 501 __le16 mss; /* Maximum segment size */ 502 } fields; 503 } tcp_seg_setup; 504 }; 505 506 /* Offload data descriptor */ 507 struct e1000_data_desc { 508 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 509 union { 510 __le32 data; 511 struct { 512 __le16 length; /* Data buffer length */ 513 u8 typ_len_ext; 514 u8 cmd; 515 } flags; 516 } lower; 517 union { 518 __le32 data; 519 struct { 520 u8 status; /* Descriptor status */ 521 u8 popts; /* Packet Options */ 522 __le16 special; 523 } fields; 524 } upper; 525 }; 526 527 /* Statistics counters collected by the MAC */ 528 struct e1000_hw_stats { 529 u64 crcerrs; 530 u64 algnerrc; 531 u64 symerrs; 532 u64 rxerrc; 533 u64 mpc; 534 u64 scc; 535 u64 ecol; 536 u64 mcc; 537 u64 latecol; 538 u64 colc; 539 u64 dc; 540 u64 tncrs; 541 u64 sec; 542 u64 cexterr; 543 u64 rlec; 544 u64 xonrxc; 545 u64 xontxc; 546 u64 xoffrxc; 547 u64 xofftxc; 548 u64 fcruc; 549 u64 prc64; 550 u64 prc127; 551 u64 prc255; 552 u64 prc511; 553 u64 prc1023; 554 u64 prc1522; 555 u64 gprc; 556 u64 bprc; 557 u64 mprc; 558 u64 gptc; 559 u64 gorc; 560 u64 gotc; 561 u64 rnbc; 562 u64 ruc; 563 u64 rfc; 564 u64 roc; 565 u64 rjc; 566 u64 mgprc; 567 u64 mgpdc; 568 u64 mgptc; 569 u64 tor; 570 u64 tot; 571 u64 tpr; 572 u64 tpt; 573 u64 ptc64; 574 u64 ptc127; 575 u64 ptc255; 576 u64 ptc511; 577 u64 ptc1023; 578 u64 ptc1522; 579 u64 mptc; 580 u64 bptc; 581 u64 tsctc; 582 u64 tsctfc; 583 u64 iac; 584 u64 icrxptc; 585 u64 icrxatc; 586 u64 ictxptc; 587 u64 ictxatc; 588 u64 ictxqec; 589 u64 ictxqmtc; 590 u64 icrxdmtc; 591 u64 icrxoc; 592 u64 cbtmpc; 593 u64 htdpmc; 594 u64 cbrdpc; 595 u64 cbrmpc; 596 u64 rpthc; 597 u64 hgptc; 598 u64 htcbdpc; 599 u64 hgorc; 600 u64 hgotc; 601 u64 lenerrs; 602 u64 scvpc; 603 u64 hrmpc; 604 u64 doosync; 605 u64 o2bgptc; 606 u64 o2bspc; 607 u64 b2ospc; 608 u64 b2ogprc; 609 }; 610 611 struct e1000_vf_stats { 612 u64 base_gprc; 613 u64 base_gptc; 614 u64 base_gorc; 615 u64 base_gotc; 616 u64 base_mprc; 617 u64 base_gotlbc; 618 u64 base_gptlbc; 619 u64 base_gorlbc; 620 u64 base_gprlbc; 621 622 u32 last_gprc; 623 u32 last_gptc; 624 u32 last_gorc; 625 u32 last_gotc; 626 u32 last_mprc; 627 u32 last_gotlbc; 628 u32 last_gptlbc; 629 u32 last_gorlbc; 630 u32 last_gprlbc; 631 632 u64 gprc; 633 u64 gptc; 634 u64 gorc; 635 u64 gotc; 636 u64 mprc; 637 u64 gotlbc; 638 u64 gptlbc; 639 u64 gorlbc; 640 u64 gprlbc; 641 }; 642 643 struct e1000_phy_stats { 644 u32 idle_errors; 645 u32 receive_errors; 646 }; 647 648 struct e1000_host_mng_dhcp_cookie { 649 u32 signature; 650 u8 status; 651 u8 reserved0; 652 u16 vlan_id; 653 u32 reserved1; 654 u16 reserved2; 655 u8 reserved3; 656 u8 checksum; 657 }; 658 659 /* Host Interface "Rev 1" */ 660 struct e1000_host_command_header { 661 u8 command_id; 662 u8 command_length; 663 u8 command_options; 664 u8 checksum; 665 }; 666 667 #define E1000_HI_MAX_DATA_LENGTH 252 668 struct e1000_host_command_info { 669 struct e1000_host_command_header command_header; 670 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 671 }; 672 673 /* Host Interface "Rev 2" */ 674 struct e1000_host_mng_command_header { 675 u8 command_id; 676 u8 checksum; 677 u16 reserved1; 678 u16 reserved2; 679 u16 command_length; 680 }; 681 682 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 683 struct e1000_host_mng_command_info { 684 struct e1000_host_mng_command_header command_header; 685 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 686 }; 687 688 #include "e1000_mac.h" 689 #include "e1000_phy.h" 690 #include "e1000_nvm.h" 691 #include "e1000_manage.h" 692 #include "e1000_mbx.h" 693 694 /* Function pointers for the MAC. */ 695 struct e1000_mac_operations { 696 s32 (*init_params)(struct e1000_hw *); 697 s32 (*id_led_init)(struct e1000_hw *); 698 s32 (*blink_led)(struct e1000_hw *); 699 bool (*check_mng_mode)(struct e1000_hw *); 700 s32 (*check_for_link)(struct e1000_hw *); 701 s32 (*cleanup_led)(struct e1000_hw *); 702 void (*clear_hw_cntrs)(struct e1000_hw *); 703 void (*clear_vfta)(struct e1000_hw *); 704 s32 (*get_bus_info)(struct e1000_hw *); 705 void (*set_lan_id)(struct e1000_hw *); 706 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 707 s32 (*led_on)(struct e1000_hw *); 708 s32 (*led_off)(struct e1000_hw *); 709 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 710 s32 (*reset_hw)(struct e1000_hw *); 711 s32 (*init_hw)(struct e1000_hw *); 712 void (*shutdown_serdes)(struct e1000_hw *); 713 void (*power_up_serdes)(struct e1000_hw *); 714 s32 (*setup_link)(struct e1000_hw *); 715 s32 (*setup_physical_interface)(struct e1000_hw *); 716 s32 (*setup_led)(struct e1000_hw *); 717 void (*write_vfta)(struct e1000_hw *, u32, u32); 718 void (*config_collision_dist)(struct e1000_hw *); 719 int (*rar_set)(struct e1000_hw *, u8*, u32); 720 s32 (*read_mac_addr)(struct e1000_hw *); 721 s32 (*validate_mdi_setting)(struct e1000_hw *); 722 s32 (*set_obff_timer)(struct e1000_hw *, u32); 723 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16); 724 void (*release_swfw_sync)(struct e1000_hw *, u16); 725 }; 726 727 /* When to use various PHY register access functions: 728 * 729 * Func Caller 730 * Function Does Does When to use 731 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 732 * X_reg L,P,A n/a for simple PHY reg accesses 733 * X_reg_locked P,A L for multiple accesses of different regs 734 * on different pages 735 * X_reg_page A L,P for multiple accesses of different regs 736 * on the same page 737 * 738 * Where X=[read|write], L=locking, P=sets page, A=register access 739 * 740 */ 741 struct e1000_phy_operations { 742 s32 (*init_params)(struct e1000_hw *); 743 s32 (*acquire)(struct e1000_hw *); 744 s32 (*cfg_on_link_up)(struct e1000_hw *); 745 s32 (*check_polarity)(struct e1000_hw *); 746 s32 (*check_reset_block)(struct e1000_hw *); 747 s32 (*commit)(struct e1000_hw *); 748 s32 (*force_speed_duplex)(struct e1000_hw *); 749 s32 (*get_cfg_done)(struct e1000_hw *hw); 750 s32 (*get_cable_length)(struct e1000_hw *); 751 s32 (*get_info)(struct e1000_hw *); 752 s32 (*set_page)(struct e1000_hw *, u16); 753 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 754 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 755 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *); 756 void (*release)(struct e1000_hw *); 757 s32 (*reset)(struct e1000_hw *); 758 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 759 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 760 s32 (*write_reg)(struct e1000_hw *, u32, u16); 761 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 762 s32 (*write_reg_page)(struct e1000_hw *, u32, u16); 763 void (*power_up)(struct e1000_hw *); 764 void (*power_down)(struct e1000_hw *); 765 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *); 766 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8); 767 }; 768 769 /* Function pointers for the NVM. */ 770 struct e1000_nvm_operations { 771 s32 (*init_params)(struct e1000_hw *); 772 s32 (*acquire)(struct e1000_hw *); 773 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 774 void (*release)(struct e1000_hw *); 775 void (*reload)(struct e1000_hw *); 776 s32 (*update)(struct e1000_hw *); 777 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 778 s32 (*validate)(struct e1000_hw *); 779 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 780 }; 781 782 struct e1000_mac_info { 783 struct e1000_mac_operations ops; 784 u8 addr[ETH_ADDR_LEN]; 785 u8 perm_addr[ETH_ADDR_LEN]; 786 787 enum e1000_mac_type type; 788 789 u32 collision_delta; 790 u32 ledctl_default; 791 u32 ledctl_mode1; 792 u32 ledctl_mode2; 793 u32 mc_filter_type; 794 u32 tx_packet_delta; 795 u32 txcw; 796 797 u16 current_ifs_val; 798 u16 ifs_max_val; 799 u16 ifs_min_val; 800 u16 ifs_ratio; 801 u16 ifs_step_size; 802 u16 mta_reg_count; 803 u16 uta_reg_count; 804 805 /* Maximum size of the MTA register table in all supported adapters */ 806 #define MAX_MTA_REG 128 807 u32 mta_shadow[MAX_MTA_REG]; 808 u16 rar_entry_count; 809 810 u8 forced_speed_duplex; 811 812 bool adaptive_ifs; 813 bool has_fwsm; 814 bool arc_subsystem_valid; 815 bool asf_firmware_present; 816 bool autoneg; 817 bool autoneg_failed; 818 bool get_link_status; 819 bool in_ifs_mode; 820 bool report_tx_early; 821 enum e1000_serdes_link_state serdes_link_state; 822 bool serdes_has_link; 823 bool tx_pkt_filtering; 824 u32 max_frame_size; 825 }; 826 827 struct e1000_phy_info { 828 struct e1000_phy_operations ops; 829 enum e1000_phy_type type; 830 831 enum e1000_1000t_rx_status local_rx; 832 enum e1000_1000t_rx_status remote_rx; 833 enum e1000_ms_type ms_type; 834 enum e1000_ms_type original_ms_type; 835 enum e1000_rev_polarity cable_polarity; 836 enum e1000_smart_speed smart_speed; 837 838 u32 addr; 839 u32 id; 840 u32 reset_delay_us; /* in usec */ 841 u32 revision; 842 843 enum e1000_media_type media_type; 844 845 u16 autoneg_advertised; 846 u16 autoneg_mask; 847 u16 cable_length; 848 u16 max_cable_length; 849 u16 min_cable_length; 850 851 u8 mdix; 852 853 bool disable_polarity_correction; 854 bool is_mdix; 855 bool polarity_correction; 856 bool speed_downgraded; 857 bool autoneg_wait_to_complete; 858 }; 859 860 struct e1000_nvm_info { 861 struct e1000_nvm_operations ops; 862 enum e1000_nvm_type type; 863 enum e1000_nvm_override override; 864 865 u32 flash_bank_size; 866 u32 flash_base_addr; 867 868 u16 word_size; 869 u16 delay_usec; 870 u16 address_bits; 871 u16 opcode_bits; 872 u16 page_size; 873 }; 874 875 struct e1000_bus_info { 876 enum e1000_bus_type type; 877 enum e1000_bus_speed speed; 878 enum e1000_bus_width width; 879 880 u16 func; 881 u16 pci_cmd_word; 882 }; 883 884 struct e1000_fc_info { 885 u32 high_water; /* Flow control high-water mark */ 886 u32 low_water; /* Flow control low-water mark */ 887 u16 pause_time; /* Flow control pause timer */ 888 u16 refresh_time; /* Flow control refresh timer */ 889 bool send_xon; /* Flow control send XON */ 890 bool strict_ieee; /* Strict IEEE mode */ 891 enum e1000_fc_mode current_mode; /* FC mode in effect */ 892 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 893 }; 894 895 struct e1000_dev_spec_82541 { 896 enum e1000_dsp_config dsp_config; 897 enum e1000_ffe_config ffe_config; 898 u16 spd_default; 899 bool phy_init_script; 900 }; 901 902 struct e1000_dev_spec_82542 { 903 bool dma_fairness; 904 }; 905 906 struct e1000_dev_spec_82543 { 907 u32 tbi_compatibility; 908 bool dma_fairness; 909 bool init_phy_disabled; 910 }; 911 912 struct e1000_dev_spec_82571 { 913 bool laa_is_present; 914 u32 smb_counter; 915 }; 916 917 struct e1000_dev_spec_80003es2lan { 918 bool mdic_wa_enable; 919 }; 920 921 struct e1000_shadow_ram { 922 u16 value; 923 bool modified; 924 }; 925 926 #define E1000_SHADOW_RAM_WORDS 2048 927 928 /* I218 PHY Ultra Low Power (ULP) states */ 929 enum e1000_ulp_state { 930 e1000_ulp_state_unknown, 931 e1000_ulp_state_off, 932 e1000_ulp_state_on, 933 }; 934 935 struct e1000_mbx_operations { 936 s32 (*init_params)(struct e1000_hw *hw); 937 s32 (*read)(struct e1000_hw *, u32 *, u16, u16); 938 s32 (*write)(struct e1000_hw *, u32 *, u16, u16); 939 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16); 940 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16); 941 s32 (*check_for_msg)(struct e1000_hw *, u16); 942 s32 (*check_for_ack)(struct e1000_hw *, u16); 943 s32 (*check_for_rst)(struct e1000_hw *, u16); 944 }; 945 946 struct e1000_mbx_stats { 947 u32 msgs_tx; 948 u32 msgs_rx; 949 950 u32 acks; 951 u32 reqs; 952 u32 rsts; 953 }; 954 955 struct e1000_mbx_info { 956 struct e1000_mbx_operations ops; 957 struct e1000_mbx_stats stats; 958 u32 timeout; 959 u32 usec_delay; 960 u16 size; 961 }; 962 963 struct e1000_dev_spec_82575 { 964 bool sgmii_active; 965 bool global_device_reset; 966 bool eee_disable; 967 bool module_plugged; 968 bool clear_semaphore_once; 969 u32 mtu; 970 struct sfp_e1000_flags eth_flags; 971 u8 media_port; 972 bool media_changed; 973 }; 974 975 struct e1000_dev_spec_vf { 976 u32 vf_number; 977 u32 v2p_mailbox; 978 }; 979 980 struct e1000_dev_spec_ich8lan { 981 bool kmrn_lock_loss_workaround_enabled; 982 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; 983 bool nvm_k1_enabled; 984 bool disable_k1_off; 985 bool eee_disable; 986 u16 eee_lp_ability; 987 enum e1000_ulp_state ulp_state; 988 bool ulp_capability_disabled; 989 bool during_suspend_flow; 990 bool during_dpg_exit; 991 }; 992 993 struct e1000_hw { 994 void *back; 995 996 u8 *hw_addr; 997 u8 *flash_address; 998 unsigned long io_base; 999 1000 struct e1000_mac_info mac; 1001 struct e1000_fc_info fc; 1002 struct e1000_phy_info phy; 1003 struct e1000_nvm_info nvm; 1004 struct e1000_bus_info bus; 1005 struct e1000_mbx_info mbx; 1006 struct e1000_host_mng_dhcp_cookie mng_cookie; 1007 1008 union { 1009 struct e1000_dev_spec_82541 _82541; 1010 struct e1000_dev_spec_82542 _82542; 1011 struct e1000_dev_spec_82543 _82543; 1012 struct e1000_dev_spec_82571 _82571; 1013 struct e1000_dev_spec_80003es2lan _80003es2lan; 1014 struct e1000_dev_spec_ich8lan ich8lan; 1015 struct e1000_dev_spec_82575 _82575; 1016 struct e1000_dev_spec_vf vf; 1017 } dev_spec; 1018 1019 u16 device_id; 1020 u16 subsystem_vendor_id; 1021 u16 subsystem_device_id; 1022 u16 vendor_id; 1023 1024 u8 revision_id; 1025 }; 1026 1027 #include "e1000_82541.h" 1028 #include "e1000_82543.h" 1029 #include "e1000_82571.h" 1030 #include "e1000_80003es2lan.h" 1031 #include "e1000_ich8lan.h" 1032 #include "e1000_82575.h" 1033 #include "e1000_i210.h" 1034 1035 /* These functions must be implemented by drivers */ 1036 void e1000_pci_clear_mwi(struct e1000_hw *hw); 1037 void e1000_pci_set_mwi(struct e1000_hw *hw); 1038 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1039 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1040 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1041 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1042 1043 #endif 1044