1 /****************************************************************************** 2 3 Copyright (c) 2001-2016, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #ifndef _E1000_HW_H_ 36 #define _E1000_HW_H_ 37 38 #include "e1000_osdep.h" 39 #include "e1000_regs.h" 40 #include "e1000_defines.h" 41 42 struct e1000_hw; 43 44 #define E1000_DEV_ID_82542 0x1000 45 #define E1000_DEV_ID_82543GC_FIBER 0x1001 46 #define E1000_DEV_ID_82543GC_COPPER 0x1004 47 #define E1000_DEV_ID_82544EI_COPPER 0x1008 48 #define E1000_DEV_ID_82544EI_FIBER 0x1009 49 #define E1000_DEV_ID_82544GC_COPPER 0x100C 50 #define E1000_DEV_ID_82544GC_LOM 0x100D 51 #define E1000_DEV_ID_82540EM 0x100E 52 #define E1000_DEV_ID_82540EM_LOM 0x1015 53 #define E1000_DEV_ID_82540EP_LOM 0x1016 54 #define E1000_DEV_ID_82540EP 0x1017 55 #define E1000_DEV_ID_82540EP_LP 0x101E 56 #define E1000_DEV_ID_82545EM_COPPER 0x100F 57 #define E1000_DEV_ID_82545EM_FIBER 0x1011 58 #define E1000_DEV_ID_82545GM_COPPER 0x1026 59 #define E1000_DEV_ID_82545GM_FIBER 0x1027 60 #define E1000_DEV_ID_82545GM_SERDES 0x1028 61 #define E1000_DEV_ID_82546EB_COPPER 0x1010 62 #define E1000_DEV_ID_82546EB_FIBER 0x1012 63 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 64 #define E1000_DEV_ID_82546GB_COPPER 0x1079 65 #define E1000_DEV_ID_82546GB_FIBER 0x107A 66 #define E1000_DEV_ID_82546GB_SERDES 0x107B 67 #define E1000_DEV_ID_82546GB_PCIE 0x108A 68 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 69 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 70 #define E1000_DEV_ID_82541EI 0x1013 71 #define E1000_DEV_ID_82541EI_MOBILE 0x1018 72 #define E1000_DEV_ID_82541ER_LOM 0x1014 73 #define E1000_DEV_ID_82541ER 0x1078 74 #define E1000_DEV_ID_82541GI 0x1076 75 #define E1000_DEV_ID_82541GI_LF 0x107C 76 #define E1000_DEV_ID_82541GI_MOBILE 0x1077 77 #define E1000_DEV_ID_82547EI 0x1019 78 #define E1000_DEV_ID_82547EI_MOBILE 0x101A 79 #define E1000_DEV_ID_82547GI 0x1075 80 #define E1000_DEV_ID_82571EB_COPPER 0x105E 81 #define E1000_DEV_ID_82571EB_FIBER 0x105F 82 #define E1000_DEV_ID_82571EB_SERDES 0x1060 83 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 84 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 85 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 86 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 87 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 88 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 89 #define E1000_DEV_ID_82571EB_QUAD_COPPER_BP 0x10A0 90 #define E1000_DEV_ID_82572EI_COPPER 0x107D 91 #define E1000_DEV_ID_82572EI_FIBER 0x107E 92 #define E1000_DEV_ID_82572EI_SERDES 0x107F 93 #define E1000_DEV_ID_82572EI 0x10B9 94 #define E1000_DEV_ID_82573E 0x108B 95 #define E1000_DEV_ID_82573E_IAMT 0x108C 96 #define E1000_DEV_ID_82573L 0x109A 97 #define E1000_DEV_ID_82574L 0x10D3 98 #define E1000_DEV_ID_82574LA 0x10F6 99 #define E1000_DEV_ID_82583V 0x150C 100 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 101 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 102 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 103 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 104 #define E1000_DEV_ID_ICH8_82567V_3 0x1501 105 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 106 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 107 #define E1000_DEV_ID_ICH8_IGP_C 0x104B 108 #define E1000_DEV_ID_ICH8_IFE 0x104C 109 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 110 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 111 #define E1000_DEV_ID_ICH8_IGP_M 0x104D 112 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF 113 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 114 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 115 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 116 #define E1000_DEV_ID_ICH9_BM 0x10E5 117 #define E1000_DEV_ID_ICH9_IGP_C 0x294C 118 #define E1000_DEV_ID_ICH9_IFE 0x10C0 119 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 120 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 121 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 122 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 123 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 124 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 125 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 126 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525 127 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 128 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 129 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 130 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 131 #define E1000_DEV_ID_PCH2_LV_LM 0x1502 132 #define E1000_DEV_ID_PCH2_LV_V 0x1503 133 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A 134 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B 135 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A 136 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559 137 #define E1000_DEV_ID_PCH_I218_LM2 0x15A0 138 #define E1000_DEV_ID_PCH_I218_V2 0x15A1 139 #define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */ 140 #define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */ 141 #define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* Sunrise Point PCH */ 142 #define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* Sunrise Point PCH */ 143 #define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* Sunrise Point-H PCH */ 144 #define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* Sunrise Point-H PCH */ 145 #define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LEWISBURG PCH */ 146 #define E1000_DEV_ID_PCH_SPT_I219_LM4 0x15D7 147 #define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8 148 #define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3 149 #define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6 150 #define E1000_DEV_ID_PCH_CNP_I219_LM6 0x15BD 151 #define E1000_DEV_ID_PCH_CNP_I219_V6 0x15BE 152 #define E1000_DEV_ID_PCH_CNP_I219_LM7 0x15BB 153 #define E1000_DEV_ID_PCH_CNP_I219_V7 0x15BC 154 #define E1000_DEV_ID_PCH_CNP_I219_LM8 0x15DF 155 #define E1000_DEV_ID_PCH_CNP_I219_V8 0x15E0 156 #define E1000_DEV_ID_PCH_CNP_I219_LM9 0x15E1 157 #define E1000_DEV_ID_PCH_CNP_I219_V9 0x15E2 158 #define E1000_DEV_ID_PCH_CNP_I219_LM10 0x0D4E 159 #define E1000_DEV_ID_PCH_CNP_I219_V10 0x0D4F 160 #define E1000_DEV_ID_PCH_CNP_I219_LM11 0x0D4C 161 #define E1000_DEV_ID_PCH_CNP_I219_V11 0x0D4D 162 #define E1000_DEV_ID_PCH_CNP_I219_LM12 0x0D53 163 #define E1000_DEV_ID_PCH_CNP_I219_V12 0x0D55 164 #define E1000_DEV_ID_PCH_CNP_I219_LM13 0x15FB 165 #define E1000_DEV_ID_PCH_CNP_I219_V13 0x15FC 166 #define E1000_DEV_ID_PCH_CNP_I219_LM14 0x15F9 167 #define E1000_DEV_ID_PCH_CNP_I219_V14 0x15FA 168 #define E1000_DEV_ID_82576 0x10C9 169 #define E1000_DEV_ID_82576_FIBER 0x10E6 170 #define E1000_DEV_ID_82576_SERDES 0x10E7 171 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 172 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526 173 #define E1000_DEV_ID_82576_NS 0x150A 174 #define E1000_DEV_ID_82576_NS_SERDES 0x1518 175 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D 176 #define E1000_DEV_ID_82576_VF 0x10CA 177 #define E1000_DEV_ID_82576_VF_HV 0x152D 178 #define E1000_DEV_ID_I350_VF 0x1520 179 #define E1000_DEV_ID_I350_VF_HV 0x152F 180 #define E1000_DEV_ID_82575EB_COPPER 0x10A7 181 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 182 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 183 #define E1000_DEV_ID_82580_COPPER 0x150E 184 #define E1000_DEV_ID_82580_FIBER 0x150F 185 #define E1000_DEV_ID_82580_SERDES 0x1510 186 #define E1000_DEV_ID_82580_SGMII 0x1511 187 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 188 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527 189 #define E1000_DEV_ID_I350_COPPER 0x1521 190 #define E1000_DEV_ID_I350_FIBER 0x1522 191 #define E1000_DEV_ID_I350_SERDES 0x1523 192 #define E1000_DEV_ID_I350_SGMII 0x1524 193 #define E1000_DEV_ID_I350_DA4 0x1546 194 #define E1000_DEV_ID_I210_COPPER 0x1533 195 #define E1000_DEV_ID_I210_COPPER_OEM1 0x1534 196 #define E1000_DEV_ID_I210_COPPER_IT 0x1535 197 #define E1000_DEV_ID_I210_FIBER 0x1536 198 #define E1000_DEV_ID_I210_SERDES 0x1537 199 #define E1000_DEV_ID_I210_SGMII 0x1538 200 #define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B 201 #define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C 202 #define E1000_DEV_ID_I211_COPPER 0x1539 203 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40 204 #define E1000_DEV_ID_I354_SGMII 0x1F41 205 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45 206 #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438 207 #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A 208 #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C 209 #define E1000_DEV_ID_DH89XXCC_SFP 0x0440 210 211 #define E1000_REVISION_0 0 212 #define E1000_REVISION_1 1 213 #define E1000_REVISION_2 2 214 #define E1000_REVISION_3 3 215 #define E1000_REVISION_4 4 216 217 #define E1000_FUNC_0 0 218 #define E1000_FUNC_1 1 219 #define E1000_FUNC_2 2 220 #define E1000_FUNC_3 3 221 222 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 223 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 224 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6 225 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9 226 227 enum e1000_mac_type { 228 e1000_undefined = 0, 229 e1000_82542, 230 e1000_82543, 231 e1000_82544, 232 e1000_82540, 233 e1000_82545, 234 e1000_82545_rev_3, 235 e1000_82546, 236 e1000_82546_rev_3, 237 e1000_82541, 238 e1000_82541_rev_2, 239 e1000_82547, 240 e1000_82547_rev_2, 241 e1000_82571, 242 e1000_82572, 243 e1000_82573, 244 e1000_82574, 245 e1000_82583, 246 e1000_80003es2lan, 247 e1000_ich8lan, 248 e1000_ich9lan, 249 e1000_ich10lan, 250 e1000_pchlan, 251 e1000_pch2lan, 252 e1000_pch_lpt, 253 e1000_pch_spt, 254 e1000_pch_cnp, 255 e1000_82575, 256 e1000_82576, 257 e1000_82580, 258 e1000_i350, 259 e1000_i354, 260 e1000_i210, 261 e1000_i211, 262 e1000_vfadapt, 263 e1000_vfadapt_i350, 264 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ 265 }; 266 267 enum e1000_media_type { 268 e1000_media_type_unknown = 0, 269 e1000_media_type_copper = 1, 270 e1000_media_type_fiber = 2, 271 e1000_media_type_internal_serdes = 3, 272 e1000_num_media_types 273 }; 274 275 enum e1000_nvm_type { 276 e1000_nvm_unknown = 0, 277 e1000_nvm_none, 278 e1000_nvm_eeprom_spi, 279 e1000_nvm_eeprom_microwire, 280 e1000_nvm_flash_hw, 281 e1000_nvm_invm, 282 e1000_nvm_flash_sw 283 }; 284 285 enum e1000_nvm_override { 286 e1000_nvm_override_none = 0, 287 e1000_nvm_override_spi_small, 288 e1000_nvm_override_spi_large, 289 e1000_nvm_override_microwire_small, 290 e1000_nvm_override_microwire_large 291 }; 292 293 enum e1000_phy_type { 294 e1000_phy_unknown = 0, 295 e1000_phy_none, 296 e1000_phy_m88, 297 e1000_phy_igp, 298 e1000_phy_igp_2, 299 e1000_phy_gg82563, 300 e1000_phy_igp_3, 301 e1000_phy_ife, 302 e1000_phy_bm, 303 e1000_phy_82578, 304 e1000_phy_82577, 305 e1000_phy_82579, 306 e1000_phy_i217, 307 e1000_phy_82580, 308 e1000_phy_vf, 309 e1000_phy_i210, 310 }; 311 312 enum e1000_bus_type { 313 e1000_bus_type_unknown = 0, 314 e1000_bus_type_pci, 315 e1000_bus_type_pcix, 316 e1000_bus_type_pci_express, 317 e1000_bus_type_reserved 318 }; 319 320 enum e1000_bus_speed { 321 e1000_bus_speed_unknown = 0, 322 e1000_bus_speed_33, 323 e1000_bus_speed_66, 324 e1000_bus_speed_100, 325 e1000_bus_speed_120, 326 e1000_bus_speed_133, 327 e1000_bus_speed_2500, 328 e1000_bus_speed_5000, 329 e1000_bus_speed_reserved 330 }; 331 332 enum e1000_bus_width { 333 e1000_bus_width_unknown = 0, 334 e1000_bus_width_pcie_x1, 335 e1000_bus_width_pcie_x2, 336 e1000_bus_width_pcie_x4 = 4, 337 e1000_bus_width_pcie_x8 = 8, 338 e1000_bus_width_32, 339 e1000_bus_width_64, 340 e1000_bus_width_reserved 341 }; 342 343 enum e1000_1000t_rx_status { 344 e1000_1000t_rx_status_not_ok = 0, 345 e1000_1000t_rx_status_ok, 346 e1000_1000t_rx_status_undefined = 0xFF 347 }; 348 349 enum e1000_rev_polarity { 350 e1000_rev_polarity_normal = 0, 351 e1000_rev_polarity_reversed, 352 e1000_rev_polarity_undefined = 0xFF 353 }; 354 355 enum e1000_fc_mode { 356 e1000_fc_none = 0, 357 e1000_fc_rx_pause, 358 e1000_fc_tx_pause, 359 e1000_fc_full, 360 e1000_fc_default = 0xFF 361 }; 362 363 enum e1000_ffe_config { 364 e1000_ffe_config_enabled = 0, 365 e1000_ffe_config_active, 366 e1000_ffe_config_blocked 367 }; 368 369 enum e1000_dsp_config { 370 e1000_dsp_config_disabled = 0, 371 e1000_dsp_config_enabled, 372 e1000_dsp_config_activated, 373 e1000_dsp_config_undefined = 0xFF 374 }; 375 376 enum e1000_ms_type { 377 e1000_ms_hw_default = 0, 378 e1000_ms_force_master, 379 e1000_ms_force_slave, 380 e1000_ms_auto 381 }; 382 383 enum e1000_smart_speed { 384 e1000_smart_speed_default = 0, 385 e1000_smart_speed_on, 386 e1000_smart_speed_off 387 }; 388 389 enum e1000_serdes_link_state { 390 e1000_serdes_link_down = 0, 391 e1000_serdes_link_autoneg_progress, 392 e1000_serdes_link_autoneg_complete, 393 e1000_serdes_link_forced_up 394 }; 395 396 #define __le16 u16 397 #define __le32 u32 398 #define __le64 u64 399 /* Receive Descriptor */ 400 struct e1000_rx_desc { 401 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 402 __le16 length; /* Length of data DMAed into data buffer */ 403 __le16 csum; /* Packet checksum */ 404 u8 status; /* Descriptor status */ 405 u8 errors; /* Descriptor Errors */ 406 __le16 special; 407 }; 408 409 /* Receive Descriptor - Extended */ 410 union e1000_rx_desc_extended { 411 struct { 412 __le64 buffer_addr; 413 __le64 reserved; 414 } read; 415 struct { 416 struct { 417 __le32 mrq; /* Multiple Rx Queues */ 418 union { 419 __le32 rss; /* RSS Hash */ 420 struct { 421 __le16 ip_id; /* IP id */ 422 __le16 csum; /* Packet Checksum */ 423 } csum_ip; 424 } hi_dword; 425 } lower; 426 struct { 427 __le32 status_error; /* ext status/error */ 428 __le16 length; 429 __le16 vlan; /* VLAN tag */ 430 } upper; 431 } wb; /* writeback */ 432 }; 433 434 #define MAX_PS_BUFFERS 4 435 436 /* Number of packet split data buffers (not including the header buffer) */ 437 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) 438 439 /* Receive Descriptor - Packet Split */ 440 union e1000_rx_desc_packet_split { 441 struct { 442 /* one buffer for protocol header(s), three data buffers */ 443 __le64 buffer_addr[MAX_PS_BUFFERS]; 444 } read; 445 struct { 446 struct { 447 __le32 mrq; /* Multiple Rx Queues */ 448 union { 449 __le32 rss; /* RSS Hash */ 450 struct { 451 __le16 ip_id; /* IP id */ 452 __le16 csum; /* Packet Checksum */ 453 } csum_ip; 454 } hi_dword; 455 } lower; 456 struct { 457 __le32 status_error; /* ext status/error */ 458 __le16 length0; /* length of buffer 0 */ 459 __le16 vlan; /* VLAN tag */ 460 } middle; 461 struct { 462 __le16 header_status; 463 /* length of buffers 1-3 */ 464 __le16 length[PS_PAGE_BUFFERS]; 465 } upper; 466 __le64 reserved; 467 } wb; /* writeback */ 468 }; 469 470 /* Transmit Descriptor */ 471 struct e1000_tx_desc { 472 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 473 union { 474 __le32 data; 475 struct { 476 __le16 length; /* Data buffer length */ 477 u8 cso; /* Checksum offset */ 478 u8 cmd; /* Descriptor control */ 479 } flags; 480 } lower; 481 union { 482 __le32 data; 483 struct { 484 u8 status; /* Descriptor status */ 485 u8 css; /* Checksum start */ 486 __le16 special; 487 } fields; 488 } upper; 489 }; 490 491 /* Offload Context Descriptor */ 492 struct e1000_context_desc { 493 union { 494 __le32 ip_config; 495 struct { 496 u8 ipcss; /* IP checksum start */ 497 u8 ipcso; /* IP checksum offset */ 498 __le16 ipcse; /* IP checksum end */ 499 } ip_fields; 500 } lower_setup; 501 union { 502 __le32 tcp_config; 503 struct { 504 u8 tucss; /* TCP checksum start */ 505 u8 tucso; /* TCP checksum offset */ 506 __le16 tucse; /* TCP checksum end */ 507 } tcp_fields; 508 } upper_setup; 509 __le32 cmd_and_length; 510 union { 511 __le32 data; 512 struct { 513 u8 status; /* Descriptor status */ 514 u8 hdr_len; /* Header length */ 515 __le16 mss; /* Maximum segment size */ 516 } fields; 517 } tcp_seg_setup; 518 }; 519 520 /* Offload data descriptor */ 521 struct e1000_data_desc { 522 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 523 union { 524 __le32 data; 525 struct { 526 __le16 length; /* Data buffer length */ 527 u8 typ_len_ext; 528 u8 cmd; 529 } flags; 530 } lower; 531 union { 532 __le32 data; 533 struct { 534 u8 status; /* Descriptor status */ 535 u8 popts; /* Packet Options */ 536 __le16 special; 537 } fields; 538 } upper; 539 }; 540 541 /* Statistics counters collected by the MAC */ 542 struct e1000_hw_stats { 543 u64 crcerrs; 544 u64 algnerrc; 545 u64 symerrs; 546 u64 rxerrc; 547 u64 mpc; 548 u64 scc; 549 u64 ecol; 550 u64 mcc; 551 u64 latecol; 552 u64 colc; 553 u64 dc; 554 u64 tncrs; 555 u64 sec; 556 u64 cexterr; 557 u64 rlec; 558 u64 xonrxc; 559 u64 xontxc; 560 u64 xoffrxc; 561 u64 xofftxc; 562 u64 fcruc; 563 u64 prc64; 564 u64 prc127; 565 u64 prc255; 566 u64 prc511; 567 u64 prc1023; 568 u64 prc1522; 569 u64 gprc; 570 u64 bprc; 571 u64 mprc; 572 u64 gptc; 573 u64 gorc; 574 u64 gotc; 575 u64 rnbc; 576 u64 ruc; 577 u64 rfc; 578 u64 roc; 579 u64 rjc; 580 u64 mgprc; 581 u64 mgpdc; 582 u64 mgptc; 583 u64 tor; 584 u64 tot; 585 u64 tpr; 586 u64 tpt; 587 u64 ptc64; 588 u64 ptc127; 589 u64 ptc255; 590 u64 ptc511; 591 u64 ptc1023; 592 u64 ptc1522; 593 u64 mptc; 594 u64 bptc; 595 u64 tsctc; 596 u64 tsctfc; 597 u64 iac; 598 u64 icrxptc; 599 u64 icrxatc; 600 u64 ictxptc; 601 u64 ictxatc; 602 u64 ictxqec; 603 u64 ictxqmtc; 604 u64 icrxdmtc; 605 u64 icrxoc; 606 u64 cbtmpc; 607 u64 htdpmc; 608 u64 cbrdpc; 609 u64 cbrmpc; 610 u64 rpthc; 611 u64 hgptc; 612 u64 htcbdpc; 613 u64 hgorc; 614 u64 hgotc; 615 u64 lenerrs; 616 u64 scvpc; 617 u64 hrmpc; 618 u64 doosync; 619 u64 o2bgptc; 620 u64 o2bspc; 621 u64 b2ospc; 622 u64 b2ogprc; 623 }; 624 625 struct e1000_vf_stats { 626 u64 base_gprc; 627 u64 base_gptc; 628 u64 base_gorc; 629 u64 base_gotc; 630 u64 base_mprc; 631 u64 base_gotlbc; 632 u64 base_gptlbc; 633 u64 base_gorlbc; 634 u64 base_gprlbc; 635 636 u32 last_gprc; 637 u32 last_gptc; 638 u32 last_gorc; 639 u32 last_gotc; 640 u32 last_mprc; 641 u32 last_gotlbc; 642 u32 last_gptlbc; 643 u32 last_gorlbc; 644 u32 last_gprlbc; 645 646 u64 gprc; 647 u64 gptc; 648 u64 gorc; 649 u64 gotc; 650 u64 mprc; 651 u64 gotlbc; 652 u64 gptlbc; 653 u64 gorlbc; 654 u64 gprlbc; 655 }; 656 657 struct e1000_phy_stats { 658 u32 idle_errors; 659 u32 receive_errors; 660 }; 661 662 struct e1000_host_mng_dhcp_cookie { 663 u32 signature; 664 u8 status; 665 u8 reserved0; 666 u16 vlan_id; 667 u32 reserved1; 668 u16 reserved2; 669 u8 reserved3; 670 u8 checksum; 671 }; 672 673 /* Host Interface "Rev 1" */ 674 struct e1000_host_command_header { 675 u8 command_id; 676 u8 command_length; 677 u8 command_options; 678 u8 checksum; 679 }; 680 681 #define E1000_HI_MAX_DATA_LENGTH 252 682 struct e1000_host_command_info { 683 struct e1000_host_command_header command_header; 684 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 685 }; 686 687 /* Host Interface "Rev 2" */ 688 struct e1000_host_mng_command_header { 689 u8 command_id; 690 u8 checksum; 691 u16 reserved1; 692 u16 reserved2; 693 u16 command_length; 694 }; 695 696 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 697 struct e1000_host_mng_command_info { 698 struct e1000_host_mng_command_header command_header; 699 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 700 }; 701 702 #include "e1000_mac.h" 703 #include "e1000_phy.h" 704 #include "e1000_nvm.h" 705 #include "e1000_manage.h" 706 #include "e1000_mbx.h" 707 708 /* Function pointers for the MAC. */ 709 struct e1000_mac_operations { 710 s32 (*init_params)(struct e1000_hw *); 711 s32 (*id_led_init)(struct e1000_hw *); 712 s32 (*blink_led)(struct e1000_hw *); 713 bool (*check_mng_mode)(struct e1000_hw *); 714 s32 (*check_for_link)(struct e1000_hw *); 715 s32 (*cleanup_led)(struct e1000_hw *); 716 void (*clear_hw_cntrs)(struct e1000_hw *); 717 void (*clear_vfta)(struct e1000_hw *); 718 s32 (*get_bus_info)(struct e1000_hw *); 719 void (*set_lan_id)(struct e1000_hw *); 720 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 721 s32 (*led_on)(struct e1000_hw *); 722 s32 (*led_off)(struct e1000_hw *); 723 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 724 s32 (*reset_hw)(struct e1000_hw *); 725 s32 (*init_hw)(struct e1000_hw *); 726 void (*shutdown_serdes)(struct e1000_hw *); 727 void (*power_up_serdes)(struct e1000_hw *); 728 s32 (*setup_link)(struct e1000_hw *); 729 s32 (*setup_physical_interface)(struct e1000_hw *); 730 s32 (*setup_led)(struct e1000_hw *); 731 void (*write_vfta)(struct e1000_hw *, u32, u32); 732 void (*config_collision_dist)(struct e1000_hw *); 733 int (*rar_set)(struct e1000_hw *, u8*, u32); 734 s32 (*read_mac_addr)(struct e1000_hw *); 735 s32 (*validate_mdi_setting)(struct e1000_hw *); 736 s32 (*set_obff_timer)(struct e1000_hw *, u32); 737 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16); 738 void (*release_swfw_sync)(struct e1000_hw *, u16); 739 }; 740 741 /* When to use various PHY register access functions: 742 * 743 * Func Caller 744 * Function Does Does When to use 745 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 746 * X_reg L,P,A n/a for simple PHY reg accesses 747 * X_reg_locked P,A L for multiple accesses of different regs 748 * on different pages 749 * X_reg_page A L,P for multiple accesses of different regs 750 * on the same page 751 * 752 * Where X=[read|write], L=locking, P=sets page, A=register access 753 * 754 */ 755 struct e1000_phy_operations { 756 s32 (*init_params)(struct e1000_hw *); 757 s32 (*acquire)(struct e1000_hw *); 758 s32 (*cfg_on_link_up)(struct e1000_hw *); 759 s32 (*check_polarity)(struct e1000_hw *); 760 s32 (*check_reset_block)(struct e1000_hw *); 761 s32 (*commit)(struct e1000_hw *); 762 s32 (*force_speed_duplex)(struct e1000_hw *); 763 s32 (*get_cfg_done)(struct e1000_hw *hw); 764 s32 (*get_cable_length)(struct e1000_hw *); 765 s32 (*get_info)(struct e1000_hw *); 766 s32 (*set_page)(struct e1000_hw *, u16); 767 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 768 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 769 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *); 770 void (*release)(struct e1000_hw *); 771 s32 (*reset)(struct e1000_hw *); 772 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 773 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 774 s32 (*write_reg)(struct e1000_hw *, u32, u16); 775 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 776 s32 (*write_reg_page)(struct e1000_hw *, u32, u16); 777 void (*power_up)(struct e1000_hw *); 778 void (*power_down)(struct e1000_hw *); 779 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *); 780 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8); 781 }; 782 783 /* Function pointers for the NVM. */ 784 struct e1000_nvm_operations { 785 s32 (*init_params)(struct e1000_hw *); 786 s32 (*acquire)(struct e1000_hw *); 787 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 788 void (*release)(struct e1000_hw *); 789 void (*reload)(struct e1000_hw *); 790 s32 (*update)(struct e1000_hw *); 791 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 792 s32 (*validate)(struct e1000_hw *); 793 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 794 }; 795 796 struct e1000_mac_info { 797 struct e1000_mac_operations ops; 798 u8 addr[ETH_ADDR_LEN]; 799 u8 perm_addr[ETH_ADDR_LEN]; 800 801 enum e1000_mac_type type; 802 803 u32 collision_delta; 804 u32 ledctl_default; 805 u32 ledctl_mode1; 806 u32 ledctl_mode2; 807 u32 mc_filter_type; 808 u32 tx_packet_delta; 809 u32 txcw; 810 811 u16 current_ifs_val; 812 u16 ifs_max_val; 813 u16 ifs_min_val; 814 u16 ifs_ratio; 815 u16 ifs_step_size; 816 u16 mta_reg_count; 817 u16 uta_reg_count; 818 819 /* Maximum size of the MTA register table in all supported adapters */ 820 #define MAX_MTA_REG 128 821 u32 mta_shadow[MAX_MTA_REG]; 822 u16 rar_entry_count; 823 824 u8 forced_speed_duplex; 825 826 bool adaptive_ifs; 827 bool has_fwsm; 828 bool arc_subsystem_valid; 829 bool asf_firmware_present; 830 bool autoneg; 831 bool autoneg_failed; 832 bool get_link_status; 833 bool in_ifs_mode; 834 bool report_tx_early; 835 enum e1000_serdes_link_state serdes_link_state; 836 bool serdes_has_link; 837 bool tx_pkt_filtering; 838 u32 max_frame_size; 839 }; 840 841 struct e1000_phy_info { 842 struct e1000_phy_operations ops; 843 enum e1000_phy_type type; 844 845 enum e1000_1000t_rx_status local_rx; 846 enum e1000_1000t_rx_status remote_rx; 847 enum e1000_ms_type ms_type; 848 enum e1000_ms_type original_ms_type; 849 enum e1000_rev_polarity cable_polarity; 850 enum e1000_smart_speed smart_speed; 851 852 u32 addr; 853 u32 id; 854 u32 reset_delay_us; /* in usec */ 855 u32 revision; 856 857 enum e1000_media_type media_type; 858 859 u16 autoneg_advertised; 860 u16 autoneg_mask; 861 u16 cable_length; 862 u16 max_cable_length; 863 u16 min_cable_length; 864 865 u8 mdix; 866 867 bool disable_polarity_correction; 868 bool is_mdix; 869 bool polarity_correction; 870 bool speed_downgraded; 871 bool autoneg_wait_to_complete; 872 }; 873 874 struct e1000_nvm_info { 875 struct e1000_nvm_operations ops; 876 enum e1000_nvm_type type; 877 enum e1000_nvm_override override; 878 879 u32 flash_bank_size; 880 u32 flash_base_addr; 881 882 u16 word_size; 883 u16 delay_usec; 884 u16 address_bits; 885 u16 opcode_bits; 886 u16 page_size; 887 }; 888 889 struct e1000_bus_info { 890 enum e1000_bus_type type; 891 enum e1000_bus_speed speed; 892 enum e1000_bus_width width; 893 894 u16 func; 895 u16 pci_cmd_word; 896 }; 897 898 struct e1000_fc_info { 899 u32 high_water; /* Flow control high-water mark */ 900 u32 low_water; /* Flow control low-water mark */ 901 u16 pause_time; /* Flow control pause timer */ 902 u16 refresh_time; /* Flow control refresh timer */ 903 bool send_xon; /* Flow control send XON */ 904 bool strict_ieee; /* Strict IEEE mode */ 905 enum e1000_fc_mode current_mode; /* FC mode in effect */ 906 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 907 }; 908 909 struct e1000_dev_spec_82541 { 910 enum e1000_dsp_config dsp_config; 911 enum e1000_ffe_config ffe_config; 912 u16 spd_default; 913 bool phy_init_script; 914 }; 915 916 struct e1000_dev_spec_82542 { 917 bool dma_fairness; 918 }; 919 920 struct e1000_dev_spec_82543 { 921 u32 tbi_compatibility; 922 bool dma_fairness; 923 bool init_phy_disabled; 924 }; 925 926 struct e1000_dev_spec_82571 { 927 bool laa_is_present; 928 u32 smb_counter; 929 }; 930 931 struct e1000_dev_spec_80003es2lan { 932 bool mdic_wa_enable; 933 }; 934 935 struct e1000_shadow_ram { 936 u16 value; 937 bool modified; 938 }; 939 940 #define E1000_SHADOW_RAM_WORDS 2048 941 942 /* I218 PHY Ultra Low Power (ULP) states */ 943 enum e1000_ulp_state { 944 e1000_ulp_state_unknown, 945 e1000_ulp_state_off, 946 e1000_ulp_state_on, 947 }; 948 949 struct e1000_mbx_operations { 950 s32 (*init_params)(struct e1000_hw *hw); 951 s32 (*read)(struct e1000_hw *, u32 *, u16, u16); 952 s32 (*write)(struct e1000_hw *, u32 *, u16, u16); 953 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16); 954 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16); 955 s32 (*check_for_msg)(struct e1000_hw *, u16); 956 s32 (*check_for_ack)(struct e1000_hw *, u16); 957 s32 (*check_for_rst)(struct e1000_hw *, u16); 958 }; 959 960 struct e1000_mbx_stats { 961 u32 msgs_tx; 962 u32 msgs_rx; 963 964 u32 acks; 965 u32 reqs; 966 u32 rsts; 967 }; 968 969 struct e1000_mbx_info { 970 struct e1000_mbx_operations ops; 971 struct e1000_mbx_stats stats; 972 u32 timeout; 973 u32 usec_delay; 974 u16 size; 975 }; 976 977 struct e1000_dev_spec_82575 { 978 bool sgmii_active; 979 bool global_device_reset; 980 bool eee_disable; 981 bool module_plugged; 982 bool clear_semaphore_once; 983 u32 mtu; 984 struct sfp_e1000_flags eth_flags; 985 u8 media_port; 986 bool media_changed; 987 }; 988 989 struct e1000_dev_spec_vf { 990 u32 vf_number; 991 u32 v2p_mailbox; 992 }; 993 994 struct e1000_dev_spec_ich8lan { 995 bool kmrn_lock_loss_workaround_enabled; 996 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; 997 bool nvm_k1_enabled; 998 bool disable_k1_off; 999 bool eee_disable; 1000 u16 eee_lp_ability; 1001 enum e1000_ulp_state ulp_state; 1002 bool ulp_capability_disabled; 1003 bool during_suspend_flow; 1004 bool during_dpg_exit; 1005 }; 1006 1007 struct e1000_hw { 1008 void *back; 1009 1010 u8 *hw_addr; 1011 u8 *flash_address; 1012 unsigned long io_base; 1013 1014 struct e1000_mac_info mac; 1015 struct e1000_fc_info fc; 1016 struct e1000_phy_info phy; 1017 struct e1000_nvm_info nvm; 1018 struct e1000_bus_info bus; 1019 struct e1000_mbx_info mbx; 1020 struct e1000_host_mng_dhcp_cookie mng_cookie; 1021 1022 union { 1023 struct e1000_dev_spec_82541 _82541; 1024 struct e1000_dev_spec_82542 _82542; 1025 struct e1000_dev_spec_82543 _82543; 1026 struct e1000_dev_spec_82571 _82571; 1027 struct e1000_dev_spec_80003es2lan _80003es2lan; 1028 struct e1000_dev_spec_ich8lan ich8lan; 1029 struct e1000_dev_spec_82575 _82575; 1030 struct e1000_dev_spec_vf vf; 1031 } dev_spec; 1032 1033 u16 device_id; 1034 u16 subsystem_vendor_id; 1035 u16 subsystem_device_id; 1036 u16 vendor_id; 1037 1038 u8 revision_id; 1039 }; 1040 1041 #include "e1000_82541.h" 1042 #include "e1000_82543.h" 1043 #include "e1000_82571.h" 1044 #include "e1000_80003es2lan.h" 1045 #include "e1000_ich8lan.h" 1046 #include "e1000_82575.h" 1047 #include "e1000_i210.h" 1048 1049 /* These functions must be implemented by drivers */ 1050 void e1000_pci_clear_mwi(struct e1000_hw *hw); 1051 void e1000_pci_set_mwi(struct e1000_hw *hw); 1052 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1053 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1054 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1055 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1056 1057 #endif 1058