1 /****************************************************************************** 2 3 Copyright (c) 2001-2014, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD:$*/ 34 35 #ifndef _E1000_HW_H_ 36 #define _E1000_HW_H_ 37 38 #include "e1000_osdep.h" 39 #include "e1000_regs.h" 40 #include "e1000_defines.h" 41 42 struct e1000_hw; 43 44 #ifndef NO_82542_SUPPORT 45 #define E1000_DEV_ID_82542 0x1000 46 #endif 47 #define E1000_DEV_ID_82543GC_FIBER 0x1001 48 #define E1000_DEV_ID_82543GC_COPPER 0x1004 49 #define E1000_DEV_ID_82544EI_COPPER 0x1008 50 #define E1000_DEV_ID_82544EI_FIBER 0x1009 51 #define E1000_DEV_ID_82544GC_COPPER 0x100C 52 #define E1000_DEV_ID_82544GC_LOM 0x100D 53 #define E1000_DEV_ID_82540EM 0x100E 54 #define E1000_DEV_ID_82540EM_LOM 0x1015 55 #define E1000_DEV_ID_82540EP_LOM 0x1016 56 #define E1000_DEV_ID_82540EP 0x1017 57 #define E1000_DEV_ID_82540EP_LP 0x101E 58 #define E1000_DEV_ID_82545EM_COPPER 0x100F 59 #define E1000_DEV_ID_82545EM_FIBER 0x1011 60 #define E1000_DEV_ID_82545GM_COPPER 0x1026 61 #define E1000_DEV_ID_82545GM_FIBER 0x1027 62 #define E1000_DEV_ID_82545GM_SERDES 0x1028 63 #define E1000_DEV_ID_82546EB_COPPER 0x1010 64 #define E1000_DEV_ID_82546EB_FIBER 0x1012 65 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 66 #define E1000_DEV_ID_82546GB_COPPER 0x1079 67 #define E1000_DEV_ID_82546GB_FIBER 0x107A 68 #define E1000_DEV_ID_82546GB_SERDES 0x107B 69 #define E1000_DEV_ID_82546GB_PCIE 0x108A 70 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 71 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 72 #define E1000_DEV_ID_82541EI 0x1013 73 #define E1000_DEV_ID_82541EI_MOBILE 0x1018 74 #define E1000_DEV_ID_82541ER_LOM 0x1014 75 #define E1000_DEV_ID_82541ER 0x1078 76 #define E1000_DEV_ID_82541GI 0x1076 77 #define E1000_DEV_ID_82541GI_LF 0x107C 78 #define E1000_DEV_ID_82541GI_MOBILE 0x1077 79 #define E1000_DEV_ID_82547EI 0x1019 80 #define E1000_DEV_ID_82547EI_MOBILE 0x101A 81 #define E1000_DEV_ID_82547GI 0x1075 82 #define E1000_DEV_ID_82571EB_COPPER 0x105E 83 #define E1000_DEV_ID_82571EB_FIBER 0x105F 84 #define E1000_DEV_ID_82571EB_SERDES 0x1060 85 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 86 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 87 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 88 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 89 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 90 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 91 #define E1000_DEV_ID_82571EB_QUAD_COPPER_BP 0x10A0 92 #define E1000_DEV_ID_82572EI_COPPER 0x107D 93 #define E1000_DEV_ID_82572EI_FIBER 0x107E 94 #define E1000_DEV_ID_82572EI_SERDES 0x107F 95 #define E1000_DEV_ID_82572EI 0x10B9 96 #define E1000_DEV_ID_82573E 0x108B 97 #define E1000_DEV_ID_82573E_IAMT 0x108C 98 #define E1000_DEV_ID_82573L 0x109A 99 #define E1000_DEV_ID_82574L 0x10D3 100 #define E1000_DEV_ID_82574LA 0x10F6 101 #define E1000_DEV_ID_82583V 0x150C 102 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 103 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 104 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 105 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 106 #define E1000_DEV_ID_ICH8_82567V_3 0x1501 107 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 108 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 109 #define E1000_DEV_ID_ICH8_IGP_C 0x104B 110 #define E1000_DEV_ID_ICH8_IFE 0x104C 111 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 112 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 113 #define E1000_DEV_ID_ICH8_IGP_M 0x104D 114 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF 115 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 116 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 117 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 118 #define E1000_DEV_ID_ICH9_BM 0x10E5 119 #define E1000_DEV_ID_ICH9_IGP_C 0x294C 120 #define E1000_DEV_ID_ICH9_IFE 0x10C0 121 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 122 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 123 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 124 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 125 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 126 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 127 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 128 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525 129 130 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 131 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 132 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 133 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 134 #define E1000_DEV_ID_PCH2_LV_LM 0x1502 135 #define E1000_DEV_ID_PCH2_LV_V 0x1503 136 137 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A 138 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B 139 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A 140 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559 141 #define E1000_DEV_ID_PCH_I218_LM2 0x15A0 142 #define E1000_DEV_ID_PCH_I218_V2 0x15A1 143 #define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */ 144 #define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */ 145 #define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* SPT */ 146 #define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 147 #define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 148 #define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 149 #define E1000_DEV_ID_PCH_SPT_I219_LM3 0x15B9 /* LEWISBURG PCH */ 150 #define E1000_DEV_ID_PCH_SPT_I219_LM4 0x15D7 151 #define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8 152 #define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3 153 #define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6 154 155 #define E1000_DEV_ID_82576 0x10C9 156 #define E1000_DEV_ID_82576_FIBER 0x10E6 157 #define E1000_DEV_ID_82576_SERDES 0x10E7 158 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 159 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526 160 #define E1000_DEV_ID_82576_NS 0x150A 161 #define E1000_DEV_ID_82576_NS_SERDES 0x1518 162 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D 163 #define E1000_DEV_ID_82576_VF 0x10CA 164 #define E1000_DEV_ID_82576_VF_HV 0x152D 165 #define E1000_DEV_ID_I350_VF 0x1520 166 #define E1000_DEV_ID_I350_VF_HV 0x152F 167 #define E1000_DEV_ID_82575EB_COPPER 0x10A7 168 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 169 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 170 #define E1000_DEV_ID_82580_COPPER 0x150E 171 #define E1000_DEV_ID_82580_FIBER 0x150F 172 #define E1000_DEV_ID_82580_SERDES 0x1510 173 #define E1000_DEV_ID_82580_SGMII 0x1511 174 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 175 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527 176 #define E1000_DEV_ID_I350_COPPER 0x1521 177 #define E1000_DEV_ID_I350_FIBER 0x1522 178 #define E1000_DEV_ID_I350_SERDES 0x1523 179 #define E1000_DEV_ID_I350_SGMII 0x1524 180 #define E1000_DEV_ID_I350_DA4 0x1546 181 #define E1000_DEV_ID_I210_COPPER 0x1533 182 #define E1000_DEV_ID_I210_COPPER_OEM1 0x1534 183 #define E1000_DEV_ID_I210_COPPER_IT 0x1535 184 #define E1000_DEV_ID_I210_FIBER 0x1536 185 #define E1000_DEV_ID_I210_SERDES 0x1537 186 #define E1000_DEV_ID_I210_SGMII 0x1538 187 #define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B 188 #define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C 189 #define E1000_DEV_ID_I211_COPPER 0x1539 190 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40 191 #define E1000_DEV_ID_I354_SGMII 0x1F41 192 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45 193 #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438 194 #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A 195 #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C 196 #define E1000_DEV_ID_DH89XXCC_SFP 0x0440 197 198 #define E1000_REVISION_0 0 199 #define E1000_REVISION_1 1 200 #define E1000_REVISION_2 2 201 #define E1000_REVISION_3 3 202 #define E1000_REVISION_4 4 203 204 #define E1000_FUNC_0 0 205 #define E1000_FUNC_1 1 206 #define E1000_FUNC_2 2 207 #define E1000_FUNC_3 3 208 209 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 210 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 211 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6 212 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9 213 214 enum e1000_mac_type { 215 e1000_undefined = 0, 216 #ifndef NO_82542_SUPPORT 217 e1000_82542, 218 #endif 219 e1000_82543, 220 e1000_82544, 221 e1000_82540, 222 e1000_82545, 223 e1000_82545_rev_3, 224 e1000_82546, 225 e1000_82546_rev_3, 226 e1000_82541, 227 e1000_82541_rev_2, 228 e1000_82547, 229 e1000_82547_rev_2, 230 e1000_82571, 231 e1000_82572, 232 e1000_82573, 233 e1000_82574, 234 e1000_82583, 235 e1000_80003es2lan, 236 e1000_ich8lan, 237 e1000_ich9lan, 238 e1000_ich10lan, 239 e1000_pchlan, 240 e1000_pch2lan, 241 e1000_pch_lpt, 242 e1000_pch_spt, 243 e1000_82575, 244 e1000_82576, 245 e1000_82580, 246 e1000_i350, 247 e1000_i354, 248 e1000_i210, 249 e1000_i211, 250 e1000_vfadapt, 251 e1000_vfadapt_i350, 252 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ 253 }; 254 255 enum e1000_media_type { 256 e1000_media_type_unknown = 0, 257 e1000_media_type_copper = 1, 258 e1000_media_type_fiber = 2, 259 e1000_media_type_internal_serdes = 3, 260 e1000_num_media_types 261 }; 262 263 enum e1000_nvm_type { 264 e1000_nvm_unknown = 0, 265 e1000_nvm_none, 266 e1000_nvm_eeprom_spi, 267 e1000_nvm_eeprom_microwire, 268 e1000_nvm_flash_hw, 269 e1000_nvm_invm, 270 e1000_nvm_flash_sw 271 }; 272 273 enum e1000_nvm_override { 274 e1000_nvm_override_none = 0, 275 e1000_nvm_override_spi_small, 276 e1000_nvm_override_spi_large, 277 e1000_nvm_override_microwire_small, 278 e1000_nvm_override_microwire_large 279 }; 280 281 enum e1000_phy_type { 282 e1000_phy_unknown = 0, 283 e1000_phy_none, 284 e1000_phy_m88, 285 e1000_phy_igp, 286 e1000_phy_igp_2, 287 e1000_phy_gg82563, 288 e1000_phy_igp_3, 289 e1000_phy_ife, 290 e1000_phy_bm, 291 e1000_phy_82578, 292 e1000_phy_82577, 293 e1000_phy_82579, 294 e1000_phy_i217, 295 e1000_phy_82580, 296 e1000_phy_vf, 297 e1000_phy_i210, 298 }; 299 300 enum e1000_bus_type { 301 e1000_bus_type_unknown = 0, 302 e1000_bus_type_pci, 303 e1000_bus_type_pcix, 304 e1000_bus_type_pci_express, 305 e1000_bus_type_reserved 306 }; 307 308 enum e1000_bus_speed { 309 e1000_bus_speed_unknown = 0, 310 e1000_bus_speed_33, 311 e1000_bus_speed_66, 312 e1000_bus_speed_100, 313 e1000_bus_speed_120, 314 e1000_bus_speed_133, 315 e1000_bus_speed_2500, 316 e1000_bus_speed_5000, 317 e1000_bus_speed_reserved 318 }; 319 320 enum e1000_bus_width { 321 e1000_bus_width_unknown = 0, 322 e1000_bus_width_pcie_x1, 323 e1000_bus_width_pcie_x2, 324 e1000_bus_width_pcie_x4 = 4, 325 e1000_bus_width_pcie_x8 = 8, 326 e1000_bus_width_32, 327 e1000_bus_width_64, 328 e1000_bus_width_reserved 329 }; 330 331 enum e1000_1000t_rx_status { 332 e1000_1000t_rx_status_not_ok = 0, 333 e1000_1000t_rx_status_ok, 334 e1000_1000t_rx_status_undefined = 0xFF 335 }; 336 337 enum e1000_rev_polarity { 338 e1000_rev_polarity_normal = 0, 339 e1000_rev_polarity_reversed, 340 e1000_rev_polarity_undefined = 0xFF 341 }; 342 343 enum e1000_fc_mode { 344 e1000_fc_none = 0, 345 e1000_fc_rx_pause, 346 e1000_fc_tx_pause, 347 e1000_fc_full, 348 e1000_fc_default = 0xFF 349 }; 350 351 enum e1000_ffe_config { 352 e1000_ffe_config_enabled = 0, 353 e1000_ffe_config_active, 354 e1000_ffe_config_blocked 355 }; 356 357 enum e1000_dsp_config { 358 e1000_dsp_config_disabled = 0, 359 e1000_dsp_config_enabled, 360 e1000_dsp_config_activated, 361 e1000_dsp_config_undefined = 0xFF 362 }; 363 364 enum e1000_ms_type { 365 e1000_ms_hw_default = 0, 366 e1000_ms_force_master, 367 e1000_ms_force_slave, 368 e1000_ms_auto 369 }; 370 371 enum e1000_smart_speed { 372 e1000_smart_speed_default = 0, 373 e1000_smart_speed_on, 374 e1000_smart_speed_off 375 }; 376 377 enum e1000_serdes_link_state { 378 e1000_serdes_link_down = 0, 379 e1000_serdes_link_autoneg_progress, 380 e1000_serdes_link_autoneg_complete, 381 e1000_serdes_link_forced_up 382 }; 383 384 #define __le16 u16 385 #define __le32 u32 386 #define __le64 u64 387 /* Receive Descriptor */ 388 struct e1000_rx_desc { 389 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 390 __le16 length; /* Length of data DMAed into data buffer */ 391 __le16 csum; /* Packet checksum */ 392 u8 status; /* Descriptor status */ 393 u8 errors; /* Descriptor Errors */ 394 __le16 special; 395 }; 396 397 /* Receive Descriptor - Extended */ 398 union e1000_rx_desc_extended { 399 struct { 400 __le64 buffer_addr; 401 __le64 reserved; 402 } read; 403 struct { 404 struct { 405 __le32 mrq; /* Multiple Rx Queues */ 406 union { 407 __le32 rss; /* RSS Hash */ 408 struct { 409 __le16 ip_id; /* IP id */ 410 __le16 csum; /* Packet Checksum */ 411 } csum_ip; 412 } hi_dword; 413 } lower; 414 struct { 415 __le32 status_error; /* ext status/error */ 416 __le16 length; 417 __le16 vlan; /* VLAN tag */ 418 } upper; 419 } wb; /* writeback */ 420 }; 421 422 #define MAX_PS_BUFFERS 4 423 424 /* Number of packet split data buffers (not including the header buffer) */ 425 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) 426 427 /* Receive Descriptor - Packet Split */ 428 union e1000_rx_desc_packet_split { 429 struct { 430 /* one buffer for protocol header(s), three data buffers */ 431 __le64 buffer_addr[MAX_PS_BUFFERS]; 432 } read; 433 struct { 434 struct { 435 __le32 mrq; /* Multiple Rx Queues */ 436 union { 437 __le32 rss; /* RSS Hash */ 438 struct { 439 __le16 ip_id; /* IP id */ 440 __le16 csum; /* Packet Checksum */ 441 } csum_ip; 442 } hi_dword; 443 } lower; 444 struct { 445 __le32 status_error; /* ext status/error */ 446 __le16 length0; /* length of buffer 0 */ 447 __le16 vlan; /* VLAN tag */ 448 } middle; 449 struct { 450 __le16 header_status; 451 /* length of buffers 1-3 */ 452 __le16 length[PS_PAGE_BUFFERS]; 453 } upper; 454 __le64 reserved; 455 } wb; /* writeback */ 456 }; 457 458 /* Transmit Descriptor */ 459 struct e1000_tx_desc { 460 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 461 union { 462 __le32 data; 463 struct { 464 __le16 length; /* Data buffer length */ 465 u8 cso; /* Checksum offset */ 466 u8 cmd; /* Descriptor control */ 467 } flags; 468 } lower; 469 union { 470 __le32 data; 471 struct { 472 u8 status; /* Descriptor status */ 473 u8 css; /* Checksum start */ 474 __le16 special; 475 } fields; 476 } upper; 477 }; 478 479 /* Offload Context Descriptor */ 480 struct e1000_context_desc { 481 union { 482 __le32 ip_config; 483 struct { 484 u8 ipcss; /* IP checksum start */ 485 u8 ipcso; /* IP checksum offset */ 486 __le16 ipcse; /* IP checksum end */ 487 } ip_fields; 488 } lower_setup; 489 union { 490 __le32 tcp_config; 491 struct { 492 u8 tucss; /* TCP checksum start */ 493 u8 tucso; /* TCP checksum offset */ 494 __le16 tucse; /* TCP checksum end */ 495 } tcp_fields; 496 } upper_setup; 497 __le32 cmd_and_length; 498 union { 499 __le32 data; 500 struct { 501 u8 status; /* Descriptor status */ 502 u8 hdr_len; /* Header length */ 503 __le16 mss; /* Maximum segment size */ 504 } fields; 505 } tcp_seg_setup; 506 }; 507 508 /* Offload data descriptor */ 509 struct e1000_data_desc { 510 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 511 union { 512 __le32 data; 513 struct { 514 __le16 length; /* Data buffer length */ 515 u8 typ_len_ext; 516 u8 cmd; 517 } flags; 518 } lower; 519 union { 520 __le32 data; 521 struct { 522 u8 status; /* Descriptor status */ 523 u8 popts; /* Packet Options */ 524 __le16 special; 525 } fields; 526 } upper; 527 }; 528 529 /* Statistics counters collected by the MAC */ 530 struct e1000_hw_stats { 531 u64 crcerrs; 532 u64 algnerrc; 533 u64 symerrs; 534 u64 rxerrc; 535 u64 mpc; 536 u64 scc; 537 u64 ecol; 538 u64 mcc; 539 u64 latecol; 540 u64 colc; 541 u64 dc; 542 u64 tncrs; 543 u64 sec; 544 u64 cexterr; 545 u64 rlec; 546 u64 xonrxc; 547 u64 xontxc; 548 u64 xoffrxc; 549 u64 xofftxc; 550 u64 fcruc; 551 u64 prc64; 552 u64 prc127; 553 u64 prc255; 554 u64 prc511; 555 u64 prc1023; 556 u64 prc1522; 557 u64 gprc; 558 u64 bprc; 559 u64 mprc; 560 u64 gptc; 561 u64 gorc; 562 u64 gotc; 563 u64 rnbc; 564 u64 ruc; 565 u64 rfc; 566 u64 roc; 567 u64 rjc; 568 u64 mgprc; 569 u64 mgpdc; 570 u64 mgptc; 571 u64 tor; 572 u64 tot; 573 u64 tpr; 574 u64 tpt; 575 u64 ptc64; 576 u64 ptc127; 577 u64 ptc255; 578 u64 ptc511; 579 u64 ptc1023; 580 u64 ptc1522; 581 u64 mptc; 582 u64 bptc; 583 u64 tsctc; 584 u64 tsctfc; 585 u64 iac; 586 u64 icrxptc; 587 u64 icrxatc; 588 u64 ictxptc; 589 u64 ictxatc; 590 u64 ictxqec; 591 u64 ictxqmtc; 592 u64 icrxdmtc; 593 u64 icrxoc; 594 u64 cbtmpc; 595 u64 htdpmc; 596 u64 cbrdpc; 597 u64 cbrmpc; 598 u64 rpthc; 599 u64 hgptc; 600 u64 htcbdpc; 601 u64 hgorc; 602 u64 hgotc; 603 u64 lenerrs; 604 u64 scvpc; 605 u64 hrmpc; 606 u64 doosync; 607 u64 o2bgptc; 608 u64 o2bspc; 609 u64 b2ospc; 610 u64 b2ogprc; 611 }; 612 613 struct e1000_vf_stats { 614 u64 base_gprc; 615 u64 base_gptc; 616 u64 base_gorc; 617 u64 base_gotc; 618 u64 base_mprc; 619 u64 base_gotlbc; 620 u64 base_gptlbc; 621 u64 base_gorlbc; 622 u64 base_gprlbc; 623 624 u32 last_gprc; 625 u32 last_gptc; 626 u32 last_gorc; 627 u32 last_gotc; 628 u32 last_mprc; 629 u32 last_gotlbc; 630 u32 last_gptlbc; 631 u32 last_gorlbc; 632 u32 last_gprlbc; 633 634 u64 gprc; 635 u64 gptc; 636 u64 gorc; 637 u64 gotc; 638 u64 mprc; 639 u64 gotlbc; 640 u64 gptlbc; 641 u64 gorlbc; 642 u64 gprlbc; 643 }; 644 645 struct e1000_phy_stats { 646 u32 idle_errors; 647 u32 receive_errors; 648 }; 649 650 struct e1000_host_mng_dhcp_cookie { 651 u32 signature; 652 u8 status; 653 u8 reserved0; 654 u16 vlan_id; 655 u32 reserved1; 656 u16 reserved2; 657 u8 reserved3; 658 u8 checksum; 659 }; 660 661 /* Host Interface "Rev 1" */ 662 struct e1000_host_command_header { 663 u8 command_id; 664 u8 command_length; 665 u8 command_options; 666 u8 checksum; 667 }; 668 669 #define E1000_HI_MAX_DATA_LENGTH 252 670 struct e1000_host_command_info { 671 struct e1000_host_command_header command_header; 672 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 673 }; 674 675 /* Host Interface "Rev 2" */ 676 struct e1000_host_mng_command_header { 677 u8 command_id; 678 u8 checksum; 679 u16 reserved1; 680 u16 reserved2; 681 u16 command_length; 682 }; 683 684 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 685 struct e1000_host_mng_command_info { 686 struct e1000_host_mng_command_header command_header; 687 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 688 }; 689 690 #include "e1000_mac.h" 691 #include "e1000_phy.h" 692 #include "e1000_nvm.h" 693 #include "e1000_manage.h" 694 #include "e1000_mbx.h" 695 696 /* Function pointers for the MAC. */ 697 struct e1000_mac_operations { 698 s32 (*init_params)(struct e1000_hw *); 699 s32 (*id_led_init)(struct e1000_hw *); 700 s32 (*blink_led)(struct e1000_hw *); 701 bool (*check_mng_mode)(struct e1000_hw *); 702 s32 (*check_for_link)(struct e1000_hw *); 703 s32 (*cleanup_led)(struct e1000_hw *); 704 void (*clear_hw_cntrs)(struct e1000_hw *); 705 void (*clear_vfta)(struct e1000_hw *); 706 s32 (*get_bus_info)(struct e1000_hw *); 707 void (*set_lan_id)(struct e1000_hw *); 708 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 709 s32 (*led_on)(struct e1000_hw *); 710 s32 (*led_off)(struct e1000_hw *); 711 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 712 s32 (*reset_hw)(struct e1000_hw *); 713 s32 (*init_hw)(struct e1000_hw *); 714 void (*shutdown_serdes)(struct e1000_hw *); 715 void (*power_up_serdes)(struct e1000_hw *); 716 s32 (*setup_link)(struct e1000_hw *); 717 s32 (*setup_physical_interface)(struct e1000_hw *); 718 s32 (*setup_led)(struct e1000_hw *); 719 void (*write_vfta)(struct e1000_hw *, u32, u32); 720 void (*config_collision_dist)(struct e1000_hw *); 721 int (*rar_set)(struct e1000_hw *, u8*, u32); 722 s32 (*read_mac_addr)(struct e1000_hw *); 723 s32 (*validate_mdi_setting)(struct e1000_hw *); 724 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16); 725 void (*release_swfw_sync)(struct e1000_hw *, u16); 726 s32 (*set_obff_timer)(struct e1000_hw *, u32); 727 }; 728 729 /* When to use various PHY register access functions: 730 * 731 * Func Caller 732 * Function Does Does When to use 733 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 734 * X_reg L,P,A n/a for simple PHY reg accesses 735 * X_reg_locked P,A L for multiple accesses of different regs 736 * on different pages 737 * X_reg_page A L,P for multiple accesses of different regs 738 * on the same page 739 * 740 * Where X=[read|write], L=locking, P=sets page, A=register access 741 * 742 */ 743 struct e1000_phy_operations { 744 s32 (*init_params)(struct e1000_hw *); 745 s32 (*acquire)(struct e1000_hw *); 746 s32 (*cfg_on_link_up)(struct e1000_hw *); 747 s32 (*check_polarity)(struct e1000_hw *); 748 s32 (*check_reset_block)(struct e1000_hw *); 749 s32 (*commit)(struct e1000_hw *); 750 s32 (*force_speed_duplex)(struct e1000_hw *); 751 s32 (*get_cfg_done)(struct e1000_hw *hw); 752 s32 (*get_cable_length)(struct e1000_hw *); 753 s32 (*get_info)(struct e1000_hw *); 754 s32 (*set_page)(struct e1000_hw *, u16); 755 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 756 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 757 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *); 758 void (*release)(struct e1000_hw *); 759 s32 (*reset)(struct e1000_hw *); 760 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 761 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 762 s32 (*write_reg)(struct e1000_hw *, u32, u16); 763 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 764 s32 (*write_reg_page)(struct e1000_hw *, u32, u16); 765 void (*power_up)(struct e1000_hw *); 766 void (*power_down)(struct e1000_hw *); 767 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *); 768 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8); 769 }; 770 771 /* Function pointers for the NVM. */ 772 struct e1000_nvm_operations { 773 s32 (*init_params)(struct e1000_hw *); 774 s32 (*acquire)(struct e1000_hw *); 775 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 776 void (*release)(struct e1000_hw *); 777 void (*reload)(struct e1000_hw *); 778 s32 (*update)(struct e1000_hw *); 779 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 780 s32 (*validate)(struct e1000_hw *); 781 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 782 }; 783 784 struct e1000_mac_info { 785 struct e1000_mac_operations ops; 786 u8 addr[ETH_ADDR_LEN]; 787 u8 perm_addr[ETH_ADDR_LEN]; 788 789 enum e1000_mac_type type; 790 791 u32 collision_delta; 792 u32 ledctl_default; 793 u32 ledctl_mode1; 794 u32 ledctl_mode2; 795 u32 mc_filter_type; 796 u32 tx_packet_delta; 797 u32 txcw; 798 799 u16 current_ifs_val; 800 u16 ifs_max_val; 801 u16 ifs_min_val; 802 u16 ifs_ratio; 803 u16 ifs_step_size; 804 u16 mta_reg_count; 805 u16 uta_reg_count; 806 807 /* Maximum size of the MTA register table in all supported adapters */ 808 #define MAX_MTA_REG 128 809 u32 mta_shadow[MAX_MTA_REG]; 810 u16 rar_entry_count; 811 812 u8 forced_speed_duplex; 813 814 bool adaptive_ifs; 815 bool has_fwsm; 816 bool arc_subsystem_valid; 817 bool asf_firmware_present; 818 bool autoneg; 819 bool autoneg_failed; 820 bool get_link_status; 821 bool in_ifs_mode; 822 #ifndef NO_82542_SUPPORT 823 bool report_tx_early; 824 #endif 825 enum e1000_serdes_link_state serdes_link_state; 826 bool serdes_has_link; 827 bool tx_pkt_filtering; 828 u32 max_frame_size; 829 }; 830 831 struct e1000_phy_info { 832 struct e1000_phy_operations ops; 833 enum e1000_phy_type type; 834 835 enum e1000_1000t_rx_status local_rx; 836 enum e1000_1000t_rx_status remote_rx; 837 enum e1000_ms_type ms_type; 838 enum e1000_ms_type original_ms_type; 839 enum e1000_rev_polarity cable_polarity; 840 enum e1000_smart_speed smart_speed; 841 842 u32 addr; 843 u32 id; 844 u32 reset_delay_us; /* in usec */ 845 u32 revision; 846 847 enum e1000_media_type media_type; 848 849 u16 autoneg_advertised; 850 u16 autoneg_mask; 851 u16 cable_length; 852 u16 max_cable_length; 853 u16 min_cable_length; 854 855 u8 mdix; 856 857 bool disable_polarity_correction; 858 bool is_mdix; 859 bool polarity_correction; 860 bool speed_downgraded; 861 bool autoneg_wait_to_complete; 862 }; 863 864 struct e1000_nvm_info { 865 struct e1000_nvm_operations ops; 866 enum e1000_nvm_type type; 867 enum e1000_nvm_override override; 868 869 u32 flash_bank_size; 870 u32 flash_base_addr; 871 872 u16 word_size; 873 u16 delay_usec; 874 u16 address_bits; 875 u16 opcode_bits; 876 u16 page_size; 877 }; 878 879 struct e1000_bus_info { 880 enum e1000_bus_type type; 881 enum e1000_bus_speed speed; 882 enum e1000_bus_width width; 883 884 u16 func; 885 u16 pci_cmd_word; 886 }; 887 888 struct e1000_fc_info { 889 u32 high_water; /* Flow control high-water mark */ 890 u32 low_water; /* Flow control low-water mark */ 891 u16 pause_time; /* Flow control pause timer */ 892 u16 refresh_time; /* Flow control refresh timer */ 893 bool send_xon; /* Flow control send XON */ 894 bool strict_ieee; /* Strict IEEE mode */ 895 enum e1000_fc_mode current_mode; /* FC mode in effect */ 896 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 897 }; 898 899 struct e1000_dev_spec_82541 { 900 enum e1000_dsp_config dsp_config; 901 enum e1000_ffe_config ffe_config; 902 u16 spd_default; 903 bool phy_init_script; 904 }; 905 906 #ifndef NO_82542_SUPPORT 907 struct e1000_dev_spec_82542 { 908 bool dma_fairness; 909 }; 910 911 #endif /* NO_82542_SUPPORT */ 912 struct e1000_dev_spec_82543 { 913 u32 tbi_compatibility; 914 bool dma_fairness; 915 bool init_phy_disabled; 916 }; 917 918 struct e1000_dev_spec_82571 { 919 bool laa_is_present; 920 u32 smb_counter; 921 }; 922 923 struct e1000_dev_spec_80003es2lan { 924 bool mdic_wa_enable; 925 }; 926 927 struct e1000_shadow_ram { 928 u16 value; 929 bool modified; 930 }; 931 932 struct e1000_mbx_operations { 933 s32 (*init_params)(struct e1000_hw *hw); 934 s32 (*read)(struct e1000_hw *, u32 *, u16, u16); 935 s32 (*write)(struct e1000_hw *, u32 *, u16, u16); 936 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16); 937 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16); 938 s32 (*check_for_msg)(struct e1000_hw *, u16); 939 s32 (*check_for_ack)(struct e1000_hw *, u16); 940 s32 (*check_for_rst)(struct e1000_hw *, u16); 941 }; 942 943 struct e1000_mbx_stats { 944 u32 msgs_tx; 945 u32 msgs_rx; 946 947 u32 acks; 948 u32 reqs; 949 u32 rsts; 950 }; 951 952 struct e1000_mbx_info { 953 struct e1000_mbx_operations ops; 954 struct e1000_mbx_stats stats; 955 u32 timeout; 956 u32 usec_delay; 957 u16 size; 958 }; 959 960 struct e1000_dev_spec_82575 { 961 bool sgmii_active; 962 bool global_device_reset; 963 bool eee_disable; 964 bool module_plugged; 965 bool clear_semaphore_once; 966 u32 mtu; 967 struct sfp_e1000_flags eth_flags; 968 u8 media_port; 969 bool media_changed; 970 }; 971 972 #define E1000_SHADOW_RAM_WORDS 2048 973 974 /* I218 PHY Ultra Low Power (ULP) states */ 975 enum e1000_ulp_state { 976 e1000_ulp_state_unknown, 977 e1000_ulp_state_off, 978 e1000_ulp_state_on, 979 }; 980 981 struct e1000_dev_spec_ich8lan { 982 bool kmrn_lock_loss_workaround_enabled; 983 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; 984 bool nvm_k1_enabled; 985 bool eee_disable; 986 u16 eee_lp_ability; 987 enum e1000_ulp_state ulp_state; 988 }; 989 990 struct e1000_dev_spec_vf { 991 u32 vf_number; 992 u32 v2p_mailbox; 993 }; 994 995 struct e1000_hw { 996 void *back; 997 998 u8 *hw_addr; 999 u8 *flash_address; 1000 unsigned long io_base; 1001 1002 struct e1000_mac_info mac; 1003 struct e1000_fc_info fc; 1004 struct e1000_phy_info phy; 1005 struct e1000_nvm_info nvm; 1006 struct e1000_bus_info bus; 1007 struct e1000_mbx_info mbx; 1008 struct e1000_host_mng_dhcp_cookie mng_cookie; 1009 1010 union { 1011 struct e1000_dev_spec_82541 _82541; 1012 #ifndef NO_82542_SUPPORT 1013 struct e1000_dev_spec_82542 _82542; 1014 #endif 1015 struct e1000_dev_spec_82543 _82543; 1016 struct e1000_dev_spec_82571 _82571; 1017 struct e1000_dev_spec_80003es2lan _80003es2lan; 1018 struct e1000_dev_spec_ich8lan ich8lan; 1019 struct e1000_dev_spec_82575 _82575; 1020 struct e1000_dev_spec_vf vf; 1021 } dev_spec; 1022 1023 u16 device_id; 1024 u16 subsystem_vendor_id; 1025 u16 subsystem_device_id; 1026 u16 vendor_id; 1027 1028 u8 revision_id; 1029 }; 1030 1031 #include "e1000_82541.h" 1032 #include "e1000_82543.h" 1033 #include "e1000_82571.h" 1034 #include "e1000_80003es2lan.h" 1035 #include "e1000_ich8lan.h" 1036 #include "e1000_82575.h" 1037 #include "e1000_i210.h" 1038 1039 /* These functions must be implemented by drivers */ 1040 #ifndef NO_82542_SUPPORT 1041 void e1000_pci_clear_mwi(struct e1000_hw *hw); 1042 void e1000_pci_set_mwi(struct e1000_hw *hw); 1043 #endif 1044 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1045 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1046 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1047 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1048 1049 #endif 1050