1 /****************************************************************************** 2 3 Copyright (c) 2001-2014, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD:$*/ 34 35 #ifndef _E1000_HW_H_ 36 #define _E1000_HW_H_ 37 38 #include "e1000_osdep.h" 39 #include "e1000_regs.h" 40 #include "e1000_defines.h" 41 42 struct e1000_hw; 43 44 #ifndef NO_82542_SUPPORT 45 #define E1000_DEV_ID_82542 0x1000 46 #endif 47 #define E1000_DEV_ID_82543GC_FIBER 0x1001 48 #define E1000_DEV_ID_82543GC_COPPER 0x1004 49 #define E1000_DEV_ID_82544EI_COPPER 0x1008 50 #define E1000_DEV_ID_82544EI_FIBER 0x1009 51 #define E1000_DEV_ID_82544GC_COPPER 0x100C 52 #define E1000_DEV_ID_82544GC_LOM 0x100D 53 #define E1000_DEV_ID_82540EM 0x100E 54 #define E1000_DEV_ID_82540EM_LOM 0x1015 55 #define E1000_DEV_ID_82540EP_LOM 0x1016 56 #define E1000_DEV_ID_82540EP 0x1017 57 #define E1000_DEV_ID_82540EP_LP 0x101E 58 #define E1000_DEV_ID_82545EM_COPPER 0x100F 59 #define E1000_DEV_ID_82545EM_FIBER 0x1011 60 #define E1000_DEV_ID_82545GM_COPPER 0x1026 61 #define E1000_DEV_ID_82545GM_FIBER 0x1027 62 #define E1000_DEV_ID_82545GM_SERDES 0x1028 63 #define E1000_DEV_ID_82546EB_COPPER 0x1010 64 #define E1000_DEV_ID_82546EB_FIBER 0x1012 65 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 66 #define E1000_DEV_ID_82546GB_COPPER 0x1079 67 #define E1000_DEV_ID_82546GB_FIBER 0x107A 68 #define E1000_DEV_ID_82546GB_SERDES 0x107B 69 #define E1000_DEV_ID_82546GB_PCIE 0x108A 70 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 71 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 72 #define E1000_DEV_ID_82541EI 0x1013 73 #define E1000_DEV_ID_82541EI_MOBILE 0x1018 74 #define E1000_DEV_ID_82541ER_LOM 0x1014 75 #define E1000_DEV_ID_82541ER 0x1078 76 #define E1000_DEV_ID_82541GI 0x1076 77 #define E1000_DEV_ID_82541GI_LF 0x107C 78 #define E1000_DEV_ID_82541GI_MOBILE 0x1077 79 #define E1000_DEV_ID_82547EI 0x1019 80 #define E1000_DEV_ID_82547EI_MOBILE 0x101A 81 #define E1000_DEV_ID_82547GI 0x1075 82 #define E1000_DEV_ID_82571EB_COPPER 0x105E 83 #define E1000_DEV_ID_82571EB_FIBER 0x105F 84 #define E1000_DEV_ID_82571EB_SERDES 0x1060 85 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 86 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 87 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 88 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 89 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 90 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 91 #define E1000_DEV_ID_82571EB_QUAD_COPPER_BP 0x10A0 92 #define E1000_DEV_ID_82572EI_COPPER 0x107D 93 #define E1000_DEV_ID_82572EI_FIBER 0x107E 94 #define E1000_DEV_ID_82572EI_SERDES 0x107F 95 #define E1000_DEV_ID_82572EI 0x10B9 96 #define E1000_DEV_ID_82573E 0x108B 97 #define E1000_DEV_ID_82573E_IAMT 0x108C 98 #define E1000_DEV_ID_82573L 0x109A 99 #define E1000_DEV_ID_82574L 0x10D3 100 #define E1000_DEV_ID_82574LA 0x10F6 101 #define E1000_DEV_ID_82583V 0x150C 102 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 103 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 104 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 105 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 106 #define E1000_DEV_ID_ICH8_82567V_3 0x1501 107 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 108 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 109 #define E1000_DEV_ID_ICH8_IGP_C 0x104B 110 #define E1000_DEV_ID_ICH8_IFE 0x104C 111 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 112 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 113 #define E1000_DEV_ID_ICH8_IGP_M 0x104D 114 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF 115 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 116 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 117 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 118 #define E1000_DEV_ID_ICH9_BM 0x10E5 119 #define E1000_DEV_ID_ICH9_IGP_C 0x294C 120 #define E1000_DEV_ID_ICH9_IFE 0x10C0 121 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 122 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 123 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 124 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 125 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 126 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 127 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 128 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525 129 130 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 131 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 132 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 133 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 134 #define E1000_DEV_ID_PCH2_LV_LM 0x1502 135 #define E1000_DEV_ID_PCH2_LV_V 0x1503 136 137 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A 138 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B 139 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A 140 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559 141 #define E1000_DEV_ID_PCH_I218_LM2 0x15A0 142 #define E1000_DEV_ID_PCH_I218_V2 0x15A1 143 #define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */ 144 #define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */ 145 146 #define E1000_DEV_ID_82576 0x10C9 147 #define E1000_DEV_ID_82576_FIBER 0x10E6 148 #define E1000_DEV_ID_82576_SERDES 0x10E7 149 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 150 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526 151 #define E1000_DEV_ID_82576_NS 0x150A 152 #define E1000_DEV_ID_82576_NS_SERDES 0x1518 153 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D 154 #define E1000_DEV_ID_82576_VF 0x10CA 155 #define E1000_DEV_ID_82576_VF_HV 0x152D 156 #define E1000_DEV_ID_I350_VF 0x1520 157 #define E1000_DEV_ID_I350_VF_HV 0x152F 158 #define E1000_DEV_ID_82575EB_COPPER 0x10A7 159 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 160 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 161 #define E1000_DEV_ID_82580_COPPER 0x150E 162 #define E1000_DEV_ID_82580_FIBER 0x150F 163 #define E1000_DEV_ID_82580_SERDES 0x1510 164 #define E1000_DEV_ID_82580_SGMII 0x1511 165 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 166 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527 167 #define E1000_DEV_ID_I350_COPPER 0x1521 168 #define E1000_DEV_ID_I350_FIBER 0x1522 169 #define E1000_DEV_ID_I350_SERDES 0x1523 170 #define E1000_DEV_ID_I350_SGMII 0x1524 171 #define E1000_DEV_ID_I350_DA4 0x1546 172 #define E1000_DEV_ID_I210_COPPER 0x1533 173 #define E1000_DEV_ID_I210_COPPER_OEM1 0x1534 174 #define E1000_DEV_ID_I210_COPPER_IT 0x1535 175 #define E1000_DEV_ID_I210_FIBER 0x1536 176 #define E1000_DEV_ID_I210_SERDES 0x1537 177 #define E1000_DEV_ID_I210_SGMII 0x1538 178 #define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B 179 #define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C 180 #define E1000_DEV_ID_I211_COPPER 0x1539 181 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40 182 #define E1000_DEV_ID_I354_SGMII 0x1F41 183 #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438 184 #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A 185 #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C 186 #define E1000_DEV_ID_DH89XXCC_SFP 0x0440 187 188 #define E1000_REVISION_0 0 189 #define E1000_REVISION_1 1 190 #define E1000_REVISION_2 2 191 #define E1000_REVISION_3 3 192 #define E1000_REVISION_4 4 193 194 #define E1000_FUNC_0 0 195 #define E1000_FUNC_1 1 196 #define E1000_FUNC_2 2 197 #define E1000_FUNC_3 3 198 199 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 200 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 201 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6 202 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9 203 204 enum e1000_mac_type { 205 e1000_undefined = 0, 206 #ifndef NO_82542_SUPPORT 207 e1000_82542, 208 #endif 209 e1000_82543, 210 e1000_82544, 211 e1000_82540, 212 e1000_82545, 213 e1000_82545_rev_3, 214 e1000_82546, 215 e1000_82546_rev_3, 216 e1000_82541, 217 e1000_82541_rev_2, 218 e1000_82547, 219 e1000_82547_rev_2, 220 e1000_82571, 221 e1000_82572, 222 e1000_82573, 223 e1000_82574, 224 e1000_82583, 225 e1000_80003es2lan, 226 e1000_ich8lan, 227 e1000_ich9lan, 228 e1000_ich10lan, 229 e1000_pchlan, 230 e1000_pch2lan, 231 e1000_pch_lpt, 232 e1000_82575, 233 e1000_82576, 234 e1000_82580, 235 e1000_i350, 236 e1000_i354, 237 e1000_i210, 238 e1000_i211, 239 e1000_vfadapt, 240 e1000_vfadapt_i350, 241 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ 242 }; 243 244 enum e1000_media_type { 245 e1000_media_type_unknown = 0, 246 e1000_media_type_copper = 1, 247 e1000_media_type_fiber = 2, 248 e1000_media_type_internal_serdes = 3, 249 e1000_num_media_types 250 }; 251 252 enum e1000_nvm_type { 253 e1000_nvm_unknown = 0, 254 e1000_nvm_none, 255 e1000_nvm_eeprom_spi, 256 e1000_nvm_eeprom_microwire, 257 e1000_nvm_flash_hw, 258 e1000_nvm_invm, 259 e1000_nvm_flash_sw 260 }; 261 262 enum e1000_nvm_override { 263 e1000_nvm_override_none = 0, 264 e1000_nvm_override_spi_small, 265 e1000_nvm_override_spi_large, 266 e1000_nvm_override_microwire_small, 267 e1000_nvm_override_microwire_large 268 }; 269 270 enum e1000_phy_type { 271 e1000_phy_unknown = 0, 272 e1000_phy_none, 273 e1000_phy_m88, 274 e1000_phy_igp, 275 e1000_phy_igp_2, 276 e1000_phy_gg82563, 277 e1000_phy_igp_3, 278 e1000_phy_ife, 279 e1000_phy_bm, 280 e1000_phy_82578, 281 e1000_phy_82577, 282 e1000_phy_82579, 283 e1000_phy_i217, 284 e1000_phy_82580, 285 e1000_phy_vf, 286 e1000_phy_i210, 287 }; 288 289 enum e1000_bus_type { 290 e1000_bus_type_unknown = 0, 291 e1000_bus_type_pci, 292 e1000_bus_type_pcix, 293 e1000_bus_type_pci_express, 294 e1000_bus_type_reserved 295 }; 296 297 enum e1000_bus_speed { 298 e1000_bus_speed_unknown = 0, 299 e1000_bus_speed_33, 300 e1000_bus_speed_66, 301 e1000_bus_speed_100, 302 e1000_bus_speed_120, 303 e1000_bus_speed_133, 304 e1000_bus_speed_2500, 305 e1000_bus_speed_5000, 306 e1000_bus_speed_reserved 307 }; 308 309 enum e1000_bus_width { 310 e1000_bus_width_unknown = 0, 311 e1000_bus_width_pcie_x1, 312 e1000_bus_width_pcie_x2, 313 e1000_bus_width_pcie_x4 = 4, 314 e1000_bus_width_pcie_x8 = 8, 315 e1000_bus_width_32, 316 e1000_bus_width_64, 317 e1000_bus_width_reserved 318 }; 319 320 enum e1000_1000t_rx_status { 321 e1000_1000t_rx_status_not_ok = 0, 322 e1000_1000t_rx_status_ok, 323 e1000_1000t_rx_status_undefined = 0xFF 324 }; 325 326 enum e1000_rev_polarity { 327 e1000_rev_polarity_normal = 0, 328 e1000_rev_polarity_reversed, 329 e1000_rev_polarity_undefined = 0xFF 330 }; 331 332 enum e1000_fc_mode { 333 e1000_fc_none = 0, 334 e1000_fc_rx_pause, 335 e1000_fc_tx_pause, 336 e1000_fc_full, 337 e1000_fc_default = 0xFF 338 }; 339 340 enum e1000_ffe_config { 341 e1000_ffe_config_enabled = 0, 342 e1000_ffe_config_active, 343 e1000_ffe_config_blocked 344 }; 345 346 enum e1000_dsp_config { 347 e1000_dsp_config_disabled = 0, 348 e1000_dsp_config_enabled, 349 e1000_dsp_config_activated, 350 e1000_dsp_config_undefined = 0xFF 351 }; 352 353 enum e1000_ms_type { 354 e1000_ms_hw_default = 0, 355 e1000_ms_force_master, 356 e1000_ms_force_slave, 357 e1000_ms_auto 358 }; 359 360 enum e1000_smart_speed { 361 e1000_smart_speed_default = 0, 362 e1000_smart_speed_on, 363 e1000_smart_speed_off 364 }; 365 366 enum e1000_serdes_link_state { 367 e1000_serdes_link_down = 0, 368 e1000_serdes_link_autoneg_progress, 369 e1000_serdes_link_autoneg_complete, 370 e1000_serdes_link_forced_up 371 }; 372 373 #define __le16 u16 374 #define __le32 u32 375 #define __le64 u64 376 /* Receive Descriptor */ 377 struct e1000_rx_desc { 378 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 379 __le16 length; /* Length of data DMAed into data buffer */ 380 __le16 csum; /* Packet checksum */ 381 u8 status; /* Descriptor status */ 382 u8 errors; /* Descriptor Errors */ 383 __le16 special; 384 }; 385 386 /* Receive Descriptor - Extended */ 387 union e1000_rx_desc_extended { 388 struct { 389 __le64 buffer_addr; 390 __le64 reserved; 391 } read; 392 struct { 393 struct { 394 __le32 mrq; /* Multiple Rx Queues */ 395 union { 396 __le32 rss; /* RSS Hash */ 397 struct { 398 __le16 ip_id; /* IP id */ 399 __le16 csum; /* Packet Checksum */ 400 } csum_ip; 401 } hi_dword; 402 } lower; 403 struct { 404 __le32 status_error; /* ext status/error */ 405 __le16 length; 406 __le16 vlan; /* VLAN tag */ 407 } upper; 408 } wb; /* writeback */ 409 }; 410 411 #define MAX_PS_BUFFERS 4 412 413 /* Number of packet split data buffers (not including the header buffer) */ 414 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) 415 416 /* Receive Descriptor - Packet Split */ 417 union e1000_rx_desc_packet_split { 418 struct { 419 /* one buffer for protocol header(s), three data buffers */ 420 __le64 buffer_addr[MAX_PS_BUFFERS]; 421 } read; 422 struct { 423 struct { 424 __le32 mrq; /* Multiple Rx Queues */ 425 union { 426 __le32 rss; /* RSS Hash */ 427 struct { 428 __le16 ip_id; /* IP id */ 429 __le16 csum; /* Packet Checksum */ 430 } csum_ip; 431 } hi_dword; 432 } lower; 433 struct { 434 __le32 status_error; /* ext status/error */ 435 __le16 length0; /* length of buffer 0 */ 436 __le16 vlan; /* VLAN tag */ 437 } middle; 438 struct { 439 __le16 header_status; 440 /* length of buffers 1-3 */ 441 __le16 length[PS_PAGE_BUFFERS]; 442 } upper; 443 __le64 reserved; 444 } wb; /* writeback */ 445 }; 446 447 /* Transmit Descriptor */ 448 struct e1000_tx_desc { 449 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 450 union { 451 __le32 data; 452 struct { 453 __le16 length; /* Data buffer length */ 454 u8 cso; /* Checksum offset */ 455 u8 cmd; /* Descriptor control */ 456 } flags; 457 } lower; 458 union { 459 __le32 data; 460 struct { 461 u8 status; /* Descriptor status */ 462 u8 css; /* Checksum start */ 463 __le16 special; 464 } fields; 465 } upper; 466 }; 467 468 /* Offload Context Descriptor */ 469 struct e1000_context_desc { 470 union { 471 __le32 ip_config; 472 struct { 473 u8 ipcss; /* IP checksum start */ 474 u8 ipcso; /* IP checksum offset */ 475 __le16 ipcse; /* IP checksum end */ 476 } ip_fields; 477 } lower_setup; 478 union { 479 __le32 tcp_config; 480 struct { 481 u8 tucss; /* TCP checksum start */ 482 u8 tucso; /* TCP checksum offset */ 483 __le16 tucse; /* TCP checksum end */ 484 } tcp_fields; 485 } upper_setup; 486 __le32 cmd_and_length; 487 union { 488 __le32 data; 489 struct { 490 u8 status; /* Descriptor status */ 491 u8 hdr_len; /* Header length */ 492 __le16 mss; /* Maximum segment size */ 493 } fields; 494 } tcp_seg_setup; 495 }; 496 497 /* Offload data descriptor */ 498 struct e1000_data_desc { 499 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 500 union { 501 __le32 data; 502 struct { 503 __le16 length; /* Data buffer length */ 504 u8 typ_len_ext; 505 u8 cmd; 506 } flags; 507 } lower; 508 union { 509 __le32 data; 510 struct { 511 u8 status; /* Descriptor status */ 512 u8 popts; /* Packet Options */ 513 __le16 special; 514 } fields; 515 } upper; 516 }; 517 518 /* Statistics counters collected by the MAC */ 519 struct e1000_hw_stats { 520 u64 crcerrs; 521 u64 algnerrc; 522 u64 symerrs; 523 u64 rxerrc; 524 u64 mpc; 525 u64 scc; 526 u64 ecol; 527 u64 mcc; 528 u64 latecol; 529 u64 colc; 530 u64 dc; 531 u64 tncrs; 532 u64 sec; 533 u64 cexterr; 534 u64 rlec; 535 u64 xonrxc; 536 u64 xontxc; 537 u64 xoffrxc; 538 u64 xofftxc; 539 u64 fcruc; 540 u64 prc64; 541 u64 prc127; 542 u64 prc255; 543 u64 prc511; 544 u64 prc1023; 545 u64 prc1522; 546 u64 gprc; 547 u64 bprc; 548 u64 mprc; 549 u64 gptc; 550 u64 gorc; 551 u64 gotc; 552 u64 rnbc; 553 u64 ruc; 554 u64 rfc; 555 u64 roc; 556 u64 rjc; 557 u64 mgprc; 558 u64 mgpdc; 559 u64 mgptc; 560 u64 tor; 561 u64 tot; 562 u64 tpr; 563 u64 tpt; 564 u64 ptc64; 565 u64 ptc127; 566 u64 ptc255; 567 u64 ptc511; 568 u64 ptc1023; 569 u64 ptc1522; 570 u64 mptc; 571 u64 bptc; 572 u64 tsctc; 573 u64 tsctfc; 574 u64 iac; 575 u64 icrxptc; 576 u64 icrxatc; 577 u64 ictxptc; 578 u64 ictxatc; 579 u64 ictxqec; 580 u64 ictxqmtc; 581 u64 icrxdmtc; 582 u64 icrxoc; 583 u64 cbtmpc; 584 u64 htdpmc; 585 u64 cbrdpc; 586 u64 cbrmpc; 587 u64 rpthc; 588 u64 hgptc; 589 u64 htcbdpc; 590 u64 hgorc; 591 u64 hgotc; 592 u64 lenerrs; 593 u64 scvpc; 594 u64 hrmpc; 595 u64 doosync; 596 u64 o2bgptc; 597 u64 o2bspc; 598 u64 b2ospc; 599 u64 b2ogprc; 600 }; 601 602 struct e1000_vf_stats { 603 u64 base_gprc; 604 u64 base_gptc; 605 u64 base_gorc; 606 u64 base_gotc; 607 u64 base_mprc; 608 u64 base_gotlbc; 609 u64 base_gptlbc; 610 u64 base_gorlbc; 611 u64 base_gprlbc; 612 613 u32 last_gprc; 614 u32 last_gptc; 615 u32 last_gorc; 616 u32 last_gotc; 617 u32 last_mprc; 618 u32 last_gotlbc; 619 u32 last_gptlbc; 620 u32 last_gorlbc; 621 u32 last_gprlbc; 622 623 u64 gprc; 624 u64 gptc; 625 u64 gorc; 626 u64 gotc; 627 u64 mprc; 628 u64 gotlbc; 629 u64 gptlbc; 630 u64 gorlbc; 631 u64 gprlbc; 632 }; 633 634 struct e1000_phy_stats { 635 u32 idle_errors; 636 u32 receive_errors; 637 }; 638 639 struct e1000_host_mng_dhcp_cookie { 640 u32 signature; 641 u8 status; 642 u8 reserved0; 643 u16 vlan_id; 644 u32 reserved1; 645 u16 reserved2; 646 u8 reserved3; 647 u8 checksum; 648 }; 649 650 /* Host Interface "Rev 1" */ 651 struct e1000_host_command_header { 652 u8 command_id; 653 u8 command_length; 654 u8 command_options; 655 u8 checksum; 656 }; 657 658 #define E1000_HI_MAX_DATA_LENGTH 252 659 struct e1000_host_command_info { 660 struct e1000_host_command_header command_header; 661 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 662 }; 663 664 /* Host Interface "Rev 2" */ 665 struct e1000_host_mng_command_header { 666 u8 command_id; 667 u8 checksum; 668 u16 reserved1; 669 u16 reserved2; 670 u16 command_length; 671 }; 672 673 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 674 struct e1000_host_mng_command_info { 675 struct e1000_host_mng_command_header command_header; 676 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 677 }; 678 679 #include "e1000_mac.h" 680 #include "e1000_phy.h" 681 #include "e1000_nvm.h" 682 #include "e1000_manage.h" 683 #include "e1000_mbx.h" 684 685 /* Function pointers for the MAC. */ 686 struct e1000_mac_operations { 687 s32 (*init_params)(struct e1000_hw *); 688 s32 (*id_led_init)(struct e1000_hw *); 689 s32 (*blink_led)(struct e1000_hw *); 690 bool (*check_mng_mode)(struct e1000_hw *); 691 s32 (*check_for_link)(struct e1000_hw *); 692 s32 (*cleanup_led)(struct e1000_hw *); 693 void (*clear_hw_cntrs)(struct e1000_hw *); 694 void (*clear_vfta)(struct e1000_hw *); 695 s32 (*get_bus_info)(struct e1000_hw *); 696 void (*set_lan_id)(struct e1000_hw *); 697 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 698 s32 (*led_on)(struct e1000_hw *); 699 s32 (*led_off)(struct e1000_hw *); 700 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 701 s32 (*reset_hw)(struct e1000_hw *); 702 s32 (*init_hw)(struct e1000_hw *); 703 void (*shutdown_serdes)(struct e1000_hw *); 704 void (*power_up_serdes)(struct e1000_hw *); 705 s32 (*setup_link)(struct e1000_hw *); 706 s32 (*setup_physical_interface)(struct e1000_hw *); 707 s32 (*setup_led)(struct e1000_hw *); 708 void (*write_vfta)(struct e1000_hw *, u32, u32); 709 void (*config_collision_dist)(struct e1000_hw *); 710 int (*rar_set)(struct e1000_hw *, u8*, u32); 711 s32 (*read_mac_addr)(struct e1000_hw *); 712 s32 (*validate_mdi_setting)(struct e1000_hw *); 713 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16); 714 void (*release_swfw_sync)(struct e1000_hw *, u16); 715 s32 (*set_obff_timer)(struct e1000_hw *, u32); 716 }; 717 718 /* When to use various PHY register access functions: 719 * 720 * Func Caller 721 * Function Does Does When to use 722 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 723 * X_reg L,P,A n/a for simple PHY reg accesses 724 * X_reg_locked P,A L for multiple accesses of different regs 725 * on different pages 726 * X_reg_page A L,P for multiple accesses of different regs 727 * on the same page 728 * 729 * Where X=[read|write], L=locking, P=sets page, A=register access 730 * 731 */ 732 struct e1000_phy_operations { 733 s32 (*init_params)(struct e1000_hw *); 734 s32 (*acquire)(struct e1000_hw *); 735 s32 (*cfg_on_link_up)(struct e1000_hw *); 736 s32 (*check_polarity)(struct e1000_hw *); 737 s32 (*check_reset_block)(struct e1000_hw *); 738 s32 (*commit)(struct e1000_hw *); 739 s32 (*force_speed_duplex)(struct e1000_hw *); 740 s32 (*get_cfg_done)(struct e1000_hw *hw); 741 s32 (*get_cable_length)(struct e1000_hw *); 742 s32 (*get_info)(struct e1000_hw *); 743 s32 (*set_page)(struct e1000_hw *, u16); 744 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 745 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 746 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *); 747 void (*release)(struct e1000_hw *); 748 s32 (*reset)(struct e1000_hw *); 749 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 750 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 751 s32 (*write_reg)(struct e1000_hw *, u32, u16); 752 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 753 s32 (*write_reg_page)(struct e1000_hw *, u32, u16); 754 void (*power_up)(struct e1000_hw *); 755 void (*power_down)(struct e1000_hw *); 756 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *); 757 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8); 758 }; 759 760 /* Function pointers for the NVM. */ 761 struct e1000_nvm_operations { 762 s32 (*init_params)(struct e1000_hw *); 763 s32 (*acquire)(struct e1000_hw *); 764 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 765 void (*release)(struct e1000_hw *); 766 void (*reload)(struct e1000_hw *); 767 s32 (*update)(struct e1000_hw *); 768 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 769 s32 (*validate)(struct e1000_hw *); 770 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 771 }; 772 773 struct e1000_mac_info { 774 struct e1000_mac_operations ops; 775 u8 addr[ETH_ADDR_LEN]; 776 u8 perm_addr[ETH_ADDR_LEN]; 777 778 enum e1000_mac_type type; 779 780 u32 collision_delta; 781 u32 ledctl_default; 782 u32 ledctl_mode1; 783 u32 ledctl_mode2; 784 u32 mc_filter_type; 785 u32 tx_packet_delta; 786 u32 txcw; 787 788 u16 current_ifs_val; 789 u16 ifs_max_val; 790 u16 ifs_min_val; 791 u16 ifs_ratio; 792 u16 ifs_step_size; 793 u16 mta_reg_count; 794 u16 uta_reg_count; 795 796 /* Maximum size of the MTA register table in all supported adapters */ 797 #define MAX_MTA_REG 128 798 u32 mta_shadow[MAX_MTA_REG]; 799 u16 rar_entry_count; 800 801 u8 forced_speed_duplex; 802 803 bool adaptive_ifs; 804 bool has_fwsm; 805 bool arc_subsystem_valid; 806 bool asf_firmware_present; 807 bool autoneg; 808 bool autoneg_failed; 809 bool get_link_status; 810 bool in_ifs_mode; 811 #ifndef NO_82542_SUPPORT 812 bool report_tx_early; 813 #endif 814 enum e1000_serdes_link_state serdes_link_state; 815 bool serdes_has_link; 816 bool tx_pkt_filtering; 817 u32 max_frame_size; 818 }; 819 820 struct e1000_phy_info { 821 struct e1000_phy_operations ops; 822 enum e1000_phy_type type; 823 824 enum e1000_1000t_rx_status local_rx; 825 enum e1000_1000t_rx_status remote_rx; 826 enum e1000_ms_type ms_type; 827 enum e1000_ms_type original_ms_type; 828 enum e1000_rev_polarity cable_polarity; 829 enum e1000_smart_speed smart_speed; 830 831 u32 addr; 832 u32 id; 833 u32 reset_delay_us; /* in usec */ 834 u32 revision; 835 836 enum e1000_media_type media_type; 837 838 u16 autoneg_advertised; 839 u16 autoneg_mask; 840 u16 cable_length; 841 u16 max_cable_length; 842 u16 min_cable_length; 843 844 u8 mdix; 845 846 bool disable_polarity_correction; 847 bool is_mdix; 848 bool polarity_correction; 849 bool speed_downgraded; 850 bool autoneg_wait_to_complete; 851 }; 852 853 struct e1000_nvm_info { 854 struct e1000_nvm_operations ops; 855 enum e1000_nvm_type type; 856 enum e1000_nvm_override override; 857 858 u32 flash_bank_size; 859 u32 flash_base_addr; 860 861 u16 word_size; 862 u16 delay_usec; 863 u16 address_bits; 864 u16 opcode_bits; 865 u16 page_size; 866 }; 867 868 struct e1000_bus_info { 869 enum e1000_bus_type type; 870 enum e1000_bus_speed speed; 871 enum e1000_bus_width width; 872 873 u16 func; 874 u16 pci_cmd_word; 875 }; 876 877 struct e1000_fc_info { 878 u32 high_water; /* Flow control high-water mark */ 879 u32 low_water; /* Flow control low-water mark */ 880 u16 pause_time; /* Flow control pause timer */ 881 u16 refresh_time; /* Flow control refresh timer */ 882 bool send_xon; /* Flow control send XON */ 883 bool strict_ieee; /* Strict IEEE mode */ 884 enum e1000_fc_mode current_mode; /* FC mode in effect */ 885 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 886 }; 887 888 struct e1000_dev_spec_82541 { 889 enum e1000_dsp_config dsp_config; 890 enum e1000_ffe_config ffe_config; 891 u16 spd_default; 892 bool phy_init_script; 893 }; 894 895 #ifndef NO_82542_SUPPORT 896 struct e1000_dev_spec_82542 { 897 bool dma_fairness; 898 }; 899 900 #endif /* NO_82542_SUPPORT */ 901 struct e1000_dev_spec_82543 { 902 u32 tbi_compatibility; 903 bool dma_fairness; 904 bool init_phy_disabled; 905 }; 906 907 struct e1000_dev_spec_82571 { 908 bool laa_is_present; 909 u32 smb_counter; 910 }; 911 912 struct e1000_dev_spec_80003es2lan { 913 bool mdic_wa_enable; 914 }; 915 916 struct e1000_shadow_ram { 917 u16 value; 918 bool modified; 919 }; 920 921 struct e1000_mbx_operations { 922 s32 (*init_params)(struct e1000_hw *hw); 923 s32 (*read)(struct e1000_hw *, u32 *, u16, u16); 924 s32 (*write)(struct e1000_hw *, u32 *, u16, u16); 925 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16); 926 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16); 927 s32 (*check_for_msg)(struct e1000_hw *, u16); 928 s32 (*check_for_ack)(struct e1000_hw *, u16); 929 s32 (*check_for_rst)(struct e1000_hw *, u16); 930 }; 931 932 struct e1000_mbx_stats { 933 u32 msgs_tx; 934 u32 msgs_rx; 935 936 u32 acks; 937 u32 reqs; 938 u32 rsts; 939 }; 940 941 struct e1000_mbx_info { 942 struct e1000_mbx_operations ops; 943 struct e1000_mbx_stats stats; 944 u32 timeout; 945 u32 usec_delay; 946 u16 size; 947 }; 948 949 struct e1000_dev_spec_82575 { 950 bool sgmii_active; 951 bool global_device_reset; 952 bool eee_disable; 953 bool module_plugged; 954 bool clear_semaphore_once; 955 u32 mtu; 956 struct sfp_e1000_flags eth_flags; 957 u8 media_port; 958 bool media_changed; 959 }; 960 961 #define E1000_SHADOW_RAM_WORDS 2048 962 963 /* I218 PHY Ultra Low Power (ULP) states */ 964 enum e1000_ulp_state { 965 e1000_ulp_state_unknown, 966 e1000_ulp_state_off, 967 e1000_ulp_state_on, 968 }; 969 970 struct e1000_dev_spec_ich8lan { 971 bool kmrn_lock_loss_workaround_enabled; 972 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; 973 bool nvm_k1_enabled; 974 bool eee_disable; 975 u16 eee_lp_ability; 976 enum e1000_ulp_state ulp_state; 977 }; 978 979 struct e1000_dev_spec_vf { 980 u32 vf_number; 981 u32 v2p_mailbox; 982 }; 983 984 struct e1000_hw { 985 void *back; 986 987 u8 *hw_addr; 988 u8 *flash_address; 989 unsigned long io_base; 990 991 struct e1000_mac_info mac; 992 struct e1000_fc_info fc; 993 struct e1000_phy_info phy; 994 struct e1000_nvm_info nvm; 995 struct e1000_bus_info bus; 996 struct e1000_mbx_info mbx; 997 struct e1000_host_mng_dhcp_cookie mng_cookie; 998 999 union { 1000 struct e1000_dev_spec_82541 _82541; 1001 #ifndef NO_82542_SUPPORT 1002 struct e1000_dev_spec_82542 _82542; 1003 #endif 1004 struct e1000_dev_spec_82543 _82543; 1005 struct e1000_dev_spec_82571 _82571; 1006 struct e1000_dev_spec_80003es2lan _80003es2lan; 1007 struct e1000_dev_spec_ich8lan ich8lan; 1008 struct e1000_dev_spec_82575 _82575; 1009 struct e1000_dev_spec_vf vf; 1010 } dev_spec; 1011 1012 u16 device_id; 1013 u16 subsystem_vendor_id; 1014 u16 subsystem_device_id; 1015 u16 vendor_id; 1016 1017 u8 revision_id; 1018 }; 1019 1020 #include "e1000_82541.h" 1021 #include "e1000_82543.h" 1022 #include "e1000_82571.h" 1023 #include "e1000_80003es2lan.h" 1024 #include "e1000_ich8lan.h" 1025 #include "e1000_82575.h" 1026 #include "e1000_i210.h" 1027 1028 /* These functions must be implemented by drivers */ 1029 #ifndef NO_82542_SUPPORT 1030 void e1000_pci_clear_mwi(struct e1000_hw *hw); 1031 void e1000_pci_set_mwi(struct e1000_hw *hw); 1032 #endif 1033 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1034 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1035 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1036 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1037 1038 #endif 1039