1 /****************************************************************************** 2 3 Copyright (c) 2001-2011, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #ifndef _E1000_HW_H_ 36 #define _E1000_HW_H_ 37 38 #include "e1000_osdep.h" 39 #include "e1000_regs.h" 40 #include "e1000_defines.h" 41 42 struct e1000_hw; 43 44 #ifndef NO_82542_SUPPORT 45 #define E1000_DEV_ID_82542 0x1000 46 #endif 47 #define E1000_DEV_ID_82543GC_FIBER 0x1001 48 #define E1000_DEV_ID_82543GC_COPPER 0x1004 49 #define E1000_DEV_ID_82544EI_COPPER 0x1008 50 #define E1000_DEV_ID_82544EI_FIBER 0x1009 51 #define E1000_DEV_ID_82544GC_COPPER 0x100C 52 #define E1000_DEV_ID_82544GC_LOM 0x100D 53 #define E1000_DEV_ID_82540EM 0x100E 54 #define E1000_DEV_ID_82540EM_LOM 0x1015 55 #define E1000_DEV_ID_82540EP_LOM 0x1016 56 #define E1000_DEV_ID_82540EP 0x1017 57 #define E1000_DEV_ID_82540EP_LP 0x101E 58 #define E1000_DEV_ID_82545EM_COPPER 0x100F 59 #define E1000_DEV_ID_82545EM_FIBER 0x1011 60 #define E1000_DEV_ID_82545GM_COPPER 0x1026 61 #define E1000_DEV_ID_82545GM_FIBER 0x1027 62 #define E1000_DEV_ID_82545GM_SERDES 0x1028 63 #define E1000_DEV_ID_82546EB_COPPER 0x1010 64 #define E1000_DEV_ID_82546EB_FIBER 0x1012 65 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 66 #define E1000_DEV_ID_82546GB_COPPER 0x1079 67 #define E1000_DEV_ID_82546GB_FIBER 0x107A 68 #define E1000_DEV_ID_82546GB_SERDES 0x107B 69 #define E1000_DEV_ID_82546GB_PCIE 0x108A 70 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 71 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 72 #define E1000_DEV_ID_82541EI 0x1013 73 #define E1000_DEV_ID_82541EI_MOBILE 0x1018 74 #define E1000_DEV_ID_82541ER_LOM 0x1014 75 #define E1000_DEV_ID_82541ER 0x1078 76 #define E1000_DEV_ID_82541GI 0x1076 77 #define E1000_DEV_ID_82541GI_LF 0x107C 78 #define E1000_DEV_ID_82541GI_MOBILE 0x1077 79 #define E1000_DEV_ID_82547EI 0x1019 80 #define E1000_DEV_ID_82547EI_MOBILE 0x101A 81 #define E1000_DEV_ID_82547GI 0x1075 82 #define E1000_DEV_ID_82571EB_COPPER 0x105E 83 #define E1000_DEV_ID_82571EB_FIBER 0x105F 84 #define E1000_DEV_ID_82571EB_SERDES 0x1060 85 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 86 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 87 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 88 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 89 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 90 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 91 #define E1000_DEV_ID_82571EB_QUAD_COPPER_BP 0x10A0 92 #define E1000_DEV_ID_82572EI_COPPER 0x107D 93 #define E1000_DEV_ID_82572EI_FIBER 0x107E 94 #define E1000_DEV_ID_82572EI_SERDES 0x107F 95 #define E1000_DEV_ID_82572EI 0x10B9 96 #define E1000_DEV_ID_82573E 0x108B 97 #define E1000_DEV_ID_82573E_IAMT 0x108C 98 #define E1000_DEV_ID_82573L 0x109A 99 #define E1000_DEV_ID_82574L 0x10D3 100 #define E1000_DEV_ID_82574LA 0x10F6 101 #define E1000_DEV_ID_82583V 0x150C 102 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 103 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 104 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 105 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 106 #define E1000_DEV_ID_ICH8_82567V_3 0x1501 107 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 108 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 109 #define E1000_DEV_ID_ICH8_IGP_C 0x104B 110 #define E1000_DEV_ID_ICH8_IFE 0x104C 111 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 112 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 113 #define E1000_DEV_ID_ICH8_IGP_M 0x104D 114 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF 115 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 116 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 117 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 118 #define E1000_DEV_ID_ICH9_BM 0x10E5 119 #define E1000_DEV_ID_ICH9_IGP_C 0x294C 120 #define E1000_DEV_ID_ICH9_IFE 0x10C0 121 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 122 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 123 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 124 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 125 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 126 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 127 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 128 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525 129 130 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 131 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 132 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 133 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 134 #define E1000_DEV_ID_PCH2_LV_LM 0x1502 135 #define E1000_DEV_ID_PCH2_LV_V 0x1503 136 137 #define E1000_DEV_ID_82576 0x10C9 138 #define E1000_DEV_ID_82576_FIBER 0x10E6 139 #define E1000_DEV_ID_82576_SERDES 0x10E7 140 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 141 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526 142 #define E1000_DEV_ID_82576_NS 0x150A 143 #define E1000_DEV_ID_82576_NS_SERDES 0x1518 144 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D 145 #define E1000_DEV_ID_82576_VF 0x10CA 146 #define E1000_DEV_ID_I350_VF 0x1520 147 #define E1000_DEV_ID_82575EB_COPPER 0x10A7 148 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 149 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 150 #define E1000_DEV_ID_82580_COPPER 0x150E 151 #define E1000_DEV_ID_82580_FIBER 0x150F 152 #define E1000_DEV_ID_82580_SERDES 0x1510 153 #define E1000_DEV_ID_82580_SGMII 0x1511 154 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 155 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527 156 #define E1000_DEV_ID_I350_COPPER 0x1521 157 #define E1000_DEV_ID_I350_FIBER 0x1522 158 #define E1000_DEV_ID_I350_SERDES 0x1523 159 #define E1000_DEV_ID_I350_SGMII 0x1524 160 #define E1000_DEV_ID_I350_DA4 0x1546 161 #if defined(QV_RELEASE) && defined(SPRINGVILLE_FLASHLESS_HW) 162 #define E1000_DEV_ID_I210_NVMLESS 0x1531 163 #endif /* QV_RELEASE && SPRINGVILLE_FLASHLESS_HW */ 164 #define E1000_DEV_ID_I210_COPPER 0x1533 165 #define E1000_DEV_ID_I210_COPPER_OEM1 0x1534 166 #define E1000_DEV_ID_I210_COPPER_IT 0x1535 167 #define E1000_DEV_ID_I210_FIBER 0x1536 168 #define E1000_DEV_ID_I210_SERDES 0x1537 169 #define E1000_DEV_ID_I210_SGMII 0x1538 170 #define E1000_DEV_ID_I211_COPPER 0x1539 171 #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438 172 #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A 173 #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C 174 #define E1000_DEV_ID_DH89XXCC_SFP 0x0440 175 176 #define E1000_REVISION_0 0 177 #define E1000_REVISION_1 1 178 #define E1000_REVISION_2 2 179 #define E1000_REVISION_3 3 180 #define E1000_REVISION_4 4 181 182 #define E1000_FUNC_0 0 183 #define E1000_FUNC_1 1 184 #define E1000_FUNC_2 2 185 #define E1000_FUNC_3 3 186 187 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 188 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 189 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6 190 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9 191 192 enum e1000_mac_type { 193 e1000_undefined = 0, 194 #ifndef NO_82542_SUPPORT 195 e1000_82542, 196 #endif 197 e1000_82543, 198 e1000_82544, 199 e1000_82540, 200 e1000_82545, 201 e1000_82545_rev_3, 202 e1000_82546, 203 e1000_82546_rev_3, 204 e1000_82541, 205 e1000_82541_rev_2, 206 e1000_82547, 207 e1000_82547_rev_2, 208 e1000_82571, 209 e1000_82572, 210 e1000_82573, 211 e1000_82574, 212 e1000_82583, 213 e1000_80003es2lan, 214 e1000_ich8lan, 215 e1000_ich9lan, 216 e1000_ich10lan, 217 e1000_pchlan, 218 e1000_pch2lan, 219 e1000_82575, 220 e1000_82576, 221 e1000_82580, 222 e1000_i350, 223 e1000_i210, 224 e1000_i211, 225 e1000_vfadapt, 226 e1000_vfadapt_i350, 227 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ 228 }; 229 230 enum e1000_media_type { 231 e1000_media_type_unknown = 0, 232 e1000_media_type_copper = 1, 233 e1000_media_type_fiber = 2, 234 e1000_media_type_internal_serdes = 3, 235 e1000_num_media_types 236 }; 237 238 enum e1000_nvm_type { 239 e1000_nvm_unknown = 0, 240 e1000_nvm_none, 241 e1000_nvm_eeprom_spi, 242 e1000_nvm_eeprom_microwire, 243 e1000_nvm_flash_hw, 244 e1000_nvm_flash_sw 245 }; 246 247 enum e1000_nvm_override { 248 e1000_nvm_override_none = 0, 249 e1000_nvm_override_spi_small, 250 e1000_nvm_override_spi_large, 251 e1000_nvm_override_microwire_small, 252 e1000_nvm_override_microwire_large 253 }; 254 255 enum e1000_phy_type { 256 e1000_phy_unknown = 0, 257 e1000_phy_none, 258 e1000_phy_m88, 259 e1000_phy_igp, 260 e1000_phy_igp_2, 261 e1000_phy_gg82563, 262 e1000_phy_igp_3, 263 e1000_phy_ife, 264 e1000_phy_bm, 265 e1000_phy_82578, 266 e1000_phy_82577, 267 e1000_phy_82579, 268 e1000_phy_82580, 269 e1000_phy_vf, 270 e1000_phy_i210, 271 }; 272 273 enum e1000_bus_type { 274 e1000_bus_type_unknown = 0, 275 e1000_bus_type_pci, 276 e1000_bus_type_pcix, 277 e1000_bus_type_pci_express, 278 e1000_bus_type_reserved 279 }; 280 281 enum e1000_bus_speed { 282 e1000_bus_speed_unknown = 0, 283 e1000_bus_speed_33, 284 e1000_bus_speed_66, 285 e1000_bus_speed_100, 286 e1000_bus_speed_120, 287 e1000_bus_speed_133, 288 e1000_bus_speed_2500, 289 e1000_bus_speed_5000, 290 e1000_bus_speed_reserved 291 }; 292 293 enum e1000_bus_width { 294 e1000_bus_width_unknown = 0, 295 e1000_bus_width_pcie_x1, 296 e1000_bus_width_pcie_x2, 297 e1000_bus_width_pcie_x4 = 4, 298 e1000_bus_width_pcie_x8 = 8, 299 e1000_bus_width_32, 300 e1000_bus_width_64, 301 e1000_bus_width_reserved 302 }; 303 304 enum e1000_1000t_rx_status { 305 e1000_1000t_rx_status_not_ok = 0, 306 e1000_1000t_rx_status_ok, 307 e1000_1000t_rx_status_undefined = 0xFF 308 }; 309 310 enum e1000_rev_polarity { 311 e1000_rev_polarity_normal = 0, 312 e1000_rev_polarity_reversed, 313 e1000_rev_polarity_undefined = 0xFF 314 }; 315 316 enum e1000_fc_mode { 317 e1000_fc_none = 0, 318 e1000_fc_rx_pause, 319 e1000_fc_tx_pause, 320 e1000_fc_full, 321 e1000_fc_default = 0xFF 322 }; 323 324 enum e1000_ffe_config { 325 e1000_ffe_config_enabled = 0, 326 e1000_ffe_config_active, 327 e1000_ffe_config_blocked 328 }; 329 330 enum e1000_dsp_config { 331 e1000_dsp_config_disabled = 0, 332 e1000_dsp_config_enabled, 333 e1000_dsp_config_activated, 334 e1000_dsp_config_undefined = 0xFF 335 }; 336 337 enum e1000_ms_type { 338 e1000_ms_hw_default = 0, 339 e1000_ms_force_master, 340 e1000_ms_force_slave, 341 e1000_ms_auto 342 }; 343 344 enum e1000_smart_speed { 345 e1000_smart_speed_default = 0, 346 e1000_smart_speed_on, 347 e1000_smart_speed_off 348 }; 349 350 enum e1000_serdes_link_state { 351 e1000_serdes_link_down = 0, 352 e1000_serdes_link_autoneg_progress, 353 e1000_serdes_link_autoneg_complete, 354 e1000_serdes_link_forced_up 355 }; 356 357 #define __le16 u16 358 #define __le32 u32 359 #define __le64 u64 360 /* Receive Descriptor */ 361 struct e1000_rx_desc { 362 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 363 __le16 length; /* Length of data DMAed into data buffer */ 364 __le16 csum; /* Packet checksum */ 365 u8 status; /* Descriptor status */ 366 u8 errors; /* Descriptor Errors */ 367 __le16 special; 368 }; 369 370 /* Receive Descriptor - Extended */ 371 union e1000_rx_desc_extended { 372 struct { 373 __le64 buffer_addr; 374 __le64 reserved; 375 } read; 376 struct { 377 struct { 378 __le32 mrq; /* Multiple Rx Queues */ 379 union { 380 __le32 rss; /* RSS Hash */ 381 struct { 382 __le16 ip_id; /* IP id */ 383 __le16 csum; /* Packet Checksum */ 384 } csum_ip; 385 } hi_dword; 386 } lower; 387 struct { 388 __le32 status_error; /* ext status/error */ 389 __le16 length; 390 __le16 vlan; /* VLAN tag */ 391 } upper; 392 } wb; /* writeback */ 393 }; 394 395 #define MAX_PS_BUFFERS 4 396 /* Receive Descriptor - Packet Split */ 397 union e1000_rx_desc_packet_split { 398 struct { 399 /* one buffer for protocol header(s), three data buffers */ 400 __le64 buffer_addr[MAX_PS_BUFFERS]; 401 } read; 402 struct { 403 struct { 404 __le32 mrq; /* Multiple Rx Queues */ 405 union { 406 __le32 rss; /* RSS Hash */ 407 struct { 408 __le16 ip_id; /* IP id */ 409 __le16 csum; /* Packet Checksum */ 410 } csum_ip; 411 } hi_dword; 412 } lower; 413 struct { 414 __le32 status_error; /* ext status/error */ 415 __le16 length0; /* length of buffer 0 */ 416 __le16 vlan; /* VLAN tag */ 417 } middle; 418 struct { 419 __le16 header_status; 420 __le16 length[3]; /* length of buffers 1-3 */ 421 } upper; 422 __le64 reserved; 423 } wb; /* writeback */ 424 }; 425 426 /* Transmit Descriptor */ 427 struct e1000_tx_desc { 428 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 429 union { 430 __le32 data; 431 struct { 432 __le16 length; /* Data buffer length */ 433 u8 cso; /* Checksum offset */ 434 u8 cmd; /* Descriptor control */ 435 } flags; 436 } lower; 437 union { 438 __le32 data; 439 struct { 440 u8 status; /* Descriptor status */ 441 u8 css; /* Checksum start */ 442 __le16 special; 443 } fields; 444 } upper; 445 }; 446 447 /* Offload Context Descriptor */ 448 struct e1000_context_desc { 449 union { 450 __le32 ip_config; 451 struct { 452 u8 ipcss; /* IP checksum start */ 453 u8 ipcso; /* IP checksum offset */ 454 __le16 ipcse; /* IP checksum end */ 455 } ip_fields; 456 } lower_setup; 457 union { 458 __le32 tcp_config; 459 struct { 460 u8 tucss; /* TCP checksum start */ 461 u8 tucso; /* TCP checksum offset */ 462 __le16 tucse; /* TCP checksum end */ 463 } tcp_fields; 464 } upper_setup; 465 __le32 cmd_and_length; 466 union { 467 __le32 data; 468 struct { 469 u8 status; /* Descriptor status */ 470 u8 hdr_len; /* Header length */ 471 __le16 mss; /* Maximum segment size */ 472 } fields; 473 } tcp_seg_setup; 474 }; 475 476 /* Offload data descriptor */ 477 struct e1000_data_desc { 478 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 479 union { 480 __le32 data; 481 struct { 482 __le16 length; /* Data buffer length */ 483 u8 typ_len_ext; 484 u8 cmd; 485 } flags; 486 } lower; 487 union { 488 __le32 data; 489 struct { 490 u8 status; /* Descriptor status */ 491 u8 popts; /* Packet Options */ 492 __le16 special; 493 } fields; 494 } upper; 495 }; 496 497 /* Statistics counters collected by the MAC */ 498 struct e1000_hw_stats { 499 u64 crcerrs; 500 u64 algnerrc; 501 u64 symerrs; 502 u64 rxerrc; 503 u64 mpc; 504 u64 scc; 505 u64 ecol; 506 u64 mcc; 507 u64 latecol; 508 u64 colc; 509 u64 dc; 510 u64 tncrs; 511 u64 sec; 512 u64 cexterr; 513 u64 rlec; 514 u64 xonrxc; 515 u64 xontxc; 516 u64 xoffrxc; 517 u64 xofftxc; 518 u64 fcruc; 519 u64 prc64; 520 u64 prc127; 521 u64 prc255; 522 u64 prc511; 523 u64 prc1023; 524 u64 prc1522; 525 u64 gprc; 526 u64 bprc; 527 u64 mprc; 528 u64 gptc; 529 u64 gorc; 530 u64 gotc; 531 u64 rnbc; 532 u64 ruc; 533 u64 rfc; 534 u64 roc; 535 u64 rjc; 536 u64 mgprc; 537 u64 mgpdc; 538 u64 mgptc; 539 u64 tor; 540 u64 tot; 541 u64 tpr; 542 u64 tpt; 543 u64 ptc64; 544 u64 ptc127; 545 u64 ptc255; 546 u64 ptc511; 547 u64 ptc1023; 548 u64 ptc1522; 549 u64 mptc; 550 u64 bptc; 551 u64 tsctc; 552 u64 tsctfc; 553 u64 iac; 554 u64 icrxptc; 555 u64 icrxatc; 556 u64 ictxptc; 557 u64 ictxatc; 558 u64 ictxqec; 559 u64 ictxqmtc; 560 u64 icrxdmtc; 561 u64 icrxoc; 562 u64 cbtmpc; 563 u64 htdpmc; 564 u64 cbrdpc; 565 u64 cbrmpc; 566 u64 rpthc; 567 u64 hgptc; 568 u64 htcbdpc; 569 u64 hgorc; 570 u64 hgotc; 571 u64 lenerrs; 572 u64 scvpc; 573 u64 hrmpc; 574 u64 doosync; 575 u64 o2bgptc; 576 u64 o2bspc; 577 u64 b2ospc; 578 u64 b2ogprc; 579 }; 580 581 struct e1000_vf_stats { 582 u64 base_gprc; 583 u64 base_gptc; 584 u64 base_gorc; 585 u64 base_gotc; 586 u64 base_mprc; 587 u64 base_gotlbc; 588 u64 base_gptlbc; 589 u64 base_gorlbc; 590 u64 base_gprlbc; 591 592 u32 last_gprc; 593 u32 last_gptc; 594 u32 last_gorc; 595 u32 last_gotc; 596 u32 last_mprc; 597 u32 last_gotlbc; 598 u32 last_gptlbc; 599 u32 last_gorlbc; 600 u32 last_gprlbc; 601 602 u64 gprc; 603 u64 gptc; 604 u64 gorc; 605 u64 gotc; 606 u64 mprc; 607 u64 gotlbc; 608 u64 gptlbc; 609 u64 gorlbc; 610 u64 gprlbc; 611 }; 612 613 struct e1000_phy_stats { 614 u32 idle_errors; 615 u32 receive_errors; 616 }; 617 618 struct e1000_host_mng_dhcp_cookie { 619 u32 signature; 620 u8 status; 621 u8 reserved0; 622 u16 vlan_id; 623 u32 reserved1; 624 u16 reserved2; 625 u8 reserved3; 626 u8 checksum; 627 }; 628 629 /* Host Interface "Rev 1" */ 630 struct e1000_host_command_header { 631 u8 command_id; 632 u8 command_length; 633 u8 command_options; 634 u8 checksum; 635 }; 636 637 #define E1000_HI_MAX_DATA_LENGTH 252 638 struct e1000_host_command_info { 639 struct e1000_host_command_header command_header; 640 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 641 }; 642 643 /* Host Interface "Rev 2" */ 644 struct e1000_host_mng_command_header { 645 u8 command_id; 646 u8 checksum; 647 u16 reserved1; 648 u16 reserved2; 649 u16 command_length; 650 }; 651 652 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 653 struct e1000_host_mng_command_info { 654 struct e1000_host_mng_command_header command_header; 655 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 656 }; 657 658 #include "e1000_mac.h" 659 #include "e1000_phy.h" 660 #include "e1000_nvm.h" 661 #include "e1000_manage.h" 662 #include "e1000_mbx.h" 663 664 struct e1000_mac_operations { 665 /* Function pointers for the MAC. */ 666 s32 (*init_params)(struct e1000_hw *); 667 s32 (*id_led_init)(struct e1000_hw *); 668 s32 (*blink_led)(struct e1000_hw *); 669 s32 (*check_for_link)(struct e1000_hw *); 670 bool (*check_mng_mode)(struct e1000_hw *hw); 671 s32 (*cleanup_led)(struct e1000_hw *); 672 void (*clear_hw_cntrs)(struct e1000_hw *); 673 void (*clear_vfta)(struct e1000_hw *); 674 s32 (*get_bus_info)(struct e1000_hw *); 675 void (*set_lan_id)(struct e1000_hw *); 676 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 677 s32 (*led_on)(struct e1000_hw *); 678 s32 (*led_off)(struct e1000_hw *); 679 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 680 s32 (*reset_hw)(struct e1000_hw *); 681 s32 (*init_hw)(struct e1000_hw *); 682 void (*shutdown_serdes)(struct e1000_hw *); 683 void (*power_up_serdes)(struct e1000_hw *); 684 s32 (*setup_link)(struct e1000_hw *); 685 s32 (*setup_physical_interface)(struct e1000_hw *); 686 s32 (*setup_led)(struct e1000_hw *); 687 void (*write_vfta)(struct e1000_hw *, u32, u32); 688 void (*config_collision_dist)(struct e1000_hw *); 689 void (*rar_set)(struct e1000_hw *, u8*, u32); 690 s32 (*read_mac_addr)(struct e1000_hw *); 691 s32 (*validate_mdi_setting)(struct e1000_hw *); 692 s32 (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*); 693 s32 (*mng_write_cmd_header)(struct e1000_hw *hw, 694 struct e1000_host_mng_command_header*); 695 s32 (*mng_enable_host_if)(struct e1000_hw *); 696 s32 (*wait_autoneg)(struct e1000_hw *); 697 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16); 698 void (*release_swfw_sync)(struct e1000_hw *, u16); 699 }; 700 701 /* 702 * When to use various PHY register access functions: 703 * 704 * Func Caller 705 * Function Does Does When to use 706 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 707 * X_reg L,P,A n/a for simple PHY reg accesses 708 * X_reg_locked P,A L for multiple accesses of different regs 709 * on different pages 710 * X_reg_page A L,P for multiple accesses of different regs 711 * on the same page 712 * 713 * Where X=[read|write], L=locking, P=sets page, A=register access 714 * 715 */ 716 struct e1000_phy_operations { 717 s32 (*init_params)(struct e1000_hw *); 718 s32 (*acquire)(struct e1000_hw *); 719 s32 (*cfg_on_link_up)(struct e1000_hw *); 720 s32 (*check_polarity)(struct e1000_hw *); 721 s32 (*check_reset_block)(struct e1000_hw *); 722 s32 (*commit)(struct e1000_hw *); 723 s32 (*force_speed_duplex)(struct e1000_hw *); 724 s32 (*get_cfg_done)(struct e1000_hw *hw); 725 s32 (*get_cable_length)(struct e1000_hw *); 726 s32 (*get_info)(struct e1000_hw *); 727 s32 (*set_page)(struct e1000_hw *, u16); 728 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 729 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 730 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *); 731 void (*release)(struct e1000_hw *); 732 s32 (*reset)(struct e1000_hw *); 733 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 734 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 735 s32 (*write_reg)(struct e1000_hw *, u32, u16); 736 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 737 s32 (*write_reg_page)(struct e1000_hw *, u32, u16); 738 void (*power_up)(struct e1000_hw *); 739 void (*power_down)(struct e1000_hw *); 740 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *); 741 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8); 742 }; 743 744 struct e1000_nvm_operations { 745 s32 (*init_params)(struct e1000_hw *); 746 s32 (*acquire)(struct e1000_hw *); 747 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 748 void (*release)(struct e1000_hw *); 749 void (*reload)(struct e1000_hw *); 750 s32 (*update)(struct e1000_hw *); 751 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 752 s32 (*validate)(struct e1000_hw *); 753 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 754 }; 755 756 struct e1000_mac_info { 757 struct e1000_mac_operations ops; 758 u8 addr[ETH_ADDR_LEN]; 759 u8 perm_addr[ETH_ADDR_LEN]; 760 761 enum e1000_mac_type type; 762 763 u32 collision_delta; 764 u32 ledctl_default; 765 u32 ledctl_mode1; 766 u32 ledctl_mode2; 767 u32 mc_filter_type; 768 u32 tx_packet_delta; 769 u32 txcw; 770 771 u16 current_ifs_val; 772 u16 ifs_max_val; 773 u16 ifs_min_val; 774 u16 ifs_ratio; 775 u16 ifs_step_size; 776 u16 mta_reg_count; 777 u16 uta_reg_count; 778 779 /* Maximum size of the MTA register table in all supported adapters */ 780 #define MAX_MTA_REG 128 781 u32 mta_shadow[MAX_MTA_REG]; 782 u16 rar_entry_count; 783 784 u8 forced_speed_duplex; 785 786 bool adaptive_ifs; 787 bool has_fwsm; 788 bool arc_subsystem_valid; 789 bool asf_firmware_present; 790 bool autoneg; 791 bool autoneg_failed; 792 bool get_link_status; 793 bool in_ifs_mode; 794 #ifndef NO_82542_SUPPORT 795 bool report_tx_early; 796 #endif 797 enum e1000_serdes_link_state serdes_link_state; 798 bool serdes_has_link; 799 bool tx_pkt_filtering; 800 }; 801 802 struct e1000_phy_info { 803 struct e1000_phy_operations ops; 804 enum e1000_phy_type type; 805 806 enum e1000_1000t_rx_status local_rx; 807 enum e1000_1000t_rx_status remote_rx; 808 enum e1000_ms_type ms_type; 809 enum e1000_ms_type original_ms_type; 810 enum e1000_rev_polarity cable_polarity; 811 enum e1000_smart_speed smart_speed; 812 813 u32 addr; 814 u32 id; 815 u32 reset_delay_us; /* in usec */ 816 u32 revision; 817 818 enum e1000_media_type media_type; 819 820 u16 autoneg_advertised; 821 u16 autoneg_mask; 822 u16 cable_length; 823 u16 max_cable_length; 824 u16 min_cable_length; 825 826 u8 mdix; 827 828 bool disable_polarity_correction; 829 bool is_mdix; 830 bool polarity_correction; 831 bool speed_downgraded; 832 bool autoneg_wait_to_complete; 833 }; 834 835 struct e1000_nvm_info { 836 struct e1000_nvm_operations ops; 837 enum e1000_nvm_type type; 838 enum e1000_nvm_override override; 839 840 u32 flash_bank_size; 841 u32 flash_base_addr; 842 843 u16 word_size; 844 u16 delay_usec; 845 u16 address_bits; 846 u16 opcode_bits; 847 u16 page_size; 848 }; 849 850 struct e1000_bus_info { 851 enum e1000_bus_type type; 852 enum e1000_bus_speed speed; 853 enum e1000_bus_width width; 854 855 u16 func; 856 u16 pci_cmd_word; 857 }; 858 859 struct e1000_fc_info { 860 u32 high_water; /* Flow control high-water mark */ 861 u32 low_water; /* Flow control low-water mark */ 862 u16 pause_time; /* Flow control pause timer */ 863 u16 refresh_time; /* Flow control refresh timer */ 864 bool send_xon; /* Flow control send XON */ 865 bool strict_ieee; /* Strict IEEE mode */ 866 enum e1000_fc_mode current_mode; /* FC mode in effect */ 867 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 868 }; 869 870 struct e1000_dev_spec_82541 { 871 enum e1000_dsp_config dsp_config; 872 enum e1000_ffe_config ffe_config; 873 u16 spd_default; 874 bool phy_init_script; 875 }; 876 877 #ifndef NO_82542_SUPPORT 878 struct e1000_dev_spec_82542 { 879 bool dma_fairness; 880 }; 881 882 #endif /* NO_82542_SUPPORT */ 883 struct e1000_dev_spec_82543 { 884 u32 tbi_compatibility; 885 bool dma_fairness; 886 bool init_phy_disabled; 887 }; 888 889 struct e1000_dev_spec_82571 { 890 bool laa_is_present; 891 u32 smb_counter; 892 }; 893 894 struct e1000_dev_spec_80003es2lan { 895 bool mdic_wa_enable; 896 }; 897 898 struct e1000_shadow_ram { 899 u16 value; 900 bool modified; 901 }; 902 903 struct e1000_mbx_operations { 904 s32 (*init_params)(struct e1000_hw *hw); 905 s32 (*read)(struct e1000_hw *, u32 *, u16, u16); 906 s32 (*write)(struct e1000_hw *, u32 *, u16, u16); 907 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16); 908 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16); 909 s32 (*check_for_msg)(struct e1000_hw *, u16); 910 s32 (*check_for_ack)(struct e1000_hw *, u16); 911 s32 (*check_for_rst)(struct e1000_hw *, u16); 912 }; 913 914 struct e1000_mbx_stats { 915 u32 msgs_tx; 916 u32 msgs_rx; 917 918 u32 acks; 919 u32 reqs; 920 u32 rsts; 921 }; 922 923 struct e1000_mbx_info { 924 struct e1000_mbx_operations ops; 925 struct e1000_mbx_stats stats; 926 u32 timeout; 927 u32 usec_delay; 928 u16 size; 929 }; 930 931 struct e1000_dev_spec_82575 { 932 bool sgmii_active; 933 bool global_device_reset; 934 bool eee_disable; 935 bool module_plugged; 936 u32 mtu; 937 struct sfp_e1000_flags eth_flags; 938 }; 939 940 #define E1000_SHADOW_RAM_WORDS 2048 941 942 struct e1000_dev_spec_ich8lan { 943 bool kmrn_lock_loss_workaround_enabled; 944 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; 945 bool nvm_k1_enabled; 946 bool eee_disable; 947 }; 948 949 struct e1000_dev_spec_vf { 950 u32 vf_number; 951 u32 v2p_mailbox; 952 }; 953 954 struct e1000_hw { 955 void *back; 956 957 u8 *hw_addr; 958 u8 *flash_address; 959 unsigned long io_base; 960 961 struct e1000_mac_info mac; 962 struct e1000_fc_info fc; 963 struct e1000_phy_info phy; 964 struct e1000_nvm_info nvm; 965 struct e1000_bus_info bus; 966 struct e1000_mbx_info mbx; 967 struct e1000_host_mng_dhcp_cookie mng_cookie; 968 969 union { 970 struct e1000_dev_spec_82541 _82541; 971 #ifndef NO_82542_SUPPORT 972 struct e1000_dev_spec_82542 _82542; 973 #endif 974 struct e1000_dev_spec_82543 _82543; 975 struct e1000_dev_spec_82571 _82571; 976 struct e1000_dev_spec_80003es2lan _80003es2lan; 977 struct e1000_dev_spec_ich8lan ich8lan; 978 struct e1000_dev_spec_82575 _82575; 979 struct e1000_dev_spec_vf vf; 980 } dev_spec; 981 982 u16 device_id; 983 u16 subsystem_vendor_id; 984 u16 subsystem_device_id; 985 u16 vendor_id; 986 987 u8 revision_id; 988 }; 989 990 #include "e1000_82541.h" 991 #include "e1000_82543.h" 992 #include "e1000_82571.h" 993 #include "e1000_80003es2lan.h" 994 #include "e1000_ich8lan.h" 995 #include "e1000_82575.h" 996 #include "e1000_i210.h" 997 998 /* These functions must be implemented by drivers */ 999 #ifndef NO_82542_SUPPORT 1000 void e1000_pci_clear_mwi(struct e1000_hw *hw); 1001 void e1000_pci_set_mwi(struct e1000_hw *hw); 1002 #endif 1003 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1004 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1005 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1006 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1007 1008 #endif 1009