1 /****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD: $*/ 34 35 #ifndef _E1000_HW_H_ 36 #define _E1000_HW_H_ 37 38 #include "e1000_osdep.h" 39 #include "e1000_regs.h" 40 #include "e1000_defines.h" 41 42 struct e1000_hw; 43 44 #ifndef NO_82542_SUPPORT 45 #define E1000_DEV_ID_82542 0x1000 46 #endif 47 #define E1000_DEV_ID_82543GC_FIBER 0x1001 48 #define E1000_DEV_ID_82543GC_COPPER 0x1004 49 #define E1000_DEV_ID_82544EI_COPPER 0x1008 50 #define E1000_DEV_ID_82544EI_FIBER 0x1009 51 #define E1000_DEV_ID_82544GC_COPPER 0x100C 52 #define E1000_DEV_ID_82544GC_LOM 0x100D 53 #define E1000_DEV_ID_82540EM 0x100E 54 #define E1000_DEV_ID_82540EM_LOM 0x1015 55 #define E1000_DEV_ID_82540EP_LOM 0x1016 56 #define E1000_DEV_ID_82540EP 0x1017 57 #define E1000_DEV_ID_82540EP_LP 0x101E 58 #define E1000_DEV_ID_82545EM_COPPER 0x100F 59 #define E1000_DEV_ID_82545EM_FIBER 0x1011 60 #define E1000_DEV_ID_82545GM_COPPER 0x1026 61 #define E1000_DEV_ID_82545GM_FIBER 0x1027 62 #define E1000_DEV_ID_82545GM_SERDES 0x1028 63 #define E1000_DEV_ID_82546EB_COPPER 0x1010 64 #define E1000_DEV_ID_82546EB_FIBER 0x1012 65 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 66 #define E1000_DEV_ID_82546GB_COPPER 0x1079 67 #define E1000_DEV_ID_82546GB_FIBER 0x107A 68 #define E1000_DEV_ID_82546GB_SERDES 0x107B 69 #define E1000_DEV_ID_82546GB_PCIE 0x108A 70 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 71 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 72 #define E1000_DEV_ID_82541EI 0x1013 73 #define E1000_DEV_ID_82541EI_MOBILE 0x1018 74 #define E1000_DEV_ID_82541ER_LOM 0x1014 75 #define E1000_DEV_ID_82541ER 0x1078 76 #define E1000_DEV_ID_82541GI 0x1076 77 #define E1000_DEV_ID_82541GI_LF 0x107C 78 #define E1000_DEV_ID_82541GI_MOBILE 0x1077 79 #define E1000_DEV_ID_82547EI 0x1019 80 #define E1000_DEV_ID_82547EI_MOBILE 0x101A 81 #define E1000_DEV_ID_82547GI 0x1075 82 #define E1000_DEV_ID_82571EB_COPPER 0x105E 83 #define E1000_DEV_ID_82571EB_FIBER 0x105F 84 #define E1000_DEV_ID_82571EB_SERDES 0x1060 85 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 86 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 87 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 88 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 89 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 90 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 91 #define E1000_DEV_ID_82571EB_QUAD_COPPER_BP 0x10A0 92 #define E1000_DEV_ID_82572EI_COPPER 0x107D 93 #define E1000_DEV_ID_82572EI_FIBER 0x107E 94 #define E1000_DEV_ID_82572EI_SERDES 0x107F 95 #define E1000_DEV_ID_82572EI 0x10B9 96 #define E1000_DEV_ID_82573E 0x108B 97 #define E1000_DEV_ID_82573E_IAMT 0x108C 98 #define E1000_DEV_ID_82573L 0x109A 99 #define E1000_DEV_ID_82574L 0x10D3 100 #define E1000_DEV_ID_82574LA 0x10F6 101 #define E1000_DEV_ID_82583V 0x150C 102 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 103 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 104 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 105 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 106 #define E1000_DEV_ID_ICH8_82567V_3 0x1501 107 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 108 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 109 #define E1000_DEV_ID_ICH8_IGP_C 0x104B 110 #define E1000_DEV_ID_ICH8_IFE 0x104C 111 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 112 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 113 #define E1000_DEV_ID_ICH8_IGP_M 0x104D 114 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF 115 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 116 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 117 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 118 #define E1000_DEV_ID_ICH9_BM 0x10E5 119 #define E1000_DEV_ID_ICH9_IGP_C 0x294C 120 #define E1000_DEV_ID_ICH9_IFE 0x10C0 121 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 122 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 123 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 124 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 125 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 126 #define E1000_DEV_ID_ICH10_HANKSVILLE 0xF0FE 127 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 128 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 129 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525 130 131 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 132 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 133 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 134 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 135 #define E1000_DEV_ID_PCH2_LV_LM 0x1502 136 #define E1000_DEV_ID_PCH2_LV_V 0x1503 137 #define E1000_DEV_ID_82580_COPPER 0x150E 138 #define E1000_DEV_ID_82580_FIBER 0x150F 139 #define E1000_DEV_ID_82580_SERDES 0x1510 140 #define E1000_DEV_ID_82580_SGMII 0x1511 141 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 142 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527 143 #define E1000_REVISION_0 0 144 #define E1000_REVISION_1 1 145 #define E1000_REVISION_2 2 146 #define E1000_REVISION_3 3 147 #define E1000_REVISION_4 4 148 149 #define E1000_FUNC_0 0 150 #define E1000_FUNC_1 1 151 #define E1000_FUNC_2 2 152 #define E1000_FUNC_3 3 153 154 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 155 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 156 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6 157 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9 158 159 enum e1000_mac_type { 160 e1000_undefined = 0, 161 #ifndef NO_82542_SUPPORT 162 e1000_82542, 163 #endif 164 e1000_82543, 165 e1000_82544, 166 e1000_82540, 167 e1000_82545, 168 e1000_82545_rev_3, 169 e1000_82546, 170 e1000_82546_rev_3, 171 e1000_82541, 172 e1000_82541_rev_2, 173 e1000_82547, 174 e1000_82547_rev_2, 175 e1000_82571, 176 e1000_82572, 177 e1000_82573, 178 e1000_82574, 179 e1000_82583, 180 e1000_80003es2lan, 181 e1000_ich8lan, 182 e1000_ich9lan, 183 e1000_ich10lan, 184 e1000_pchlan, 185 e1000_pch2lan, 186 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ 187 }; 188 189 enum e1000_media_type { 190 e1000_media_type_unknown = 0, 191 e1000_media_type_copper = 1, 192 e1000_media_type_fiber = 2, 193 e1000_media_type_internal_serdes = 3, 194 e1000_num_media_types 195 }; 196 197 enum e1000_nvm_type { 198 e1000_nvm_unknown = 0, 199 e1000_nvm_none, 200 e1000_nvm_eeprom_spi, 201 e1000_nvm_eeprom_microwire, 202 e1000_nvm_flash_hw, 203 e1000_nvm_flash_sw 204 }; 205 206 enum e1000_nvm_override { 207 e1000_nvm_override_none = 0, 208 e1000_nvm_override_spi_small, 209 e1000_nvm_override_spi_large, 210 e1000_nvm_override_microwire_small, 211 e1000_nvm_override_microwire_large 212 }; 213 214 enum e1000_phy_type { 215 e1000_phy_unknown = 0, 216 e1000_phy_none, 217 e1000_phy_m88, 218 e1000_phy_igp, 219 e1000_phy_igp_2, 220 e1000_phy_gg82563, 221 e1000_phy_igp_3, 222 e1000_phy_ife, 223 e1000_phy_bm, 224 e1000_phy_82578, 225 e1000_phy_82577, 226 e1000_phy_82579, 227 e1000_phy_82580, 228 }; 229 230 enum e1000_bus_type { 231 e1000_bus_type_unknown = 0, 232 e1000_bus_type_pci, 233 e1000_bus_type_pcix, 234 e1000_bus_type_pci_express, 235 e1000_bus_type_reserved 236 }; 237 238 enum e1000_bus_speed { 239 e1000_bus_speed_unknown = 0, 240 e1000_bus_speed_33, 241 e1000_bus_speed_66, 242 e1000_bus_speed_100, 243 e1000_bus_speed_120, 244 e1000_bus_speed_133, 245 e1000_bus_speed_2500, 246 e1000_bus_speed_5000, 247 e1000_bus_speed_reserved 248 }; 249 250 enum e1000_bus_width { 251 e1000_bus_width_unknown = 0, 252 e1000_bus_width_pcie_x1, 253 e1000_bus_width_pcie_x2, 254 e1000_bus_width_pcie_x4 = 4, 255 e1000_bus_width_pcie_x8 = 8, 256 e1000_bus_width_32, 257 e1000_bus_width_64, 258 e1000_bus_width_reserved 259 }; 260 261 enum e1000_1000t_rx_status { 262 e1000_1000t_rx_status_not_ok = 0, 263 e1000_1000t_rx_status_ok, 264 e1000_1000t_rx_status_undefined = 0xFF 265 }; 266 267 enum e1000_rev_polarity { 268 e1000_rev_polarity_normal = 0, 269 e1000_rev_polarity_reversed, 270 e1000_rev_polarity_undefined = 0xFF 271 }; 272 273 enum e1000_fc_mode { 274 e1000_fc_none = 0, 275 e1000_fc_rx_pause, 276 e1000_fc_tx_pause, 277 e1000_fc_full, 278 e1000_fc_default = 0xFF 279 }; 280 281 enum e1000_ffe_config { 282 e1000_ffe_config_enabled = 0, 283 e1000_ffe_config_active, 284 e1000_ffe_config_blocked 285 }; 286 287 enum e1000_dsp_config { 288 e1000_dsp_config_disabled = 0, 289 e1000_dsp_config_enabled, 290 e1000_dsp_config_activated, 291 e1000_dsp_config_undefined = 0xFF 292 }; 293 294 enum e1000_ms_type { 295 e1000_ms_hw_default = 0, 296 e1000_ms_force_master, 297 e1000_ms_force_slave, 298 e1000_ms_auto 299 }; 300 301 enum e1000_smart_speed { 302 e1000_smart_speed_default = 0, 303 e1000_smart_speed_on, 304 e1000_smart_speed_off 305 }; 306 307 enum e1000_serdes_link_state { 308 e1000_serdes_link_down = 0, 309 e1000_serdes_link_autoneg_progress, 310 e1000_serdes_link_autoneg_complete, 311 e1000_serdes_link_forced_up 312 }; 313 314 #define __le16 u16 315 #define __le32 u32 316 #define __le64 u64 317 /* Receive Descriptor */ 318 struct e1000_rx_desc { 319 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 320 __le16 length; /* Length of data DMAed into data buffer */ 321 __le16 csum; /* Packet checksum */ 322 u8 status; /* Descriptor status */ 323 u8 errors; /* Descriptor Errors */ 324 __le16 special; 325 }; 326 327 /* Receive Descriptor - Extended */ 328 union e1000_rx_desc_extended { 329 struct { 330 __le64 buffer_addr; 331 __le64 reserved; 332 } read; 333 struct { 334 struct { 335 __le32 mrq; /* Multiple Rx Queues */ 336 union { 337 __le32 rss; /* RSS Hash */ 338 struct { 339 __le16 ip_id; /* IP id */ 340 __le16 csum; /* Packet Checksum */ 341 } csum_ip; 342 } hi_dword; 343 } lower; 344 struct { 345 __le32 status_error; /* ext status/error */ 346 __le16 length; 347 __le16 vlan; /* VLAN tag */ 348 } upper; 349 } wb; /* writeback */ 350 }; 351 352 #define MAX_PS_BUFFERS 4 353 /* Receive Descriptor - Packet Split */ 354 union e1000_rx_desc_packet_split { 355 struct { 356 /* one buffer for protocol header(s), three data buffers */ 357 __le64 buffer_addr[MAX_PS_BUFFERS]; 358 } read; 359 struct { 360 struct { 361 __le32 mrq; /* Multiple Rx Queues */ 362 union { 363 __le32 rss; /* RSS Hash */ 364 struct { 365 __le16 ip_id; /* IP id */ 366 __le16 csum; /* Packet Checksum */ 367 } csum_ip; 368 } hi_dword; 369 } lower; 370 struct { 371 __le32 status_error; /* ext status/error */ 372 __le16 length0; /* length of buffer 0 */ 373 __le16 vlan; /* VLAN tag */ 374 } middle; 375 struct { 376 __le16 header_status; 377 __le16 length[3]; /* length of buffers 1-3 */ 378 } upper; 379 __le64 reserved; 380 } wb; /* writeback */ 381 }; 382 383 /* Transmit Descriptor */ 384 struct e1000_tx_desc { 385 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 386 union { 387 __le32 data; 388 struct { 389 __le16 length; /* Data buffer length */ 390 u8 cso; /* Checksum offset */ 391 u8 cmd; /* Descriptor control */ 392 } flags; 393 } lower; 394 union { 395 __le32 data; 396 struct { 397 u8 status; /* Descriptor status */ 398 u8 css; /* Checksum start */ 399 __le16 special; 400 } fields; 401 } upper; 402 }; 403 404 /* Offload Context Descriptor */ 405 struct e1000_context_desc { 406 union { 407 __le32 ip_config; 408 struct { 409 u8 ipcss; /* IP checksum start */ 410 u8 ipcso; /* IP checksum offset */ 411 __le16 ipcse; /* IP checksum end */ 412 } ip_fields; 413 } lower_setup; 414 union { 415 __le32 tcp_config; 416 struct { 417 u8 tucss; /* TCP checksum start */ 418 u8 tucso; /* TCP checksum offset */ 419 __le16 tucse; /* TCP checksum end */ 420 } tcp_fields; 421 } upper_setup; 422 __le32 cmd_and_length; 423 union { 424 __le32 data; 425 struct { 426 u8 status; /* Descriptor status */ 427 u8 hdr_len; /* Header length */ 428 __le16 mss; /* Maximum segment size */ 429 } fields; 430 } tcp_seg_setup; 431 }; 432 433 /* Offload data descriptor */ 434 struct e1000_data_desc { 435 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 436 union { 437 __le32 data; 438 struct { 439 __le16 length; /* Data buffer length */ 440 u8 typ_len_ext; 441 u8 cmd; 442 } flags; 443 } lower; 444 union { 445 __le32 data; 446 struct { 447 u8 status; /* Descriptor status */ 448 u8 popts; /* Packet Options */ 449 __le16 special; 450 } fields; 451 } upper; 452 }; 453 454 /* Statistics counters collected by the MAC */ 455 struct e1000_hw_stats { 456 u64 crcerrs; 457 u64 algnerrc; 458 u64 symerrs; 459 u64 rxerrc; 460 u64 mpc; 461 u64 scc; 462 u64 ecol; 463 u64 mcc; 464 u64 latecol; 465 u64 colc; 466 u64 dc; 467 u64 tncrs; 468 u64 sec; 469 u64 cexterr; 470 u64 rlec; 471 u64 xonrxc; 472 u64 xontxc; 473 u64 xoffrxc; 474 u64 xofftxc; 475 u64 fcruc; 476 u64 prc64; 477 u64 prc127; 478 u64 prc255; 479 u64 prc511; 480 u64 prc1023; 481 u64 prc1522; 482 u64 gprc; 483 u64 bprc; 484 u64 mprc; 485 u64 gptc; 486 u64 gorc; 487 u64 gotc; 488 u64 rnbc; 489 u64 ruc; 490 u64 rfc; 491 u64 roc; 492 u64 rjc; 493 u64 mgprc; 494 u64 mgpdc; 495 u64 mgptc; 496 u64 tor; 497 u64 tot; 498 u64 tpr; 499 u64 tpt; 500 u64 ptc64; 501 u64 ptc127; 502 u64 ptc255; 503 u64 ptc511; 504 u64 ptc1023; 505 u64 ptc1522; 506 u64 mptc; 507 u64 bptc; 508 u64 tsctc; 509 u64 tsctfc; 510 u64 iac; 511 u64 icrxptc; 512 u64 icrxatc; 513 u64 ictxptc; 514 u64 ictxatc; 515 u64 ictxqec; 516 u64 ictxqmtc; 517 u64 icrxdmtc; 518 u64 icrxoc; 519 u64 cbtmpc; 520 u64 htdpmc; 521 u64 cbrdpc; 522 u64 cbrmpc; 523 u64 rpthc; 524 u64 hgptc; 525 u64 htcbdpc; 526 u64 hgorc; 527 u64 hgotc; 528 u64 lenerrs; 529 u64 scvpc; 530 u64 hrmpc; 531 u64 doosync; 532 }; 533 534 535 struct e1000_phy_stats { 536 u32 idle_errors; 537 u32 receive_errors; 538 }; 539 540 struct e1000_host_mng_dhcp_cookie { 541 u32 signature; 542 u8 status; 543 u8 reserved0; 544 u16 vlan_id; 545 u32 reserved1; 546 u16 reserved2; 547 u8 reserved3; 548 u8 checksum; 549 }; 550 551 /* Host Interface "Rev 1" */ 552 struct e1000_host_command_header { 553 u8 command_id; 554 u8 command_length; 555 u8 command_options; 556 u8 checksum; 557 }; 558 559 #define E1000_HI_MAX_DATA_LENGTH 252 560 struct e1000_host_command_info { 561 struct e1000_host_command_header command_header; 562 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 563 }; 564 565 /* Host Interface "Rev 2" */ 566 struct e1000_host_mng_command_header { 567 u8 command_id; 568 u8 checksum; 569 u16 reserved1; 570 u16 reserved2; 571 u16 command_length; 572 }; 573 574 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 575 struct e1000_host_mng_command_info { 576 struct e1000_host_mng_command_header command_header; 577 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 578 }; 579 580 #include "e1000_mac.h" 581 #include "e1000_phy.h" 582 #include "e1000_nvm.h" 583 #include "e1000_manage.h" 584 585 struct e1000_mac_operations { 586 /* Function pointers for the MAC. */ 587 s32 (*init_params)(struct e1000_hw *); 588 s32 (*id_led_init)(struct e1000_hw *); 589 s32 (*blink_led)(struct e1000_hw *); 590 s32 (*check_for_link)(struct e1000_hw *); 591 bool (*check_mng_mode)(struct e1000_hw *hw); 592 s32 (*cleanup_led)(struct e1000_hw *); 593 void (*clear_hw_cntrs)(struct e1000_hw *); 594 void (*clear_vfta)(struct e1000_hw *); 595 s32 (*get_bus_info)(struct e1000_hw *); 596 void (*set_lan_id)(struct e1000_hw *); 597 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 598 s32 (*led_on)(struct e1000_hw *); 599 s32 (*led_off)(struct e1000_hw *); 600 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 601 s32 (*reset_hw)(struct e1000_hw *); 602 s32 (*init_hw)(struct e1000_hw *); 603 s32 (*setup_link)(struct e1000_hw *); 604 s32 (*setup_physical_interface)(struct e1000_hw *); 605 s32 (*setup_led)(struct e1000_hw *); 606 void (*write_vfta)(struct e1000_hw *, u32, u32); 607 void (*config_collision_dist)(struct e1000_hw *); 608 void (*rar_set)(struct e1000_hw *, u8*, u32); 609 s32 (*read_mac_addr)(struct e1000_hw *); 610 s32 (*validate_mdi_setting)(struct e1000_hw *); 611 s32 (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*); 612 s32 (*mng_write_cmd_header)(struct e1000_hw *hw, 613 struct e1000_host_mng_command_header*); 614 s32 (*mng_enable_host_if)(struct e1000_hw *); 615 s32 (*wait_autoneg)(struct e1000_hw *); 616 }; 617 618 struct e1000_phy_operations { 619 s32 (*init_params)(struct e1000_hw *); 620 s32 (*acquire)(struct e1000_hw *); 621 s32 (*cfg_on_link_up)(struct e1000_hw *); 622 s32 (*check_polarity)(struct e1000_hw *); 623 s32 (*check_reset_block)(struct e1000_hw *); 624 s32 (*commit)(struct e1000_hw *); 625 s32 (*force_speed_duplex)(struct e1000_hw *); 626 s32 (*get_cfg_done)(struct e1000_hw *hw); 627 s32 (*get_cable_length)(struct e1000_hw *); 628 s32 (*get_info)(struct e1000_hw *); 629 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 630 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 631 void (*release)(struct e1000_hw *); 632 s32 (*reset)(struct e1000_hw *); 633 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 634 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 635 s32 (*write_reg)(struct e1000_hw *, u32, u16); 636 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 637 void (*power_up)(struct e1000_hw *); 638 void (*power_down)(struct e1000_hw *); 639 }; 640 641 struct e1000_nvm_operations { 642 s32 (*init_params)(struct e1000_hw *); 643 s32 (*acquire)(struct e1000_hw *); 644 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 645 void (*release)(struct e1000_hw *); 646 void (*reload)(struct e1000_hw *); 647 s32 (*update)(struct e1000_hw *); 648 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 649 s32 (*validate)(struct e1000_hw *); 650 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 651 }; 652 653 struct e1000_mac_info { 654 struct e1000_mac_operations ops; 655 u8 addr[6]; 656 u8 perm_addr[6]; 657 658 enum e1000_mac_type type; 659 660 u32 collision_delta; 661 u32 ledctl_default; 662 u32 ledctl_mode1; 663 u32 ledctl_mode2; 664 u32 mc_filter_type; 665 u32 tx_packet_delta; 666 u32 txcw; 667 668 u16 current_ifs_val; 669 u16 ifs_max_val; 670 u16 ifs_min_val; 671 u16 ifs_ratio; 672 u16 ifs_step_size; 673 u16 mta_reg_count; 674 675 /* Maximum size of the MTA register table in all supported adapters */ 676 #define MAX_MTA_REG 128 677 u32 mta_shadow[MAX_MTA_REG]; 678 u16 rar_entry_count; 679 680 u8 forced_speed_duplex; 681 682 bool adaptive_ifs; 683 bool has_fwsm; 684 bool arc_subsystem_valid; 685 bool asf_firmware_present; 686 bool autoneg; 687 bool autoneg_failed; 688 bool get_link_status; 689 bool in_ifs_mode; 690 #ifndef NO_82542_SUPPORT 691 bool report_tx_early; 692 #endif 693 enum e1000_serdes_link_state serdes_link_state; 694 bool serdes_has_link; 695 bool tx_pkt_filtering; 696 }; 697 698 struct e1000_phy_info { 699 struct e1000_phy_operations ops; 700 enum e1000_phy_type type; 701 702 enum e1000_1000t_rx_status local_rx; 703 enum e1000_1000t_rx_status remote_rx; 704 enum e1000_ms_type ms_type; 705 enum e1000_ms_type original_ms_type; 706 enum e1000_rev_polarity cable_polarity; 707 enum e1000_smart_speed smart_speed; 708 709 u32 addr; 710 u32 id; 711 u32 reset_delay_us; /* in usec */ 712 u32 revision; 713 714 enum e1000_media_type media_type; 715 716 u16 autoneg_advertised; 717 u16 autoneg_mask; 718 u16 cable_length; 719 u16 max_cable_length; 720 u16 min_cable_length; 721 722 u8 mdix; 723 724 bool disable_polarity_correction; 725 bool is_mdix; 726 bool polarity_correction; 727 bool reset_disable; 728 bool speed_downgraded; 729 bool autoneg_wait_to_complete; 730 }; 731 732 struct e1000_nvm_info { 733 struct e1000_nvm_operations ops; 734 enum e1000_nvm_type type; 735 enum e1000_nvm_override override; 736 737 u32 flash_bank_size; 738 u32 flash_base_addr; 739 740 u16 word_size; 741 u16 delay_usec; 742 u16 address_bits; 743 u16 opcode_bits; 744 u16 page_size; 745 }; 746 747 struct e1000_bus_info { 748 enum e1000_bus_type type; 749 enum e1000_bus_speed speed; 750 enum e1000_bus_width width; 751 752 u16 func; 753 u16 pci_cmd_word; 754 }; 755 756 struct e1000_fc_info { 757 u32 high_water; /* Flow control high-water mark */ 758 u32 low_water; /* Flow control low-water mark */ 759 u16 pause_time; /* Flow control pause timer */ 760 u16 refresh_time; /* Flow control refresh timer */ 761 bool send_xon; /* Flow control send XON */ 762 bool strict_ieee; /* Strict IEEE mode */ 763 enum e1000_fc_mode current_mode; /* FC mode in effect */ 764 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 765 }; 766 767 struct e1000_dev_spec_82541 { 768 enum e1000_dsp_config dsp_config; 769 enum e1000_ffe_config ffe_config; 770 u16 spd_default; 771 bool phy_init_script; 772 }; 773 774 #ifndef NO_82542_SUPPORT 775 struct e1000_dev_spec_82542 { 776 bool dma_fairness; 777 }; 778 779 #endif /* NO_82542_SUPPORT */ 780 struct e1000_dev_spec_82543 { 781 u32 tbi_compatibility; 782 bool dma_fairness; 783 bool init_phy_disabled; 784 }; 785 786 struct e1000_dev_spec_82571 { 787 bool laa_is_present; 788 u32 smb_counter; 789 }; 790 791 struct e1000_dev_spec_80003es2lan { 792 bool mdic_wa_enable; 793 }; 794 795 struct e1000_shadow_ram { 796 u16 value; 797 bool modified; 798 }; 799 800 #define E1000_SHADOW_RAM_WORDS 2048 801 802 struct e1000_dev_spec_ich8lan { 803 bool kmrn_lock_loss_workaround_enabled; 804 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; 805 bool nvm_k1_enabled; 806 bool eee_disable; 807 }; 808 809 struct e1000_hw { 810 void *back; 811 812 u8 *hw_addr; 813 u8 *flash_address; 814 unsigned long io_base; 815 816 struct e1000_mac_info mac; 817 struct e1000_fc_info fc; 818 struct e1000_phy_info phy; 819 struct e1000_nvm_info nvm; 820 struct e1000_bus_info bus; 821 struct e1000_host_mng_dhcp_cookie mng_cookie; 822 823 union { 824 struct e1000_dev_spec_82541 _82541; 825 #ifndef NO_82542_SUPPORT 826 struct e1000_dev_spec_82542 _82542; 827 #endif 828 struct e1000_dev_spec_82543 _82543; 829 struct e1000_dev_spec_82571 _82571; 830 struct e1000_dev_spec_80003es2lan _80003es2lan; 831 struct e1000_dev_spec_ich8lan ich8lan; 832 } dev_spec; 833 834 u16 device_id; 835 u16 subsystem_vendor_id; 836 u16 subsystem_device_id; 837 u16 vendor_id; 838 839 u8 revision_id; 840 }; 841 842 #include "e1000_82541.h" 843 #include "e1000_82543.h" 844 #include "e1000_82571.h" 845 #include "e1000_80003es2lan.h" 846 #include "e1000_ich8lan.h" 847 848 /* These functions must be implemented by drivers */ 849 #ifndef NO_82542_SUPPORT 850 void e1000_pci_clear_mwi(struct e1000_hw *hw); 851 void e1000_pci_set_mwi(struct e1000_hw *hw); 852 #endif 853 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 854 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 855 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 856 857 #endif 858