1 /****************************************************************************** 2 3 Copyright (c) 2001-2014, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD:$*/ 34 35 #include "e1000_api.h" 36 37 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw); 38 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); 39 static void e1000_config_collision_dist_generic(struct e1000_hw *hw); 40 static int e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index); 41 42 /** 43 * e1000_init_mac_ops_generic - Initialize MAC function pointers 44 * @hw: pointer to the HW structure 45 * 46 * Setups up the function pointers to no-op functions 47 **/ 48 void e1000_init_mac_ops_generic(struct e1000_hw *hw) 49 { 50 struct e1000_mac_info *mac = &hw->mac; 51 DEBUGFUNC("e1000_init_mac_ops_generic"); 52 53 /* General Setup */ 54 mac->ops.init_params = e1000_null_ops_generic; 55 mac->ops.init_hw = e1000_null_ops_generic; 56 mac->ops.reset_hw = e1000_null_ops_generic; 57 mac->ops.setup_physical_interface = e1000_null_ops_generic; 58 mac->ops.get_bus_info = e1000_null_ops_generic; 59 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie; 60 mac->ops.read_mac_addr = e1000_read_mac_addr_generic; 61 mac->ops.config_collision_dist = e1000_config_collision_dist_generic; 62 mac->ops.clear_hw_cntrs = e1000_null_mac_generic; 63 /* LED */ 64 mac->ops.cleanup_led = e1000_null_ops_generic; 65 mac->ops.setup_led = e1000_null_ops_generic; 66 mac->ops.blink_led = e1000_null_ops_generic; 67 mac->ops.led_on = e1000_null_ops_generic; 68 mac->ops.led_off = e1000_null_ops_generic; 69 /* LINK */ 70 mac->ops.setup_link = e1000_null_ops_generic; 71 mac->ops.get_link_up_info = e1000_null_link_info; 72 mac->ops.check_for_link = e1000_null_ops_generic; 73 mac->ops.set_obff_timer = e1000_null_set_obff_timer; 74 /* Management */ 75 mac->ops.check_mng_mode = e1000_null_mng_mode; 76 /* VLAN, MC, etc. */ 77 mac->ops.update_mc_addr_list = e1000_null_update_mc; 78 mac->ops.clear_vfta = e1000_null_mac_generic; 79 mac->ops.write_vfta = e1000_null_write_vfta; 80 mac->ops.rar_set = e1000_rar_set_generic; 81 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; 82 } 83 84 /** 85 * e1000_null_ops_generic - No-op function, returns 0 86 * @hw: pointer to the HW structure 87 **/ 88 s32 e1000_null_ops_generic(struct e1000_hw E1000_UNUSEDARG *hw) 89 { 90 DEBUGFUNC("e1000_null_ops_generic"); 91 return E1000_SUCCESS; 92 } 93 94 /** 95 * e1000_null_mac_generic - No-op function, return void 96 * @hw: pointer to the HW structure 97 **/ 98 void e1000_null_mac_generic(struct e1000_hw E1000_UNUSEDARG *hw) 99 { 100 DEBUGFUNC("e1000_null_mac_generic"); 101 return; 102 } 103 104 /** 105 * e1000_null_link_info - No-op function, return 0 106 * @hw: pointer to the HW structure 107 **/ 108 s32 e1000_null_link_info(struct e1000_hw E1000_UNUSEDARG *hw, 109 u16 E1000_UNUSEDARG *s, u16 E1000_UNUSEDARG *d) 110 { 111 DEBUGFUNC("e1000_null_link_info"); 112 return E1000_SUCCESS; 113 } 114 115 /** 116 * e1000_null_mng_mode - No-op function, return FALSE 117 * @hw: pointer to the HW structure 118 **/ 119 bool e1000_null_mng_mode(struct e1000_hw E1000_UNUSEDARG *hw) 120 { 121 DEBUGFUNC("e1000_null_mng_mode"); 122 return FALSE; 123 } 124 125 /** 126 * e1000_null_update_mc - No-op function, return void 127 * @hw: pointer to the HW structure 128 **/ 129 void e1000_null_update_mc(struct e1000_hw E1000_UNUSEDARG *hw, 130 u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a) 131 { 132 DEBUGFUNC("e1000_null_update_mc"); 133 return; 134 } 135 136 /** 137 * e1000_null_write_vfta - No-op function, return void 138 * @hw: pointer to the HW structure 139 **/ 140 void e1000_null_write_vfta(struct e1000_hw E1000_UNUSEDARG *hw, 141 u32 E1000_UNUSEDARG a, u32 E1000_UNUSEDARG b) 142 { 143 DEBUGFUNC("e1000_null_write_vfta"); 144 return; 145 } 146 147 /** 148 * e1000_null_rar_set - No-op function, return 0 149 * @hw: pointer to the HW structure 150 **/ 151 int e1000_null_rar_set(struct e1000_hw E1000_UNUSEDARG *hw, 152 u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a) 153 { 154 DEBUGFUNC("e1000_null_rar_set"); 155 return E1000_SUCCESS; 156 } 157 158 /** 159 * e1000_null_set_obff_timer - No-op function, return 0 160 * @hw: pointer to the HW structure 161 **/ 162 s32 e1000_null_set_obff_timer(struct e1000_hw E1000_UNUSEDARG *hw, 163 u32 E1000_UNUSEDARG a) 164 { 165 DEBUGFUNC("e1000_null_set_obff_timer"); 166 return E1000_SUCCESS; 167 } 168 169 /** 170 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information 171 * @hw: pointer to the HW structure 172 * 173 * Determines and stores the system bus information for a particular 174 * network interface. The following bus information is determined and stored: 175 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function. 176 **/ 177 s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw) 178 { 179 struct e1000_mac_info *mac = &hw->mac; 180 struct e1000_bus_info *bus = &hw->bus; 181 u32 status = E1000_READ_REG(hw, E1000_STATUS); 182 s32 ret_val = E1000_SUCCESS; 183 184 DEBUGFUNC("e1000_get_bus_info_pci_generic"); 185 186 /* PCI or PCI-X? */ 187 bus->type = (status & E1000_STATUS_PCIX_MODE) 188 ? e1000_bus_type_pcix 189 : e1000_bus_type_pci; 190 191 /* Bus speed */ 192 if (bus->type == e1000_bus_type_pci) { 193 bus->speed = (status & E1000_STATUS_PCI66) 194 ? e1000_bus_speed_66 195 : e1000_bus_speed_33; 196 } else { 197 switch (status & E1000_STATUS_PCIX_SPEED) { 198 case E1000_STATUS_PCIX_SPEED_66: 199 bus->speed = e1000_bus_speed_66; 200 break; 201 case E1000_STATUS_PCIX_SPEED_100: 202 bus->speed = e1000_bus_speed_100; 203 break; 204 case E1000_STATUS_PCIX_SPEED_133: 205 bus->speed = e1000_bus_speed_133; 206 break; 207 default: 208 bus->speed = e1000_bus_speed_reserved; 209 break; 210 } 211 } 212 213 /* Bus width */ 214 bus->width = (status & E1000_STATUS_BUS64) 215 ? e1000_bus_width_64 216 : e1000_bus_width_32; 217 218 /* Which PCI(-X) function? */ 219 mac->ops.set_lan_id(hw); 220 221 return ret_val; 222 } 223 224 /** 225 * e1000_get_bus_info_pcie_generic - Get PCIe bus information 226 * @hw: pointer to the HW structure 227 * 228 * Determines and stores the system bus information for a particular 229 * network interface. The following bus information is determined and stored: 230 * bus speed, bus width, type (PCIe), and PCIe function. 231 **/ 232 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 233 { 234 struct e1000_mac_info *mac = &hw->mac; 235 struct e1000_bus_info *bus = &hw->bus; 236 s32 ret_val; 237 u16 pcie_link_status; 238 239 DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 240 241 bus->type = e1000_bus_type_pci_express; 242 243 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS, 244 &pcie_link_status); 245 if (ret_val) { 246 bus->width = e1000_bus_width_unknown; 247 bus->speed = e1000_bus_speed_unknown; 248 } else { 249 switch (pcie_link_status & PCIE_LINK_SPEED_MASK) { 250 case PCIE_LINK_SPEED_2500: 251 bus->speed = e1000_bus_speed_2500; 252 break; 253 case PCIE_LINK_SPEED_5000: 254 bus->speed = e1000_bus_speed_5000; 255 break; 256 default: 257 bus->speed = e1000_bus_speed_unknown; 258 break; 259 } 260 261 bus->width = (enum e1000_bus_width)((pcie_link_status & 262 PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT); 263 } 264 265 mac->ops.set_lan_id(hw); 266 267 return E1000_SUCCESS; 268 } 269 270 /** 271 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 272 * 273 * @hw: pointer to the HW structure 274 * 275 * Determines the LAN function id by reading memory-mapped registers 276 * and swaps the port value if requested. 277 **/ 278 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) 279 { 280 struct e1000_bus_info *bus = &hw->bus; 281 u32 reg; 282 283 /* The status register reports the correct function number 284 * for the device regardless of function swap state. 285 */ 286 reg = E1000_READ_REG(hw, E1000_STATUS); 287 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 288 } 289 290 /** 291 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices 292 * @hw: pointer to the HW structure 293 * 294 * Determines the LAN function id by reading PCI config space. 295 **/ 296 void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw) 297 { 298 struct e1000_bus_info *bus = &hw->bus; 299 u16 pci_header_type; 300 u32 status; 301 302 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 303 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { 304 status = E1000_READ_REG(hw, E1000_STATUS); 305 bus->func = (status & E1000_STATUS_FUNC_MASK) 306 >> E1000_STATUS_FUNC_SHIFT; 307 } else { 308 bus->func = 0; 309 } 310 } 311 312 /** 313 * e1000_set_lan_id_single_port - Set LAN id for a single port device 314 * @hw: pointer to the HW structure 315 * 316 * Sets the LAN function id to zero for a single port device. 317 **/ 318 void e1000_set_lan_id_single_port(struct e1000_hw *hw) 319 { 320 struct e1000_bus_info *bus = &hw->bus; 321 322 bus->func = 0; 323 } 324 325 /** 326 * e1000_clear_vfta_generic - Clear VLAN filter table 327 * @hw: pointer to the HW structure 328 * 329 * Clears the register array which contains the VLAN filter table by 330 * setting all the values to 0. 331 **/ 332 void e1000_clear_vfta_generic(struct e1000_hw *hw) 333 { 334 u32 offset; 335 336 DEBUGFUNC("e1000_clear_vfta_generic"); 337 338 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 339 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 340 E1000_WRITE_FLUSH(hw); 341 } 342 } 343 344 /** 345 * e1000_write_vfta_generic - Write value to VLAN filter table 346 * @hw: pointer to the HW structure 347 * @offset: register offset in VLAN filter table 348 * @value: register value written to VLAN filter table 349 * 350 * Writes value at the given offset in the register array which stores 351 * the VLAN filter table. 352 **/ 353 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 354 { 355 DEBUGFUNC("e1000_write_vfta_generic"); 356 357 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 358 E1000_WRITE_FLUSH(hw); 359 } 360 361 /** 362 * e1000_init_rx_addrs_generic - Initialize receive address's 363 * @hw: pointer to the HW structure 364 * @rar_count: receive address registers 365 * 366 * Setup the receive address registers by setting the base receive address 367 * register to the devices MAC address and clearing all the other receive 368 * address registers to 0. 369 **/ 370 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 371 { 372 u32 i; 373 u8 mac_addr[ETH_ADDR_LEN] = {0}; 374 375 DEBUGFUNC("e1000_init_rx_addrs_generic"); 376 377 /* Setup the receive address */ 378 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 379 380 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 381 382 /* Zero out the other (rar_entry_count - 1) receive addresses */ 383 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 384 for (i = 1; i < rar_count; i++) 385 hw->mac.ops.rar_set(hw, mac_addr, i); 386 } 387 388 /** 389 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 390 * @hw: pointer to the HW structure 391 * 392 * Checks the nvm for an alternate MAC address. An alternate MAC address 393 * can be setup by pre-boot software and must be treated like a permanent 394 * address and must override the actual permanent MAC address. If an 395 * alternate MAC address is found it is programmed into RAR0, replacing 396 * the permanent address that was installed into RAR0 by the Si on reset. 397 * This function will return SUCCESS unless it encounters an error while 398 * reading the EEPROM. 399 **/ 400 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 401 { 402 u32 i; 403 s32 ret_val; 404 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 405 u8 alt_mac_addr[ETH_ADDR_LEN]; 406 407 DEBUGFUNC("e1000_check_alt_mac_addr_generic"); 408 409 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data); 410 if (ret_val) 411 return ret_val; 412 413 /* not supported on older hardware or 82573 */ 414 if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573)) 415 return E1000_SUCCESS; 416 417 /* Alternate MAC address is handled by the option ROM for 82580 418 * and newer. SW support not required. 419 */ 420 if (hw->mac.type >= e1000_82580) 421 return E1000_SUCCESS; 422 423 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 424 &nvm_alt_mac_addr_offset); 425 if (ret_val) { 426 DEBUGOUT("NVM Read Error\n"); 427 return ret_val; 428 } 429 430 if ((nvm_alt_mac_addr_offset == 0xFFFF) || 431 (nvm_alt_mac_addr_offset == 0x0000)) 432 /* There is no Alternate MAC Address */ 433 return E1000_SUCCESS; 434 435 if (hw->bus.func == E1000_FUNC_1) 436 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 437 if (hw->bus.func == E1000_FUNC_2) 438 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2; 439 440 if (hw->bus.func == E1000_FUNC_3) 441 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3; 442 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 443 offset = nvm_alt_mac_addr_offset + (i >> 1); 444 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 445 if (ret_val) { 446 DEBUGOUT("NVM Read Error\n"); 447 return ret_val; 448 } 449 450 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 451 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 452 } 453 454 /* if multicast bit is set, the alternate address will not be used */ 455 if (alt_mac_addr[0] & 0x01) { 456 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); 457 return E1000_SUCCESS; 458 } 459 460 /* We have a valid alternate MAC address, and we want to treat it the 461 * same as the normal permanent MAC address stored by the HW into the 462 * RAR. Do this by mapping this address into RAR0. 463 */ 464 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 465 466 return E1000_SUCCESS; 467 } 468 469 /** 470 * e1000_rar_set_generic - Set receive address register 471 * @hw: pointer to the HW structure 472 * @addr: pointer to the receive address 473 * @index: receive address array register 474 * 475 * Sets the receive address array register at index to the address passed 476 * in by addr. 477 **/ 478 static int e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 479 { 480 u32 rar_low, rar_high; 481 482 DEBUGFUNC("e1000_rar_set_generic"); 483 484 /* HW expects these in little endian so we reverse the byte order 485 * from network order (big endian) to little endian 486 */ 487 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 488 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 489 490 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 491 492 /* If MAC address zero, no need to set the AV bit */ 493 if (rar_low || rar_high) 494 rar_high |= E1000_RAH_AV; 495 496 /* Some bridges will combine consecutive 32-bit writes into 497 * a single burst write, which will malfunction on some parts. 498 * The flushes avoid this. 499 */ 500 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 501 E1000_WRITE_FLUSH(hw); 502 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 503 E1000_WRITE_FLUSH(hw); 504 505 return E1000_SUCCESS; 506 } 507 508 /** 509 * e1000_hash_mc_addr_generic - Generate a multicast hash value 510 * @hw: pointer to the HW structure 511 * @mc_addr: pointer to a multicast address 512 * 513 * Generates a multicast address hash value which is used to determine 514 * the multicast filter table array address and new table value. 515 **/ 516 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 517 { 518 u32 hash_value, hash_mask; 519 u8 bit_shift = 0; 520 521 DEBUGFUNC("e1000_hash_mc_addr_generic"); 522 523 /* Register count multiplied by bits per register */ 524 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 525 526 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts 527 * where 0xFF would still fall within the hash mask. 528 */ 529 while (hash_mask >> bit_shift != 0xFF) 530 bit_shift++; 531 532 /* The portion of the address that is used for the hash table 533 * is determined by the mc_filter_type setting. 534 * The algorithm is such that there is a total of 8 bits of shifting. 535 * The bit_shift for a mc_filter_type of 0 represents the number of 536 * left-shifts where the MSB of mc_addr[5] would still fall within 537 * the hash_mask. Case 0 does this exactly. Since there are a total 538 * of 8 bits of shifting, then mc_addr[4] will shift right the 539 * remaining number of bits. Thus 8 - bit_shift. The rest of the 540 * cases are a variation of this algorithm...essentially raising the 541 * number of bits to shift mc_addr[5] left, while still keeping the 542 * 8-bit shifting total. 543 * 544 * For example, given the following Destination MAC Address and an 545 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 546 * we can see that the bit_shift for case 0 is 4. These are the hash 547 * values resulting from each mc_filter_type... 548 * [0] [1] [2] [3] [4] [5] 549 * 01 AA 00 12 34 56 550 * LSB MSB 551 * 552 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 553 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 554 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 555 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 556 */ 557 switch (hw->mac.mc_filter_type) { 558 default: 559 case 0: 560 break; 561 case 1: 562 bit_shift += 1; 563 break; 564 case 2: 565 bit_shift += 2; 566 break; 567 case 3: 568 bit_shift += 4; 569 break; 570 } 571 572 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 573 (((u16) mc_addr[5]) << bit_shift))); 574 575 return hash_value; 576 } 577 578 /** 579 * e1000_update_mc_addr_list_generic - Update Multicast addresses 580 * @hw: pointer to the HW structure 581 * @mc_addr_list: array of multicast addresses to program 582 * @mc_addr_count: number of multicast addresses to program 583 * 584 * Updates entire Multicast Table Array. 585 * The caller must have a packed mc_addr_list of multicast addresses. 586 **/ 587 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw, 588 u8 *mc_addr_list, u32 mc_addr_count) 589 { 590 u32 hash_value, hash_bit, hash_reg; 591 int i; 592 593 DEBUGFUNC("e1000_update_mc_addr_list_generic"); 594 595 /* clear mta_shadow */ 596 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 597 598 /* update mta_shadow from mc_addr_list */ 599 for (i = 0; (u32) i < mc_addr_count; i++) { 600 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list); 601 602 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 603 hash_bit = hash_value & 0x1F; 604 605 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 606 mc_addr_list += (ETH_ADDR_LEN); 607 } 608 609 /* replace the entire MTA table */ 610 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 611 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 612 E1000_WRITE_FLUSH(hw); 613 } 614 615 /** 616 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value 617 * @hw: pointer to the HW structure 618 * 619 * In certain situations, a system BIOS may report that the PCIx maximum 620 * memory read byte count (MMRBC) value is higher than than the actual 621 * value. We check the PCIx command register with the current PCIx status 622 * register. 623 **/ 624 void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw) 625 { 626 u16 cmd_mmrbc; 627 u16 pcix_cmd; 628 u16 pcix_stat_hi_word; 629 u16 stat_mmrbc; 630 631 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); 632 633 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ 634 if (hw->bus.type != e1000_bus_type_pcix) 635 return; 636 637 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 638 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 639 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> 640 PCIX_COMMAND_MMRBC_SHIFT; 641 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 642 PCIX_STATUS_HI_MMRBC_SHIFT; 643 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 644 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 645 if (cmd_mmrbc > stat_mmrbc) { 646 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; 647 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 648 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 649 } 650 } 651 652 /** 653 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 654 * @hw: pointer to the HW structure 655 * 656 * Clears the base hardware counters by reading the counter registers. 657 **/ 658 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 659 { 660 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 661 662 E1000_READ_REG(hw, E1000_CRCERRS); 663 E1000_READ_REG(hw, E1000_SYMERRS); 664 E1000_READ_REG(hw, E1000_MPC); 665 E1000_READ_REG(hw, E1000_SCC); 666 E1000_READ_REG(hw, E1000_ECOL); 667 E1000_READ_REG(hw, E1000_MCC); 668 E1000_READ_REG(hw, E1000_LATECOL); 669 E1000_READ_REG(hw, E1000_COLC); 670 E1000_READ_REG(hw, E1000_DC); 671 E1000_READ_REG(hw, E1000_SEC); 672 E1000_READ_REG(hw, E1000_RLEC); 673 E1000_READ_REG(hw, E1000_XONRXC); 674 E1000_READ_REG(hw, E1000_XONTXC); 675 E1000_READ_REG(hw, E1000_XOFFRXC); 676 E1000_READ_REG(hw, E1000_XOFFTXC); 677 E1000_READ_REG(hw, E1000_FCRUC); 678 E1000_READ_REG(hw, E1000_GPRC); 679 E1000_READ_REG(hw, E1000_BPRC); 680 E1000_READ_REG(hw, E1000_MPRC); 681 E1000_READ_REG(hw, E1000_GPTC); 682 E1000_READ_REG(hw, E1000_GORCL); 683 E1000_READ_REG(hw, E1000_GORCH); 684 E1000_READ_REG(hw, E1000_GOTCL); 685 E1000_READ_REG(hw, E1000_GOTCH); 686 E1000_READ_REG(hw, E1000_RNBC); 687 E1000_READ_REG(hw, E1000_RUC); 688 E1000_READ_REG(hw, E1000_RFC); 689 E1000_READ_REG(hw, E1000_ROC); 690 E1000_READ_REG(hw, E1000_RJC); 691 E1000_READ_REG(hw, E1000_TORL); 692 E1000_READ_REG(hw, E1000_TORH); 693 E1000_READ_REG(hw, E1000_TOTL); 694 E1000_READ_REG(hw, E1000_TOTH); 695 E1000_READ_REG(hw, E1000_TPR); 696 E1000_READ_REG(hw, E1000_TPT); 697 E1000_READ_REG(hw, E1000_MPTC); 698 E1000_READ_REG(hw, E1000_BPTC); 699 } 700 701 /** 702 * e1000_check_for_copper_link_generic - Check for link (Copper) 703 * @hw: pointer to the HW structure 704 * 705 * Checks to see of the link status of the hardware has changed. If a 706 * change in link status has been detected, then we read the PHY registers 707 * to get the current speed/duplex if link exists. 708 **/ 709 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) 710 { 711 struct e1000_mac_info *mac = &hw->mac; 712 s32 ret_val; 713 bool link; 714 715 DEBUGFUNC("e1000_check_for_copper_link"); 716 717 /* We only want to go out to the PHY registers to see if Auto-Neg 718 * has completed and/or if our link status has changed. The 719 * get_link_status flag is set upon receiving a Link Status 720 * Change or Rx Sequence Error interrupt. 721 */ 722 if (!mac->get_link_status) 723 return E1000_SUCCESS; 724 725 /* First we want to see if the MII Status Register reports 726 * link. If so, then we want to get the current speed/duplex 727 * of the PHY. 728 */ 729 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 730 if (ret_val) 731 return ret_val; 732 733 if (!link) 734 return E1000_SUCCESS; /* No link detected */ 735 736 mac->get_link_status = FALSE; 737 738 /* Check if there was DownShift, must be checked 739 * immediately after link-up 740 */ 741 e1000_check_downshift_generic(hw); 742 743 /* If we are forcing speed/duplex, then we simply return since 744 * we have already determined whether we have link or not. 745 */ 746 if (!mac->autoneg) 747 return -E1000_ERR_CONFIG; 748 749 /* Auto-Neg is enabled. Auto Speed Detection takes care 750 * of MAC speed/duplex configuration. So we only need to 751 * configure Collision Distance in the MAC. 752 */ 753 mac->ops.config_collision_dist(hw); 754 755 /* Configure Flow Control now that Auto-Neg has completed. 756 * First, we need to restore the desired flow control 757 * settings because we may have had to re-autoneg with a 758 * different link partner. 759 */ 760 ret_val = e1000_config_fc_after_link_up_generic(hw); 761 if (ret_val) 762 DEBUGOUT("Error configuring flow control\n"); 763 764 return ret_val; 765 } 766 767 /** 768 * e1000_check_for_fiber_link_generic - Check for link (Fiber) 769 * @hw: pointer to the HW structure 770 * 771 * Checks for link up on the hardware. If link is not up and we have 772 * a signal, then we need to force link up. 773 **/ 774 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 775 { 776 struct e1000_mac_info *mac = &hw->mac; 777 u32 rxcw; 778 u32 ctrl; 779 u32 status; 780 s32 ret_val; 781 782 DEBUGFUNC("e1000_check_for_fiber_link_generic"); 783 784 ctrl = E1000_READ_REG(hw, E1000_CTRL); 785 status = E1000_READ_REG(hw, E1000_STATUS); 786 rxcw = E1000_READ_REG(hw, E1000_RXCW); 787 788 /* If we don't have link (auto-negotiation failed or link partner 789 * cannot auto-negotiate), the cable is plugged in (we have signal), 790 * and our link partner is not trying to auto-negotiate with us (we 791 * are receiving idles or data), we need to force link up. We also 792 * need to give auto-negotiation time to complete, in case the cable 793 * was just plugged in. The autoneg_failed flag does this. 794 */ 795 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 796 if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) && 797 !(rxcw & E1000_RXCW_C)) { 798 if (!mac->autoneg_failed) { 799 mac->autoneg_failed = TRUE; 800 return E1000_SUCCESS; 801 } 802 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 803 804 /* Disable auto-negotiation in the TXCW register */ 805 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 806 807 /* Force link-up and also force full-duplex. */ 808 ctrl = E1000_READ_REG(hw, E1000_CTRL); 809 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 810 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 811 812 /* Configure Flow Control after forcing link up. */ 813 ret_val = e1000_config_fc_after_link_up_generic(hw); 814 if (ret_val) { 815 DEBUGOUT("Error configuring flow control\n"); 816 return ret_val; 817 } 818 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 819 /* If we are forcing link and we are receiving /C/ ordered 820 * sets, re-enable auto-negotiation in the TXCW register 821 * and disable forced link in the Device Control register 822 * in an attempt to auto-negotiate with our link partner. 823 */ 824 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 825 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 826 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 827 828 mac->serdes_has_link = TRUE; 829 } 830 831 return E1000_SUCCESS; 832 } 833 834 /** 835 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 836 * @hw: pointer to the HW structure 837 * 838 * Checks for link up on the hardware. If link is not up and we have 839 * a signal, then we need to force link up. 840 **/ 841 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 842 { 843 struct e1000_mac_info *mac = &hw->mac; 844 u32 rxcw; 845 u32 ctrl; 846 u32 status; 847 s32 ret_val; 848 849 DEBUGFUNC("e1000_check_for_serdes_link_generic"); 850 851 ctrl = E1000_READ_REG(hw, E1000_CTRL); 852 status = E1000_READ_REG(hw, E1000_STATUS); 853 rxcw = E1000_READ_REG(hw, E1000_RXCW); 854 855 /* If we don't have link (auto-negotiation failed or link partner 856 * cannot auto-negotiate), and our link partner is not trying to 857 * auto-negotiate with us (we are receiving idles or data), 858 * we need to force link up. We also need to give auto-negotiation 859 * time to complete. 860 */ 861 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 862 if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) { 863 if (!mac->autoneg_failed) { 864 mac->autoneg_failed = TRUE; 865 return E1000_SUCCESS; 866 } 867 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 868 869 /* Disable auto-negotiation in the TXCW register */ 870 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 871 872 /* Force link-up and also force full-duplex. */ 873 ctrl = E1000_READ_REG(hw, E1000_CTRL); 874 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 875 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 876 877 /* Configure Flow Control after forcing link up. */ 878 ret_val = e1000_config_fc_after_link_up_generic(hw); 879 if (ret_val) { 880 DEBUGOUT("Error configuring flow control\n"); 881 return ret_val; 882 } 883 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 884 /* If we are forcing link and we are receiving /C/ ordered 885 * sets, re-enable auto-negotiation in the TXCW register 886 * and disable forced link in the Device Control register 887 * in an attempt to auto-negotiate with our link partner. 888 */ 889 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 890 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 891 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 892 893 mac->serdes_has_link = TRUE; 894 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 895 /* If we force link for non-auto-negotiation switch, check 896 * link status based on MAC synchronization for internal 897 * serdes media type. 898 */ 899 /* SYNCH bit and IV bit are sticky. */ 900 usec_delay(10); 901 rxcw = E1000_READ_REG(hw, E1000_RXCW); 902 if (rxcw & E1000_RXCW_SYNCH) { 903 if (!(rxcw & E1000_RXCW_IV)) { 904 mac->serdes_has_link = TRUE; 905 DEBUGOUT("SERDES: Link up - forced.\n"); 906 } 907 } else { 908 mac->serdes_has_link = FALSE; 909 DEBUGOUT("SERDES: Link down - force failed.\n"); 910 } 911 } 912 913 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 914 status = E1000_READ_REG(hw, E1000_STATUS); 915 if (status & E1000_STATUS_LU) { 916 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 917 usec_delay(10); 918 rxcw = E1000_READ_REG(hw, E1000_RXCW); 919 if (rxcw & E1000_RXCW_SYNCH) { 920 if (!(rxcw & E1000_RXCW_IV)) { 921 mac->serdes_has_link = TRUE; 922 DEBUGOUT("SERDES: Link up - autoneg completed successfully.\n"); 923 } else { 924 mac->serdes_has_link = FALSE; 925 DEBUGOUT("SERDES: Link down - invalid codewords detected in autoneg.\n"); 926 } 927 } else { 928 mac->serdes_has_link = FALSE; 929 DEBUGOUT("SERDES: Link down - no sync.\n"); 930 } 931 } else { 932 mac->serdes_has_link = FALSE; 933 DEBUGOUT("SERDES: Link down - autoneg failed\n"); 934 } 935 } 936 937 return E1000_SUCCESS; 938 } 939 940 /** 941 * e1000_set_default_fc_generic - Set flow control default values 942 * @hw: pointer to the HW structure 943 * 944 * Read the EEPROM for the default values for flow control and store the 945 * values. 946 **/ 947 #ifdef NO_82542_SUPPORT 948 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw) 949 #else 950 s32 e1000_set_default_fc_generic(struct e1000_hw *hw) 951 #endif 952 { 953 s32 ret_val; 954 u16 nvm_data; 955 956 DEBUGFUNC("e1000_set_default_fc_generic"); 957 958 /* Read and store word 0x0F of the EEPROM. This word contains bits 959 * that determine the hardware's default PAUSE (flow control) mode, 960 * a bit that determines whether the HW defaults to enabling or 961 * disabling auto-negotiation, and the direction of the 962 * SW defined pins. If there is no SW over-ride of the flow 963 * control setting, then the variable hw->fc will 964 * be initialized based on a value in the EEPROM. 965 */ 966 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); 967 968 if (ret_val) { 969 DEBUGOUT("NVM Read Error\n"); 970 return ret_val; 971 } 972 973 if (!(nvm_data & NVM_WORD0F_PAUSE_MASK)) 974 hw->fc.requested_mode = e1000_fc_none; 975 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 976 NVM_WORD0F_ASM_DIR) 977 hw->fc.requested_mode = e1000_fc_tx_pause; 978 else 979 hw->fc.requested_mode = e1000_fc_full; 980 981 return E1000_SUCCESS; 982 } 983 984 /** 985 * e1000_setup_link_generic - Setup flow control and link settings 986 * @hw: pointer to the HW structure 987 * 988 * Determines which flow control settings to use, then configures flow 989 * control. Calls the appropriate media-specific link configuration 990 * function. Assuming the adapter has a valid link partner, a valid link 991 * should be established. Assumes the hardware has previously been reset 992 * and the transmitter and receiver are not enabled. 993 **/ 994 s32 e1000_setup_link_generic(struct e1000_hw *hw) 995 { 996 s32 ret_val; 997 998 DEBUGFUNC("e1000_setup_link_generic"); 999 1000 /* In the case of the phy reset being blocked, we already have a link. 1001 * We do not need to set it up again. 1002 */ 1003 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 1004 return E1000_SUCCESS; 1005 1006 /* If requested flow control is set to default, set flow control 1007 * based on the EEPROM flow control settings. 1008 */ 1009 if (hw->fc.requested_mode == e1000_fc_default) { 1010 ret_val = e1000_set_default_fc_generic(hw); 1011 if (ret_val) 1012 return ret_val; 1013 } 1014 1015 /* Save off the requested flow control mode for use later. Depending 1016 * on the link partner's capabilities, we may or may not use this mode. 1017 */ 1018 hw->fc.current_mode = hw->fc.requested_mode; 1019 1020 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 1021 hw->fc.current_mode); 1022 1023 /* Call the necessary media_type subroutine to configure the link. */ 1024 ret_val = hw->mac.ops.setup_physical_interface(hw); 1025 if (ret_val) 1026 return ret_val; 1027 1028 /* Initialize the flow control address, type, and PAUSE timer 1029 * registers to their default values. This is done even if flow 1030 * control is disabled, because it does not hurt anything to 1031 * initialize these registers. 1032 */ 1033 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 1034 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 1035 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1036 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 1037 1038 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 1039 1040 return e1000_set_fc_watermarks_generic(hw); 1041 } 1042 1043 /** 1044 * e1000_commit_fc_settings_generic - Configure flow control 1045 * @hw: pointer to the HW structure 1046 * 1047 * Write the flow control settings to the Transmit Config Word Register (TXCW) 1048 * base on the flow control settings in e1000_mac_info. 1049 **/ 1050 s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 1051 { 1052 struct e1000_mac_info *mac = &hw->mac; 1053 u32 txcw; 1054 1055 DEBUGFUNC("e1000_commit_fc_settings_generic"); 1056 1057 /* Check for a software override of the flow control settings, and 1058 * setup the device accordingly. If auto-negotiation is enabled, then 1059 * software will have to set the "PAUSE" bits to the correct value in 1060 * the Transmit Config Word Register (TXCW) and re-start auto- 1061 * negotiation. However, if auto-negotiation is disabled, then 1062 * software will have to manually configure the two flow control enable 1063 * bits in the CTRL register. 1064 * 1065 * The possible values of the "fc" parameter are: 1066 * 0: Flow control is completely disabled 1067 * 1: Rx flow control is enabled (we can receive pause frames, 1068 * but not send pause frames). 1069 * 2: Tx flow control is enabled (we can send pause frames but we 1070 * do not support receiving pause frames). 1071 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1072 */ 1073 switch (hw->fc.current_mode) { 1074 case e1000_fc_none: 1075 /* Flow control completely disabled by a software over-ride. */ 1076 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1077 break; 1078 case e1000_fc_rx_pause: 1079 /* Rx Flow control is enabled and Tx Flow control is disabled 1080 * by a software over-ride. Since there really isn't a way to 1081 * advertise that we are capable of Rx Pause ONLY, we will 1082 * advertise that we support both symmetric and asymmetric Rx 1083 * PAUSE. Later, we will disable the adapter's ability to send 1084 * PAUSE frames. 1085 */ 1086 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1087 break; 1088 case e1000_fc_tx_pause: 1089 /* Tx Flow control is enabled, and Rx Flow control is disabled, 1090 * by a software over-ride. 1091 */ 1092 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1093 break; 1094 case e1000_fc_full: 1095 /* Flow control (both Rx and Tx) is enabled by a software 1096 * over-ride. 1097 */ 1098 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1099 break; 1100 default: 1101 DEBUGOUT("Flow control param set incorrectly\n"); 1102 return -E1000_ERR_CONFIG; 1103 break; 1104 } 1105 1106 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1107 mac->txcw = txcw; 1108 1109 return E1000_SUCCESS; 1110 } 1111 1112 /** 1113 * e1000_poll_fiber_serdes_link_generic - Poll for link up 1114 * @hw: pointer to the HW structure 1115 * 1116 * Polls for link up by reading the status register, if link fails to come 1117 * up with auto-negotiation, then the link is forced if a signal is detected. 1118 **/ 1119 s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 1120 { 1121 struct e1000_mac_info *mac = &hw->mac; 1122 u32 i, status; 1123 s32 ret_val; 1124 1125 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 1126 1127 /* If we have a signal (the cable is plugged in, or assumed TRUE for 1128 * serdes media) then poll for a "Link-Up" indication in the Device 1129 * Status Register. Time-out if a link isn't seen in 500 milliseconds 1130 * seconds (Auto-negotiation should complete in less than 500 1131 * milliseconds even if the other end is doing it in SW). 1132 */ 1133 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 1134 msec_delay(10); 1135 status = E1000_READ_REG(hw, E1000_STATUS); 1136 if (status & E1000_STATUS_LU) 1137 break; 1138 } 1139 if (i == FIBER_LINK_UP_LIMIT) { 1140 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1141 mac->autoneg_failed = TRUE; 1142 /* AutoNeg failed to achieve a link, so we'll call 1143 * mac->check_for_link. This routine will force the 1144 * link up if we detect a signal. This will allow us to 1145 * communicate with non-autonegotiating link partners. 1146 */ 1147 ret_val = mac->ops.check_for_link(hw); 1148 if (ret_val) { 1149 DEBUGOUT("Error while checking for link\n"); 1150 return ret_val; 1151 } 1152 mac->autoneg_failed = FALSE; 1153 } else { 1154 mac->autoneg_failed = FALSE; 1155 DEBUGOUT("Valid Link Found\n"); 1156 } 1157 1158 return E1000_SUCCESS; 1159 } 1160 1161 /** 1162 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 1163 * @hw: pointer to the HW structure 1164 * 1165 * Configures collision distance and flow control for fiber and serdes 1166 * links. Upon successful setup, poll for link. 1167 **/ 1168 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 1169 { 1170 u32 ctrl; 1171 s32 ret_val; 1172 1173 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 1174 1175 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1176 1177 /* Take the link out of reset */ 1178 ctrl &= ~E1000_CTRL_LRST; 1179 1180 hw->mac.ops.config_collision_dist(hw); 1181 1182 ret_val = e1000_commit_fc_settings_generic(hw); 1183 if (ret_val) 1184 return ret_val; 1185 1186 /* Since auto-negotiation is enabled, take the link out of reset (the 1187 * link will be in reset, because we previously reset the chip). This 1188 * will restart auto-negotiation. If auto-negotiation is successful 1189 * then the link-up status bit will be set and the flow control enable 1190 * bits (RFCE and TFCE) will be set according to their negotiated value. 1191 */ 1192 DEBUGOUT("Auto-negotiation enabled\n"); 1193 1194 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1195 E1000_WRITE_FLUSH(hw); 1196 msec_delay(1); 1197 1198 /* For these adapters, the SW definable pin 1 is set when the optics 1199 * detect a signal. If we have a signal, then poll for a "Link-Up" 1200 * indication. 1201 */ 1202 if (hw->phy.media_type == e1000_media_type_internal_serdes || 1203 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1204 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1205 } else { 1206 DEBUGOUT("No signal detected\n"); 1207 } 1208 1209 return ret_val; 1210 } 1211 1212 /** 1213 * e1000_config_collision_dist_generic - Configure collision distance 1214 * @hw: pointer to the HW structure 1215 * 1216 * Configures the collision distance to the default value and is used 1217 * during link setup. 1218 **/ 1219 static void e1000_config_collision_dist_generic(struct e1000_hw *hw) 1220 { 1221 u32 tctl; 1222 1223 DEBUGFUNC("e1000_config_collision_dist_generic"); 1224 1225 tctl = E1000_READ_REG(hw, E1000_TCTL); 1226 1227 tctl &= ~E1000_TCTL_COLD; 1228 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1229 1230 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 1231 E1000_WRITE_FLUSH(hw); 1232 } 1233 1234 /** 1235 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 1236 * @hw: pointer to the HW structure 1237 * 1238 * Sets the flow control high/low threshold (watermark) registers. If 1239 * flow control XON frame transmission is enabled, then set XON frame 1240 * transmission as well. 1241 **/ 1242 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 1243 { 1244 u32 fcrtl = 0, fcrth = 0; 1245 1246 DEBUGFUNC("e1000_set_fc_watermarks_generic"); 1247 1248 /* Set the flow control receive threshold registers. Normally, 1249 * these registers will be set to a default threshold that may be 1250 * adjusted later by the driver's runtime code. However, if the 1251 * ability to transmit pause frames is not enabled, then these 1252 * registers will be set to 0. 1253 */ 1254 if (hw->fc.current_mode & e1000_fc_tx_pause) { 1255 /* We need to set up the Receive Threshold high and low water 1256 * marks as well as (optionally) enabling the transmission of 1257 * XON frames. 1258 */ 1259 fcrtl = hw->fc.low_water; 1260 if (hw->fc.send_xon) 1261 fcrtl |= E1000_FCRTL_XONE; 1262 1263 fcrth = hw->fc.high_water; 1264 } 1265 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 1266 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 1267 1268 return E1000_SUCCESS; 1269 } 1270 1271 /** 1272 * e1000_force_mac_fc_generic - Force the MAC's flow control settings 1273 * @hw: pointer to the HW structure 1274 * 1275 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 1276 * device control register to reflect the adapter settings. TFCE and RFCE 1277 * need to be explicitly set by software when a copper PHY is used because 1278 * autonegotiation is managed by the PHY rather than the MAC. Software must 1279 * also configure these bits when link is forced on a fiber connection. 1280 **/ 1281 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw) 1282 { 1283 u32 ctrl; 1284 1285 DEBUGFUNC("e1000_force_mac_fc_generic"); 1286 1287 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1288 1289 /* Because we didn't get link via the internal auto-negotiation 1290 * mechanism (we either forced link or we got link via PHY 1291 * auto-neg), we have to manually enable/disable transmit an 1292 * receive flow control. 1293 * 1294 * The "Case" statement below enables/disable flow control 1295 * according to the "hw->fc.current_mode" parameter. 1296 * 1297 * The possible values of the "fc" parameter are: 1298 * 0: Flow control is completely disabled 1299 * 1: Rx flow control is enabled (we can receive pause 1300 * frames but not send pause frames). 1301 * 2: Tx flow control is enabled (we can send pause frames 1302 * frames but we do not receive pause frames). 1303 * 3: Both Rx and Tx flow control (symmetric) is enabled. 1304 * other: No other values should be possible at this point. 1305 */ 1306 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); 1307 1308 switch (hw->fc.current_mode) { 1309 case e1000_fc_none: 1310 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1311 break; 1312 case e1000_fc_rx_pause: 1313 ctrl &= (~E1000_CTRL_TFCE); 1314 ctrl |= E1000_CTRL_RFCE; 1315 break; 1316 case e1000_fc_tx_pause: 1317 ctrl &= (~E1000_CTRL_RFCE); 1318 ctrl |= E1000_CTRL_TFCE; 1319 break; 1320 case e1000_fc_full: 1321 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1322 break; 1323 default: 1324 DEBUGOUT("Flow control param set incorrectly\n"); 1325 return -E1000_ERR_CONFIG; 1326 } 1327 1328 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1329 1330 return E1000_SUCCESS; 1331 } 1332 1333 /** 1334 * e1000_config_fc_after_link_up_generic - Configures flow control after link 1335 * @hw: pointer to the HW structure 1336 * 1337 * Checks the status of auto-negotiation after link up to ensure that the 1338 * speed and duplex were not forced. If the link needed to be forced, then 1339 * flow control needs to be forced also. If auto-negotiation is enabled 1340 * and did not fail, then we configure flow control based on our link 1341 * partner. 1342 **/ 1343 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 1344 { 1345 struct e1000_mac_info *mac = &hw->mac; 1346 s32 ret_val = E1000_SUCCESS; 1347 u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg; 1348 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1349 u16 speed, duplex; 1350 1351 DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 1352 1353 /* Check for the case where we have fiber media and auto-neg failed 1354 * so we had to force link. In this case, we need to force the 1355 * configuration of the MAC to match the "fc" parameter. 1356 */ 1357 if (mac->autoneg_failed) { 1358 if (hw->phy.media_type == e1000_media_type_fiber || 1359 hw->phy.media_type == e1000_media_type_internal_serdes) 1360 ret_val = e1000_force_mac_fc_generic(hw); 1361 } else { 1362 if (hw->phy.media_type == e1000_media_type_copper) 1363 ret_val = e1000_force_mac_fc_generic(hw); 1364 } 1365 1366 if (ret_val) { 1367 DEBUGOUT("Error forcing flow control settings\n"); 1368 return ret_val; 1369 } 1370 1371 /* Check for the case where we have copper media and auto-neg is 1372 * enabled. In this case, we need to check and see if Auto-Neg 1373 * has completed, and if so, how the PHY and link partner has 1374 * flow control configured. 1375 */ 1376 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1377 /* Read the MII Status Register and check to see if AutoNeg 1378 * has completed. We read this twice because this reg has 1379 * some "sticky" (latched) bits. 1380 */ 1381 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1382 if (ret_val) 1383 return ret_val; 1384 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1385 if (ret_val) 1386 return ret_val; 1387 1388 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1389 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n"); 1390 return ret_val; 1391 } 1392 1393 /* The AutoNeg process has completed, so we now need to 1394 * read both the Auto Negotiation Advertisement 1395 * Register (Address 4) and the Auto_Negotiation Base 1396 * Page Ability Register (Address 5) to determine how 1397 * flow control was negotiated. 1398 */ 1399 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 1400 &mii_nway_adv_reg); 1401 if (ret_val) 1402 return ret_val; 1403 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 1404 &mii_nway_lp_ability_reg); 1405 if (ret_val) 1406 return ret_val; 1407 1408 /* Two bits in the Auto Negotiation Advertisement Register 1409 * (Address 4) and two bits in the Auto Negotiation Base 1410 * Page Ability Register (Address 5) determine flow control 1411 * for both the PHY and the link partner. The following 1412 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1413 * 1999, describes these PAUSE resolution bits and how flow 1414 * control is determined based upon these settings. 1415 * NOTE: DC = Don't Care 1416 * 1417 * LOCAL DEVICE | LINK PARTNER 1418 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1419 *-------|---------|-------|---------|-------------------- 1420 * 0 | 0 | DC | DC | e1000_fc_none 1421 * 0 | 1 | 0 | DC | e1000_fc_none 1422 * 0 | 1 | 1 | 0 | e1000_fc_none 1423 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1424 * 1 | 0 | 0 | DC | e1000_fc_none 1425 * 1 | DC | 1 | DC | e1000_fc_full 1426 * 1 | 1 | 0 | 0 | e1000_fc_none 1427 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1428 * 1429 * Are both PAUSE bits set to 1? If so, this implies 1430 * Symmetric Flow Control is enabled at both ends. The 1431 * ASM_DIR bits are irrelevant per the spec. 1432 * 1433 * For Symmetric Flow Control: 1434 * 1435 * LOCAL DEVICE | LINK PARTNER 1436 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1437 *-------|---------|-------|---------|-------------------- 1438 * 1 | DC | 1 | DC | E1000_fc_full 1439 * 1440 */ 1441 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1442 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1443 /* Now we need to check if the user selected Rx ONLY 1444 * of pause frames. In this case, we had to advertise 1445 * FULL flow control because we could not advertise Rx 1446 * ONLY. Hence, we must now check to see if we need to 1447 * turn OFF the TRANSMISSION of PAUSE frames. 1448 */ 1449 if (hw->fc.requested_mode == e1000_fc_full) { 1450 hw->fc.current_mode = e1000_fc_full; 1451 DEBUGOUT("Flow Control = FULL.\n"); 1452 } else { 1453 hw->fc.current_mode = e1000_fc_rx_pause; 1454 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1455 } 1456 } 1457 /* For receiving PAUSE frames ONLY. 1458 * 1459 * LOCAL DEVICE | LINK PARTNER 1460 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1461 *-------|---------|-------|---------|-------------------- 1462 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1463 */ 1464 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1465 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1466 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1467 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1468 hw->fc.current_mode = e1000_fc_tx_pause; 1469 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); 1470 } 1471 /* For transmitting PAUSE frames ONLY. 1472 * 1473 * LOCAL DEVICE | LINK PARTNER 1474 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1475 *-------|---------|-------|---------|-------------------- 1476 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1477 */ 1478 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1479 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1480 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1481 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1482 hw->fc.current_mode = e1000_fc_rx_pause; 1483 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1484 } else { 1485 /* Per the IEEE spec, at this point flow control 1486 * should be disabled. 1487 */ 1488 hw->fc.current_mode = e1000_fc_none; 1489 DEBUGOUT("Flow Control = NONE.\n"); 1490 } 1491 1492 /* Now we need to do one last check... If we auto- 1493 * negotiated to HALF DUPLEX, flow control should not be 1494 * enabled per IEEE 802.3 spec. 1495 */ 1496 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1497 if (ret_val) { 1498 DEBUGOUT("Error getting link speed and duplex\n"); 1499 return ret_val; 1500 } 1501 1502 if (duplex == HALF_DUPLEX) 1503 hw->fc.current_mode = e1000_fc_none; 1504 1505 /* Now we call a subroutine to actually force the MAC 1506 * controller to use the correct flow control settings. 1507 */ 1508 ret_val = e1000_force_mac_fc_generic(hw); 1509 if (ret_val) { 1510 DEBUGOUT("Error forcing flow control settings\n"); 1511 return ret_val; 1512 } 1513 } 1514 1515 /* Check for the case where we have SerDes media and auto-neg is 1516 * enabled. In this case, we need to check and see if Auto-Neg 1517 * has completed, and if so, how the PHY and link partner has 1518 * flow control configured. 1519 */ 1520 if ((hw->phy.media_type == e1000_media_type_internal_serdes) && 1521 mac->autoneg) { 1522 /* Read the PCS_LSTS and check to see if AutoNeg 1523 * has completed. 1524 */ 1525 pcs_status_reg = E1000_READ_REG(hw, E1000_PCS_LSTAT); 1526 1527 if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) { 1528 DEBUGOUT("PCS Auto Neg has not completed.\n"); 1529 return ret_val; 1530 } 1531 1532 /* The AutoNeg process has completed, so we now need to 1533 * read both the Auto Negotiation Advertisement 1534 * Register (PCS_ANADV) and the Auto_Negotiation Base 1535 * Page Ability Register (PCS_LPAB) to determine how 1536 * flow control was negotiated. 1537 */ 1538 pcs_adv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV); 1539 pcs_lp_ability_reg = E1000_READ_REG(hw, E1000_PCS_LPAB); 1540 1541 /* Two bits in the Auto Negotiation Advertisement Register 1542 * (PCS_ANADV) and two bits in the Auto Negotiation Base 1543 * Page Ability Register (PCS_LPAB) determine flow control 1544 * for both the PHY and the link partner. The following 1545 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1546 * 1999, describes these PAUSE resolution bits and how flow 1547 * control is determined based upon these settings. 1548 * NOTE: DC = Don't Care 1549 * 1550 * LOCAL DEVICE | LINK PARTNER 1551 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1552 *-------|---------|-------|---------|-------------------- 1553 * 0 | 0 | DC | DC | e1000_fc_none 1554 * 0 | 1 | 0 | DC | e1000_fc_none 1555 * 0 | 1 | 1 | 0 | e1000_fc_none 1556 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1557 * 1 | 0 | 0 | DC | e1000_fc_none 1558 * 1 | DC | 1 | DC | e1000_fc_full 1559 * 1 | 1 | 0 | 0 | e1000_fc_none 1560 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1561 * 1562 * Are both PAUSE bits set to 1? If so, this implies 1563 * Symmetric Flow Control is enabled at both ends. The 1564 * ASM_DIR bits are irrelevant per the spec. 1565 * 1566 * For Symmetric Flow Control: 1567 * 1568 * LOCAL DEVICE | LINK PARTNER 1569 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1570 *-------|---------|-------|---------|-------------------- 1571 * 1 | DC | 1 | DC | e1000_fc_full 1572 * 1573 */ 1574 if ((pcs_adv_reg & E1000_TXCW_PAUSE) && 1575 (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) { 1576 /* Now we need to check if the user selected Rx ONLY 1577 * of pause frames. In this case, we had to advertise 1578 * FULL flow control because we could not advertise Rx 1579 * ONLY. Hence, we must now check to see if we need to 1580 * turn OFF the TRANSMISSION of PAUSE frames. 1581 */ 1582 if (hw->fc.requested_mode == e1000_fc_full) { 1583 hw->fc.current_mode = e1000_fc_full; 1584 DEBUGOUT("Flow Control = FULL.\n"); 1585 } else { 1586 hw->fc.current_mode = e1000_fc_rx_pause; 1587 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1588 } 1589 } 1590 /* For receiving PAUSE frames ONLY. 1591 * 1592 * LOCAL DEVICE | LINK PARTNER 1593 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1594 *-------|---------|-------|---------|-------------------- 1595 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1596 */ 1597 else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) && 1598 (pcs_adv_reg & E1000_TXCW_ASM_DIR) && 1599 (pcs_lp_ability_reg & E1000_TXCW_PAUSE) && 1600 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { 1601 hw->fc.current_mode = e1000_fc_tx_pause; 1602 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); 1603 } 1604 /* For transmitting PAUSE frames ONLY. 1605 * 1606 * LOCAL DEVICE | LINK PARTNER 1607 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1608 *-------|---------|-------|---------|-------------------- 1609 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1610 */ 1611 else if ((pcs_adv_reg & E1000_TXCW_PAUSE) && 1612 (pcs_adv_reg & E1000_TXCW_ASM_DIR) && 1613 !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) && 1614 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { 1615 hw->fc.current_mode = e1000_fc_rx_pause; 1616 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1617 } else { 1618 /* Per the IEEE spec, at this point flow control 1619 * should be disabled. 1620 */ 1621 hw->fc.current_mode = e1000_fc_none; 1622 DEBUGOUT("Flow Control = NONE.\n"); 1623 } 1624 1625 /* Now we call a subroutine to actually force the MAC 1626 * controller to use the correct flow control settings. 1627 */ 1628 pcs_ctrl_reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 1629 pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1630 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_ctrl_reg); 1631 1632 ret_val = e1000_force_mac_fc_generic(hw); 1633 if (ret_val) { 1634 DEBUGOUT("Error forcing flow control settings\n"); 1635 return ret_val; 1636 } 1637 } 1638 1639 return E1000_SUCCESS; 1640 } 1641 1642 /** 1643 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 1644 * @hw: pointer to the HW structure 1645 * @speed: stores the current speed 1646 * @duplex: stores the current duplex 1647 * 1648 * Read the status register for the current speed/duplex and store the current 1649 * speed and duplex for copper connections. 1650 **/ 1651 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 1652 u16 *duplex) 1653 { 1654 u32 status; 1655 1656 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 1657 1658 status = E1000_READ_REG(hw, E1000_STATUS); 1659 if (status & E1000_STATUS_SPEED_1000) { 1660 *speed = SPEED_1000; 1661 DEBUGOUT("1000 Mbs, "); 1662 } else if (status & E1000_STATUS_SPEED_100) { 1663 *speed = SPEED_100; 1664 DEBUGOUT("100 Mbs, "); 1665 } else { 1666 *speed = SPEED_10; 1667 DEBUGOUT("10 Mbs, "); 1668 } 1669 1670 if (status & E1000_STATUS_FD) { 1671 *duplex = FULL_DUPLEX; 1672 DEBUGOUT("Full Duplex\n"); 1673 } else { 1674 *duplex = HALF_DUPLEX; 1675 DEBUGOUT("Half Duplex\n"); 1676 } 1677 1678 return E1000_SUCCESS; 1679 } 1680 1681 /** 1682 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex 1683 * @hw: pointer to the HW structure 1684 * @speed: stores the current speed 1685 * @duplex: stores the current duplex 1686 * 1687 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1688 * for fiber/serdes links. 1689 **/ 1690 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw E1000_UNUSEDARG *hw, 1691 u16 *speed, u16 *duplex) 1692 { 1693 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 1694 1695 *speed = SPEED_1000; 1696 *duplex = FULL_DUPLEX; 1697 1698 return E1000_SUCCESS; 1699 } 1700 1701 /** 1702 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 1703 * @hw: pointer to the HW structure 1704 * 1705 * Acquire the HW semaphore to access the PHY or NVM 1706 **/ 1707 s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 1708 { 1709 u32 swsm; 1710 s32 timeout = hw->nvm.word_size + 1; 1711 s32 i = 0; 1712 1713 DEBUGFUNC("e1000_get_hw_semaphore_generic"); 1714 1715 /* Get the SW semaphore */ 1716 while (i < timeout) { 1717 swsm = E1000_READ_REG(hw, E1000_SWSM); 1718 if (!(swsm & E1000_SWSM_SMBI)) 1719 break; 1720 1721 usec_delay(50); 1722 i++; 1723 } 1724 1725 if (i == timeout) { 1726 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1727 return -E1000_ERR_NVM; 1728 } 1729 1730 /* Get the FW semaphore. */ 1731 for (i = 0; i < timeout; i++) { 1732 swsm = E1000_READ_REG(hw, E1000_SWSM); 1733 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 1734 1735 /* Semaphore acquired if bit latched */ 1736 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 1737 break; 1738 1739 usec_delay(50); 1740 } 1741 1742 if (i == timeout) { 1743 /* Release semaphores */ 1744 e1000_put_hw_semaphore_generic(hw); 1745 DEBUGOUT("Driver can't access the NVM\n"); 1746 return -E1000_ERR_NVM; 1747 } 1748 1749 return E1000_SUCCESS; 1750 } 1751 1752 /** 1753 * e1000_put_hw_semaphore_generic - Release hardware semaphore 1754 * @hw: pointer to the HW structure 1755 * 1756 * Release hardware semaphore used to access the PHY or NVM 1757 **/ 1758 void e1000_put_hw_semaphore_generic(struct e1000_hw *hw) 1759 { 1760 u32 swsm; 1761 1762 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 1763 1764 swsm = E1000_READ_REG(hw, E1000_SWSM); 1765 1766 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1767 1768 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 1769 } 1770 1771 /** 1772 * e1000_get_auto_rd_done_generic - Check for auto read completion 1773 * @hw: pointer to the HW structure 1774 * 1775 * Check EEPROM for Auto Read done bit. 1776 **/ 1777 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 1778 { 1779 s32 i = 0; 1780 1781 DEBUGFUNC("e1000_get_auto_rd_done_generic"); 1782 1783 while (i < AUTO_READ_DONE_TIMEOUT) { 1784 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 1785 break; 1786 msec_delay(1); 1787 i++; 1788 } 1789 1790 if (i == AUTO_READ_DONE_TIMEOUT) { 1791 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1792 return -E1000_ERR_RESET; 1793 } 1794 1795 return E1000_SUCCESS; 1796 } 1797 1798 /** 1799 * e1000_valid_led_default_generic - Verify a valid default LED config 1800 * @hw: pointer to the HW structure 1801 * @data: pointer to the NVM (EEPROM) 1802 * 1803 * Read the EEPROM for the current default LED configuration. If the 1804 * LED configuration is not valid, set to a valid LED configuration. 1805 **/ 1806 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 1807 { 1808 s32 ret_val; 1809 1810 DEBUGFUNC("e1000_valid_led_default_generic"); 1811 1812 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1813 if (ret_val) { 1814 DEBUGOUT("NVM Read Error\n"); 1815 return ret_val; 1816 } 1817 1818 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1819 *data = ID_LED_DEFAULT; 1820 1821 return E1000_SUCCESS; 1822 } 1823 1824 /** 1825 * e1000_id_led_init_generic - 1826 * @hw: pointer to the HW structure 1827 * 1828 **/ 1829 s32 e1000_id_led_init_generic(struct e1000_hw *hw) 1830 { 1831 struct e1000_mac_info *mac = &hw->mac; 1832 s32 ret_val; 1833 const u32 ledctl_mask = 0x000000FF; 1834 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1835 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1836 u16 data, i, temp; 1837 const u16 led_mask = 0x0F; 1838 1839 DEBUGFUNC("e1000_id_led_init_generic"); 1840 1841 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 1842 if (ret_val) 1843 return ret_val; 1844 1845 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 1846 mac->ledctl_mode1 = mac->ledctl_default; 1847 mac->ledctl_mode2 = mac->ledctl_default; 1848 1849 for (i = 0; i < 4; i++) { 1850 temp = (data >> (i << 2)) & led_mask; 1851 switch (temp) { 1852 case ID_LED_ON1_DEF2: 1853 case ID_LED_ON1_ON2: 1854 case ID_LED_ON1_OFF2: 1855 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1856 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1857 break; 1858 case ID_LED_OFF1_DEF2: 1859 case ID_LED_OFF1_ON2: 1860 case ID_LED_OFF1_OFF2: 1861 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1862 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1863 break; 1864 default: 1865 /* Do nothing */ 1866 break; 1867 } 1868 switch (temp) { 1869 case ID_LED_DEF1_ON2: 1870 case ID_LED_ON1_ON2: 1871 case ID_LED_OFF1_ON2: 1872 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1873 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1874 break; 1875 case ID_LED_DEF1_OFF2: 1876 case ID_LED_ON1_OFF2: 1877 case ID_LED_OFF1_OFF2: 1878 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1879 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1880 break; 1881 default: 1882 /* Do nothing */ 1883 break; 1884 } 1885 } 1886 1887 return E1000_SUCCESS; 1888 } 1889 1890 /** 1891 * e1000_setup_led_generic - Configures SW controllable LED 1892 * @hw: pointer to the HW structure 1893 * 1894 * This prepares the SW controllable LED for use and saves the current state 1895 * of the LED so it can be later restored. 1896 **/ 1897 s32 e1000_setup_led_generic(struct e1000_hw *hw) 1898 { 1899 u32 ledctl; 1900 1901 DEBUGFUNC("e1000_setup_led_generic"); 1902 1903 if (hw->mac.ops.setup_led != e1000_setup_led_generic) 1904 return -E1000_ERR_CONFIG; 1905 1906 if (hw->phy.media_type == e1000_media_type_fiber) { 1907 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 1908 hw->mac.ledctl_default = ledctl; 1909 /* Turn off LED0 */ 1910 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK | 1911 E1000_LEDCTL_LED0_MODE_MASK); 1912 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1913 E1000_LEDCTL_LED0_MODE_SHIFT); 1914 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 1915 } else if (hw->phy.media_type == e1000_media_type_copper) { 1916 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1917 } 1918 1919 return E1000_SUCCESS; 1920 } 1921 1922 /** 1923 * e1000_cleanup_led_generic - Set LED config to default operation 1924 * @hw: pointer to the HW structure 1925 * 1926 * Remove the current LED configuration and set the LED configuration 1927 * to the default value, saved from the EEPROM. 1928 **/ 1929 s32 e1000_cleanup_led_generic(struct e1000_hw *hw) 1930 { 1931 DEBUGFUNC("e1000_cleanup_led_generic"); 1932 1933 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1934 return E1000_SUCCESS; 1935 } 1936 1937 /** 1938 * e1000_blink_led_generic - Blink LED 1939 * @hw: pointer to the HW structure 1940 * 1941 * Blink the LEDs which are set to be on. 1942 **/ 1943 s32 e1000_blink_led_generic(struct e1000_hw *hw) 1944 { 1945 u32 ledctl_blink = 0; 1946 u32 i; 1947 1948 DEBUGFUNC("e1000_blink_led_generic"); 1949 1950 if (hw->phy.media_type == e1000_media_type_fiber) { 1951 /* always blink LED0 for PCI-E fiber */ 1952 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1953 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1954 } else { 1955 /* Set the blink bit for each LED that's "on" (0x0E) 1956 * (or "off" if inverted) in ledctl_mode2. The blink 1957 * logic in hardware only works when mode is set to "on" 1958 * so it must be changed accordingly when the mode is 1959 * "off" and inverted. 1960 */ 1961 ledctl_blink = hw->mac.ledctl_mode2; 1962 for (i = 0; i < 32; i += 8) { 1963 u32 mode = (hw->mac.ledctl_mode2 >> i) & 1964 E1000_LEDCTL_LED0_MODE_MASK; 1965 u32 led_default = hw->mac.ledctl_default >> i; 1966 1967 if ((!(led_default & E1000_LEDCTL_LED0_IVRT) && 1968 (mode == E1000_LEDCTL_MODE_LED_ON)) || 1969 ((led_default & E1000_LEDCTL_LED0_IVRT) && 1970 (mode == E1000_LEDCTL_MODE_LED_OFF))) { 1971 ledctl_blink &= 1972 ~(E1000_LEDCTL_LED0_MODE_MASK << i); 1973 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK | 1974 E1000_LEDCTL_MODE_LED_ON) << i; 1975 } 1976 } 1977 } 1978 1979 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 1980 1981 return E1000_SUCCESS; 1982 } 1983 1984 /** 1985 * e1000_led_on_generic - Turn LED on 1986 * @hw: pointer to the HW structure 1987 * 1988 * Turn LED on. 1989 **/ 1990 s32 e1000_led_on_generic(struct e1000_hw *hw) 1991 { 1992 u32 ctrl; 1993 1994 DEBUGFUNC("e1000_led_on_generic"); 1995 1996 switch (hw->phy.media_type) { 1997 case e1000_media_type_fiber: 1998 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1999 ctrl &= ~E1000_CTRL_SWDPIN0; 2000 ctrl |= E1000_CTRL_SWDPIO0; 2001 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2002 break; 2003 case e1000_media_type_copper: 2004 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 2005 break; 2006 default: 2007 break; 2008 } 2009 2010 return E1000_SUCCESS; 2011 } 2012 2013 /** 2014 * e1000_led_off_generic - Turn LED off 2015 * @hw: pointer to the HW structure 2016 * 2017 * Turn LED off. 2018 **/ 2019 s32 e1000_led_off_generic(struct e1000_hw *hw) 2020 { 2021 u32 ctrl; 2022 2023 DEBUGFUNC("e1000_led_off_generic"); 2024 2025 switch (hw->phy.media_type) { 2026 case e1000_media_type_fiber: 2027 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2028 ctrl |= E1000_CTRL_SWDPIN0; 2029 ctrl |= E1000_CTRL_SWDPIO0; 2030 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2031 break; 2032 case e1000_media_type_copper: 2033 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 2034 break; 2035 default: 2036 break; 2037 } 2038 2039 return E1000_SUCCESS; 2040 } 2041 2042 /** 2043 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 2044 * @hw: pointer to the HW structure 2045 * @no_snoop: bitmap of snoop events 2046 * 2047 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 2048 **/ 2049 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 2050 { 2051 u32 gcr; 2052 2053 DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 2054 2055 if (hw->bus.type != e1000_bus_type_pci_express) 2056 return; 2057 2058 if (no_snoop) { 2059 gcr = E1000_READ_REG(hw, E1000_GCR); 2060 gcr &= ~(PCIE_NO_SNOOP_ALL); 2061 gcr |= no_snoop; 2062 E1000_WRITE_REG(hw, E1000_GCR, gcr); 2063 } 2064 } 2065 2066 /** 2067 * e1000_disable_pcie_master_generic - Disables PCI-express master access 2068 * @hw: pointer to the HW structure 2069 * 2070 * Returns E1000_SUCCESS if successful, else returns -10 2071 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 2072 * the master requests to be disabled. 2073 * 2074 * Disables PCI-Express master access and verifies there are no pending 2075 * requests. 2076 **/ 2077 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw) 2078 { 2079 u32 ctrl; 2080 s32 timeout = MASTER_DISABLE_TIMEOUT; 2081 2082 DEBUGFUNC("e1000_disable_pcie_master_generic"); 2083 2084 if (hw->bus.type != e1000_bus_type_pci_express) 2085 return E1000_SUCCESS; 2086 2087 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2088 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 2089 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2090 2091 while (timeout) { 2092 if (!(E1000_READ_REG(hw, E1000_STATUS) & 2093 E1000_STATUS_GIO_MASTER_ENABLE)) 2094 break; 2095 usec_delay(100); 2096 timeout--; 2097 } 2098 2099 if (!timeout) { 2100 DEBUGOUT("Master requests are pending.\n"); 2101 return -E1000_ERR_MASTER_REQUESTS_PENDING; 2102 } 2103 2104 return E1000_SUCCESS; 2105 } 2106 2107 /** 2108 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 2109 * @hw: pointer to the HW structure 2110 * 2111 * Reset the Adaptive Interframe Spacing throttle to default values. 2112 **/ 2113 void e1000_reset_adaptive_generic(struct e1000_hw *hw) 2114 { 2115 struct e1000_mac_info *mac = &hw->mac; 2116 2117 DEBUGFUNC("e1000_reset_adaptive_generic"); 2118 2119 if (!mac->adaptive_ifs) { 2120 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2121 return; 2122 } 2123 2124 mac->current_ifs_val = 0; 2125 mac->ifs_min_val = IFS_MIN; 2126 mac->ifs_max_val = IFS_MAX; 2127 mac->ifs_step_size = IFS_STEP; 2128 mac->ifs_ratio = IFS_RATIO; 2129 2130 mac->in_ifs_mode = FALSE; 2131 E1000_WRITE_REG(hw, E1000_AIT, 0); 2132 } 2133 2134 /** 2135 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 2136 * @hw: pointer to the HW structure 2137 * 2138 * Update the Adaptive Interframe Spacing Throttle value based on the 2139 * time between transmitted packets and time between collisions. 2140 **/ 2141 void e1000_update_adaptive_generic(struct e1000_hw *hw) 2142 { 2143 struct e1000_mac_info *mac = &hw->mac; 2144 2145 DEBUGFUNC("e1000_update_adaptive_generic"); 2146 2147 if (!mac->adaptive_ifs) { 2148 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2149 return; 2150 } 2151 2152 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 2153 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 2154 mac->in_ifs_mode = TRUE; 2155 if (mac->current_ifs_val < mac->ifs_max_val) { 2156 if (!mac->current_ifs_val) 2157 mac->current_ifs_val = mac->ifs_min_val; 2158 else 2159 mac->current_ifs_val += 2160 mac->ifs_step_size; 2161 E1000_WRITE_REG(hw, E1000_AIT, 2162 mac->current_ifs_val); 2163 } 2164 } 2165 } else { 2166 if (mac->in_ifs_mode && 2167 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 2168 mac->current_ifs_val = 0; 2169 mac->in_ifs_mode = FALSE; 2170 E1000_WRITE_REG(hw, E1000_AIT, 0); 2171 } 2172 } 2173 } 2174 2175 /** 2176 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 2177 * @hw: pointer to the HW structure 2178 * 2179 * Verify that when not using auto-negotiation that MDI/MDIx is correctly 2180 * set, which is forced to MDI mode only. 2181 **/ 2182 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 2183 { 2184 DEBUGFUNC("e1000_validate_mdi_setting_generic"); 2185 2186 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 2187 DEBUGOUT("Invalid MDI setting detected\n"); 2188 hw->phy.mdix = 1; 2189 return -E1000_ERR_CONFIG; 2190 } 2191 2192 return E1000_SUCCESS; 2193 } 2194 2195 /** 2196 * e1000_validate_mdi_setting_crossover_generic - Verify MDI/MDIx settings 2197 * @hw: pointer to the HW structure 2198 * 2199 * Validate the MDI/MDIx setting, allowing for auto-crossover during forced 2200 * operation. 2201 **/ 2202 s32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw E1000_UNUSEDARG *hw) 2203 { 2204 DEBUGFUNC("e1000_validate_mdi_setting_crossover_generic"); 2205 2206 return E1000_SUCCESS; 2207 } 2208 2209 /** 2210 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register 2211 * @hw: pointer to the HW structure 2212 * @reg: 32bit register offset such as E1000_SCTL 2213 * @offset: register offset to write to 2214 * @data: data to write at register offset 2215 * 2216 * Writes an address/data control type register. There are several of these 2217 * and they all have the format address << 8 | data and bit 31 is polled for 2218 * completion. 2219 **/ 2220 s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, 2221 u32 offset, u8 data) 2222 { 2223 u32 i, regvalue = 0; 2224 2225 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); 2226 2227 /* Set up the address and data */ 2228 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 2229 E1000_WRITE_REG(hw, reg, regvalue); 2230 2231 /* Poll the ready bit to see if the MDI read completed */ 2232 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 2233 usec_delay(5); 2234 regvalue = E1000_READ_REG(hw, reg); 2235 if (regvalue & E1000_GEN_CTL_READY) 2236 break; 2237 } 2238 if (!(regvalue & E1000_GEN_CTL_READY)) { 2239 DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 2240 return -E1000_ERR_PHY; 2241 } 2242 2243 return E1000_SUCCESS; 2244 } 2245