1 /****************************************************************************** 2 3 Copyright (c) 2001-2014, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD:$*/ 34 35 #include "e1000_api.h" 36 37 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw); 38 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); 39 static void e1000_config_collision_dist_generic(struct e1000_hw *hw); 40 static int e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index); 41 42 /** 43 * e1000_init_mac_ops_generic - Initialize MAC function pointers 44 * @hw: pointer to the HW structure 45 * 46 * Setups up the function pointers to no-op functions 47 **/ 48 void e1000_init_mac_ops_generic(struct e1000_hw *hw) 49 { 50 struct e1000_mac_info *mac = &hw->mac; 51 DEBUGFUNC("e1000_init_mac_ops_generic"); 52 53 /* General Setup */ 54 mac->ops.init_params = e1000_null_ops_generic; 55 mac->ops.init_hw = e1000_null_ops_generic; 56 mac->ops.reset_hw = e1000_null_ops_generic; 57 mac->ops.setup_physical_interface = e1000_null_ops_generic; 58 mac->ops.get_bus_info = e1000_null_ops_generic; 59 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie; 60 mac->ops.read_mac_addr = e1000_read_mac_addr_generic; 61 mac->ops.config_collision_dist = e1000_config_collision_dist_generic; 62 mac->ops.clear_hw_cntrs = e1000_null_mac_generic; 63 /* LED */ 64 mac->ops.cleanup_led = e1000_null_ops_generic; 65 mac->ops.setup_led = e1000_null_ops_generic; 66 mac->ops.blink_led = e1000_null_ops_generic; 67 mac->ops.led_on = e1000_null_ops_generic; 68 mac->ops.led_off = e1000_null_ops_generic; 69 /* LINK */ 70 mac->ops.setup_link = e1000_null_ops_generic; 71 mac->ops.get_link_up_info = e1000_null_link_info; 72 mac->ops.check_for_link = e1000_null_ops_generic; 73 mac->ops.set_obff_timer = e1000_null_set_obff_timer; 74 /* Management */ 75 mac->ops.check_mng_mode = e1000_null_mng_mode; 76 /* VLAN, MC, etc. */ 77 mac->ops.update_mc_addr_list = e1000_null_update_mc; 78 mac->ops.clear_vfta = e1000_null_mac_generic; 79 mac->ops.write_vfta = e1000_null_write_vfta; 80 mac->ops.rar_set = e1000_rar_set_generic; 81 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; 82 } 83 84 /** 85 * e1000_null_ops_generic - No-op function, returns 0 86 * @hw: pointer to the HW structure 87 **/ 88 s32 e1000_null_ops_generic(struct e1000_hw E1000_UNUSEDARG *hw) 89 { 90 DEBUGFUNC("e1000_null_ops_generic"); 91 return E1000_SUCCESS; 92 } 93 94 /** 95 * e1000_null_mac_generic - No-op function, return void 96 * @hw: pointer to the HW structure 97 **/ 98 void e1000_null_mac_generic(struct e1000_hw E1000_UNUSEDARG *hw) 99 { 100 DEBUGFUNC("e1000_null_mac_generic"); 101 return; 102 } 103 104 /** 105 * e1000_null_link_info - No-op function, return 0 106 * @hw: pointer to the HW structure 107 **/ 108 s32 e1000_null_link_info(struct e1000_hw E1000_UNUSEDARG *hw, 109 u16 E1000_UNUSEDARG *s, u16 E1000_UNUSEDARG *d) 110 { 111 DEBUGFUNC("e1000_null_link_info"); 112 return E1000_SUCCESS; 113 } 114 115 /** 116 * e1000_null_mng_mode - No-op function, return FALSE 117 * @hw: pointer to the HW structure 118 **/ 119 bool e1000_null_mng_mode(struct e1000_hw E1000_UNUSEDARG *hw) 120 { 121 DEBUGFUNC("e1000_null_mng_mode"); 122 return FALSE; 123 } 124 125 /** 126 * e1000_null_update_mc - No-op function, return void 127 * @hw: pointer to the HW structure 128 **/ 129 void e1000_null_update_mc(struct e1000_hw E1000_UNUSEDARG *hw, 130 u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a) 131 { 132 DEBUGFUNC("e1000_null_update_mc"); 133 return; 134 } 135 136 /** 137 * e1000_null_write_vfta - No-op function, return void 138 * @hw: pointer to the HW structure 139 **/ 140 void e1000_null_write_vfta(struct e1000_hw E1000_UNUSEDARG *hw, 141 u32 E1000_UNUSEDARG a, u32 E1000_UNUSEDARG b) 142 { 143 DEBUGFUNC("e1000_null_write_vfta"); 144 return; 145 } 146 147 /** 148 * e1000_null_rar_set - No-op function, return 0 149 * @hw: pointer to the HW structure 150 **/ 151 int e1000_null_rar_set(struct e1000_hw E1000_UNUSEDARG *hw, 152 u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a) 153 { 154 DEBUGFUNC("e1000_null_rar_set"); 155 return E1000_SUCCESS; 156 } 157 158 /** 159 * e1000_null_set_obff_timer - No-op function, return 0 160 * @hw: pointer to the HW structure 161 **/ 162 s32 e1000_null_set_obff_timer(struct e1000_hw E1000_UNUSEDARG *hw, 163 u32 E1000_UNUSEDARG a) 164 { 165 DEBUGFUNC("e1000_null_set_obff_timer"); 166 return E1000_SUCCESS; 167 } 168 169 /** 170 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information 171 * @hw: pointer to the HW structure 172 * 173 * Determines and stores the system bus information for a particular 174 * network interface. The following bus information is determined and stored: 175 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function. 176 **/ 177 s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw) 178 { 179 struct e1000_mac_info *mac = &hw->mac; 180 struct e1000_bus_info *bus = &hw->bus; 181 u32 status = E1000_READ_REG(hw, E1000_STATUS); 182 s32 ret_val = E1000_SUCCESS; 183 184 DEBUGFUNC("e1000_get_bus_info_pci_generic"); 185 186 /* PCI or PCI-X? */ 187 bus->type = (status & E1000_STATUS_PCIX_MODE) 188 ? e1000_bus_type_pcix 189 : e1000_bus_type_pci; 190 191 /* Bus speed */ 192 if (bus->type == e1000_bus_type_pci) { 193 bus->speed = (status & E1000_STATUS_PCI66) 194 ? e1000_bus_speed_66 195 : e1000_bus_speed_33; 196 } else { 197 switch (status & E1000_STATUS_PCIX_SPEED) { 198 case E1000_STATUS_PCIX_SPEED_66: 199 bus->speed = e1000_bus_speed_66; 200 break; 201 case E1000_STATUS_PCIX_SPEED_100: 202 bus->speed = e1000_bus_speed_100; 203 break; 204 case E1000_STATUS_PCIX_SPEED_133: 205 bus->speed = e1000_bus_speed_133; 206 break; 207 default: 208 bus->speed = e1000_bus_speed_reserved; 209 break; 210 } 211 } 212 213 /* Bus width */ 214 bus->width = (status & E1000_STATUS_BUS64) 215 ? e1000_bus_width_64 216 : e1000_bus_width_32; 217 218 /* Which PCI(-X) function? */ 219 mac->ops.set_lan_id(hw); 220 221 return ret_val; 222 } 223 224 /** 225 * e1000_get_bus_info_pcie_generic - Get PCIe bus information 226 * @hw: pointer to the HW structure 227 * 228 * Determines and stores the system bus information for a particular 229 * network interface. The following bus information is determined and stored: 230 * bus speed, bus width, type (PCIe), and PCIe function. 231 **/ 232 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 233 { 234 struct e1000_mac_info *mac = &hw->mac; 235 struct e1000_bus_info *bus = &hw->bus; 236 s32 ret_val; 237 u16 pcie_link_status; 238 239 DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 240 241 bus->type = e1000_bus_type_pci_express; 242 243 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS, 244 &pcie_link_status); 245 if (ret_val) { 246 bus->width = e1000_bus_width_unknown; 247 bus->speed = e1000_bus_speed_unknown; 248 } else { 249 switch (pcie_link_status & PCIE_LINK_SPEED_MASK) { 250 case PCIE_LINK_SPEED_2500: 251 bus->speed = e1000_bus_speed_2500; 252 break; 253 case PCIE_LINK_SPEED_5000: 254 bus->speed = e1000_bus_speed_5000; 255 break; 256 default: 257 bus->speed = e1000_bus_speed_unknown; 258 break; 259 } 260 261 bus->width = (enum e1000_bus_width)((pcie_link_status & 262 PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT); 263 } 264 265 mac->ops.set_lan_id(hw); 266 267 return E1000_SUCCESS; 268 } 269 270 /** 271 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 272 * 273 * @hw: pointer to the HW structure 274 * 275 * Determines the LAN function id by reading memory-mapped registers 276 * and swaps the port value if requested. 277 **/ 278 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) 279 { 280 struct e1000_bus_info *bus = &hw->bus; 281 u32 reg; 282 283 /* The status register reports the correct function number 284 * for the device regardless of function swap state. 285 */ 286 reg = E1000_READ_REG(hw, E1000_STATUS); 287 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 288 } 289 290 /** 291 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices 292 * @hw: pointer to the HW structure 293 * 294 * Determines the LAN function id by reading PCI config space. 295 **/ 296 void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw) 297 { 298 struct e1000_bus_info *bus = &hw->bus; 299 u16 pci_header_type; 300 u32 status; 301 302 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 303 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { 304 status = E1000_READ_REG(hw, E1000_STATUS); 305 bus->func = (status & E1000_STATUS_FUNC_MASK) 306 >> E1000_STATUS_FUNC_SHIFT; 307 } else { 308 bus->func = 0; 309 } 310 } 311 312 /** 313 * e1000_set_lan_id_single_port - Set LAN id for a single port device 314 * @hw: pointer to the HW structure 315 * 316 * Sets the LAN function id to zero for a single port device. 317 **/ 318 void e1000_set_lan_id_single_port(struct e1000_hw *hw) 319 { 320 struct e1000_bus_info *bus = &hw->bus; 321 322 bus->func = 0; 323 } 324 325 /** 326 * e1000_clear_vfta_generic - Clear VLAN filter table 327 * @hw: pointer to the HW structure 328 * 329 * Clears the register array which contains the VLAN filter table by 330 * setting all the values to 0. 331 **/ 332 void e1000_clear_vfta_generic(struct e1000_hw *hw) 333 { 334 u32 offset; 335 336 DEBUGFUNC("e1000_clear_vfta_generic"); 337 338 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 339 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 340 E1000_WRITE_FLUSH(hw); 341 } 342 } 343 344 /** 345 * e1000_write_vfta_generic - Write value to VLAN filter table 346 * @hw: pointer to the HW structure 347 * @offset: register offset in VLAN filter table 348 * @value: register value written to VLAN filter table 349 * 350 * Writes value at the given offset in the register array which stores 351 * the VLAN filter table. 352 **/ 353 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 354 { 355 DEBUGFUNC("e1000_write_vfta_generic"); 356 357 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 358 E1000_WRITE_FLUSH(hw); 359 } 360 361 /** 362 * e1000_init_rx_addrs_generic - Initialize receive address's 363 * @hw: pointer to the HW structure 364 * @rar_count: receive address registers 365 * 366 * Setup the receive address registers by setting the base receive address 367 * register to the devices MAC address and clearing all the other receive 368 * address registers to 0. 369 **/ 370 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 371 { 372 u32 i; 373 u8 mac_addr[ETH_ADDR_LEN] = {0}; 374 375 DEBUGFUNC("e1000_init_rx_addrs_generic"); 376 377 /* Setup the receive address */ 378 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 379 380 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 381 382 /* Zero out the other (rar_entry_count - 1) receive addresses */ 383 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 384 for (i = 1; i < rar_count; i++) 385 hw->mac.ops.rar_set(hw, mac_addr, i); 386 } 387 388 /** 389 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 390 * @hw: pointer to the HW structure 391 * 392 * Checks the nvm for an alternate MAC address. An alternate MAC address 393 * can be setup by pre-boot software and must be treated like a permanent 394 * address and must override the actual permanent MAC address. If an 395 * alternate MAC address is found it is programmed into RAR0, replacing 396 * the permanent address that was installed into RAR0 by the Si on reset. 397 * This function will return SUCCESS unless it encounters an error while 398 * reading the EEPROM. 399 **/ 400 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 401 { 402 u32 i; 403 s32 ret_val; 404 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 405 u8 alt_mac_addr[ETH_ADDR_LEN]; 406 407 DEBUGFUNC("e1000_check_alt_mac_addr_generic"); 408 409 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data); 410 if (ret_val) 411 return ret_val; 412 413 /* not supported on older hardware or 82573 */ 414 if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573)) 415 return E1000_SUCCESS; 416 417 /* Alternate MAC address is handled by the option ROM for 82580 418 * and newer. SW support not required. 419 */ 420 if (hw->mac.type >= e1000_82580) 421 return E1000_SUCCESS; 422 423 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 424 &nvm_alt_mac_addr_offset); 425 if (ret_val) { 426 DEBUGOUT("NVM Read Error\n"); 427 return ret_val; 428 } 429 430 if ((nvm_alt_mac_addr_offset == 0xFFFF) || 431 (nvm_alt_mac_addr_offset == 0x0000)) 432 /* There is no Alternate MAC Address */ 433 return E1000_SUCCESS; 434 435 if (hw->bus.func == E1000_FUNC_1) 436 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 437 if (hw->bus.func == E1000_FUNC_2) 438 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2; 439 440 if (hw->bus.func == E1000_FUNC_3) 441 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3; 442 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 443 offset = nvm_alt_mac_addr_offset + (i >> 1); 444 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 445 if (ret_val) { 446 DEBUGOUT("NVM Read Error\n"); 447 return ret_val; 448 } 449 450 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 451 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 452 } 453 454 /* if multicast bit is set, the alternate address will not be used */ 455 if (alt_mac_addr[0] & 0x01) { 456 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); 457 return E1000_SUCCESS; 458 } 459 460 /* We have a valid alternate MAC address, and we want to treat it the 461 * same as the normal permanent MAC address stored by the HW into the 462 * RAR. Do this by mapping this address into RAR0. 463 */ 464 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 465 466 return E1000_SUCCESS; 467 } 468 469 /** 470 * e1000_rar_set_generic - Set receive address register 471 * @hw: pointer to the HW structure 472 * @addr: pointer to the receive address 473 * @index: receive address array register 474 * 475 * Sets the receive address array register at index to the address passed 476 * in by addr. 477 **/ 478 static int e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 479 { 480 u32 rar_low, rar_high; 481 482 DEBUGFUNC("e1000_rar_set_generic"); 483 484 /* HW expects these in little endian so we reverse the byte order 485 * from network order (big endian) to little endian 486 */ 487 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 488 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 489 490 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 491 492 /* If MAC address zero, no need to set the AV bit */ 493 if (rar_low || rar_high) 494 rar_high |= E1000_RAH_AV; 495 496 /* Some bridges will combine consecutive 32-bit writes into 497 * a single burst write, which will malfunction on some parts. 498 * The flushes avoid this. 499 */ 500 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 501 E1000_WRITE_FLUSH(hw); 502 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 503 E1000_WRITE_FLUSH(hw); 504 505 return E1000_SUCCESS; 506 } 507 508 /** 509 * e1000_hash_mc_addr_generic - Generate a multicast hash value 510 * @hw: pointer to the HW structure 511 * @mc_addr: pointer to a multicast address 512 * 513 * Generates a multicast address hash value which is used to determine 514 * the multicast filter table array address and new table value. 515 **/ 516 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 517 { 518 u32 hash_value, hash_mask; 519 u8 bit_shift = 0; 520 521 DEBUGFUNC("e1000_hash_mc_addr_generic"); 522 523 /* Register count multiplied by bits per register */ 524 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 525 526 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts 527 * where 0xFF would still fall within the hash mask. 528 */ 529 while (hash_mask >> bit_shift != 0xFF) 530 bit_shift++; 531 532 /* The portion of the address that is used for the hash table 533 * is determined by the mc_filter_type setting. 534 * The algorithm is such that there is a total of 8 bits of shifting. 535 * The bit_shift for a mc_filter_type of 0 represents the number of 536 * left-shifts where the MSB of mc_addr[5] would still fall within 537 * the hash_mask. Case 0 does this exactly. Since there are a total 538 * of 8 bits of shifting, then mc_addr[4] will shift right the 539 * remaining number of bits. Thus 8 - bit_shift. The rest of the 540 * cases are a variation of this algorithm...essentially raising the 541 * number of bits to shift mc_addr[5] left, while still keeping the 542 * 8-bit shifting total. 543 * 544 * For example, given the following Destination MAC Address and an 545 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 546 * we can see that the bit_shift for case 0 is 4. These are the hash 547 * values resulting from each mc_filter_type... 548 * [0] [1] [2] [3] [4] [5] 549 * 01 AA 00 12 34 56 550 * LSB MSB 551 * 552 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 553 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 554 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 555 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 556 */ 557 switch (hw->mac.mc_filter_type) { 558 default: 559 case 0: 560 break; 561 case 1: 562 bit_shift += 1; 563 break; 564 case 2: 565 bit_shift += 2; 566 break; 567 case 3: 568 bit_shift += 4; 569 break; 570 } 571 572 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 573 (((u16) mc_addr[5]) << bit_shift))); 574 575 return hash_value; 576 } 577 578 /** 579 * e1000_update_mc_addr_list_generic - Update Multicast addresses 580 * @hw: pointer to the HW structure 581 * @mc_addr_list: array of multicast addresses to program 582 * @mc_addr_count: number of multicast addresses to program 583 * 584 * Updates entire Multicast Table Array. 585 * The caller must have a packed mc_addr_list of multicast addresses. 586 **/ 587 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw, 588 u8 *mc_addr_list, u32 mc_addr_count) 589 { 590 u32 hash_value, hash_bit, hash_reg; 591 int i; 592 593 DEBUGFUNC("e1000_update_mc_addr_list_generic"); 594 595 /* clear mta_shadow */ 596 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 597 598 /* update mta_shadow from mc_addr_list */ 599 for (i = 0; (u32) i < mc_addr_count; i++) { 600 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list); 601 602 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 603 hash_bit = hash_value & 0x1F; 604 605 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 606 mc_addr_list += (ETH_ADDR_LEN); 607 } 608 609 /* replace the entire MTA table */ 610 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 611 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 612 E1000_WRITE_FLUSH(hw); 613 } 614 615 /** 616 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value 617 * @hw: pointer to the HW structure 618 * 619 * In certain situations, a system BIOS may report that the PCIx maximum 620 * memory read byte count (MMRBC) value is higher than than the actual 621 * value. We check the PCIx command register with the current PCIx status 622 * register. 623 **/ 624 void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw) 625 { 626 u16 cmd_mmrbc; 627 u16 pcix_cmd; 628 u16 pcix_stat_hi_word; 629 u16 stat_mmrbc; 630 631 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); 632 633 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ 634 if (hw->bus.type != e1000_bus_type_pcix) 635 return; 636 637 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 638 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 639 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> 640 PCIX_COMMAND_MMRBC_SHIFT; 641 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 642 PCIX_STATUS_HI_MMRBC_SHIFT; 643 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 644 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 645 if (cmd_mmrbc > stat_mmrbc) { 646 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; 647 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 648 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 649 } 650 } 651 652 /** 653 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 654 * @hw: pointer to the HW structure 655 * 656 * Clears the base hardware counters by reading the counter registers. 657 **/ 658 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 659 { 660 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 661 662 E1000_READ_REG(hw, E1000_CRCERRS); 663 E1000_READ_REG(hw, E1000_SYMERRS); 664 E1000_READ_REG(hw, E1000_MPC); 665 E1000_READ_REG(hw, E1000_SCC); 666 E1000_READ_REG(hw, E1000_ECOL); 667 E1000_READ_REG(hw, E1000_MCC); 668 E1000_READ_REG(hw, E1000_LATECOL); 669 E1000_READ_REG(hw, E1000_COLC); 670 E1000_READ_REG(hw, E1000_DC); 671 E1000_READ_REG(hw, E1000_SEC); 672 E1000_READ_REG(hw, E1000_RLEC); 673 E1000_READ_REG(hw, E1000_XONRXC); 674 E1000_READ_REG(hw, E1000_XONTXC); 675 E1000_READ_REG(hw, E1000_XOFFRXC); 676 E1000_READ_REG(hw, E1000_XOFFTXC); 677 E1000_READ_REG(hw, E1000_FCRUC); 678 E1000_READ_REG(hw, E1000_GPRC); 679 E1000_READ_REG(hw, E1000_BPRC); 680 E1000_READ_REG(hw, E1000_MPRC); 681 E1000_READ_REG(hw, E1000_GPTC); 682 E1000_READ_REG(hw, E1000_GORCL); 683 E1000_READ_REG(hw, E1000_GORCH); 684 E1000_READ_REG(hw, E1000_GOTCL); 685 E1000_READ_REG(hw, E1000_GOTCH); 686 E1000_READ_REG(hw, E1000_RNBC); 687 E1000_READ_REG(hw, E1000_RUC); 688 E1000_READ_REG(hw, E1000_RFC); 689 E1000_READ_REG(hw, E1000_ROC); 690 E1000_READ_REG(hw, E1000_RJC); 691 E1000_READ_REG(hw, E1000_TORL); 692 E1000_READ_REG(hw, E1000_TORH); 693 E1000_READ_REG(hw, E1000_TOTL); 694 E1000_READ_REG(hw, E1000_TOTH); 695 E1000_READ_REG(hw, E1000_TPR); 696 E1000_READ_REG(hw, E1000_TPT); 697 E1000_READ_REG(hw, E1000_MPTC); 698 E1000_READ_REG(hw, E1000_BPTC); 699 } 700 701 /** 702 * e1000_check_for_copper_link_generic - Check for link (Copper) 703 * @hw: pointer to the HW structure 704 * 705 * Checks to see of the link status of the hardware has changed. If a 706 * change in link status has been detected, then we read the PHY registers 707 * to get the current speed/duplex if link exists. 708 **/ 709 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) 710 { 711 struct e1000_mac_info *mac = &hw->mac; 712 s32 ret_val; 713 bool link; 714 715 DEBUGFUNC("e1000_check_for_copper_link"); 716 717 /* We only want to go out to the PHY registers to see if Auto-Neg 718 * has completed and/or if our link status has changed. The 719 * get_link_status flag is set upon receiving a Link Status 720 * Change or Rx Sequence Error interrupt. 721 */ 722 if (!mac->get_link_status) 723 return E1000_SUCCESS; 724 725 /* First we want to see if the MII Status Register reports 726 * link. If so, then we want to get the current speed/duplex 727 * of the PHY. 728 */ 729 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 730 if (ret_val) 731 return ret_val; 732 733 if (!link) 734 return E1000_SUCCESS; /* No link detected */ 735 736 mac->get_link_status = FALSE; 737 738 /* Check if there was DownShift, must be checked 739 * immediately after link-up 740 */ 741 e1000_check_downshift_generic(hw); 742 743 /* If we are forcing speed/duplex, then we simply return since 744 * we have already determined whether we have link or not. 745 */ 746 if (!mac->autoneg) 747 return -E1000_ERR_CONFIG; 748 749 /* Auto-Neg is enabled. Auto Speed Detection takes care 750 * of MAC speed/duplex configuration. So we only need to 751 * configure Collision Distance in the MAC. 752 */ 753 mac->ops.config_collision_dist(hw); 754 755 /* Configure Flow Control now that Auto-Neg has completed. 756 * First, we need to restore the desired flow control 757 * settings because we may have had to re-autoneg with a 758 * different link partner. 759 */ 760 ret_val = e1000_config_fc_after_link_up_generic(hw); 761 if (ret_val) 762 DEBUGOUT("Error configuring flow control\n"); 763 764 return ret_val; 765 } 766 767 /** 768 * e1000_check_for_fiber_link_generic - Check for link (Fiber) 769 * @hw: pointer to the HW structure 770 * 771 * Checks for link up on the hardware. If link is not up and we have 772 * a signal, then we need to force link up. 773 **/ 774 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 775 { 776 struct e1000_mac_info *mac = &hw->mac; 777 u32 rxcw; 778 u32 ctrl; 779 u32 status; 780 s32 ret_val; 781 782 DEBUGFUNC("e1000_check_for_fiber_link_generic"); 783 784 ctrl = E1000_READ_REG(hw, E1000_CTRL); 785 status = E1000_READ_REG(hw, E1000_STATUS); 786 rxcw = E1000_READ_REG(hw, E1000_RXCW); 787 788 /* If we don't have link (auto-negotiation failed or link partner 789 * cannot auto-negotiate), the cable is plugged in (we have signal), 790 * and our link partner is not trying to auto-negotiate with us (we 791 * are receiving idles or data), we need to force link up. We also 792 * need to give auto-negotiation time to complete, in case the cable 793 * was just plugged in. The autoneg_failed flag does this. 794 */ 795 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 796 if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) && 797 !(rxcw & E1000_RXCW_C)) { 798 if (!mac->autoneg_failed) { 799 mac->autoneg_failed = TRUE; 800 return E1000_SUCCESS; 801 } 802 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 803 804 /* Disable auto-negotiation in the TXCW register */ 805 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 806 807 /* Force link-up and also force full-duplex. */ 808 ctrl = E1000_READ_REG(hw, E1000_CTRL); 809 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 810 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 811 812 /* Configure Flow Control after forcing link up. */ 813 ret_val = e1000_config_fc_after_link_up_generic(hw); 814 if (ret_val) { 815 DEBUGOUT("Error configuring flow control\n"); 816 return ret_val; 817 } 818 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 819 /* If we are forcing link and we are receiving /C/ ordered 820 * sets, re-enable auto-negotiation in the TXCW register 821 * and disable forced link in the Device Control register 822 * in an attempt to auto-negotiate with our link partner. 823 */ 824 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 825 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 826 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 827 828 mac->serdes_has_link = TRUE; 829 } 830 831 return E1000_SUCCESS; 832 } 833 834 /** 835 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 836 * @hw: pointer to the HW structure 837 * 838 * Checks for link up on the hardware. If link is not up and we have 839 * a signal, then we need to force link up. 840 **/ 841 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 842 { 843 struct e1000_mac_info *mac = &hw->mac; 844 u32 rxcw; 845 u32 ctrl; 846 u32 status; 847 s32 ret_val; 848 849 DEBUGFUNC("e1000_check_for_serdes_link_generic"); 850 851 ctrl = E1000_READ_REG(hw, E1000_CTRL); 852 status = E1000_READ_REG(hw, E1000_STATUS); 853 rxcw = E1000_READ_REG(hw, E1000_RXCW); 854 855 /* If we don't have link (auto-negotiation failed or link partner 856 * cannot auto-negotiate), and our link partner is not trying to 857 * auto-negotiate with us (we are receiving idles or data), 858 * we need to force link up. We also need to give auto-negotiation 859 * time to complete. 860 */ 861 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 862 if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) { 863 if (!mac->autoneg_failed) { 864 mac->autoneg_failed = TRUE; 865 return E1000_SUCCESS; 866 } 867 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 868 869 /* Disable auto-negotiation in the TXCW register */ 870 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 871 872 /* Force link-up and also force full-duplex. */ 873 ctrl = E1000_READ_REG(hw, E1000_CTRL); 874 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 875 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 876 877 /* Configure Flow Control after forcing link up. */ 878 ret_val = e1000_config_fc_after_link_up_generic(hw); 879 if (ret_val) { 880 DEBUGOUT("Error configuring flow control\n"); 881 return ret_val; 882 } 883 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 884 /* If we are forcing link and we are receiving /C/ ordered 885 * sets, re-enable auto-negotiation in the TXCW register 886 * and disable forced link in the Device Control register 887 * in an attempt to auto-negotiate with our link partner. 888 */ 889 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 890 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 891 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 892 893 mac->serdes_has_link = TRUE; 894 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 895 /* If we force link for non-auto-negotiation switch, check 896 * link status based on MAC synchronization for internal 897 * serdes media type. 898 */ 899 /* SYNCH bit and IV bit are sticky. */ 900 usec_delay(10); 901 rxcw = E1000_READ_REG(hw, E1000_RXCW); 902 if (rxcw & E1000_RXCW_SYNCH) { 903 if (!(rxcw & E1000_RXCW_IV)) { 904 mac->serdes_has_link = TRUE; 905 DEBUGOUT("SERDES: Link up - forced.\n"); 906 } 907 } else { 908 mac->serdes_has_link = FALSE; 909 DEBUGOUT("SERDES: Link down - force failed.\n"); 910 } 911 } 912 913 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 914 status = E1000_READ_REG(hw, E1000_STATUS); 915 if (status & E1000_STATUS_LU) { 916 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 917 usec_delay(10); 918 rxcw = E1000_READ_REG(hw, E1000_RXCW); 919 if (rxcw & E1000_RXCW_SYNCH) { 920 if (!(rxcw & E1000_RXCW_IV)) { 921 mac->serdes_has_link = TRUE; 922 DEBUGOUT("SERDES: Link up - autoneg completed successfully.\n"); 923 } else { 924 mac->serdes_has_link = FALSE; 925 DEBUGOUT("SERDES: Link down - invalid codewords detected in autoneg.\n"); 926 } 927 } else { 928 mac->serdes_has_link = FALSE; 929 DEBUGOUT("SERDES: Link down - no sync.\n"); 930 } 931 } else { 932 mac->serdes_has_link = FALSE; 933 DEBUGOUT("SERDES: Link down - autoneg failed\n"); 934 } 935 } 936 937 return E1000_SUCCESS; 938 } 939 940 /** 941 * e1000_set_default_fc_generic - Set flow control default values 942 * @hw: pointer to the HW structure 943 * 944 * Read the EEPROM for the default values for flow control and store the 945 * values. 946 **/ 947 #ifdef NO_82542_SUPPORT 948 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw) 949 #else 950 s32 e1000_set_default_fc_generic(struct e1000_hw *hw) 951 #endif 952 { 953 s32 ret_val; 954 u16 nvm_data; 955 u16 nvm_offset = 0; 956 957 DEBUGFUNC("e1000_set_default_fc_generic"); 958 959 /* Read and store word 0x0F of the EEPROM. This word contains bits 960 * that determine the hardware's default PAUSE (flow control) mode, 961 * a bit that determines whether the HW defaults to enabling or 962 * disabling auto-negotiation, and the direction of the 963 * SW defined pins. If there is no SW over-ride of the flow 964 * control setting, then the variable hw->fc will 965 * be initialized based on a value in the EEPROM. 966 */ 967 if (hw->mac.type == e1000_i350) { 968 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(hw->bus.func); 969 ret_val = hw->nvm.ops.read(hw, 970 NVM_INIT_CONTROL2_REG + 971 nvm_offset, 972 1, &nvm_data); 973 } else { 974 ret_val = hw->nvm.ops.read(hw, 975 NVM_INIT_CONTROL2_REG, 976 1, &nvm_data); 977 } 978 979 980 if (ret_val) { 981 DEBUGOUT("NVM Read Error\n"); 982 return ret_val; 983 } 984 985 if (!(nvm_data & NVM_WORD0F_PAUSE_MASK)) 986 hw->fc.requested_mode = e1000_fc_none; 987 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 988 NVM_WORD0F_ASM_DIR) 989 hw->fc.requested_mode = e1000_fc_tx_pause; 990 else 991 hw->fc.requested_mode = e1000_fc_full; 992 993 return E1000_SUCCESS; 994 } 995 996 /** 997 * e1000_setup_link_generic - Setup flow control and link settings 998 * @hw: pointer to the HW structure 999 * 1000 * Determines which flow control settings to use, then configures flow 1001 * control. Calls the appropriate media-specific link configuration 1002 * function. Assuming the adapter has a valid link partner, a valid link 1003 * should be established. Assumes the hardware has previously been reset 1004 * and the transmitter and receiver are not enabled. 1005 **/ 1006 s32 e1000_setup_link_generic(struct e1000_hw *hw) 1007 { 1008 s32 ret_val; 1009 1010 DEBUGFUNC("e1000_setup_link_generic"); 1011 1012 /* In the case of the phy reset being blocked, we already have a link. 1013 * We do not need to set it up again. 1014 */ 1015 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 1016 return E1000_SUCCESS; 1017 1018 /* If requested flow control is set to default, set flow control 1019 * based on the EEPROM flow control settings. 1020 */ 1021 if (hw->fc.requested_mode == e1000_fc_default) { 1022 ret_val = e1000_set_default_fc_generic(hw); 1023 if (ret_val) 1024 return ret_val; 1025 } 1026 1027 /* Save off the requested flow control mode for use later. Depending 1028 * on the link partner's capabilities, we may or may not use this mode. 1029 */ 1030 hw->fc.current_mode = hw->fc.requested_mode; 1031 1032 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 1033 hw->fc.current_mode); 1034 1035 /* Call the necessary media_type subroutine to configure the link. */ 1036 ret_val = hw->mac.ops.setup_physical_interface(hw); 1037 if (ret_val) 1038 return ret_val; 1039 1040 /* Initialize the flow control address, type, and PAUSE timer 1041 * registers to their default values. This is done even if flow 1042 * control is disabled, because it does not hurt anything to 1043 * initialize these registers. 1044 */ 1045 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 1046 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 1047 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1048 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 1049 1050 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 1051 1052 return e1000_set_fc_watermarks_generic(hw); 1053 } 1054 1055 /** 1056 * e1000_commit_fc_settings_generic - Configure flow control 1057 * @hw: pointer to the HW structure 1058 * 1059 * Write the flow control settings to the Transmit Config Word Register (TXCW) 1060 * base on the flow control settings in e1000_mac_info. 1061 **/ 1062 s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 1063 { 1064 struct e1000_mac_info *mac = &hw->mac; 1065 u32 txcw; 1066 1067 DEBUGFUNC("e1000_commit_fc_settings_generic"); 1068 1069 /* Check for a software override of the flow control settings, and 1070 * setup the device accordingly. If auto-negotiation is enabled, then 1071 * software will have to set the "PAUSE" bits to the correct value in 1072 * the Transmit Config Word Register (TXCW) and re-start auto- 1073 * negotiation. However, if auto-negotiation is disabled, then 1074 * software will have to manually configure the two flow control enable 1075 * bits in the CTRL register. 1076 * 1077 * The possible values of the "fc" parameter are: 1078 * 0: Flow control is completely disabled 1079 * 1: Rx flow control is enabled (we can receive pause frames, 1080 * but not send pause frames). 1081 * 2: Tx flow control is enabled (we can send pause frames but we 1082 * do not support receiving pause frames). 1083 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1084 */ 1085 switch (hw->fc.current_mode) { 1086 case e1000_fc_none: 1087 /* Flow control completely disabled by a software over-ride. */ 1088 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1089 break; 1090 case e1000_fc_rx_pause: 1091 /* Rx Flow control is enabled and Tx Flow control is disabled 1092 * by a software over-ride. Since there really isn't a way to 1093 * advertise that we are capable of Rx Pause ONLY, we will 1094 * advertise that we support both symmetric and asymmetric Rx 1095 * PAUSE. Later, we will disable the adapter's ability to send 1096 * PAUSE frames. 1097 */ 1098 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1099 break; 1100 case e1000_fc_tx_pause: 1101 /* Tx Flow control is enabled, and Rx Flow control is disabled, 1102 * by a software over-ride. 1103 */ 1104 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1105 break; 1106 case e1000_fc_full: 1107 /* Flow control (both Rx and Tx) is enabled by a software 1108 * over-ride. 1109 */ 1110 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1111 break; 1112 default: 1113 DEBUGOUT("Flow control param set incorrectly\n"); 1114 return -E1000_ERR_CONFIG; 1115 break; 1116 } 1117 1118 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1119 mac->txcw = txcw; 1120 1121 return E1000_SUCCESS; 1122 } 1123 1124 /** 1125 * e1000_poll_fiber_serdes_link_generic - Poll for link up 1126 * @hw: pointer to the HW structure 1127 * 1128 * Polls for link up by reading the status register, if link fails to come 1129 * up with auto-negotiation, then the link is forced if a signal is detected. 1130 **/ 1131 s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 1132 { 1133 struct e1000_mac_info *mac = &hw->mac; 1134 u32 i, status; 1135 s32 ret_val; 1136 1137 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 1138 1139 /* If we have a signal (the cable is plugged in, or assumed TRUE for 1140 * serdes media) then poll for a "Link-Up" indication in the Device 1141 * Status Register. Time-out if a link isn't seen in 500 milliseconds 1142 * seconds (Auto-negotiation should complete in less than 500 1143 * milliseconds even if the other end is doing it in SW). 1144 */ 1145 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 1146 msec_delay(10); 1147 status = E1000_READ_REG(hw, E1000_STATUS); 1148 if (status & E1000_STATUS_LU) 1149 break; 1150 } 1151 if (i == FIBER_LINK_UP_LIMIT) { 1152 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1153 mac->autoneg_failed = TRUE; 1154 /* AutoNeg failed to achieve a link, so we'll call 1155 * mac->check_for_link. This routine will force the 1156 * link up if we detect a signal. This will allow us to 1157 * communicate with non-autonegotiating link partners. 1158 */ 1159 ret_val = mac->ops.check_for_link(hw); 1160 if (ret_val) { 1161 DEBUGOUT("Error while checking for link\n"); 1162 return ret_val; 1163 } 1164 mac->autoneg_failed = FALSE; 1165 } else { 1166 mac->autoneg_failed = FALSE; 1167 DEBUGOUT("Valid Link Found\n"); 1168 } 1169 1170 return E1000_SUCCESS; 1171 } 1172 1173 /** 1174 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 1175 * @hw: pointer to the HW structure 1176 * 1177 * Configures collision distance and flow control for fiber and serdes 1178 * links. Upon successful setup, poll for link. 1179 **/ 1180 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 1181 { 1182 u32 ctrl; 1183 s32 ret_val; 1184 1185 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 1186 1187 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1188 1189 /* Take the link out of reset */ 1190 ctrl &= ~E1000_CTRL_LRST; 1191 1192 hw->mac.ops.config_collision_dist(hw); 1193 1194 ret_val = e1000_commit_fc_settings_generic(hw); 1195 if (ret_val) 1196 return ret_val; 1197 1198 /* Since auto-negotiation is enabled, take the link out of reset (the 1199 * link will be in reset, because we previously reset the chip). This 1200 * will restart auto-negotiation. If auto-negotiation is successful 1201 * then the link-up status bit will be set and the flow control enable 1202 * bits (RFCE and TFCE) will be set according to their negotiated value. 1203 */ 1204 DEBUGOUT("Auto-negotiation enabled\n"); 1205 1206 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1207 E1000_WRITE_FLUSH(hw); 1208 msec_delay(1); 1209 1210 /* For these adapters, the SW definable pin 1 is set when the optics 1211 * detect a signal. If we have a signal, then poll for a "Link-Up" 1212 * indication. 1213 */ 1214 if (hw->phy.media_type == e1000_media_type_internal_serdes || 1215 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1216 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1217 } else { 1218 DEBUGOUT("No signal detected\n"); 1219 } 1220 1221 return ret_val; 1222 } 1223 1224 /** 1225 * e1000_config_collision_dist_generic - Configure collision distance 1226 * @hw: pointer to the HW structure 1227 * 1228 * Configures the collision distance to the default value and is used 1229 * during link setup. 1230 **/ 1231 static void e1000_config_collision_dist_generic(struct e1000_hw *hw) 1232 { 1233 u32 tctl; 1234 1235 DEBUGFUNC("e1000_config_collision_dist_generic"); 1236 1237 tctl = E1000_READ_REG(hw, E1000_TCTL); 1238 1239 tctl &= ~E1000_TCTL_COLD; 1240 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1241 1242 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 1243 E1000_WRITE_FLUSH(hw); 1244 } 1245 1246 /** 1247 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 1248 * @hw: pointer to the HW structure 1249 * 1250 * Sets the flow control high/low threshold (watermark) registers. If 1251 * flow control XON frame transmission is enabled, then set XON frame 1252 * transmission as well. 1253 **/ 1254 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 1255 { 1256 u32 fcrtl = 0, fcrth = 0; 1257 1258 DEBUGFUNC("e1000_set_fc_watermarks_generic"); 1259 1260 /* Set the flow control receive threshold registers. Normally, 1261 * these registers will be set to a default threshold that may be 1262 * adjusted later by the driver's runtime code. However, if the 1263 * ability to transmit pause frames is not enabled, then these 1264 * registers will be set to 0. 1265 */ 1266 if (hw->fc.current_mode & e1000_fc_tx_pause) { 1267 /* We need to set up the Receive Threshold high and low water 1268 * marks as well as (optionally) enabling the transmission of 1269 * XON frames. 1270 */ 1271 fcrtl = hw->fc.low_water; 1272 if (hw->fc.send_xon) 1273 fcrtl |= E1000_FCRTL_XONE; 1274 1275 fcrth = hw->fc.high_water; 1276 } 1277 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 1278 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 1279 1280 return E1000_SUCCESS; 1281 } 1282 1283 /** 1284 * e1000_force_mac_fc_generic - Force the MAC's flow control settings 1285 * @hw: pointer to the HW structure 1286 * 1287 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 1288 * device control register to reflect the adapter settings. TFCE and RFCE 1289 * need to be explicitly set by software when a copper PHY is used because 1290 * autonegotiation is managed by the PHY rather than the MAC. Software must 1291 * also configure these bits when link is forced on a fiber connection. 1292 **/ 1293 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw) 1294 { 1295 u32 ctrl; 1296 1297 DEBUGFUNC("e1000_force_mac_fc_generic"); 1298 1299 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1300 1301 /* Because we didn't get link via the internal auto-negotiation 1302 * mechanism (we either forced link or we got link via PHY 1303 * auto-neg), we have to manually enable/disable transmit an 1304 * receive flow control. 1305 * 1306 * The "Case" statement below enables/disable flow control 1307 * according to the "hw->fc.current_mode" parameter. 1308 * 1309 * The possible values of the "fc" parameter are: 1310 * 0: Flow control is completely disabled 1311 * 1: Rx flow control is enabled (we can receive pause 1312 * frames but not send pause frames). 1313 * 2: Tx flow control is enabled (we can send pause frames 1314 * frames but we do not receive pause frames). 1315 * 3: Both Rx and Tx flow control (symmetric) is enabled. 1316 * other: No other values should be possible at this point. 1317 */ 1318 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); 1319 1320 switch (hw->fc.current_mode) { 1321 case e1000_fc_none: 1322 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1323 break; 1324 case e1000_fc_rx_pause: 1325 ctrl &= (~E1000_CTRL_TFCE); 1326 ctrl |= E1000_CTRL_RFCE; 1327 break; 1328 case e1000_fc_tx_pause: 1329 ctrl &= (~E1000_CTRL_RFCE); 1330 ctrl |= E1000_CTRL_TFCE; 1331 break; 1332 case e1000_fc_full: 1333 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1334 break; 1335 default: 1336 DEBUGOUT("Flow control param set incorrectly\n"); 1337 return -E1000_ERR_CONFIG; 1338 } 1339 1340 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1341 1342 return E1000_SUCCESS; 1343 } 1344 1345 /** 1346 * e1000_config_fc_after_link_up_generic - Configures flow control after link 1347 * @hw: pointer to the HW structure 1348 * 1349 * Checks the status of auto-negotiation after link up to ensure that the 1350 * speed and duplex were not forced. If the link needed to be forced, then 1351 * flow control needs to be forced also. If auto-negotiation is enabled 1352 * and did not fail, then we configure flow control based on our link 1353 * partner. 1354 **/ 1355 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 1356 { 1357 struct e1000_mac_info *mac = &hw->mac; 1358 s32 ret_val = E1000_SUCCESS; 1359 u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg; 1360 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1361 u16 speed, duplex; 1362 1363 DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 1364 1365 /* Check for the case where we have fiber media and auto-neg failed 1366 * so we had to force link. In this case, we need to force the 1367 * configuration of the MAC to match the "fc" parameter. 1368 */ 1369 if (mac->autoneg_failed) { 1370 if (hw->phy.media_type == e1000_media_type_fiber || 1371 hw->phy.media_type == e1000_media_type_internal_serdes) 1372 ret_val = e1000_force_mac_fc_generic(hw); 1373 } else { 1374 if (hw->phy.media_type == e1000_media_type_copper) 1375 ret_val = e1000_force_mac_fc_generic(hw); 1376 } 1377 1378 if (ret_val) { 1379 DEBUGOUT("Error forcing flow control settings\n"); 1380 return ret_val; 1381 } 1382 1383 /* Check for the case where we have copper media and auto-neg is 1384 * enabled. In this case, we need to check and see if Auto-Neg 1385 * has completed, and if so, how the PHY and link partner has 1386 * flow control configured. 1387 */ 1388 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1389 /* Read the MII Status Register and check to see if AutoNeg 1390 * has completed. We read this twice because this reg has 1391 * some "sticky" (latched) bits. 1392 */ 1393 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1394 if (ret_val) 1395 return ret_val; 1396 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1397 if (ret_val) 1398 return ret_val; 1399 1400 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1401 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n"); 1402 return ret_val; 1403 } 1404 1405 /* The AutoNeg process has completed, so we now need to 1406 * read both the Auto Negotiation Advertisement 1407 * Register (Address 4) and the Auto_Negotiation Base 1408 * Page Ability Register (Address 5) to determine how 1409 * flow control was negotiated. 1410 */ 1411 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 1412 &mii_nway_adv_reg); 1413 if (ret_val) 1414 return ret_val; 1415 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 1416 &mii_nway_lp_ability_reg); 1417 if (ret_val) 1418 return ret_val; 1419 1420 /* Two bits in the Auto Negotiation Advertisement Register 1421 * (Address 4) and two bits in the Auto Negotiation Base 1422 * Page Ability Register (Address 5) determine flow control 1423 * for both the PHY and the link partner. The following 1424 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1425 * 1999, describes these PAUSE resolution bits and how flow 1426 * control is determined based upon these settings. 1427 * NOTE: DC = Don't Care 1428 * 1429 * LOCAL DEVICE | LINK PARTNER 1430 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1431 *-------|---------|-------|---------|-------------------- 1432 * 0 | 0 | DC | DC | e1000_fc_none 1433 * 0 | 1 | 0 | DC | e1000_fc_none 1434 * 0 | 1 | 1 | 0 | e1000_fc_none 1435 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1436 * 1 | 0 | 0 | DC | e1000_fc_none 1437 * 1 | DC | 1 | DC | e1000_fc_full 1438 * 1 | 1 | 0 | 0 | e1000_fc_none 1439 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1440 * 1441 * Are both PAUSE bits set to 1? If so, this implies 1442 * Symmetric Flow Control is enabled at both ends. The 1443 * ASM_DIR bits are irrelevant per the spec. 1444 * 1445 * For Symmetric Flow Control: 1446 * 1447 * LOCAL DEVICE | LINK PARTNER 1448 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1449 *-------|---------|-------|---------|-------------------- 1450 * 1 | DC | 1 | DC | E1000_fc_full 1451 * 1452 */ 1453 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1454 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1455 /* Now we need to check if the user selected Rx ONLY 1456 * of pause frames. In this case, we had to advertise 1457 * FULL flow control because we could not advertise Rx 1458 * ONLY. Hence, we must now check to see if we need to 1459 * turn OFF the TRANSMISSION of PAUSE frames. 1460 */ 1461 if (hw->fc.requested_mode == e1000_fc_full) { 1462 hw->fc.current_mode = e1000_fc_full; 1463 DEBUGOUT("Flow Control = FULL.\n"); 1464 } else { 1465 hw->fc.current_mode = e1000_fc_rx_pause; 1466 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1467 } 1468 } 1469 /* For receiving PAUSE frames ONLY. 1470 * 1471 * LOCAL DEVICE | LINK PARTNER 1472 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1473 *-------|---------|-------|---------|-------------------- 1474 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1475 */ 1476 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1477 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1478 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1479 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1480 hw->fc.current_mode = e1000_fc_tx_pause; 1481 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); 1482 } 1483 /* For transmitting PAUSE frames ONLY. 1484 * 1485 * LOCAL DEVICE | LINK PARTNER 1486 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1487 *-------|---------|-------|---------|-------------------- 1488 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1489 */ 1490 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1491 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1492 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1493 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1494 hw->fc.current_mode = e1000_fc_rx_pause; 1495 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1496 } else { 1497 /* Per the IEEE spec, at this point flow control 1498 * should be disabled. 1499 */ 1500 hw->fc.current_mode = e1000_fc_none; 1501 DEBUGOUT("Flow Control = NONE.\n"); 1502 } 1503 1504 /* Now we need to do one last check... If we auto- 1505 * negotiated to HALF DUPLEX, flow control should not be 1506 * enabled per IEEE 802.3 spec. 1507 */ 1508 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1509 if (ret_val) { 1510 DEBUGOUT("Error getting link speed and duplex\n"); 1511 return ret_val; 1512 } 1513 1514 if (duplex == HALF_DUPLEX) 1515 hw->fc.current_mode = e1000_fc_none; 1516 1517 /* Now we call a subroutine to actually force the MAC 1518 * controller to use the correct flow control settings. 1519 */ 1520 ret_val = e1000_force_mac_fc_generic(hw); 1521 if (ret_val) { 1522 DEBUGOUT("Error forcing flow control settings\n"); 1523 return ret_val; 1524 } 1525 } 1526 1527 /* Check for the case where we have SerDes media and auto-neg is 1528 * enabled. In this case, we need to check and see if Auto-Neg 1529 * has completed, and if so, how the PHY and link partner has 1530 * flow control configured. 1531 */ 1532 if ((hw->phy.media_type == e1000_media_type_internal_serdes) && 1533 mac->autoneg) { 1534 /* Read the PCS_LSTS and check to see if AutoNeg 1535 * has completed. 1536 */ 1537 pcs_status_reg = E1000_READ_REG(hw, E1000_PCS_LSTAT); 1538 1539 if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) { 1540 DEBUGOUT("PCS Auto Neg has not completed.\n"); 1541 return ret_val; 1542 } 1543 1544 /* The AutoNeg process has completed, so we now need to 1545 * read both the Auto Negotiation Advertisement 1546 * Register (PCS_ANADV) and the Auto_Negotiation Base 1547 * Page Ability Register (PCS_LPAB) to determine how 1548 * flow control was negotiated. 1549 */ 1550 pcs_adv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV); 1551 pcs_lp_ability_reg = E1000_READ_REG(hw, E1000_PCS_LPAB); 1552 1553 /* Two bits in the Auto Negotiation Advertisement Register 1554 * (PCS_ANADV) and two bits in the Auto Negotiation Base 1555 * Page Ability Register (PCS_LPAB) determine flow control 1556 * for both the PHY and the link partner. The following 1557 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1558 * 1999, describes these PAUSE resolution bits and how flow 1559 * control is determined based upon these settings. 1560 * NOTE: DC = Don't Care 1561 * 1562 * LOCAL DEVICE | LINK PARTNER 1563 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1564 *-------|---------|-------|---------|-------------------- 1565 * 0 | 0 | DC | DC | e1000_fc_none 1566 * 0 | 1 | 0 | DC | e1000_fc_none 1567 * 0 | 1 | 1 | 0 | e1000_fc_none 1568 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1569 * 1 | 0 | 0 | DC | e1000_fc_none 1570 * 1 | DC | 1 | DC | e1000_fc_full 1571 * 1 | 1 | 0 | 0 | e1000_fc_none 1572 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1573 * 1574 * Are both PAUSE bits set to 1? If so, this implies 1575 * Symmetric Flow Control is enabled at both ends. The 1576 * ASM_DIR bits are irrelevant per the spec. 1577 * 1578 * For Symmetric Flow Control: 1579 * 1580 * LOCAL DEVICE | LINK PARTNER 1581 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1582 *-------|---------|-------|---------|-------------------- 1583 * 1 | DC | 1 | DC | e1000_fc_full 1584 * 1585 */ 1586 if ((pcs_adv_reg & E1000_TXCW_PAUSE) && 1587 (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) { 1588 /* Now we need to check if the user selected Rx ONLY 1589 * of pause frames. In this case, we had to advertise 1590 * FULL flow control because we could not advertise Rx 1591 * ONLY. Hence, we must now check to see if we need to 1592 * turn OFF the TRANSMISSION of PAUSE frames. 1593 */ 1594 if (hw->fc.requested_mode == e1000_fc_full) { 1595 hw->fc.current_mode = e1000_fc_full; 1596 DEBUGOUT("Flow Control = FULL.\n"); 1597 } else { 1598 hw->fc.current_mode = e1000_fc_rx_pause; 1599 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1600 } 1601 } 1602 /* For receiving PAUSE frames ONLY. 1603 * 1604 * LOCAL DEVICE | LINK PARTNER 1605 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1606 *-------|---------|-------|---------|-------------------- 1607 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1608 */ 1609 else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) && 1610 (pcs_adv_reg & E1000_TXCW_ASM_DIR) && 1611 (pcs_lp_ability_reg & E1000_TXCW_PAUSE) && 1612 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { 1613 hw->fc.current_mode = e1000_fc_tx_pause; 1614 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); 1615 } 1616 /* For transmitting PAUSE frames ONLY. 1617 * 1618 * LOCAL DEVICE | LINK PARTNER 1619 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1620 *-------|---------|-------|---------|-------------------- 1621 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1622 */ 1623 else if ((pcs_adv_reg & E1000_TXCW_PAUSE) && 1624 (pcs_adv_reg & E1000_TXCW_ASM_DIR) && 1625 !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) && 1626 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { 1627 hw->fc.current_mode = e1000_fc_rx_pause; 1628 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1629 } else { 1630 /* Per the IEEE spec, at this point flow control 1631 * should be disabled. 1632 */ 1633 hw->fc.current_mode = e1000_fc_none; 1634 DEBUGOUT("Flow Control = NONE.\n"); 1635 } 1636 1637 /* Now we call a subroutine to actually force the MAC 1638 * controller to use the correct flow control settings. 1639 */ 1640 pcs_ctrl_reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 1641 pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1642 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_ctrl_reg); 1643 1644 ret_val = e1000_force_mac_fc_generic(hw); 1645 if (ret_val) { 1646 DEBUGOUT("Error forcing flow control settings\n"); 1647 return ret_val; 1648 } 1649 } 1650 1651 return E1000_SUCCESS; 1652 } 1653 1654 /** 1655 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 1656 * @hw: pointer to the HW structure 1657 * @speed: stores the current speed 1658 * @duplex: stores the current duplex 1659 * 1660 * Read the status register for the current speed/duplex and store the current 1661 * speed and duplex for copper connections. 1662 **/ 1663 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 1664 u16 *duplex) 1665 { 1666 u32 status; 1667 1668 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 1669 1670 status = E1000_READ_REG(hw, E1000_STATUS); 1671 if (status & E1000_STATUS_SPEED_1000) { 1672 *speed = SPEED_1000; 1673 DEBUGOUT("1000 Mbs, "); 1674 } else if (status & E1000_STATUS_SPEED_100) { 1675 *speed = SPEED_100; 1676 DEBUGOUT("100 Mbs, "); 1677 } else { 1678 *speed = SPEED_10; 1679 DEBUGOUT("10 Mbs, "); 1680 } 1681 1682 if (status & E1000_STATUS_FD) { 1683 *duplex = FULL_DUPLEX; 1684 DEBUGOUT("Full Duplex\n"); 1685 } else { 1686 *duplex = HALF_DUPLEX; 1687 DEBUGOUT("Half Duplex\n"); 1688 } 1689 1690 return E1000_SUCCESS; 1691 } 1692 1693 /** 1694 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex 1695 * @hw: pointer to the HW structure 1696 * @speed: stores the current speed 1697 * @duplex: stores the current duplex 1698 * 1699 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1700 * for fiber/serdes links. 1701 **/ 1702 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw E1000_UNUSEDARG *hw, 1703 u16 *speed, u16 *duplex) 1704 { 1705 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 1706 1707 *speed = SPEED_1000; 1708 *duplex = FULL_DUPLEX; 1709 1710 return E1000_SUCCESS; 1711 } 1712 1713 /** 1714 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 1715 * @hw: pointer to the HW structure 1716 * 1717 * Acquire the HW semaphore to access the PHY or NVM 1718 **/ 1719 s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 1720 { 1721 u32 swsm; 1722 s32 timeout = hw->nvm.word_size + 1; 1723 s32 i = 0; 1724 1725 DEBUGFUNC("e1000_get_hw_semaphore_generic"); 1726 1727 /* Get the SW semaphore */ 1728 while (i < timeout) { 1729 swsm = E1000_READ_REG(hw, E1000_SWSM); 1730 if (!(swsm & E1000_SWSM_SMBI)) 1731 break; 1732 1733 usec_delay(50); 1734 i++; 1735 } 1736 1737 if (i == timeout) { 1738 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1739 return -E1000_ERR_NVM; 1740 } 1741 1742 /* Get the FW semaphore. */ 1743 for (i = 0; i < timeout; i++) { 1744 swsm = E1000_READ_REG(hw, E1000_SWSM); 1745 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 1746 1747 /* Semaphore acquired if bit latched */ 1748 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 1749 break; 1750 1751 usec_delay(50); 1752 } 1753 1754 if (i == timeout) { 1755 /* Release semaphores */ 1756 e1000_put_hw_semaphore_generic(hw); 1757 DEBUGOUT("Driver can't access the NVM\n"); 1758 return -E1000_ERR_NVM; 1759 } 1760 1761 return E1000_SUCCESS; 1762 } 1763 1764 /** 1765 * e1000_put_hw_semaphore_generic - Release hardware semaphore 1766 * @hw: pointer to the HW structure 1767 * 1768 * Release hardware semaphore used to access the PHY or NVM 1769 **/ 1770 void e1000_put_hw_semaphore_generic(struct e1000_hw *hw) 1771 { 1772 u32 swsm; 1773 1774 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 1775 1776 swsm = E1000_READ_REG(hw, E1000_SWSM); 1777 1778 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1779 1780 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 1781 } 1782 1783 /** 1784 * e1000_get_auto_rd_done_generic - Check for auto read completion 1785 * @hw: pointer to the HW structure 1786 * 1787 * Check EEPROM for Auto Read done bit. 1788 **/ 1789 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 1790 { 1791 s32 i = 0; 1792 1793 DEBUGFUNC("e1000_get_auto_rd_done_generic"); 1794 1795 while (i < AUTO_READ_DONE_TIMEOUT) { 1796 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 1797 break; 1798 msec_delay(1); 1799 i++; 1800 } 1801 1802 if (i == AUTO_READ_DONE_TIMEOUT) { 1803 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1804 return -E1000_ERR_RESET; 1805 } 1806 1807 return E1000_SUCCESS; 1808 } 1809 1810 /** 1811 * e1000_valid_led_default_generic - Verify a valid default LED config 1812 * @hw: pointer to the HW structure 1813 * @data: pointer to the NVM (EEPROM) 1814 * 1815 * Read the EEPROM for the current default LED configuration. If the 1816 * LED configuration is not valid, set to a valid LED configuration. 1817 **/ 1818 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 1819 { 1820 s32 ret_val; 1821 1822 DEBUGFUNC("e1000_valid_led_default_generic"); 1823 1824 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1825 if (ret_val) { 1826 DEBUGOUT("NVM Read Error\n"); 1827 return ret_val; 1828 } 1829 1830 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1831 *data = ID_LED_DEFAULT; 1832 1833 return E1000_SUCCESS; 1834 } 1835 1836 /** 1837 * e1000_id_led_init_generic - 1838 * @hw: pointer to the HW structure 1839 * 1840 **/ 1841 s32 e1000_id_led_init_generic(struct e1000_hw *hw) 1842 { 1843 struct e1000_mac_info *mac = &hw->mac; 1844 s32 ret_val; 1845 const u32 ledctl_mask = 0x000000FF; 1846 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1847 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1848 u16 data, i, temp; 1849 const u16 led_mask = 0x0F; 1850 1851 DEBUGFUNC("e1000_id_led_init_generic"); 1852 1853 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 1854 if (ret_val) 1855 return ret_val; 1856 1857 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 1858 mac->ledctl_mode1 = mac->ledctl_default; 1859 mac->ledctl_mode2 = mac->ledctl_default; 1860 1861 for (i = 0; i < 4; i++) { 1862 temp = (data >> (i << 2)) & led_mask; 1863 switch (temp) { 1864 case ID_LED_ON1_DEF2: 1865 case ID_LED_ON1_ON2: 1866 case ID_LED_ON1_OFF2: 1867 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1868 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1869 break; 1870 case ID_LED_OFF1_DEF2: 1871 case ID_LED_OFF1_ON2: 1872 case ID_LED_OFF1_OFF2: 1873 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1874 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1875 break; 1876 default: 1877 /* Do nothing */ 1878 break; 1879 } 1880 switch (temp) { 1881 case ID_LED_DEF1_ON2: 1882 case ID_LED_ON1_ON2: 1883 case ID_LED_OFF1_ON2: 1884 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1885 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1886 break; 1887 case ID_LED_DEF1_OFF2: 1888 case ID_LED_ON1_OFF2: 1889 case ID_LED_OFF1_OFF2: 1890 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1891 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1892 break; 1893 default: 1894 /* Do nothing */ 1895 break; 1896 } 1897 } 1898 1899 return E1000_SUCCESS; 1900 } 1901 1902 /** 1903 * e1000_setup_led_generic - Configures SW controllable LED 1904 * @hw: pointer to the HW structure 1905 * 1906 * This prepares the SW controllable LED for use and saves the current state 1907 * of the LED so it can be later restored. 1908 **/ 1909 s32 e1000_setup_led_generic(struct e1000_hw *hw) 1910 { 1911 u32 ledctl; 1912 1913 DEBUGFUNC("e1000_setup_led_generic"); 1914 1915 if (hw->mac.ops.setup_led != e1000_setup_led_generic) 1916 return -E1000_ERR_CONFIG; 1917 1918 if (hw->phy.media_type == e1000_media_type_fiber) { 1919 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 1920 hw->mac.ledctl_default = ledctl; 1921 /* Turn off LED0 */ 1922 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK | 1923 E1000_LEDCTL_LED0_MODE_MASK); 1924 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1925 E1000_LEDCTL_LED0_MODE_SHIFT); 1926 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 1927 } else if (hw->phy.media_type == e1000_media_type_copper) { 1928 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1929 } 1930 1931 return E1000_SUCCESS; 1932 } 1933 1934 /** 1935 * e1000_cleanup_led_generic - Set LED config to default operation 1936 * @hw: pointer to the HW structure 1937 * 1938 * Remove the current LED configuration and set the LED configuration 1939 * to the default value, saved from the EEPROM. 1940 **/ 1941 s32 e1000_cleanup_led_generic(struct e1000_hw *hw) 1942 { 1943 DEBUGFUNC("e1000_cleanup_led_generic"); 1944 1945 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1946 return E1000_SUCCESS; 1947 } 1948 1949 /** 1950 * e1000_blink_led_generic - Blink LED 1951 * @hw: pointer to the HW structure 1952 * 1953 * Blink the LEDs which are set to be on. 1954 **/ 1955 s32 e1000_blink_led_generic(struct e1000_hw *hw) 1956 { 1957 u32 ledctl_blink = 0; 1958 u32 i; 1959 1960 DEBUGFUNC("e1000_blink_led_generic"); 1961 1962 if (hw->phy.media_type == e1000_media_type_fiber) { 1963 /* always blink LED0 for PCI-E fiber */ 1964 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1965 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1966 } else { 1967 /* Set the blink bit for each LED that's "on" (0x0E) 1968 * (or "off" if inverted) in ledctl_mode2. The blink 1969 * logic in hardware only works when mode is set to "on" 1970 * so it must be changed accordingly when the mode is 1971 * "off" and inverted. 1972 */ 1973 ledctl_blink = hw->mac.ledctl_mode2; 1974 for (i = 0; i < 32; i += 8) { 1975 u32 mode = (hw->mac.ledctl_mode2 >> i) & 1976 E1000_LEDCTL_LED0_MODE_MASK; 1977 u32 led_default = hw->mac.ledctl_default >> i; 1978 1979 if ((!(led_default & E1000_LEDCTL_LED0_IVRT) && 1980 (mode == E1000_LEDCTL_MODE_LED_ON)) || 1981 ((led_default & E1000_LEDCTL_LED0_IVRT) && 1982 (mode == E1000_LEDCTL_MODE_LED_OFF))) { 1983 ledctl_blink &= 1984 ~(E1000_LEDCTL_LED0_MODE_MASK << i); 1985 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK | 1986 E1000_LEDCTL_MODE_LED_ON) << i; 1987 } 1988 } 1989 } 1990 1991 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 1992 1993 return E1000_SUCCESS; 1994 } 1995 1996 /** 1997 * e1000_led_on_generic - Turn LED on 1998 * @hw: pointer to the HW structure 1999 * 2000 * Turn LED on. 2001 **/ 2002 s32 e1000_led_on_generic(struct e1000_hw *hw) 2003 { 2004 u32 ctrl; 2005 2006 DEBUGFUNC("e1000_led_on_generic"); 2007 2008 switch (hw->phy.media_type) { 2009 case e1000_media_type_fiber: 2010 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2011 ctrl &= ~E1000_CTRL_SWDPIN0; 2012 ctrl |= E1000_CTRL_SWDPIO0; 2013 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2014 break; 2015 case e1000_media_type_copper: 2016 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 2017 break; 2018 default: 2019 break; 2020 } 2021 2022 return E1000_SUCCESS; 2023 } 2024 2025 /** 2026 * e1000_led_off_generic - Turn LED off 2027 * @hw: pointer to the HW structure 2028 * 2029 * Turn LED off. 2030 **/ 2031 s32 e1000_led_off_generic(struct e1000_hw *hw) 2032 { 2033 u32 ctrl; 2034 2035 DEBUGFUNC("e1000_led_off_generic"); 2036 2037 switch (hw->phy.media_type) { 2038 case e1000_media_type_fiber: 2039 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2040 ctrl |= E1000_CTRL_SWDPIN0; 2041 ctrl |= E1000_CTRL_SWDPIO0; 2042 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2043 break; 2044 case e1000_media_type_copper: 2045 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 2046 break; 2047 default: 2048 break; 2049 } 2050 2051 return E1000_SUCCESS; 2052 } 2053 2054 /** 2055 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 2056 * @hw: pointer to the HW structure 2057 * @no_snoop: bitmap of snoop events 2058 * 2059 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 2060 **/ 2061 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 2062 { 2063 u32 gcr; 2064 2065 DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 2066 2067 if (hw->bus.type != e1000_bus_type_pci_express) 2068 return; 2069 2070 if (no_snoop) { 2071 gcr = E1000_READ_REG(hw, E1000_GCR); 2072 gcr &= ~(PCIE_NO_SNOOP_ALL); 2073 gcr |= no_snoop; 2074 E1000_WRITE_REG(hw, E1000_GCR, gcr); 2075 } 2076 } 2077 2078 /** 2079 * e1000_disable_pcie_master_generic - Disables PCI-express master access 2080 * @hw: pointer to the HW structure 2081 * 2082 * Returns E1000_SUCCESS if successful, else returns -10 2083 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 2084 * the master requests to be disabled. 2085 * 2086 * Disables PCI-Express master access and verifies there are no pending 2087 * requests. 2088 **/ 2089 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw) 2090 { 2091 u32 ctrl; 2092 s32 timeout = MASTER_DISABLE_TIMEOUT; 2093 2094 DEBUGFUNC("e1000_disable_pcie_master_generic"); 2095 2096 if (hw->bus.type != e1000_bus_type_pci_express) 2097 return E1000_SUCCESS; 2098 2099 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2100 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 2101 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2102 2103 while (timeout) { 2104 if (!(E1000_READ_REG(hw, E1000_STATUS) & 2105 E1000_STATUS_GIO_MASTER_ENABLE) || 2106 E1000_REMOVED(hw->hw_addr)) 2107 break; 2108 usec_delay(100); 2109 timeout--; 2110 } 2111 2112 if (!timeout) { 2113 DEBUGOUT("Master requests are pending.\n"); 2114 return -E1000_ERR_MASTER_REQUESTS_PENDING; 2115 } 2116 2117 return E1000_SUCCESS; 2118 } 2119 2120 /** 2121 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 2122 * @hw: pointer to the HW structure 2123 * 2124 * Reset the Adaptive Interframe Spacing throttle to default values. 2125 **/ 2126 void e1000_reset_adaptive_generic(struct e1000_hw *hw) 2127 { 2128 struct e1000_mac_info *mac = &hw->mac; 2129 2130 DEBUGFUNC("e1000_reset_adaptive_generic"); 2131 2132 if (!mac->adaptive_ifs) { 2133 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2134 return; 2135 } 2136 2137 mac->current_ifs_val = 0; 2138 mac->ifs_min_val = IFS_MIN; 2139 mac->ifs_max_val = IFS_MAX; 2140 mac->ifs_step_size = IFS_STEP; 2141 mac->ifs_ratio = IFS_RATIO; 2142 2143 mac->in_ifs_mode = FALSE; 2144 E1000_WRITE_REG(hw, E1000_AIT, 0); 2145 } 2146 2147 /** 2148 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 2149 * @hw: pointer to the HW structure 2150 * 2151 * Update the Adaptive Interframe Spacing Throttle value based on the 2152 * time between transmitted packets and time between collisions. 2153 **/ 2154 void e1000_update_adaptive_generic(struct e1000_hw *hw) 2155 { 2156 struct e1000_mac_info *mac = &hw->mac; 2157 2158 DEBUGFUNC("e1000_update_adaptive_generic"); 2159 2160 if (!mac->adaptive_ifs) { 2161 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2162 return; 2163 } 2164 2165 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 2166 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 2167 mac->in_ifs_mode = TRUE; 2168 if (mac->current_ifs_val < mac->ifs_max_val) { 2169 if (!mac->current_ifs_val) 2170 mac->current_ifs_val = mac->ifs_min_val; 2171 else 2172 mac->current_ifs_val += 2173 mac->ifs_step_size; 2174 E1000_WRITE_REG(hw, E1000_AIT, 2175 mac->current_ifs_val); 2176 } 2177 } 2178 } else { 2179 if (mac->in_ifs_mode && 2180 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 2181 mac->current_ifs_val = 0; 2182 mac->in_ifs_mode = FALSE; 2183 E1000_WRITE_REG(hw, E1000_AIT, 0); 2184 } 2185 } 2186 } 2187 2188 /** 2189 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 2190 * @hw: pointer to the HW structure 2191 * 2192 * Verify that when not using auto-negotiation that MDI/MDIx is correctly 2193 * set, which is forced to MDI mode only. 2194 **/ 2195 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 2196 { 2197 DEBUGFUNC("e1000_validate_mdi_setting_generic"); 2198 2199 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 2200 DEBUGOUT("Invalid MDI setting detected\n"); 2201 hw->phy.mdix = 1; 2202 return -E1000_ERR_CONFIG; 2203 } 2204 2205 return E1000_SUCCESS; 2206 } 2207 2208 /** 2209 * e1000_validate_mdi_setting_crossover_generic - Verify MDI/MDIx settings 2210 * @hw: pointer to the HW structure 2211 * 2212 * Validate the MDI/MDIx setting, allowing for auto-crossover during forced 2213 * operation. 2214 **/ 2215 s32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw E1000_UNUSEDARG *hw) 2216 { 2217 DEBUGFUNC("e1000_validate_mdi_setting_crossover_generic"); 2218 2219 return E1000_SUCCESS; 2220 } 2221 2222 /** 2223 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register 2224 * @hw: pointer to the HW structure 2225 * @reg: 32bit register offset such as E1000_SCTL 2226 * @offset: register offset to write to 2227 * @data: data to write at register offset 2228 * 2229 * Writes an address/data control type register. There are several of these 2230 * and they all have the format address << 8 | data and bit 31 is polled for 2231 * completion. 2232 **/ 2233 s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, 2234 u32 offset, u8 data) 2235 { 2236 u32 i, regvalue = 0; 2237 2238 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); 2239 2240 /* Set up the address and data */ 2241 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 2242 E1000_WRITE_REG(hw, reg, regvalue); 2243 2244 /* Poll the ready bit to see if the MDI read completed */ 2245 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 2246 usec_delay(5); 2247 regvalue = E1000_READ_REG(hw, reg); 2248 if (regvalue & E1000_GEN_CTL_READY) 2249 break; 2250 } 2251 if (!(regvalue & E1000_GEN_CTL_READY)) { 2252 DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 2253 return -E1000_ERR_PHY; 2254 } 2255 2256 return E1000_SUCCESS; 2257 } 2258