1 /****************************************************************************** 2 3 Copyright (c) 2001-2012, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD:$*/ 34 35 #include "e1000_api.h" 36 37 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw); 38 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); 39 static void e1000_config_collision_dist_generic(struct e1000_hw *hw); 40 static void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index); 41 42 /** 43 * e1000_init_mac_ops_generic - Initialize MAC function pointers 44 * @hw: pointer to the HW structure 45 * 46 * Setups up the function pointers to no-op functions 47 **/ 48 void e1000_init_mac_ops_generic(struct e1000_hw *hw) 49 { 50 struct e1000_mac_info *mac = &hw->mac; 51 DEBUGFUNC("e1000_init_mac_ops_generic"); 52 53 /* General Setup */ 54 mac->ops.init_params = e1000_null_ops_generic; 55 mac->ops.init_hw = e1000_null_ops_generic; 56 mac->ops.reset_hw = e1000_null_ops_generic; 57 mac->ops.setup_physical_interface = e1000_null_ops_generic; 58 mac->ops.get_bus_info = e1000_null_ops_generic; 59 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie; 60 mac->ops.read_mac_addr = e1000_read_mac_addr_generic; 61 mac->ops.config_collision_dist = e1000_config_collision_dist_generic; 62 mac->ops.clear_hw_cntrs = e1000_null_mac_generic; 63 /* LED */ 64 mac->ops.cleanup_led = e1000_null_ops_generic; 65 mac->ops.setup_led = e1000_null_ops_generic; 66 mac->ops.blink_led = e1000_null_ops_generic; 67 mac->ops.led_on = e1000_null_ops_generic; 68 mac->ops.led_off = e1000_null_ops_generic; 69 /* LINK */ 70 mac->ops.setup_link = e1000_null_ops_generic; 71 mac->ops.get_link_up_info = e1000_null_link_info; 72 mac->ops.check_for_link = e1000_null_ops_generic; 73 mac->ops.set_obff_timer = e1000_null_set_obff_timer; 74 /* Management */ 75 mac->ops.check_mng_mode = e1000_null_mng_mode; 76 /* VLAN, MC, etc. */ 77 mac->ops.update_mc_addr_list = e1000_null_update_mc; 78 mac->ops.clear_vfta = e1000_null_mac_generic; 79 mac->ops.write_vfta = e1000_null_write_vfta; 80 mac->ops.rar_set = e1000_rar_set_generic; 81 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; 82 } 83 84 /** 85 * e1000_null_ops_generic - No-op function, returns 0 86 * @hw: pointer to the HW structure 87 **/ 88 s32 e1000_null_ops_generic(struct e1000_hw E1000_UNUSEDARG *hw) 89 { 90 DEBUGFUNC("e1000_null_ops_generic"); 91 return E1000_SUCCESS; 92 } 93 94 /** 95 * e1000_null_mac_generic - No-op function, return void 96 * @hw: pointer to the HW structure 97 **/ 98 void e1000_null_mac_generic(struct e1000_hw E1000_UNUSEDARG *hw) 99 { 100 DEBUGFUNC("e1000_null_mac_generic"); 101 return; 102 } 103 104 /** 105 * e1000_null_link_info - No-op function, return 0 106 * @hw: pointer to the HW structure 107 **/ 108 s32 e1000_null_link_info(struct e1000_hw E1000_UNUSEDARG *hw, 109 u16 E1000_UNUSEDARG *s, u16 E1000_UNUSEDARG *d) 110 { 111 DEBUGFUNC("e1000_null_link_info"); 112 return E1000_SUCCESS; 113 } 114 115 /** 116 * e1000_null_mng_mode - No-op function, return FALSE 117 * @hw: pointer to the HW structure 118 **/ 119 bool e1000_null_mng_mode(struct e1000_hw E1000_UNUSEDARG *hw) 120 { 121 DEBUGFUNC("e1000_null_mng_mode"); 122 return FALSE; 123 } 124 125 /** 126 * e1000_null_update_mc - No-op function, return void 127 * @hw: pointer to the HW structure 128 **/ 129 void e1000_null_update_mc(struct e1000_hw E1000_UNUSEDARG *hw, 130 u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a) 131 { 132 DEBUGFUNC("e1000_null_update_mc"); 133 return; 134 } 135 136 /** 137 * e1000_null_write_vfta - No-op function, return void 138 * @hw: pointer to the HW structure 139 **/ 140 void e1000_null_write_vfta(struct e1000_hw E1000_UNUSEDARG *hw, 141 u32 E1000_UNUSEDARG a, u32 E1000_UNUSEDARG b) 142 { 143 DEBUGFUNC("e1000_null_write_vfta"); 144 return; 145 } 146 147 /** 148 * e1000_null_rar_set - No-op function, return void 149 * @hw: pointer to the HW structure 150 **/ 151 void e1000_null_rar_set(struct e1000_hw E1000_UNUSEDARG *hw, 152 u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a) 153 { 154 DEBUGFUNC("e1000_null_rar_set"); 155 return; 156 } 157 158 /** 159 * e1000_null_set_obff_timer - No-op function, return 0 160 * @hw: pointer to the HW structure 161 **/ 162 s32 e1000_null_set_obff_timer(struct e1000_hw E1000_UNUSEDARG *hw, 163 u32 E1000_UNUSEDARG a) 164 { 165 DEBUGFUNC("e1000_null_set_obff_timer"); 166 return E1000_SUCCESS; 167 } 168 169 /** 170 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information 171 * @hw: pointer to the HW structure 172 * 173 * Determines and stores the system bus information for a particular 174 * network interface. The following bus information is determined and stored: 175 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function. 176 **/ 177 s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw) 178 { 179 struct e1000_mac_info *mac = &hw->mac; 180 struct e1000_bus_info *bus = &hw->bus; 181 u32 status = E1000_READ_REG(hw, E1000_STATUS); 182 s32 ret_val = E1000_SUCCESS; 183 184 DEBUGFUNC("e1000_get_bus_info_pci_generic"); 185 186 /* PCI or PCI-X? */ 187 bus->type = (status & E1000_STATUS_PCIX_MODE) 188 ? e1000_bus_type_pcix 189 : e1000_bus_type_pci; 190 191 /* Bus speed */ 192 if (bus->type == e1000_bus_type_pci) { 193 bus->speed = (status & E1000_STATUS_PCI66) 194 ? e1000_bus_speed_66 195 : e1000_bus_speed_33; 196 } else { 197 switch (status & E1000_STATUS_PCIX_SPEED) { 198 case E1000_STATUS_PCIX_SPEED_66: 199 bus->speed = e1000_bus_speed_66; 200 break; 201 case E1000_STATUS_PCIX_SPEED_100: 202 bus->speed = e1000_bus_speed_100; 203 break; 204 case E1000_STATUS_PCIX_SPEED_133: 205 bus->speed = e1000_bus_speed_133; 206 break; 207 default: 208 bus->speed = e1000_bus_speed_reserved; 209 break; 210 } 211 } 212 213 /* Bus width */ 214 bus->width = (status & E1000_STATUS_BUS64) 215 ? e1000_bus_width_64 216 : e1000_bus_width_32; 217 218 /* Which PCI(-X) function? */ 219 mac->ops.set_lan_id(hw); 220 221 return ret_val; 222 } 223 224 /** 225 * e1000_get_bus_info_pcie_generic - Get PCIe bus information 226 * @hw: pointer to the HW structure 227 * 228 * Determines and stores the system bus information for a particular 229 * network interface. The following bus information is determined and stored: 230 * bus speed, bus width, type (PCIe), and PCIe function. 231 **/ 232 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 233 { 234 struct e1000_mac_info *mac = &hw->mac; 235 struct e1000_bus_info *bus = &hw->bus; 236 s32 ret_val; 237 u16 pcie_link_status; 238 239 DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 240 241 bus->type = e1000_bus_type_pci_express; 242 243 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS, 244 &pcie_link_status); 245 if (ret_val) { 246 bus->width = e1000_bus_width_unknown; 247 bus->speed = e1000_bus_speed_unknown; 248 } else { 249 switch (pcie_link_status & PCIE_LINK_SPEED_MASK) { 250 case PCIE_LINK_SPEED_2500: 251 bus->speed = e1000_bus_speed_2500; 252 break; 253 case PCIE_LINK_SPEED_5000: 254 bus->speed = e1000_bus_speed_5000; 255 break; 256 default: 257 bus->speed = e1000_bus_speed_unknown; 258 break; 259 } 260 261 bus->width = (enum e1000_bus_width)((pcie_link_status & 262 PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT); 263 } 264 265 mac->ops.set_lan_id(hw); 266 267 return E1000_SUCCESS; 268 } 269 270 /** 271 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 272 * 273 * @hw: pointer to the HW structure 274 * 275 * Determines the LAN function id by reading memory-mapped registers 276 * and swaps the port value if requested. 277 **/ 278 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) 279 { 280 struct e1000_bus_info *bus = &hw->bus; 281 u32 reg; 282 283 /* The status register reports the correct function number 284 * for the device regardless of function swap state. 285 */ 286 reg = E1000_READ_REG(hw, E1000_STATUS); 287 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 288 } 289 290 /** 291 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices 292 * @hw: pointer to the HW structure 293 * 294 * Determines the LAN function id by reading PCI config space. 295 **/ 296 void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw) 297 { 298 struct e1000_bus_info *bus = &hw->bus; 299 u16 pci_header_type; 300 u32 status; 301 302 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 303 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { 304 status = E1000_READ_REG(hw, E1000_STATUS); 305 bus->func = (status & E1000_STATUS_FUNC_MASK) 306 >> E1000_STATUS_FUNC_SHIFT; 307 } else { 308 bus->func = 0; 309 } 310 } 311 312 /** 313 * e1000_set_lan_id_single_port - Set LAN id for a single port device 314 * @hw: pointer to the HW structure 315 * 316 * Sets the LAN function id to zero for a single port device. 317 **/ 318 void e1000_set_lan_id_single_port(struct e1000_hw *hw) 319 { 320 struct e1000_bus_info *bus = &hw->bus; 321 322 bus->func = 0; 323 } 324 325 /** 326 * e1000_clear_vfta_generic - Clear VLAN filter table 327 * @hw: pointer to the HW structure 328 * 329 * Clears the register array which contains the VLAN filter table by 330 * setting all the values to 0. 331 **/ 332 void e1000_clear_vfta_generic(struct e1000_hw *hw) 333 { 334 u32 offset; 335 336 DEBUGFUNC("e1000_clear_vfta_generic"); 337 338 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 339 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 340 E1000_WRITE_FLUSH(hw); 341 } 342 } 343 344 /** 345 * e1000_write_vfta_generic - Write value to VLAN filter table 346 * @hw: pointer to the HW structure 347 * @offset: register offset in VLAN filter table 348 * @value: register value written to VLAN filter table 349 * 350 * Writes value at the given offset in the register array which stores 351 * the VLAN filter table. 352 **/ 353 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 354 { 355 DEBUGFUNC("e1000_write_vfta_generic"); 356 357 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 358 E1000_WRITE_FLUSH(hw); 359 } 360 361 /** 362 * e1000_init_rx_addrs_generic - Initialize receive address's 363 * @hw: pointer to the HW structure 364 * @rar_count: receive address registers 365 * 366 * Setup the receive address registers by setting the base receive address 367 * register to the devices MAC address and clearing all the other receive 368 * address registers to 0. 369 **/ 370 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 371 { 372 u32 i; 373 u8 mac_addr[ETH_ADDR_LEN] = {0}; 374 375 DEBUGFUNC("e1000_init_rx_addrs_generic"); 376 377 /* Setup the receive address */ 378 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 379 380 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 381 382 /* Zero out the other (rar_entry_count - 1) receive addresses */ 383 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 384 for (i = 1; i < rar_count; i++) 385 hw->mac.ops.rar_set(hw, mac_addr, i); 386 } 387 388 /** 389 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 390 * @hw: pointer to the HW structure 391 * 392 * Checks the nvm for an alternate MAC address. An alternate MAC address 393 * can be setup by pre-boot software and must be treated like a permanent 394 * address and must override the actual permanent MAC address. If an 395 * alternate MAC address is found it is programmed into RAR0, replacing 396 * the permanent address that was installed into RAR0 by the Si on reset. 397 * This function will return SUCCESS unless it encounters an error while 398 * reading the EEPROM. 399 **/ 400 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 401 { 402 u32 i; 403 s32 ret_val; 404 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 405 u8 alt_mac_addr[ETH_ADDR_LEN]; 406 407 DEBUGFUNC("e1000_check_alt_mac_addr_generic"); 408 409 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data); 410 if (ret_val) 411 return ret_val; 412 413 #if !defined(NO_82542_SUPPORT) || !defined(NO_82543_SUPPORT) || !defined(NO_82540_SUPPORT) || !defined(NO_82541_SUPPORT) 414 /* not supported on older hardware or 82573 */ 415 if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573)) 416 #else 417 /* not supported on 82573 */ 418 if (hw->mac.type == e1000_82573) 419 #endif 420 return E1000_SUCCESS; 421 422 /* Alternate MAC address is handled by the option ROM for 82580 423 * and newer. SW support not required. 424 */ 425 if (hw->mac.type >= e1000_82580) 426 return E1000_SUCCESS; 427 428 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 429 &nvm_alt_mac_addr_offset); 430 if (ret_val) { 431 DEBUGOUT("NVM Read Error\n"); 432 return ret_val; 433 } 434 435 if ((nvm_alt_mac_addr_offset == 0xFFFF) || 436 (nvm_alt_mac_addr_offset == 0x0000)) 437 /* There is no Alternate MAC Address */ 438 return E1000_SUCCESS; 439 440 if (hw->bus.func == E1000_FUNC_1) 441 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 442 if (hw->bus.func == E1000_FUNC_2) 443 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2; 444 445 if (hw->bus.func == E1000_FUNC_3) 446 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3; 447 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 448 offset = nvm_alt_mac_addr_offset + (i >> 1); 449 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 450 if (ret_val) { 451 DEBUGOUT("NVM Read Error\n"); 452 return ret_val; 453 } 454 455 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 456 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 457 } 458 459 /* if multicast bit is set, the alternate address will not be used */ 460 if (alt_mac_addr[0] & 0x01) { 461 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); 462 return E1000_SUCCESS; 463 } 464 465 /* We have a valid alternate MAC address, and we want to treat it the 466 * same as the normal permanent MAC address stored by the HW into the 467 * RAR. Do this by mapping this address into RAR0. 468 */ 469 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 470 471 return E1000_SUCCESS; 472 } 473 474 /** 475 * e1000_rar_set_generic - Set receive address register 476 * @hw: pointer to the HW structure 477 * @addr: pointer to the receive address 478 * @index: receive address array register 479 * 480 * Sets the receive address array register at index to the address passed 481 * in by addr. 482 **/ 483 static void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 484 { 485 u32 rar_low, rar_high; 486 487 DEBUGFUNC("e1000_rar_set_generic"); 488 489 /* HW expects these in little endian so we reverse the byte order 490 * from network order (big endian) to little endian 491 */ 492 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 493 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 494 495 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 496 497 /* If MAC address zero, no need to set the AV bit */ 498 if (rar_low || rar_high) 499 rar_high |= E1000_RAH_AV; 500 501 /* Some bridges will combine consecutive 32-bit writes into 502 * a single burst write, which will malfunction on some parts. 503 * The flushes avoid this. 504 */ 505 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 506 E1000_WRITE_FLUSH(hw); 507 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 508 E1000_WRITE_FLUSH(hw); 509 } 510 511 /** 512 * e1000_hash_mc_addr_generic - Generate a multicast hash value 513 * @hw: pointer to the HW structure 514 * @mc_addr: pointer to a multicast address 515 * 516 * Generates a multicast address hash value which is used to determine 517 * the multicast filter table array address and new table value. 518 **/ 519 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 520 { 521 u32 hash_value, hash_mask; 522 u8 bit_shift = 0; 523 524 DEBUGFUNC("e1000_hash_mc_addr_generic"); 525 526 /* Register count multiplied by bits per register */ 527 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 528 529 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts 530 * where 0xFF would still fall within the hash mask. 531 */ 532 while (hash_mask >> bit_shift != 0xFF) 533 bit_shift++; 534 535 /* The portion of the address that is used for the hash table 536 * is determined by the mc_filter_type setting. 537 * The algorithm is such that there is a total of 8 bits of shifting. 538 * The bit_shift for a mc_filter_type of 0 represents the number of 539 * left-shifts where the MSB of mc_addr[5] would still fall within 540 * the hash_mask. Case 0 does this exactly. Since there are a total 541 * of 8 bits of shifting, then mc_addr[4] will shift right the 542 * remaining number of bits. Thus 8 - bit_shift. The rest of the 543 * cases are a variation of this algorithm...essentially raising the 544 * number of bits to shift mc_addr[5] left, while still keeping the 545 * 8-bit shifting total. 546 * 547 * For example, given the following Destination MAC Address and an 548 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 549 * we can see that the bit_shift for case 0 is 4. These are the hash 550 * values resulting from each mc_filter_type... 551 * [0] [1] [2] [3] [4] [5] 552 * 01 AA 00 12 34 56 553 * LSB MSB 554 * 555 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 556 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 557 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 558 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 559 */ 560 switch (hw->mac.mc_filter_type) { 561 default: 562 case 0: 563 break; 564 case 1: 565 bit_shift += 1; 566 break; 567 case 2: 568 bit_shift += 2; 569 break; 570 case 3: 571 bit_shift += 4; 572 break; 573 } 574 575 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 576 (((u16) mc_addr[5]) << bit_shift))); 577 578 return hash_value; 579 } 580 581 /** 582 * e1000_update_mc_addr_list_generic - Update Multicast addresses 583 * @hw: pointer to the HW structure 584 * @mc_addr_list: array of multicast addresses to program 585 * @mc_addr_count: number of multicast addresses to program 586 * 587 * Updates entire Multicast Table Array. 588 * The caller must have a packed mc_addr_list of multicast addresses. 589 **/ 590 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw, 591 u8 *mc_addr_list, u32 mc_addr_count) 592 { 593 u32 hash_value, hash_bit, hash_reg; 594 int i; 595 596 DEBUGFUNC("e1000_update_mc_addr_list_generic"); 597 598 /* clear mta_shadow */ 599 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 600 601 /* update mta_shadow from mc_addr_list */ 602 for (i = 0; (u32) i < mc_addr_count; i++) { 603 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list); 604 605 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 606 hash_bit = hash_value & 0x1F; 607 608 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 609 mc_addr_list += (ETH_ADDR_LEN); 610 } 611 612 /* replace the entire MTA table */ 613 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 614 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 615 E1000_WRITE_FLUSH(hw); 616 } 617 618 /** 619 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value 620 * @hw: pointer to the HW structure 621 * 622 * In certain situations, a system BIOS may report that the PCIx maximum 623 * memory read byte count (MMRBC) value is higher than than the actual 624 * value. We check the PCIx command register with the current PCIx status 625 * register. 626 **/ 627 void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw) 628 { 629 u16 cmd_mmrbc; 630 u16 pcix_cmd; 631 u16 pcix_stat_hi_word; 632 u16 stat_mmrbc; 633 634 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); 635 636 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ 637 if (hw->bus.type != e1000_bus_type_pcix) 638 return; 639 640 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 641 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 642 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> 643 PCIX_COMMAND_MMRBC_SHIFT; 644 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 645 PCIX_STATUS_HI_MMRBC_SHIFT; 646 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 647 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 648 if (cmd_mmrbc > stat_mmrbc) { 649 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; 650 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 651 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 652 } 653 } 654 655 /** 656 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 657 * @hw: pointer to the HW structure 658 * 659 * Clears the base hardware counters by reading the counter registers. 660 **/ 661 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 662 { 663 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 664 665 E1000_READ_REG(hw, E1000_CRCERRS); 666 E1000_READ_REG(hw, E1000_SYMERRS); 667 E1000_READ_REG(hw, E1000_MPC); 668 E1000_READ_REG(hw, E1000_SCC); 669 E1000_READ_REG(hw, E1000_ECOL); 670 E1000_READ_REG(hw, E1000_MCC); 671 E1000_READ_REG(hw, E1000_LATECOL); 672 E1000_READ_REG(hw, E1000_COLC); 673 E1000_READ_REG(hw, E1000_DC); 674 E1000_READ_REG(hw, E1000_SEC); 675 E1000_READ_REG(hw, E1000_RLEC); 676 E1000_READ_REG(hw, E1000_XONRXC); 677 E1000_READ_REG(hw, E1000_XONTXC); 678 E1000_READ_REG(hw, E1000_XOFFRXC); 679 E1000_READ_REG(hw, E1000_XOFFTXC); 680 E1000_READ_REG(hw, E1000_FCRUC); 681 E1000_READ_REG(hw, E1000_GPRC); 682 E1000_READ_REG(hw, E1000_BPRC); 683 E1000_READ_REG(hw, E1000_MPRC); 684 E1000_READ_REG(hw, E1000_GPTC); 685 E1000_READ_REG(hw, E1000_GORCL); 686 E1000_READ_REG(hw, E1000_GORCH); 687 E1000_READ_REG(hw, E1000_GOTCL); 688 E1000_READ_REG(hw, E1000_GOTCH); 689 E1000_READ_REG(hw, E1000_RNBC); 690 E1000_READ_REG(hw, E1000_RUC); 691 E1000_READ_REG(hw, E1000_RFC); 692 E1000_READ_REG(hw, E1000_ROC); 693 E1000_READ_REG(hw, E1000_RJC); 694 E1000_READ_REG(hw, E1000_TORL); 695 E1000_READ_REG(hw, E1000_TORH); 696 E1000_READ_REG(hw, E1000_TOTL); 697 E1000_READ_REG(hw, E1000_TOTH); 698 E1000_READ_REG(hw, E1000_TPR); 699 E1000_READ_REG(hw, E1000_TPT); 700 E1000_READ_REG(hw, E1000_MPTC); 701 E1000_READ_REG(hw, E1000_BPTC); 702 } 703 704 /** 705 * e1000_check_for_copper_link_generic - Check for link (Copper) 706 * @hw: pointer to the HW structure 707 * 708 * Checks to see of the link status of the hardware has changed. If a 709 * change in link status has been detected, then we read the PHY registers 710 * to get the current speed/duplex if link exists. 711 **/ 712 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) 713 { 714 struct e1000_mac_info *mac = &hw->mac; 715 s32 ret_val; 716 bool link; 717 718 DEBUGFUNC("e1000_check_for_copper_link"); 719 720 /* We only want to go out to the PHY registers to see if Auto-Neg 721 * has completed and/or if our link status has changed. The 722 * get_link_status flag is set upon receiving a Link Status 723 * Change or Rx Sequence Error interrupt. 724 */ 725 if (!mac->get_link_status) 726 return E1000_SUCCESS; 727 728 /* First we want to see if the MII Status Register reports 729 * link. If so, then we want to get the current speed/duplex 730 * of the PHY. 731 */ 732 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 733 if (ret_val) 734 return ret_val; 735 736 if (!link) 737 return E1000_SUCCESS; /* No link detected */ 738 739 mac->get_link_status = FALSE; 740 741 /* Check if there was DownShift, must be checked 742 * immediately after link-up 743 */ 744 e1000_check_downshift_generic(hw); 745 746 /* If we are forcing speed/duplex, then we simply return since 747 * we have already determined whether we have link or not. 748 */ 749 if (!mac->autoneg) 750 return -E1000_ERR_CONFIG; 751 752 /* Auto-Neg is enabled. Auto Speed Detection takes care 753 * of MAC speed/duplex configuration. So we only need to 754 * configure Collision Distance in the MAC. 755 */ 756 mac->ops.config_collision_dist(hw); 757 758 /* Configure Flow Control now that Auto-Neg has completed. 759 * First, we need to restore the desired flow control 760 * settings because we may have had to re-autoneg with a 761 * different link partner. 762 */ 763 ret_val = e1000_config_fc_after_link_up_generic(hw); 764 if (ret_val) 765 DEBUGOUT("Error configuring flow control\n"); 766 767 return ret_val; 768 } 769 770 /** 771 * e1000_check_for_fiber_link_generic - Check for link (Fiber) 772 * @hw: pointer to the HW structure 773 * 774 * Checks for link up on the hardware. If link is not up and we have 775 * a signal, then we need to force link up. 776 **/ 777 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 778 { 779 struct e1000_mac_info *mac = &hw->mac; 780 u32 rxcw; 781 u32 ctrl; 782 u32 status; 783 s32 ret_val; 784 785 DEBUGFUNC("e1000_check_for_fiber_link_generic"); 786 787 ctrl = E1000_READ_REG(hw, E1000_CTRL); 788 status = E1000_READ_REG(hw, E1000_STATUS); 789 rxcw = E1000_READ_REG(hw, E1000_RXCW); 790 791 /* If we don't have link (auto-negotiation failed or link partner 792 * cannot auto-negotiate), the cable is plugged in (we have signal), 793 * and our link partner is not trying to auto-negotiate with us (we 794 * are receiving idles or data), we need to force link up. We also 795 * need to give auto-negotiation time to complete, in case the cable 796 * was just plugged in. The autoneg_failed flag does this. 797 */ 798 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 799 if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) && 800 !(rxcw & E1000_RXCW_C)) { 801 if (!mac->autoneg_failed) { 802 mac->autoneg_failed = TRUE; 803 return E1000_SUCCESS; 804 } 805 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 806 807 /* Disable auto-negotiation in the TXCW register */ 808 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 809 810 /* Force link-up and also force full-duplex. */ 811 ctrl = E1000_READ_REG(hw, E1000_CTRL); 812 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 813 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 814 815 /* Configure Flow Control after forcing link up. */ 816 ret_val = e1000_config_fc_after_link_up_generic(hw); 817 if (ret_val) { 818 DEBUGOUT("Error configuring flow control\n"); 819 return ret_val; 820 } 821 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 822 /* If we are forcing link and we are receiving /C/ ordered 823 * sets, re-enable auto-negotiation in the TXCW register 824 * and disable forced link in the Device Control register 825 * in an attempt to auto-negotiate with our link partner. 826 */ 827 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 828 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 829 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 830 831 mac->serdes_has_link = TRUE; 832 } 833 834 return E1000_SUCCESS; 835 } 836 837 /** 838 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 839 * @hw: pointer to the HW structure 840 * 841 * Checks for link up on the hardware. If link is not up and we have 842 * a signal, then we need to force link up. 843 **/ 844 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 845 { 846 struct e1000_mac_info *mac = &hw->mac; 847 u32 rxcw; 848 u32 ctrl; 849 u32 status; 850 s32 ret_val; 851 852 DEBUGFUNC("e1000_check_for_serdes_link_generic"); 853 854 ctrl = E1000_READ_REG(hw, E1000_CTRL); 855 status = E1000_READ_REG(hw, E1000_STATUS); 856 rxcw = E1000_READ_REG(hw, E1000_RXCW); 857 858 /* If we don't have link (auto-negotiation failed or link partner 859 * cannot auto-negotiate), and our link partner is not trying to 860 * auto-negotiate with us (we are receiving idles or data), 861 * we need to force link up. We also need to give auto-negotiation 862 * time to complete. 863 */ 864 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 865 if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) { 866 if (!mac->autoneg_failed) { 867 mac->autoneg_failed = TRUE; 868 return E1000_SUCCESS; 869 } 870 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 871 872 /* Disable auto-negotiation in the TXCW register */ 873 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 874 875 /* Force link-up and also force full-duplex. */ 876 ctrl = E1000_READ_REG(hw, E1000_CTRL); 877 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 878 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 879 880 /* Configure Flow Control after forcing link up. */ 881 ret_val = e1000_config_fc_after_link_up_generic(hw); 882 if (ret_val) { 883 DEBUGOUT("Error configuring flow control\n"); 884 return ret_val; 885 } 886 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 887 /* If we are forcing link and we are receiving /C/ ordered 888 * sets, re-enable auto-negotiation in the TXCW register 889 * and disable forced link in the Device Control register 890 * in an attempt to auto-negotiate with our link partner. 891 */ 892 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 893 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 894 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 895 896 mac->serdes_has_link = TRUE; 897 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 898 /* If we force link for non-auto-negotiation switch, check 899 * link status based on MAC synchronization for internal 900 * serdes media type. 901 */ 902 /* SYNCH bit and IV bit are sticky. */ 903 usec_delay(10); 904 rxcw = E1000_READ_REG(hw, E1000_RXCW); 905 if (rxcw & E1000_RXCW_SYNCH) { 906 if (!(rxcw & E1000_RXCW_IV)) { 907 mac->serdes_has_link = TRUE; 908 DEBUGOUT("SERDES: Link up - forced.\n"); 909 } 910 } else { 911 mac->serdes_has_link = FALSE; 912 DEBUGOUT("SERDES: Link down - force failed.\n"); 913 } 914 } 915 916 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 917 status = E1000_READ_REG(hw, E1000_STATUS); 918 if (status & E1000_STATUS_LU) { 919 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 920 usec_delay(10); 921 rxcw = E1000_READ_REG(hw, E1000_RXCW); 922 if (rxcw & E1000_RXCW_SYNCH) { 923 if (!(rxcw & E1000_RXCW_IV)) { 924 mac->serdes_has_link = TRUE; 925 DEBUGOUT("SERDES: Link up - autoneg completed successfully.\n"); 926 } else { 927 mac->serdes_has_link = FALSE; 928 DEBUGOUT("SERDES: Link down - invalid codewords detected in autoneg.\n"); 929 } 930 } else { 931 mac->serdes_has_link = FALSE; 932 DEBUGOUT("SERDES: Link down - no sync.\n"); 933 } 934 } else { 935 mac->serdes_has_link = FALSE; 936 DEBUGOUT("SERDES: Link down - autoneg failed\n"); 937 } 938 } 939 940 return E1000_SUCCESS; 941 } 942 943 /** 944 * e1000_set_default_fc_generic - Set flow control default values 945 * @hw: pointer to the HW structure 946 * 947 * Read the EEPROM for the default values for flow control and store the 948 * values. 949 **/ 950 #ifdef NO_82542_SUPPORT 951 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw) 952 #else 953 s32 e1000_set_default_fc_generic(struct e1000_hw *hw) 954 #endif 955 { 956 s32 ret_val; 957 u16 nvm_data; 958 959 DEBUGFUNC("e1000_set_default_fc_generic"); 960 961 /* Read and store word 0x0F of the EEPROM. This word contains bits 962 * that determine the hardware's default PAUSE (flow control) mode, 963 * a bit that determines whether the HW defaults to enabling or 964 * disabling auto-negotiation, and the direction of the 965 * SW defined pins. If there is no SW over-ride of the flow 966 * control setting, then the variable hw->fc will 967 * be initialized based on a value in the EEPROM. 968 */ 969 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); 970 971 if (ret_val) { 972 DEBUGOUT("NVM Read Error\n"); 973 return ret_val; 974 } 975 976 if (!(nvm_data & NVM_WORD0F_PAUSE_MASK)) 977 hw->fc.requested_mode = e1000_fc_none; 978 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 979 NVM_WORD0F_ASM_DIR) 980 hw->fc.requested_mode = e1000_fc_tx_pause; 981 else 982 hw->fc.requested_mode = e1000_fc_full; 983 984 return E1000_SUCCESS; 985 } 986 987 /** 988 * e1000_setup_link_generic - Setup flow control and link settings 989 * @hw: pointer to the HW structure 990 * 991 * Determines which flow control settings to use, then configures flow 992 * control. Calls the appropriate media-specific link configuration 993 * function. Assuming the adapter has a valid link partner, a valid link 994 * should be established. Assumes the hardware has previously been reset 995 * and the transmitter and receiver are not enabled. 996 **/ 997 s32 e1000_setup_link_generic(struct e1000_hw *hw) 998 { 999 s32 ret_val; 1000 1001 DEBUGFUNC("e1000_setup_link_generic"); 1002 1003 /* In the case of the phy reset being blocked, we already have a link. 1004 * We do not need to set it up again. 1005 */ 1006 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 1007 return E1000_SUCCESS; 1008 1009 /* If requested flow control is set to default, set flow control 1010 * based on the EEPROM flow control settings. 1011 */ 1012 if (hw->fc.requested_mode == e1000_fc_default) { 1013 ret_val = e1000_set_default_fc_generic(hw); 1014 if (ret_val) 1015 return ret_val; 1016 } 1017 1018 /* Save off the requested flow control mode for use later. Depending 1019 * on the link partner's capabilities, we may or may not use this mode. 1020 */ 1021 hw->fc.current_mode = hw->fc.requested_mode; 1022 1023 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 1024 hw->fc.current_mode); 1025 1026 /* Call the necessary media_type subroutine to configure the link. */ 1027 ret_val = hw->mac.ops.setup_physical_interface(hw); 1028 if (ret_val) 1029 return ret_val; 1030 1031 /* Initialize the flow control address, type, and PAUSE timer 1032 * registers to their default values. This is done even if flow 1033 * control is disabled, because it does not hurt anything to 1034 * initialize these registers. 1035 */ 1036 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 1037 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 1038 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1039 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 1040 1041 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 1042 1043 return e1000_set_fc_watermarks_generic(hw); 1044 } 1045 1046 /** 1047 * e1000_commit_fc_settings_generic - Configure flow control 1048 * @hw: pointer to the HW structure 1049 * 1050 * Write the flow control settings to the Transmit Config Word Register (TXCW) 1051 * base on the flow control settings in e1000_mac_info. 1052 **/ 1053 s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 1054 { 1055 struct e1000_mac_info *mac = &hw->mac; 1056 u32 txcw; 1057 1058 DEBUGFUNC("e1000_commit_fc_settings_generic"); 1059 1060 /* Check for a software override of the flow control settings, and 1061 * setup the device accordingly. If auto-negotiation is enabled, then 1062 * software will have to set the "PAUSE" bits to the correct value in 1063 * the Transmit Config Word Register (TXCW) and re-start auto- 1064 * negotiation. However, if auto-negotiation is disabled, then 1065 * software will have to manually configure the two flow control enable 1066 * bits in the CTRL register. 1067 * 1068 * The possible values of the "fc" parameter are: 1069 * 0: Flow control is completely disabled 1070 * 1: Rx flow control is enabled (we can receive pause frames, 1071 * but not send pause frames). 1072 * 2: Tx flow control is enabled (we can send pause frames but we 1073 * do not support receiving pause frames). 1074 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1075 */ 1076 switch (hw->fc.current_mode) { 1077 case e1000_fc_none: 1078 /* Flow control completely disabled by a software over-ride. */ 1079 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1080 break; 1081 case e1000_fc_rx_pause: 1082 /* Rx Flow control is enabled and Tx Flow control is disabled 1083 * by a software over-ride. Since there really isn't a way to 1084 * advertise that we are capable of Rx Pause ONLY, we will 1085 * advertise that we support both symmetric and asymmetric Rx 1086 * PAUSE. Later, we will disable the adapter's ability to send 1087 * PAUSE frames. 1088 */ 1089 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1090 break; 1091 case e1000_fc_tx_pause: 1092 /* Tx Flow control is enabled, and Rx Flow control is disabled, 1093 * by a software over-ride. 1094 */ 1095 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1096 break; 1097 case e1000_fc_full: 1098 /* Flow control (both Rx and Tx) is enabled by a software 1099 * over-ride. 1100 */ 1101 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1102 break; 1103 default: 1104 DEBUGOUT("Flow control param set incorrectly\n"); 1105 return -E1000_ERR_CONFIG; 1106 break; 1107 } 1108 1109 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1110 mac->txcw = txcw; 1111 1112 return E1000_SUCCESS; 1113 } 1114 1115 /** 1116 * e1000_poll_fiber_serdes_link_generic - Poll for link up 1117 * @hw: pointer to the HW structure 1118 * 1119 * Polls for link up by reading the status register, if link fails to come 1120 * up with auto-negotiation, then the link is forced if a signal is detected. 1121 **/ 1122 s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 1123 { 1124 struct e1000_mac_info *mac = &hw->mac; 1125 u32 i, status; 1126 s32 ret_val; 1127 1128 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 1129 1130 /* If we have a signal (the cable is plugged in, or assumed TRUE for 1131 * serdes media) then poll for a "Link-Up" indication in the Device 1132 * Status Register. Time-out if a link isn't seen in 500 milliseconds 1133 * seconds (Auto-negotiation should complete in less than 500 1134 * milliseconds even if the other end is doing it in SW). 1135 */ 1136 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 1137 msec_delay(10); 1138 status = E1000_READ_REG(hw, E1000_STATUS); 1139 if (status & E1000_STATUS_LU) 1140 break; 1141 } 1142 if (i == FIBER_LINK_UP_LIMIT) { 1143 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1144 mac->autoneg_failed = TRUE; 1145 /* AutoNeg failed to achieve a link, so we'll call 1146 * mac->check_for_link. This routine will force the 1147 * link up if we detect a signal. This will allow us to 1148 * communicate with non-autonegotiating link partners. 1149 */ 1150 ret_val = mac->ops.check_for_link(hw); 1151 if (ret_val) { 1152 DEBUGOUT("Error while checking for link\n"); 1153 return ret_val; 1154 } 1155 mac->autoneg_failed = FALSE; 1156 } else { 1157 mac->autoneg_failed = FALSE; 1158 DEBUGOUT("Valid Link Found\n"); 1159 } 1160 1161 return E1000_SUCCESS; 1162 } 1163 1164 /** 1165 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 1166 * @hw: pointer to the HW structure 1167 * 1168 * Configures collision distance and flow control for fiber and serdes 1169 * links. Upon successful setup, poll for link. 1170 **/ 1171 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 1172 { 1173 u32 ctrl; 1174 s32 ret_val; 1175 1176 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 1177 1178 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1179 1180 /* Take the link out of reset */ 1181 ctrl &= ~E1000_CTRL_LRST; 1182 1183 hw->mac.ops.config_collision_dist(hw); 1184 1185 ret_val = e1000_commit_fc_settings_generic(hw); 1186 if (ret_val) 1187 return ret_val; 1188 1189 /* Since auto-negotiation is enabled, take the link out of reset (the 1190 * link will be in reset, because we previously reset the chip). This 1191 * will restart auto-negotiation. If auto-negotiation is successful 1192 * then the link-up status bit will be set and the flow control enable 1193 * bits (RFCE and TFCE) will be set according to their negotiated value. 1194 */ 1195 DEBUGOUT("Auto-negotiation enabled\n"); 1196 1197 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1198 E1000_WRITE_FLUSH(hw); 1199 msec_delay(1); 1200 1201 /* For these adapters, the SW definable pin 1 is set when the optics 1202 * detect a signal. If we have a signal, then poll for a "Link-Up" 1203 * indication. 1204 */ 1205 if (hw->phy.media_type == e1000_media_type_internal_serdes || 1206 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1207 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1208 } else { 1209 DEBUGOUT("No signal detected\n"); 1210 } 1211 1212 return ret_val; 1213 } 1214 1215 /** 1216 * e1000_config_collision_dist_generic - Configure collision distance 1217 * @hw: pointer to the HW structure 1218 * 1219 * Configures the collision distance to the default value and is used 1220 * during link setup. 1221 **/ 1222 static void e1000_config_collision_dist_generic(struct e1000_hw *hw) 1223 { 1224 u32 tctl; 1225 1226 DEBUGFUNC("e1000_config_collision_dist_generic"); 1227 1228 tctl = E1000_READ_REG(hw, E1000_TCTL); 1229 1230 tctl &= ~E1000_TCTL_COLD; 1231 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1232 1233 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 1234 E1000_WRITE_FLUSH(hw); 1235 } 1236 1237 /** 1238 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 1239 * @hw: pointer to the HW structure 1240 * 1241 * Sets the flow control high/low threshold (watermark) registers. If 1242 * flow control XON frame transmission is enabled, then set XON frame 1243 * transmission as well. 1244 **/ 1245 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 1246 { 1247 u32 fcrtl = 0, fcrth = 0; 1248 1249 DEBUGFUNC("e1000_set_fc_watermarks_generic"); 1250 1251 /* Set the flow control receive threshold registers. Normally, 1252 * these registers will be set to a default threshold that may be 1253 * adjusted later by the driver's runtime code. However, if the 1254 * ability to transmit pause frames is not enabled, then these 1255 * registers will be set to 0. 1256 */ 1257 if (hw->fc.current_mode & e1000_fc_tx_pause) { 1258 /* We need to set up the Receive Threshold high and low water 1259 * marks as well as (optionally) enabling the transmission of 1260 * XON frames. 1261 */ 1262 fcrtl = hw->fc.low_water; 1263 if (hw->fc.send_xon) 1264 fcrtl |= E1000_FCRTL_XONE; 1265 1266 fcrth = hw->fc.high_water; 1267 } 1268 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 1269 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 1270 1271 return E1000_SUCCESS; 1272 } 1273 1274 /** 1275 * e1000_force_mac_fc_generic - Force the MAC's flow control settings 1276 * @hw: pointer to the HW structure 1277 * 1278 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 1279 * device control register to reflect the adapter settings. TFCE and RFCE 1280 * need to be explicitly set by software when a copper PHY is used because 1281 * autonegotiation is managed by the PHY rather than the MAC. Software must 1282 * also configure these bits when link is forced on a fiber connection. 1283 **/ 1284 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw) 1285 { 1286 u32 ctrl; 1287 1288 DEBUGFUNC("e1000_force_mac_fc_generic"); 1289 1290 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1291 1292 /* Because we didn't get link via the internal auto-negotiation 1293 * mechanism (we either forced link or we got link via PHY 1294 * auto-neg), we have to manually enable/disable transmit an 1295 * receive flow control. 1296 * 1297 * The "Case" statement below enables/disable flow control 1298 * according to the "hw->fc.current_mode" parameter. 1299 * 1300 * The possible values of the "fc" parameter are: 1301 * 0: Flow control is completely disabled 1302 * 1: Rx flow control is enabled (we can receive pause 1303 * frames but not send pause frames). 1304 * 2: Tx flow control is enabled (we can send pause frames 1305 * frames but we do not receive pause frames). 1306 * 3: Both Rx and Tx flow control (symmetric) is enabled. 1307 * other: No other values should be possible at this point. 1308 */ 1309 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); 1310 1311 switch (hw->fc.current_mode) { 1312 case e1000_fc_none: 1313 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1314 break; 1315 case e1000_fc_rx_pause: 1316 ctrl &= (~E1000_CTRL_TFCE); 1317 ctrl |= E1000_CTRL_RFCE; 1318 break; 1319 case e1000_fc_tx_pause: 1320 ctrl &= (~E1000_CTRL_RFCE); 1321 ctrl |= E1000_CTRL_TFCE; 1322 break; 1323 case e1000_fc_full: 1324 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1325 break; 1326 default: 1327 DEBUGOUT("Flow control param set incorrectly\n"); 1328 return -E1000_ERR_CONFIG; 1329 } 1330 1331 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1332 1333 return E1000_SUCCESS; 1334 } 1335 1336 /** 1337 * e1000_config_fc_after_link_up_generic - Configures flow control after link 1338 * @hw: pointer to the HW structure 1339 * 1340 * Checks the status of auto-negotiation after link up to ensure that the 1341 * speed and duplex were not forced. If the link needed to be forced, then 1342 * flow control needs to be forced also. If auto-negotiation is enabled 1343 * and did not fail, then we configure flow control based on our link 1344 * partner. 1345 **/ 1346 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 1347 { 1348 struct e1000_mac_info *mac = &hw->mac; 1349 s32 ret_val = E1000_SUCCESS; 1350 u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg; 1351 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1352 u16 speed, duplex; 1353 1354 DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 1355 1356 /* Check for the case where we have fiber media and auto-neg failed 1357 * so we had to force link. In this case, we need to force the 1358 * configuration of the MAC to match the "fc" parameter. 1359 */ 1360 if (mac->autoneg_failed) { 1361 if (hw->phy.media_type == e1000_media_type_fiber || 1362 hw->phy.media_type == e1000_media_type_internal_serdes) 1363 ret_val = e1000_force_mac_fc_generic(hw); 1364 } else { 1365 if (hw->phy.media_type == e1000_media_type_copper) 1366 ret_val = e1000_force_mac_fc_generic(hw); 1367 } 1368 1369 if (ret_val) { 1370 DEBUGOUT("Error forcing flow control settings\n"); 1371 return ret_val; 1372 } 1373 1374 /* Check for the case where we have copper media and auto-neg is 1375 * enabled. In this case, we need to check and see if Auto-Neg 1376 * has completed, and if so, how the PHY and link partner has 1377 * flow control configured. 1378 */ 1379 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1380 /* Read the MII Status Register and check to see if AutoNeg 1381 * has completed. We read this twice because this reg has 1382 * some "sticky" (latched) bits. 1383 */ 1384 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1385 if (ret_val) 1386 return ret_val; 1387 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1388 if (ret_val) 1389 return ret_val; 1390 1391 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1392 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n"); 1393 return ret_val; 1394 } 1395 1396 /* The AutoNeg process has completed, so we now need to 1397 * read both the Auto Negotiation Advertisement 1398 * Register (Address 4) and the Auto_Negotiation Base 1399 * Page Ability Register (Address 5) to determine how 1400 * flow control was negotiated. 1401 */ 1402 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 1403 &mii_nway_adv_reg); 1404 if (ret_val) 1405 return ret_val; 1406 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 1407 &mii_nway_lp_ability_reg); 1408 if (ret_val) 1409 return ret_val; 1410 1411 /* Two bits in the Auto Negotiation Advertisement Register 1412 * (Address 4) and two bits in the Auto Negotiation Base 1413 * Page Ability Register (Address 5) determine flow control 1414 * for both the PHY and the link partner. The following 1415 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1416 * 1999, describes these PAUSE resolution bits and how flow 1417 * control is determined based upon these settings. 1418 * NOTE: DC = Don't Care 1419 * 1420 * LOCAL DEVICE | LINK PARTNER 1421 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1422 *-------|---------|-------|---------|-------------------- 1423 * 0 | 0 | DC | DC | e1000_fc_none 1424 * 0 | 1 | 0 | DC | e1000_fc_none 1425 * 0 | 1 | 1 | 0 | e1000_fc_none 1426 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1427 * 1 | 0 | 0 | DC | e1000_fc_none 1428 * 1 | DC | 1 | DC | e1000_fc_full 1429 * 1 | 1 | 0 | 0 | e1000_fc_none 1430 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1431 * 1432 * Are both PAUSE bits set to 1? If so, this implies 1433 * Symmetric Flow Control is enabled at both ends. The 1434 * ASM_DIR bits are irrelevant per the spec. 1435 * 1436 * For Symmetric Flow Control: 1437 * 1438 * LOCAL DEVICE | LINK PARTNER 1439 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1440 *-------|---------|-------|---------|-------------------- 1441 * 1 | DC | 1 | DC | E1000_fc_full 1442 * 1443 */ 1444 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1445 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1446 /* Now we need to check if the user selected Rx ONLY 1447 * of pause frames. In this case, we had to advertise 1448 * FULL flow control because we could not advertise Rx 1449 * ONLY. Hence, we must now check to see if we need to 1450 * turn OFF the TRANSMISSION of PAUSE frames. 1451 */ 1452 if (hw->fc.requested_mode == e1000_fc_full) { 1453 hw->fc.current_mode = e1000_fc_full; 1454 DEBUGOUT("Flow Control = FULL.\n"); 1455 } else { 1456 hw->fc.current_mode = e1000_fc_rx_pause; 1457 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1458 } 1459 } 1460 /* For receiving PAUSE frames ONLY. 1461 * 1462 * LOCAL DEVICE | LINK PARTNER 1463 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1464 *-------|---------|-------|---------|-------------------- 1465 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1466 */ 1467 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1468 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1469 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1470 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1471 hw->fc.current_mode = e1000_fc_tx_pause; 1472 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); 1473 } 1474 /* For transmitting PAUSE frames ONLY. 1475 * 1476 * LOCAL DEVICE | LINK PARTNER 1477 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1478 *-------|---------|-------|---------|-------------------- 1479 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1480 */ 1481 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1482 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1483 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1484 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1485 hw->fc.current_mode = e1000_fc_rx_pause; 1486 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1487 } else { 1488 /* Per the IEEE spec, at this point flow control 1489 * should be disabled. 1490 */ 1491 hw->fc.current_mode = e1000_fc_none; 1492 DEBUGOUT("Flow Control = NONE.\n"); 1493 } 1494 1495 /* Now we need to do one last check... If we auto- 1496 * negotiated to HALF DUPLEX, flow control should not be 1497 * enabled per IEEE 802.3 spec. 1498 */ 1499 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1500 if (ret_val) { 1501 DEBUGOUT("Error getting link speed and duplex\n"); 1502 return ret_val; 1503 } 1504 1505 if (duplex == HALF_DUPLEX) 1506 hw->fc.current_mode = e1000_fc_none; 1507 1508 /* Now we call a subroutine to actually force the MAC 1509 * controller to use the correct flow control settings. 1510 */ 1511 ret_val = e1000_force_mac_fc_generic(hw); 1512 if (ret_val) { 1513 DEBUGOUT("Error forcing flow control settings\n"); 1514 return ret_val; 1515 } 1516 } 1517 1518 /* Check for the case where we have SerDes media and auto-neg is 1519 * enabled. In this case, we need to check and see if Auto-Neg 1520 * has completed, and if so, how the PHY and link partner has 1521 * flow control configured. 1522 */ 1523 if ((hw->phy.media_type == e1000_media_type_internal_serdes) && 1524 mac->autoneg) { 1525 /* Read the PCS_LSTS and check to see if AutoNeg 1526 * has completed. 1527 */ 1528 pcs_status_reg = E1000_READ_REG(hw, E1000_PCS_LSTAT); 1529 1530 if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) { 1531 DEBUGOUT("PCS Auto Neg has not completed.\n"); 1532 return ret_val; 1533 } 1534 1535 /* The AutoNeg process has completed, so we now need to 1536 * read both the Auto Negotiation Advertisement 1537 * Register (PCS_ANADV) and the Auto_Negotiation Base 1538 * Page Ability Register (PCS_LPAB) to determine how 1539 * flow control was negotiated. 1540 */ 1541 pcs_adv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV); 1542 pcs_lp_ability_reg = E1000_READ_REG(hw, E1000_PCS_LPAB); 1543 1544 /* Two bits in the Auto Negotiation Advertisement Register 1545 * (PCS_ANADV) and two bits in the Auto Negotiation Base 1546 * Page Ability Register (PCS_LPAB) determine flow control 1547 * for both the PHY and the link partner. The following 1548 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1549 * 1999, describes these PAUSE resolution bits and how flow 1550 * control is determined based upon these settings. 1551 * NOTE: DC = Don't Care 1552 * 1553 * LOCAL DEVICE | LINK PARTNER 1554 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1555 *-------|---------|-------|---------|-------------------- 1556 * 0 | 0 | DC | DC | e1000_fc_none 1557 * 0 | 1 | 0 | DC | e1000_fc_none 1558 * 0 | 1 | 1 | 0 | e1000_fc_none 1559 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1560 * 1 | 0 | 0 | DC | e1000_fc_none 1561 * 1 | DC | 1 | DC | e1000_fc_full 1562 * 1 | 1 | 0 | 0 | e1000_fc_none 1563 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1564 * 1565 * Are both PAUSE bits set to 1? If so, this implies 1566 * Symmetric Flow Control is enabled at both ends. The 1567 * ASM_DIR bits are irrelevant per the spec. 1568 * 1569 * For Symmetric Flow Control: 1570 * 1571 * LOCAL DEVICE | LINK PARTNER 1572 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1573 *-------|---------|-------|---------|-------------------- 1574 * 1 | DC | 1 | DC | e1000_fc_full 1575 * 1576 */ 1577 if ((pcs_adv_reg & E1000_TXCW_PAUSE) && 1578 (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) { 1579 /* Now we need to check if the user selected Rx ONLY 1580 * of pause frames. In this case, we had to advertise 1581 * FULL flow control because we could not advertise Rx 1582 * ONLY. Hence, we must now check to see if we need to 1583 * turn OFF the TRANSMISSION of PAUSE frames. 1584 */ 1585 if (hw->fc.requested_mode == e1000_fc_full) { 1586 hw->fc.current_mode = e1000_fc_full; 1587 DEBUGOUT("Flow Control = FULL.\n"); 1588 } else { 1589 hw->fc.current_mode = e1000_fc_rx_pause; 1590 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1591 } 1592 } 1593 /* For receiving PAUSE frames ONLY. 1594 * 1595 * LOCAL DEVICE | LINK PARTNER 1596 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1597 *-------|---------|-------|---------|-------------------- 1598 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1599 */ 1600 else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) && 1601 (pcs_adv_reg & E1000_TXCW_ASM_DIR) && 1602 (pcs_lp_ability_reg & E1000_TXCW_PAUSE) && 1603 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { 1604 hw->fc.current_mode = e1000_fc_tx_pause; 1605 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); 1606 } 1607 /* For transmitting PAUSE frames ONLY. 1608 * 1609 * LOCAL DEVICE | LINK PARTNER 1610 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1611 *-------|---------|-------|---------|-------------------- 1612 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1613 */ 1614 else if ((pcs_adv_reg & E1000_TXCW_PAUSE) && 1615 (pcs_adv_reg & E1000_TXCW_ASM_DIR) && 1616 !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) && 1617 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { 1618 hw->fc.current_mode = e1000_fc_rx_pause; 1619 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1620 } else { 1621 /* Per the IEEE spec, at this point flow control 1622 * should be disabled. 1623 */ 1624 hw->fc.current_mode = e1000_fc_none; 1625 DEBUGOUT("Flow Control = NONE.\n"); 1626 } 1627 1628 /* Now we call a subroutine to actually force the MAC 1629 * controller to use the correct flow control settings. 1630 */ 1631 pcs_ctrl_reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 1632 pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1633 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_ctrl_reg); 1634 1635 ret_val = e1000_force_mac_fc_generic(hw); 1636 if (ret_val) { 1637 DEBUGOUT("Error forcing flow control settings\n"); 1638 return ret_val; 1639 } 1640 } 1641 1642 return E1000_SUCCESS; 1643 } 1644 1645 /** 1646 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 1647 * @hw: pointer to the HW structure 1648 * @speed: stores the current speed 1649 * @duplex: stores the current duplex 1650 * 1651 * Read the status register for the current speed/duplex and store the current 1652 * speed and duplex for copper connections. 1653 **/ 1654 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 1655 u16 *duplex) 1656 { 1657 u32 status; 1658 1659 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 1660 1661 status = E1000_READ_REG(hw, E1000_STATUS); 1662 if (status & E1000_STATUS_SPEED_1000) { 1663 *speed = SPEED_1000; 1664 DEBUGOUT("1000 Mbs, "); 1665 } else if (status & E1000_STATUS_SPEED_100) { 1666 *speed = SPEED_100; 1667 DEBUGOUT("100 Mbs, "); 1668 } else { 1669 *speed = SPEED_10; 1670 DEBUGOUT("10 Mbs, "); 1671 } 1672 1673 if (status & E1000_STATUS_FD) { 1674 *duplex = FULL_DUPLEX; 1675 DEBUGOUT("Full Duplex\n"); 1676 } else { 1677 *duplex = HALF_DUPLEX; 1678 DEBUGOUT("Half Duplex\n"); 1679 } 1680 1681 return E1000_SUCCESS; 1682 } 1683 1684 /** 1685 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex 1686 * @hw: pointer to the HW structure 1687 * @speed: stores the current speed 1688 * @duplex: stores the current duplex 1689 * 1690 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1691 * for fiber/serdes links. 1692 **/ 1693 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw E1000_UNUSEDARG *hw, 1694 u16 *speed, u16 *duplex) 1695 { 1696 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 1697 1698 *speed = SPEED_1000; 1699 *duplex = FULL_DUPLEX; 1700 1701 return E1000_SUCCESS; 1702 } 1703 1704 /** 1705 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 1706 * @hw: pointer to the HW structure 1707 * 1708 * Acquire the HW semaphore to access the PHY or NVM 1709 **/ 1710 s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 1711 { 1712 u32 swsm; 1713 s32 timeout = hw->nvm.word_size + 1; 1714 s32 i = 0; 1715 1716 DEBUGFUNC("e1000_get_hw_semaphore_generic"); 1717 1718 /* Get the SW semaphore */ 1719 while (i < timeout) { 1720 swsm = E1000_READ_REG(hw, E1000_SWSM); 1721 if (!(swsm & E1000_SWSM_SMBI)) 1722 break; 1723 1724 usec_delay(50); 1725 i++; 1726 } 1727 1728 if (i == timeout) { 1729 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1730 return -E1000_ERR_NVM; 1731 } 1732 1733 /* Get the FW semaphore. */ 1734 for (i = 0; i < timeout; i++) { 1735 swsm = E1000_READ_REG(hw, E1000_SWSM); 1736 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 1737 1738 /* Semaphore acquired if bit latched */ 1739 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 1740 break; 1741 1742 usec_delay(50); 1743 } 1744 1745 if (i == timeout) { 1746 /* Release semaphores */ 1747 e1000_put_hw_semaphore_generic(hw); 1748 DEBUGOUT("Driver can't access the NVM\n"); 1749 return -E1000_ERR_NVM; 1750 } 1751 1752 return E1000_SUCCESS; 1753 } 1754 1755 /** 1756 * e1000_put_hw_semaphore_generic - Release hardware semaphore 1757 * @hw: pointer to the HW structure 1758 * 1759 * Release hardware semaphore used to access the PHY or NVM 1760 **/ 1761 void e1000_put_hw_semaphore_generic(struct e1000_hw *hw) 1762 { 1763 u32 swsm; 1764 1765 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 1766 1767 swsm = E1000_READ_REG(hw, E1000_SWSM); 1768 1769 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1770 1771 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 1772 } 1773 1774 /** 1775 * e1000_get_auto_rd_done_generic - Check for auto read completion 1776 * @hw: pointer to the HW structure 1777 * 1778 * Check EEPROM for Auto Read done bit. 1779 **/ 1780 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 1781 { 1782 s32 i = 0; 1783 1784 DEBUGFUNC("e1000_get_auto_rd_done_generic"); 1785 1786 while (i < AUTO_READ_DONE_TIMEOUT) { 1787 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 1788 break; 1789 msec_delay(1); 1790 i++; 1791 } 1792 1793 if (i == AUTO_READ_DONE_TIMEOUT) { 1794 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1795 return -E1000_ERR_RESET; 1796 } 1797 1798 return E1000_SUCCESS; 1799 } 1800 1801 /** 1802 * e1000_valid_led_default_generic - Verify a valid default LED config 1803 * @hw: pointer to the HW structure 1804 * @data: pointer to the NVM (EEPROM) 1805 * 1806 * Read the EEPROM for the current default LED configuration. If the 1807 * LED configuration is not valid, set to a valid LED configuration. 1808 **/ 1809 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 1810 { 1811 s32 ret_val; 1812 1813 DEBUGFUNC("e1000_valid_led_default_generic"); 1814 1815 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1816 if (ret_val) { 1817 DEBUGOUT("NVM Read Error\n"); 1818 return ret_val; 1819 } 1820 1821 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1822 *data = ID_LED_DEFAULT; 1823 1824 return E1000_SUCCESS; 1825 } 1826 1827 /** 1828 * e1000_id_led_init_generic - 1829 * @hw: pointer to the HW structure 1830 * 1831 **/ 1832 s32 e1000_id_led_init_generic(struct e1000_hw *hw) 1833 { 1834 struct e1000_mac_info *mac = &hw->mac; 1835 s32 ret_val; 1836 const u32 ledctl_mask = 0x000000FF; 1837 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1838 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1839 u16 data, i, temp; 1840 const u16 led_mask = 0x0F; 1841 1842 DEBUGFUNC("e1000_id_led_init_generic"); 1843 1844 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 1845 if (ret_val) 1846 return ret_val; 1847 1848 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 1849 mac->ledctl_mode1 = mac->ledctl_default; 1850 mac->ledctl_mode2 = mac->ledctl_default; 1851 1852 for (i = 0; i < 4; i++) { 1853 temp = (data >> (i << 2)) & led_mask; 1854 switch (temp) { 1855 case ID_LED_ON1_DEF2: 1856 case ID_LED_ON1_ON2: 1857 case ID_LED_ON1_OFF2: 1858 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1859 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1860 break; 1861 case ID_LED_OFF1_DEF2: 1862 case ID_LED_OFF1_ON2: 1863 case ID_LED_OFF1_OFF2: 1864 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1865 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1866 break; 1867 default: 1868 /* Do nothing */ 1869 break; 1870 } 1871 switch (temp) { 1872 case ID_LED_DEF1_ON2: 1873 case ID_LED_ON1_ON2: 1874 case ID_LED_OFF1_ON2: 1875 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1876 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1877 break; 1878 case ID_LED_DEF1_OFF2: 1879 case ID_LED_ON1_OFF2: 1880 case ID_LED_OFF1_OFF2: 1881 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1882 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1883 break; 1884 default: 1885 /* Do nothing */ 1886 break; 1887 } 1888 } 1889 1890 return E1000_SUCCESS; 1891 } 1892 1893 /** 1894 * e1000_setup_led_generic - Configures SW controllable LED 1895 * @hw: pointer to the HW structure 1896 * 1897 * This prepares the SW controllable LED for use and saves the current state 1898 * of the LED so it can be later restored. 1899 **/ 1900 s32 e1000_setup_led_generic(struct e1000_hw *hw) 1901 { 1902 u32 ledctl; 1903 1904 DEBUGFUNC("e1000_setup_led_generic"); 1905 1906 if (hw->mac.ops.setup_led != e1000_setup_led_generic) 1907 return -E1000_ERR_CONFIG; 1908 1909 if (hw->phy.media_type == e1000_media_type_fiber) { 1910 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 1911 hw->mac.ledctl_default = ledctl; 1912 /* Turn off LED0 */ 1913 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK | 1914 E1000_LEDCTL_LED0_MODE_MASK); 1915 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1916 E1000_LEDCTL_LED0_MODE_SHIFT); 1917 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 1918 } else if (hw->phy.media_type == e1000_media_type_copper) { 1919 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1920 } 1921 1922 return E1000_SUCCESS; 1923 } 1924 1925 /** 1926 * e1000_cleanup_led_generic - Set LED config to default operation 1927 * @hw: pointer to the HW structure 1928 * 1929 * Remove the current LED configuration and set the LED configuration 1930 * to the default value, saved from the EEPROM. 1931 **/ 1932 s32 e1000_cleanup_led_generic(struct e1000_hw *hw) 1933 { 1934 DEBUGFUNC("e1000_cleanup_led_generic"); 1935 1936 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1937 return E1000_SUCCESS; 1938 } 1939 1940 /** 1941 * e1000_blink_led_generic - Blink LED 1942 * @hw: pointer to the HW structure 1943 * 1944 * Blink the LEDs which are set to be on. 1945 **/ 1946 s32 e1000_blink_led_generic(struct e1000_hw *hw) 1947 { 1948 u32 ledctl_blink = 0; 1949 u32 i; 1950 1951 DEBUGFUNC("e1000_blink_led_generic"); 1952 1953 if (hw->phy.media_type == e1000_media_type_fiber) { 1954 /* always blink LED0 for PCI-E fiber */ 1955 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1956 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1957 } else { 1958 /* Set the blink bit for each LED that's "on" (0x0E) 1959 * (or "off" if inverted) in ledctl_mode2. The blink 1960 * logic in hardware only works when mode is set to "on" 1961 * so it must be changed accordingly when the mode is 1962 * "off" and inverted. 1963 */ 1964 ledctl_blink = hw->mac.ledctl_mode2; 1965 for (i = 0; i < 32; i += 8) { 1966 u32 mode = (hw->mac.ledctl_mode2 >> i) & 1967 E1000_LEDCTL_LED0_MODE_MASK; 1968 u32 led_default = hw->mac.ledctl_default >> i; 1969 1970 if ((!(led_default & E1000_LEDCTL_LED0_IVRT) && 1971 (mode == E1000_LEDCTL_MODE_LED_ON)) || 1972 ((led_default & E1000_LEDCTL_LED0_IVRT) && 1973 (mode == E1000_LEDCTL_MODE_LED_OFF))) { 1974 ledctl_blink &= 1975 ~(E1000_LEDCTL_LED0_MODE_MASK << i); 1976 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK | 1977 E1000_LEDCTL_MODE_LED_ON) << i; 1978 } 1979 } 1980 } 1981 1982 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 1983 1984 return E1000_SUCCESS; 1985 } 1986 1987 /** 1988 * e1000_led_on_generic - Turn LED on 1989 * @hw: pointer to the HW structure 1990 * 1991 * Turn LED on. 1992 **/ 1993 s32 e1000_led_on_generic(struct e1000_hw *hw) 1994 { 1995 u32 ctrl; 1996 1997 DEBUGFUNC("e1000_led_on_generic"); 1998 1999 switch (hw->phy.media_type) { 2000 case e1000_media_type_fiber: 2001 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2002 ctrl &= ~E1000_CTRL_SWDPIN0; 2003 ctrl |= E1000_CTRL_SWDPIO0; 2004 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2005 break; 2006 case e1000_media_type_copper: 2007 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 2008 break; 2009 default: 2010 break; 2011 } 2012 2013 return E1000_SUCCESS; 2014 } 2015 2016 /** 2017 * e1000_led_off_generic - Turn LED off 2018 * @hw: pointer to the HW structure 2019 * 2020 * Turn LED off. 2021 **/ 2022 s32 e1000_led_off_generic(struct e1000_hw *hw) 2023 { 2024 u32 ctrl; 2025 2026 DEBUGFUNC("e1000_led_off_generic"); 2027 2028 switch (hw->phy.media_type) { 2029 case e1000_media_type_fiber: 2030 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2031 ctrl |= E1000_CTRL_SWDPIN0; 2032 ctrl |= E1000_CTRL_SWDPIO0; 2033 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2034 break; 2035 case e1000_media_type_copper: 2036 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 2037 break; 2038 default: 2039 break; 2040 } 2041 2042 return E1000_SUCCESS; 2043 } 2044 2045 /** 2046 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 2047 * @hw: pointer to the HW structure 2048 * @no_snoop: bitmap of snoop events 2049 * 2050 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 2051 **/ 2052 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 2053 { 2054 u32 gcr; 2055 2056 DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 2057 2058 if (hw->bus.type != e1000_bus_type_pci_express) 2059 return; 2060 2061 if (no_snoop) { 2062 gcr = E1000_READ_REG(hw, E1000_GCR); 2063 gcr &= ~(PCIE_NO_SNOOP_ALL); 2064 gcr |= no_snoop; 2065 E1000_WRITE_REG(hw, E1000_GCR, gcr); 2066 } 2067 } 2068 2069 /** 2070 * e1000_disable_pcie_master_generic - Disables PCI-express master access 2071 * @hw: pointer to the HW structure 2072 * 2073 * Returns E1000_SUCCESS if successful, else returns -10 2074 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 2075 * the master requests to be disabled. 2076 * 2077 * Disables PCI-Express master access and verifies there are no pending 2078 * requests. 2079 **/ 2080 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw) 2081 { 2082 u32 ctrl; 2083 s32 timeout = MASTER_DISABLE_TIMEOUT; 2084 2085 DEBUGFUNC("e1000_disable_pcie_master_generic"); 2086 2087 if (hw->bus.type != e1000_bus_type_pci_express) 2088 return E1000_SUCCESS; 2089 2090 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2091 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 2092 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2093 2094 while (timeout) { 2095 if (!(E1000_READ_REG(hw, E1000_STATUS) & 2096 E1000_STATUS_GIO_MASTER_ENABLE)) 2097 break; 2098 usec_delay(100); 2099 timeout--; 2100 } 2101 2102 if (!timeout) { 2103 DEBUGOUT("Master requests are pending.\n"); 2104 return -E1000_ERR_MASTER_REQUESTS_PENDING; 2105 } 2106 2107 return E1000_SUCCESS; 2108 } 2109 2110 /** 2111 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 2112 * @hw: pointer to the HW structure 2113 * 2114 * Reset the Adaptive Interframe Spacing throttle to default values. 2115 **/ 2116 void e1000_reset_adaptive_generic(struct e1000_hw *hw) 2117 { 2118 struct e1000_mac_info *mac = &hw->mac; 2119 2120 DEBUGFUNC("e1000_reset_adaptive_generic"); 2121 2122 if (!mac->adaptive_ifs) { 2123 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2124 return; 2125 } 2126 2127 mac->current_ifs_val = 0; 2128 mac->ifs_min_val = IFS_MIN; 2129 mac->ifs_max_val = IFS_MAX; 2130 mac->ifs_step_size = IFS_STEP; 2131 mac->ifs_ratio = IFS_RATIO; 2132 2133 mac->in_ifs_mode = FALSE; 2134 E1000_WRITE_REG(hw, E1000_AIT, 0); 2135 } 2136 2137 /** 2138 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 2139 * @hw: pointer to the HW structure 2140 * 2141 * Update the Adaptive Interframe Spacing Throttle value based on the 2142 * time between transmitted packets and time between collisions. 2143 **/ 2144 void e1000_update_adaptive_generic(struct e1000_hw *hw) 2145 { 2146 struct e1000_mac_info *mac = &hw->mac; 2147 2148 DEBUGFUNC("e1000_update_adaptive_generic"); 2149 2150 if (!mac->adaptive_ifs) { 2151 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2152 return; 2153 } 2154 2155 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 2156 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 2157 mac->in_ifs_mode = TRUE; 2158 if (mac->current_ifs_val < mac->ifs_max_val) { 2159 if (!mac->current_ifs_val) 2160 mac->current_ifs_val = mac->ifs_min_val; 2161 else 2162 mac->current_ifs_val += 2163 mac->ifs_step_size; 2164 E1000_WRITE_REG(hw, E1000_AIT, 2165 mac->current_ifs_val); 2166 } 2167 } 2168 } else { 2169 if (mac->in_ifs_mode && 2170 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 2171 mac->current_ifs_val = 0; 2172 mac->in_ifs_mode = FALSE; 2173 E1000_WRITE_REG(hw, E1000_AIT, 0); 2174 } 2175 } 2176 } 2177 2178 /** 2179 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 2180 * @hw: pointer to the HW structure 2181 * 2182 * Verify that when not using auto-negotiation that MDI/MDIx is correctly 2183 * set, which is forced to MDI mode only. 2184 **/ 2185 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 2186 { 2187 DEBUGFUNC("e1000_validate_mdi_setting_generic"); 2188 2189 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 2190 DEBUGOUT("Invalid MDI setting detected\n"); 2191 hw->phy.mdix = 1; 2192 return -E1000_ERR_CONFIG; 2193 } 2194 2195 return E1000_SUCCESS; 2196 } 2197 2198 /** 2199 * e1000_validate_mdi_setting_crossover_generic - Verify MDI/MDIx settings 2200 * @hw: pointer to the HW structure 2201 * 2202 * Validate the MDI/MDIx setting, allowing for auto-crossover during forced 2203 * operation. 2204 **/ 2205 s32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw E1000_UNUSEDARG *hw) 2206 { 2207 DEBUGFUNC("e1000_validate_mdi_setting_crossover_generic"); 2208 2209 return E1000_SUCCESS; 2210 } 2211 2212 /** 2213 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register 2214 * @hw: pointer to the HW structure 2215 * @reg: 32bit register offset such as E1000_SCTL 2216 * @offset: register offset to write to 2217 * @data: data to write at register offset 2218 * 2219 * Writes an address/data control type register. There are several of these 2220 * and they all have the format address << 8 | data and bit 31 is polled for 2221 * completion. 2222 **/ 2223 s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, 2224 u32 offset, u8 data) 2225 { 2226 u32 i, regvalue = 0; 2227 2228 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); 2229 2230 /* Set up the address and data */ 2231 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 2232 E1000_WRITE_REG(hw, reg, regvalue); 2233 2234 /* Poll the ready bit to see if the MDI read completed */ 2235 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 2236 usec_delay(5); 2237 regvalue = E1000_READ_REG(hw, reg); 2238 if (regvalue & E1000_GEN_CTL_READY) 2239 break; 2240 } 2241 if (!(regvalue & E1000_GEN_CTL_READY)) { 2242 DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 2243 return -E1000_ERR_PHY; 2244 } 2245 2246 return E1000_SUCCESS; 2247 } 2248