1 /****************************************************************************** 2 3 Copyright (c) 2001-2011, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "e1000_api.h" 36 37 #ifdef NO_82542_SUPPORT 38 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw); 39 #endif 40 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw); 41 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); 42 43 /** 44 * e1000_init_mac_ops_generic - Initialize MAC function pointers 45 * @hw: pointer to the HW structure 46 * 47 * Setups up the function pointers to no-op functions 48 **/ 49 void e1000_init_mac_ops_generic(struct e1000_hw *hw) 50 { 51 struct e1000_mac_info *mac = &hw->mac; 52 DEBUGFUNC("e1000_init_mac_ops_generic"); 53 54 /* General Setup */ 55 mac->ops.init_params = e1000_null_ops_generic; 56 mac->ops.init_hw = e1000_null_ops_generic; 57 mac->ops.reset_hw = e1000_null_ops_generic; 58 mac->ops.setup_physical_interface = e1000_null_ops_generic; 59 mac->ops.get_bus_info = e1000_null_ops_generic; 60 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie; 61 mac->ops.read_mac_addr = e1000_read_mac_addr_generic; 62 mac->ops.config_collision_dist = e1000_config_collision_dist_generic; 63 mac->ops.clear_hw_cntrs = e1000_null_mac_generic; 64 /* LED */ 65 mac->ops.cleanup_led = e1000_null_ops_generic; 66 mac->ops.setup_led = e1000_null_ops_generic; 67 mac->ops.blink_led = e1000_null_ops_generic; 68 mac->ops.led_on = e1000_null_ops_generic; 69 mac->ops.led_off = e1000_null_ops_generic; 70 /* LINK */ 71 mac->ops.setup_link = e1000_null_ops_generic; 72 mac->ops.get_link_up_info = e1000_null_link_info; 73 mac->ops.check_for_link = e1000_null_ops_generic; 74 mac->ops.wait_autoneg = e1000_wait_autoneg_generic; 75 /* Management */ 76 mac->ops.check_mng_mode = e1000_null_mng_mode; 77 mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic; 78 mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic; 79 mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic; 80 /* VLAN, MC, etc. */ 81 mac->ops.update_mc_addr_list = e1000_null_update_mc; 82 mac->ops.clear_vfta = e1000_null_mac_generic; 83 mac->ops.write_vfta = e1000_null_write_vfta; 84 mac->ops.rar_set = e1000_rar_set_generic; 85 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; 86 } 87 88 /** 89 * e1000_null_ops_generic - No-op function, returns 0 90 * @hw: pointer to the HW structure 91 **/ 92 s32 e1000_null_ops_generic(struct e1000_hw *hw) 93 { 94 DEBUGFUNC("e1000_null_ops_generic"); 95 return E1000_SUCCESS; 96 } 97 98 /** 99 * e1000_null_mac_generic - No-op function, return void 100 * @hw: pointer to the HW structure 101 **/ 102 void e1000_null_mac_generic(struct e1000_hw *hw) 103 { 104 DEBUGFUNC("e1000_null_mac_generic"); 105 return; 106 } 107 108 /** 109 * e1000_null_link_info - No-op function, return 0 110 * @hw: pointer to the HW structure 111 **/ 112 s32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d) 113 { 114 DEBUGFUNC("e1000_null_link_info"); 115 return E1000_SUCCESS; 116 } 117 118 /** 119 * e1000_null_mng_mode - No-op function, return FALSE 120 * @hw: pointer to the HW structure 121 **/ 122 bool e1000_null_mng_mode(struct e1000_hw *hw) 123 { 124 DEBUGFUNC("e1000_null_mng_mode"); 125 return FALSE; 126 } 127 128 /** 129 * e1000_null_update_mc - No-op function, return void 130 * @hw: pointer to the HW structure 131 **/ 132 void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a) 133 { 134 DEBUGFUNC("e1000_null_update_mc"); 135 return; 136 } 137 138 /** 139 * e1000_null_write_vfta - No-op function, return void 140 * @hw: pointer to the HW structure 141 **/ 142 void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b) 143 { 144 DEBUGFUNC("e1000_null_write_vfta"); 145 return; 146 } 147 148 /** 149 * e1000_null_rar_set - No-op function, return void 150 * @hw: pointer to the HW structure 151 **/ 152 void e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a) 153 { 154 DEBUGFUNC("e1000_null_rar_set"); 155 return; 156 } 157 158 /** 159 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information 160 * @hw: pointer to the HW structure 161 * 162 * Determines and stores the system bus information for a particular 163 * network interface. The following bus information is determined and stored: 164 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function. 165 **/ 166 s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw) 167 { 168 struct e1000_mac_info *mac = &hw->mac; 169 struct e1000_bus_info *bus = &hw->bus; 170 u32 status = E1000_READ_REG(hw, E1000_STATUS); 171 s32 ret_val = E1000_SUCCESS; 172 173 DEBUGFUNC("e1000_get_bus_info_pci_generic"); 174 175 /* PCI or PCI-X? */ 176 bus->type = (status & E1000_STATUS_PCIX_MODE) 177 ? e1000_bus_type_pcix 178 : e1000_bus_type_pci; 179 180 /* Bus speed */ 181 if (bus->type == e1000_bus_type_pci) { 182 bus->speed = (status & E1000_STATUS_PCI66) 183 ? e1000_bus_speed_66 184 : e1000_bus_speed_33; 185 } else { 186 switch (status & E1000_STATUS_PCIX_SPEED) { 187 case E1000_STATUS_PCIX_SPEED_66: 188 bus->speed = e1000_bus_speed_66; 189 break; 190 case E1000_STATUS_PCIX_SPEED_100: 191 bus->speed = e1000_bus_speed_100; 192 break; 193 case E1000_STATUS_PCIX_SPEED_133: 194 bus->speed = e1000_bus_speed_133; 195 break; 196 default: 197 bus->speed = e1000_bus_speed_reserved; 198 break; 199 } 200 } 201 202 /* Bus width */ 203 bus->width = (status & E1000_STATUS_BUS64) 204 ? e1000_bus_width_64 205 : e1000_bus_width_32; 206 207 /* Which PCI(-X) function? */ 208 mac->ops.set_lan_id(hw); 209 210 return ret_val; 211 } 212 213 /** 214 * e1000_get_bus_info_pcie_generic - Get PCIe bus information 215 * @hw: pointer to the HW structure 216 * 217 * Determines and stores the system bus information for a particular 218 * network interface. The following bus information is determined and stored: 219 * bus speed, bus width, type (PCIe), and PCIe function. 220 **/ 221 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 222 { 223 struct e1000_mac_info *mac = &hw->mac; 224 struct e1000_bus_info *bus = &hw->bus; 225 s32 ret_val; 226 u16 pcie_link_status; 227 228 DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 229 230 bus->type = e1000_bus_type_pci_express; 231 232 ret_val = e1000_read_pcie_cap_reg(hw, 233 PCIE_LINK_STATUS, 234 &pcie_link_status); 235 if (ret_val) { 236 bus->width = e1000_bus_width_unknown; 237 bus->speed = e1000_bus_speed_unknown; 238 } else { 239 switch (pcie_link_status & PCIE_LINK_SPEED_MASK) { 240 case PCIE_LINK_SPEED_2500: 241 bus->speed = e1000_bus_speed_2500; 242 break; 243 case PCIE_LINK_SPEED_5000: 244 bus->speed = e1000_bus_speed_5000; 245 break; 246 default: 247 bus->speed = e1000_bus_speed_unknown; 248 break; 249 } 250 251 bus->width = (enum e1000_bus_width)((pcie_link_status & 252 PCIE_LINK_WIDTH_MASK) >> 253 PCIE_LINK_WIDTH_SHIFT); 254 } 255 256 mac->ops.set_lan_id(hw); 257 258 return E1000_SUCCESS; 259 } 260 261 /** 262 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 263 * 264 * @hw: pointer to the HW structure 265 * 266 * Determines the LAN function id by reading memory-mapped registers 267 * and swaps the port value if requested. 268 **/ 269 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) 270 { 271 struct e1000_bus_info *bus = &hw->bus; 272 u32 reg; 273 274 /* 275 * The status register reports the correct function number 276 * for the device regardless of function swap state. 277 */ 278 reg = E1000_READ_REG(hw, E1000_STATUS); 279 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 280 } 281 282 /** 283 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices 284 * @hw: pointer to the HW structure 285 * 286 * Determines the LAN function id by reading PCI config space. 287 **/ 288 void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw) 289 { 290 struct e1000_bus_info *bus = &hw->bus; 291 u16 pci_header_type; 292 u32 status; 293 294 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 295 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { 296 status = E1000_READ_REG(hw, E1000_STATUS); 297 bus->func = (status & E1000_STATUS_FUNC_MASK) 298 >> E1000_STATUS_FUNC_SHIFT; 299 } else { 300 bus->func = 0; 301 } 302 } 303 304 /** 305 * e1000_set_lan_id_single_port - Set LAN id for a single port device 306 * @hw: pointer to the HW structure 307 * 308 * Sets the LAN function id to zero for a single port device. 309 **/ 310 void e1000_set_lan_id_single_port(struct e1000_hw *hw) 311 { 312 struct e1000_bus_info *bus = &hw->bus; 313 314 bus->func = 0; 315 } 316 317 /** 318 * e1000_clear_vfta_generic - Clear VLAN filter table 319 * @hw: pointer to the HW structure 320 * 321 * Clears the register array which contains the VLAN filter table by 322 * setting all the values to 0. 323 **/ 324 void e1000_clear_vfta_generic(struct e1000_hw *hw) 325 { 326 u32 offset; 327 328 DEBUGFUNC("e1000_clear_vfta_generic"); 329 330 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 331 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 332 E1000_WRITE_FLUSH(hw); 333 } 334 } 335 336 /** 337 * e1000_write_vfta_generic - Write value to VLAN filter table 338 * @hw: pointer to the HW structure 339 * @offset: register offset in VLAN filter table 340 * @value: register value written to VLAN filter table 341 * 342 * Writes value at the given offset in the register array which stores 343 * the VLAN filter table. 344 **/ 345 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 346 { 347 DEBUGFUNC("e1000_write_vfta_generic"); 348 349 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 350 E1000_WRITE_FLUSH(hw); 351 } 352 353 /** 354 * e1000_init_rx_addrs_generic - Initialize receive address's 355 * @hw: pointer to the HW structure 356 * @rar_count: receive address registers 357 * 358 * Setup the receive address registers by setting the base receive address 359 * register to the devices MAC address and clearing all the other receive 360 * address registers to 0. 361 **/ 362 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 363 { 364 u32 i; 365 u8 mac_addr[ETH_ADDR_LEN] = {0}; 366 367 DEBUGFUNC("e1000_init_rx_addrs_generic"); 368 369 /* Setup the receive address */ 370 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 371 372 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 373 374 /* Zero out the other (rar_entry_count - 1) receive addresses */ 375 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 376 for (i = 1; i < rar_count; i++) 377 hw->mac.ops.rar_set(hw, mac_addr, i); 378 } 379 380 /** 381 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 382 * @hw: pointer to the HW structure 383 * 384 * Checks the nvm for an alternate MAC address. An alternate MAC address 385 * can be setup by pre-boot software and must be treated like a permanent 386 * address and must override the actual permanent MAC address. If an 387 * alternate MAC address is found it is programmed into RAR0, replacing 388 * the permanent address that was installed into RAR0 by the Si on reset. 389 * This function will return SUCCESS unless it encounters an error while 390 * reading the EEPROM. 391 **/ 392 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 393 { 394 u32 i; 395 s32 ret_val = E1000_SUCCESS; 396 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 397 u8 alt_mac_addr[ETH_ADDR_LEN]; 398 399 DEBUGFUNC("e1000_check_alt_mac_addr_generic"); 400 401 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data); 402 if (ret_val) 403 goto out; 404 405 /* Check for LOM (vs. NIC) or one of two valid mezzanine cards */ 406 if (!((nvm_data & NVM_COMPAT_LOM) || 407 (hw->device_id == E1000_DEV_ID_82571EB_SERDES_DUAL) || 408 (hw->device_id == E1000_DEV_ID_82571EB_SERDES_QUAD))) 409 goto out; 410 411 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 412 &nvm_alt_mac_addr_offset); 413 if (ret_val) { 414 DEBUGOUT("NVM Read Error\n"); 415 goto out; 416 } 417 418 if (nvm_alt_mac_addr_offset == 0xFFFF) { 419 /* There is no Alternate MAC Address */ 420 goto out; 421 } 422 423 if (hw->bus.func == E1000_FUNC_1) 424 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 425 if (hw->bus.func == E1000_FUNC_2) 426 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2; 427 428 if (hw->bus.func == E1000_FUNC_3) 429 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3; 430 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 431 offset = nvm_alt_mac_addr_offset + (i >> 1); 432 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 433 if (ret_val) { 434 DEBUGOUT("NVM Read Error\n"); 435 goto out; 436 } 437 438 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 439 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 440 } 441 442 /* if multicast bit is set, the alternate address will not be used */ 443 if (alt_mac_addr[0] & 0x01) { 444 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); 445 goto out; 446 } 447 448 /* 449 * We have a valid alternate MAC address, and we want to treat it the 450 * same as the normal permanent MAC address stored by the HW into the 451 * RAR. Do this by mapping this address into RAR0. 452 */ 453 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 454 455 out: 456 return ret_val; 457 } 458 459 /** 460 * e1000_rar_set_generic - Set receive address register 461 * @hw: pointer to the HW structure 462 * @addr: pointer to the receive address 463 * @index: receive address array register 464 * 465 * Sets the receive address array register at index to the address passed 466 * in by addr. 467 **/ 468 void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 469 { 470 u32 rar_low, rar_high; 471 472 DEBUGFUNC("e1000_rar_set_generic"); 473 474 /* 475 * HW expects these in little endian so we reverse the byte order 476 * from network order (big endian) to little endian 477 */ 478 rar_low = ((u32) addr[0] | 479 ((u32) addr[1] << 8) | 480 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 481 482 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 483 484 /* If MAC address zero, no need to set the AV bit */ 485 if (rar_low || rar_high) 486 rar_high |= E1000_RAH_AV; 487 488 /* 489 * Some bridges will combine consecutive 32-bit writes into 490 * a single burst write, which will malfunction on some parts. 491 * The flushes avoid this. 492 */ 493 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 494 E1000_WRITE_FLUSH(hw); 495 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 496 E1000_WRITE_FLUSH(hw); 497 } 498 499 /** 500 * e1000_update_mc_addr_list_generic - Update Multicast addresses 501 * @hw: pointer to the HW structure 502 * @mc_addr_list: array of multicast addresses to program 503 * @mc_addr_count: number of multicast addresses to program 504 * 505 * Updates entire Multicast Table Array. 506 * The caller must have a packed mc_addr_list of multicast addresses. 507 **/ 508 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw, 509 u8 *mc_addr_list, u32 mc_addr_count) 510 { 511 u32 hash_value, hash_bit, hash_reg; 512 int i; 513 514 DEBUGFUNC("e1000_update_mc_addr_list_generic"); 515 516 /* clear mta_shadow */ 517 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 518 519 /* update mta_shadow from mc_addr_list */ 520 for (i = 0; (u32) i < mc_addr_count; i++) { 521 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list); 522 523 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 524 hash_bit = hash_value & 0x1F; 525 526 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 527 mc_addr_list += (ETH_ADDR_LEN); 528 } 529 530 /* replace the entire MTA table */ 531 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 532 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 533 E1000_WRITE_FLUSH(hw); 534 } 535 536 /** 537 * e1000_hash_mc_addr_generic - Generate a multicast hash value 538 * @hw: pointer to the HW structure 539 * @mc_addr: pointer to a multicast address 540 * 541 * Generates a multicast address hash value which is used to determine 542 * the multicast filter table array address and new table value. 543 **/ 544 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 545 { 546 u32 hash_value, hash_mask; 547 u8 bit_shift = 0; 548 549 DEBUGFUNC("e1000_hash_mc_addr_generic"); 550 551 /* Register count multiplied by bits per register */ 552 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 553 554 /* 555 * For a mc_filter_type of 0, bit_shift is the number of left-shifts 556 * where 0xFF would still fall within the hash mask. 557 */ 558 while (hash_mask >> bit_shift != 0xFF) 559 bit_shift++; 560 561 /* 562 * The portion of the address that is used for the hash table 563 * is determined by the mc_filter_type setting. 564 * The algorithm is such that there is a total of 8 bits of shifting. 565 * The bit_shift for a mc_filter_type of 0 represents the number of 566 * left-shifts where the MSB of mc_addr[5] would still fall within 567 * the hash_mask. Case 0 does this exactly. Since there are a total 568 * of 8 bits of shifting, then mc_addr[4] will shift right the 569 * remaining number of bits. Thus 8 - bit_shift. The rest of the 570 * cases are a variation of this algorithm...essentially raising the 571 * number of bits to shift mc_addr[5] left, while still keeping the 572 * 8-bit shifting total. 573 * 574 * For example, given the following Destination MAC Address and an 575 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 576 * we can see that the bit_shift for case 0 is 4. These are the hash 577 * values resulting from each mc_filter_type... 578 * [0] [1] [2] [3] [4] [5] 579 * 01 AA 00 12 34 56 580 * LSB MSB 581 * 582 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 583 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 584 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 585 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 586 */ 587 switch (hw->mac.mc_filter_type) { 588 default: 589 case 0: 590 break; 591 case 1: 592 bit_shift += 1; 593 break; 594 case 2: 595 bit_shift += 2; 596 break; 597 case 3: 598 bit_shift += 4; 599 break; 600 } 601 602 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 603 (((u16) mc_addr[5]) << bit_shift))); 604 605 return hash_value; 606 } 607 608 /** 609 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value 610 * @hw: pointer to the HW structure 611 * 612 * In certain situations, a system BIOS may report that the PCIx maximum 613 * memory read byte count (MMRBC) value is higher than than the actual 614 * value. We check the PCIx command register with the current PCIx status 615 * register. 616 **/ 617 void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw) 618 { 619 u16 cmd_mmrbc; 620 u16 pcix_cmd; 621 u16 pcix_stat_hi_word; 622 u16 stat_mmrbc; 623 624 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); 625 626 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ 627 if (hw->bus.type != e1000_bus_type_pcix) 628 return; 629 630 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 631 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 632 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> 633 PCIX_COMMAND_MMRBC_SHIFT; 634 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 635 PCIX_STATUS_HI_MMRBC_SHIFT; 636 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 637 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 638 if (cmd_mmrbc > stat_mmrbc) { 639 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; 640 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 641 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 642 } 643 } 644 645 /** 646 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 647 * @hw: pointer to the HW structure 648 * 649 * Clears the base hardware counters by reading the counter registers. 650 **/ 651 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 652 { 653 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 654 655 E1000_READ_REG(hw, E1000_CRCERRS); 656 E1000_READ_REG(hw, E1000_SYMERRS); 657 E1000_READ_REG(hw, E1000_MPC); 658 E1000_READ_REG(hw, E1000_SCC); 659 E1000_READ_REG(hw, E1000_ECOL); 660 E1000_READ_REG(hw, E1000_MCC); 661 E1000_READ_REG(hw, E1000_LATECOL); 662 E1000_READ_REG(hw, E1000_COLC); 663 E1000_READ_REG(hw, E1000_DC); 664 E1000_READ_REG(hw, E1000_SEC); 665 E1000_READ_REG(hw, E1000_RLEC); 666 E1000_READ_REG(hw, E1000_XONRXC); 667 E1000_READ_REG(hw, E1000_XONTXC); 668 E1000_READ_REG(hw, E1000_XOFFRXC); 669 E1000_READ_REG(hw, E1000_XOFFTXC); 670 E1000_READ_REG(hw, E1000_FCRUC); 671 E1000_READ_REG(hw, E1000_GPRC); 672 E1000_READ_REG(hw, E1000_BPRC); 673 E1000_READ_REG(hw, E1000_MPRC); 674 E1000_READ_REG(hw, E1000_GPTC); 675 E1000_READ_REG(hw, E1000_GORCL); 676 E1000_READ_REG(hw, E1000_GORCH); 677 E1000_READ_REG(hw, E1000_GOTCL); 678 E1000_READ_REG(hw, E1000_GOTCH); 679 E1000_READ_REG(hw, E1000_RNBC); 680 E1000_READ_REG(hw, E1000_RUC); 681 E1000_READ_REG(hw, E1000_RFC); 682 E1000_READ_REG(hw, E1000_ROC); 683 E1000_READ_REG(hw, E1000_RJC); 684 E1000_READ_REG(hw, E1000_TORL); 685 E1000_READ_REG(hw, E1000_TORH); 686 E1000_READ_REG(hw, E1000_TOTL); 687 E1000_READ_REG(hw, E1000_TOTH); 688 E1000_READ_REG(hw, E1000_TPR); 689 E1000_READ_REG(hw, E1000_TPT); 690 E1000_READ_REG(hw, E1000_MPTC); 691 E1000_READ_REG(hw, E1000_BPTC); 692 } 693 694 /** 695 * e1000_check_for_copper_link_generic - Check for link (Copper) 696 * @hw: pointer to the HW structure 697 * 698 * Checks to see of the link status of the hardware has changed. If a 699 * change in link status has been detected, then we read the PHY registers 700 * to get the current speed/duplex if link exists. 701 **/ 702 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) 703 { 704 struct e1000_mac_info *mac = &hw->mac; 705 s32 ret_val; 706 bool link; 707 708 DEBUGFUNC("e1000_check_for_copper_link"); 709 710 /* 711 * We only want to go out to the PHY registers to see if Auto-Neg 712 * has completed and/or if our link status has changed. The 713 * get_link_status flag is set upon receiving a Link Status 714 * Change or Rx Sequence Error interrupt. 715 */ 716 if (!mac->get_link_status) { 717 ret_val = E1000_SUCCESS; 718 goto out; 719 } 720 721 /* 722 * First we want to see if the MII Status Register reports 723 * link. If so, then we want to get the current speed/duplex 724 * of the PHY. 725 */ 726 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 727 if (ret_val) 728 goto out; 729 730 if (!link) 731 goto out; /* No link detected */ 732 733 mac->get_link_status = FALSE; 734 735 /* 736 * Check if there was DownShift, must be checked 737 * immediately after link-up 738 */ 739 e1000_check_downshift_generic(hw); 740 741 /* 742 * If we are forcing speed/duplex, then we simply return since 743 * we have already determined whether we have link or not. 744 */ 745 if (!mac->autoneg) { 746 ret_val = -E1000_ERR_CONFIG; 747 goto out; 748 } 749 750 /* 751 * Auto-Neg is enabled. Auto Speed Detection takes care 752 * of MAC speed/duplex configuration. So we only need to 753 * configure Collision Distance in the MAC. 754 */ 755 mac->ops.config_collision_dist(hw); 756 757 /* 758 * Configure Flow Control now that Auto-Neg has completed. 759 * First, we need to restore the desired flow control 760 * settings because we may have had to re-autoneg with a 761 * different link partner. 762 */ 763 ret_val = e1000_config_fc_after_link_up_generic(hw); 764 if (ret_val) 765 DEBUGOUT("Error configuring flow control\n"); 766 767 out: 768 return ret_val; 769 } 770 771 /** 772 * e1000_check_for_fiber_link_generic - Check for link (Fiber) 773 * @hw: pointer to the HW structure 774 * 775 * Checks for link up on the hardware. If link is not up and we have 776 * a signal, then we need to force link up. 777 **/ 778 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 779 { 780 struct e1000_mac_info *mac = &hw->mac; 781 u32 rxcw; 782 u32 ctrl; 783 u32 status; 784 s32 ret_val = E1000_SUCCESS; 785 786 DEBUGFUNC("e1000_check_for_fiber_link_generic"); 787 788 ctrl = E1000_READ_REG(hw, E1000_CTRL); 789 status = E1000_READ_REG(hw, E1000_STATUS); 790 rxcw = E1000_READ_REG(hw, E1000_RXCW); 791 792 /* 793 * If we don't have link (auto-negotiation failed or link partner 794 * cannot auto-negotiate), the cable is plugged in (we have signal), 795 * and our link partner is not trying to auto-negotiate with us (we 796 * are receiving idles or data), we need to force link up. We also 797 * need to give auto-negotiation time to complete, in case the cable 798 * was just plugged in. The autoneg_failed flag does this. 799 */ 800 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 801 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) && 802 (!(rxcw & E1000_RXCW_C))) { 803 if (mac->autoneg_failed == 0) { 804 mac->autoneg_failed = 1; 805 goto out; 806 } 807 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 808 809 /* Disable auto-negotiation in the TXCW register */ 810 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 811 812 /* Force link-up and also force full-duplex. */ 813 ctrl = E1000_READ_REG(hw, E1000_CTRL); 814 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 815 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 816 817 /* Configure Flow Control after forcing link up. */ 818 ret_val = e1000_config_fc_after_link_up_generic(hw); 819 if (ret_val) { 820 DEBUGOUT("Error configuring flow control\n"); 821 goto out; 822 } 823 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 824 /* 825 * If we are forcing link and we are receiving /C/ ordered 826 * sets, re-enable auto-negotiation in the TXCW register 827 * and disable forced link in the Device Control register 828 * in an attempt to auto-negotiate with our link partner. 829 */ 830 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 831 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 832 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 833 834 mac->serdes_has_link = TRUE; 835 } 836 837 out: 838 return ret_val; 839 } 840 841 /** 842 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 843 * @hw: pointer to the HW structure 844 * 845 * Checks for link up on the hardware. If link is not up and we have 846 * a signal, then we need to force link up. 847 **/ 848 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 849 { 850 struct e1000_mac_info *mac = &hw->mac; 851 u32 rxcw; 852 u32 ctrl; 853 u32 status; 854 s32 ret_val = E1000_SUCCESS; 855 856 DEBUGFUNC("e1000_check_for_serdes_link_generic"); 857 858 ctrl = E1000_READ_REG(hw, E1000_CTRL); 859 status = E1000_READ_REG(hw, E1000_STATUS); 860 rxcw = E1000_READ_REG(hw, E1000_RXCW); 861 862 /* 863 * If we don't have link (auto-negotiation failed or link partner 864 * cannot auto-negotiate), and our link partner is not trying to 865 * auto-negotiate with us (we are receiving idles or data), 866 * we need to force link up. We also need to give auto-negotiation 867 * time to complete. 868 */ 869 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 870 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 871 if (mac->autoneg_failed == 0) { 872 mac->autoneg_failed = 1; 873 goto out; 874 } 875 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 876 877 /* Disable auto-negotiation in the TXCW register */ 878 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 879 880 /* Force link-up and also force full-duplex. */ 881 ctrl = E1000_READ_REG(hw, E1000_CTRL); 882 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 883 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 884 885 /* Configure Flow Control after forcing link up. */ 886 ret_val = e1000_config_fc_after_link_up_generic(hw); 887 if (ret_val) { 888 DEBUGOUT("Error configuring flow control\n"); 889 goto out; 890 } 891 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 892 /* 893 * If we are forcing link and we are receiving /C/ ordered 894 * sets, re-enable auto-negotiation in the TXCW register 895 * and disable forced link in the Device Control register 896 * in an attempt to auto-negotiate with our link partner. 897 */ 898 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 899 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 900 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 901 902 mac->serdes_has_link = TRUE; 903 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 904 /* 905 * If we force link for non-auto-negotiation switch, check 906 * link status based on MAC synchronization for internal 907 * serdes media type. 908 */ 909 /* SYNCH bit and IV bit are sticky. */ 910 usec_delay(10); 911 rxcw = E1000_READ_REG(hw, E1000_RXCW); 912 if (rxcw & E1000_RXCW_SYNCH) { 913 if (!(rxcw & E1000_RXCW_IV)) { 914 mac->serdes_has_link = TRUE; 915 DEBUGOUT("SERDES: Link up - forced.\n"); 916 } 917 } else { 918 mac->serdes_has_link = FALSE; 919 DEBUGOUT("SERDES: Link down - force failed.\n"); 920 } 921 } 922 923 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 924 status = E1000_READ_REG(hw, E1000_STATUS); 925 if (status & E1000_STATUS_LU) { 926 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 927 usec_delay(10); 928 rxcw = E1000_READ_REG(hw, E1000_RXCW); 929 if (rxcw & E1000_RXCW_SYNCH) { 930 if (!(rxcw & E1000_RXCW_IV)) { 931 mac->serdes_has_link = TRUE; 932 DEBUGOUT("SERDES: Link up - autoneg " 933 "completed sucessfully.\n"); 934 } else { 935 mac->serdes_has_link = FALSE; 936 DEBUGOUT("SERDES: Link down - invalid" 937 "codewords detected in autoneg.\n"); 938 } 939 } else { 940 mac->serdes_has_link = FALSE; 941 DEBUGOUT("SERDES: Link down - no sync.\n"); 942 } 943 } else { 944 mac->serdes_has_link = FALSE; 945 DEBUGOUT("SERDES: Link down - autoneg failed\n"); 946 } 947 } 948 949 out: 950 return ret_val; 951 } 952 953 /** 954 * e1000_setup_link_generic - Setup flow control and link settings 955 * @hw: pointer to the HW structure 956 * 957 * Determines which flow control settings to use, then configures flow 958 * control. Calls the appropriate media-specific link configuration 959 * function. Assuming the adapter has a valid link partner, a valid link 960 * should be established. Assumes the hardware has previously been reset 961 * and the transmitter and receiver are not enabled. 962 **/ 963 s32 e1000_setup_link_generic(struct e1000_hw *hw) 964 { 965 s32 ret_val = E1000_SUCCESS; 966 967 DEBUGFUNC("e1000_setup_link_generic"); 968 969 /* 970 * In the case of the phy reset being blocked, we already have a link. 971 * We do not need to set it up again. 972 */ 973 if (e1000_check_reset_block(hw)) 974 goto out; 975 976 /* 977 * If requested flow control is set to default, set flow control 978 * based on the EEPROM flow control settings. 979 */ 980 if (hw->fc.requested_mode == e1000_fc_default) { 981 ret_val = e1000_set_default_fc_generic(hw); 982 if (ret_val) 983 goto out; 984 } 985 986 /* 987 * Save off the requested flow control mode for use later. Depending 988 * on the link partner's capabilities, we may or may not use this mode. 989 */ 990 hw->fc.current_mode = hw->fc.requested_mode; 991 992 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 993 hw->fc.current_mode); 994 995 /* Call the necessary media_type subroutine to configure the link. */ 996 ret_val = hw->mac.ops.setup_physical_interface(hw); 997 if (ret_val) 998 goto out; 999 1000 /* 1001 * Initialize the flow control address, type, and PAUSE timer 1002 * registers to their default values. This is done even if flow 1003 * control is disabled, because it does not hurt anything to 1004 * initialize these registers. 1005 */ 1006 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 1007 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 1008 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1009 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 1010 1011 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 1012 1013 ret_val = e1000_set_fc_watermarks_generic(hw); 1014 1015 out: 1016 return ret_val; 1017 } 1018 1019 /** 1020 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 1021 * @hw: pointer to the HW structure 1022 * 1023 * Configures collision distance and flow control for fiber and serdes 1024 * links. Upon successful setup, poll for link. 1025 **/ 1026 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 1027 { 1028 struct e1000_mac_info *mac = &hw->mac; 1029 u32 ctrl; 1030 s32 ret_val = E1000_SUCCESS; 1031 1032 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 1033 1034 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1035 1036 /* Take the link out of reset */ 1037 ctrl &= ~E1000_CTRL_LRST; 1038 1039 mac->ops.config_collision_dist(hw); 1040 1041 ret_val = e1000_commit_fc_settings_generic(hw); 1042 if (ret_val) 1043 goto out; 1044 1045 /* 1046 * Since auto-negotiation is enabled, take the link out of reset (the 1047 * link will be in reset, because we previously reset the chip). This 1048 * will restart auto-negotiation. If auto-negotiation is successful 1049 * then the link-up status bit will be set and the flow control enable 1050 * bits (RFCE and TFCE) will be set according to their negotiated value. 1051 */ 1052 DEBUGOUT("Auto-negotiation enabled\n"); 1053 1054 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1055 E1000_WRITE_FLUSH(hw); 1056 msec_delay(1); 1057 1058 /* 1059 * For these adapters, the SW definable pin 1 is set when the optics 1060 * detect a signal. If we have a signal, then poll for a "Link-Up" 1061 * indication. 1062 */ 1063 if (hw->phy.media_type == e1000_media_type_internal_serdes || 1064 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1065 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1066 } else { 1067 DEBUGOUT("No signal detected\n"); 1068 } 1069 1070 out: 1071 return ret_val; 1072 } 1073 1074 /** 1075 * e1000_config_collision_dist_generic - Configure collision distance 1076 * @hw: pointer to the HW structure 1077 * 1078 * Configures the collision distance to the default value and is used 1079 * during link setup. 1080 **/ 1081 void e1000_config_collision_dist_generic(struct e1000_hw *hw) 1082 { 1083 u32 tctl; 1084 1085 DEBUGFUNC("e1000_config_collision_dist_generic"); 1086 1087 tctl = E1000_READ_REG(hw, E1000_TCTL); 1088 1089 tctl &= ~E1000_TCTL_COLD; 1090 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1091 1092 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 1093 E1000_WRITE_FLUSH(hw); 1094 } 1095 1096 /** 1097 * e1000_poll_fiber_serdes_link_generic - Poll for link up 1098 * @hw: pointer to the HW structure 1099 * 1100 * Polls for link up by reading the status register, if link fails to come 1101 * up with auto-negotiation, then the link is forced if a signal is detected. 1102 **/ 1103 s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 1104 { 1105 struct e1000_mac_info *mac = &hw->mac; 1106 u32 i, status; 1107 s32 ret_val = E1000_SUCCESS; 1108 1109 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 1110 1111 /* 1112 * If we have a signal (the cable is plugged in, or assumed TRUE for 1113 * serdes media) then poll for a "Link-Up" indication in the Device 1114 * Status Register. Time-out if a link isn't seen in 500 milliseconds 1115 * seconds (Auto-negotiation should complete in less than 500 1116 * milliseconds even if the other end is doing it in SW). 1117 */ 1118 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 1119 msec_delay(10); 1120 status = E1000_READ_REG(hw, E1000_STATUS); 1121 if (status & E1000_STATUS_LU) 1122 break; 1123 } 1124 if (i == FIBER_LINK_UP_LIMIT) { 1125 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1126 mac->autoneg_failed = 1; 1127 /* 1128 * AutoNeg failed to achieve a link, so we'll call 1129 * mac->check_for_link. This routine will force the 1130 * link up if we detect a signal. This will allow us to 1131 * communicate with non-autonegotiating link partners. 1132 */ 1133 ret_val = mac->ops.check_for_link(hw); 1134 if (ret_val) { 1135 DEBUGOUT("Error while checking for link\n"); 1136 goto out; 1137 } 1138 mac->autoneg_failed = 0; 1139 } else { 1140 mac->autoneg_failed = 0; 1141 DEBUGOUT("Valid Link Found\n"); 1142 } 1143 1144 out: 1145 return ret_val; 1146 } 1147 1148 /** 1149 * e1000_commit_fc_settings_generic - Configure flow control 1150 * @hw: pointer to the HW structure 1151 * 1152 * Write the flow control settings to the Transmit Config Word Register (TXCW) 1153 * base on the flow control settings in e1000_mac_info. 1154 **/ 1155 s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 1156 { 1157 struct e1000_mac_info *mac = &hw->mac; 1158 u32 txcw; 1159 s32 ret_val = E1000_SUCCESS; 1160 1161 DEBUGFUNC("e1000_commit_fc_settings_generic"); 1162 1163 /* 1164 * Check for a software override of the flow control settings, and 1165 * setup the device accordingly. If auto-negotiation is enabled, then 1166 * software will have to set the "PAUSE" bits to the correct value in 1167 * the Transmit Config Word Register (TXCW) and re-start auto- 1168 * negotiation. However, if auto-negotiation is disabled, then 1169 * software will have to manually configure the two flow control enable 1170 * bits in the CTRL register. 1171 * 1172 * The possible values of the "fc" parameter are: 1173 * 0: Flow control is completely disabled 1174 * 1: Rx flow control is enabled (we can receive pause frames, 1175 * but not send pause frames). 1176 * 2: Tx flow control is enabled (we can send pause frames but we 1177 * do not support receiving pause frames). 1178 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1179 */ 1180 switch (hw->fc.current_mode) { 1181 case e1000_fc_none: 1182 /* Flow control completely disabled by a software over-ride. */ 1183 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1184 break; 1185 case e1000_fc_rx_pause: 1186 /* 1187 * Rx Flow control is enabled and Tx Flow control is disabled 1188 * by a software over-ride. Since there really isn't a way to 1189 * advertise that we are capable of Rx Pause ONLY, we will 1190 * advertise that we support both symmetric and asymmetric Rx 1191 * PAUSE. Later, we will disable the adapter's ability to send 1192 * PAUSE frames. 1193 */ 1194 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1195 break; 1196 case e1000_fc_tx_pause: 1197 /* 1198 * Tx Flow control is enabled, and Rx Flow control is disabled, 1199 * by a software over-ride. 1200 */ 1201 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1202 break; 1203 case e1000_fc_full: 1204 /* 1205 * Flow control (both Rx and Tx) is enabled by a software 1206 * over-ride. 1207 */ 1208 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1209 break; 1210 default: 1211 DEBUGOUT("Flow control param set incorrectly\n"); 1212 ret_val = -E1000_ERR_CONFIG; 1213 goto out; 1214 break; 1215 } 1216 1217 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1218 mac->txcw = txcw; 1219 1220 out: 1221 return ret_val; 1222 } 1223 1224 /** 1225 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 1226 * @hw: pointer to the HW structure 1227 * 1228 * Sets the flow control high/low threshold (watermark) registers. If 1229 * flow control XON frame transmission is enabled, then set XON frame 1230 * transmission as well. 1231 **/ 1232 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 1233 { 1234 u32 fcrtl = 0, fcrth = 0; 1235 1236 DEBUGFUNC("e1000_set_fc_watermarks_generic"); 1237 1238 /* 1239 * Set the flow control receive threshold registers. Normally, 1240 * these registers will be set to a default threshold that may be 1241 * adjusted later by the driver's runtime code. However, if the 1242 * ability to transmit pause frames is not enabled, then these 1243 * registers will be set to 0. 1244 */ 1245 if (hw->fc.current_mode & e1000_fc_tx_pause) { 1246 /* 1247 * We need to set up the Receive Threshold high and low water 1248 * marks as well as (optionally) enabling the transmission of 1249 * XON frames. 1250 */ 1251 fcrtl = hw->fc.low_water; 1252 if (hw->fc.send_xon) 1253 fcrtl |= E1000_FCRTL_XONE; 1254 1255 fcrth = hw->fc.high_water; 1256 } 1257 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 1258 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 1259 1260 return E1000_SUCCESS; 1261 } 1262 1263 /** 1264 * e1000_set_default_fc_generic - Set flow control default values 1265 * @hw: pointer to the HW structure 1266 * 1267 * Read the EEPROM for the default values for flow control and store the 1268 * values. 1269 **/ 1270 #ifdef NO_82542_SUPPORT 1271 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw) 1272 #else 1273 s32 e1000_set_default_fc_generic(struct e1000_hw *hw) 1274 #endif 1275 { 1276 s32 ret_val = E1000_SUCCESS; 1277 u16 nvm_data; 1278 1279 DEBUGFUNC("e1000_set_default_fc_generic"); 1280 1281 /* 1282 * Read and store word 0x0F of the EEPROM. This word contains bits 1283 * that determine the hardware's default PAUSE (flow control) mode, 1284 * a bit that determines whether the HW defaults to enabling or 1285 * disabling auto-negotiation, and the direction of the 1286 * SW defined pins. If there is no SW over-ride of the flow 1287 * control setting, then the variable hw->fc will 1288 * be initialized based on a value in the EEPROM. 1289 */ 1290 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); 1291 1292 if (ret_val) { 1293 DEBUGOUT("NVM Read Error\n"); 1294 goto out; 1295 } 1296 1297 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) 1298 hw->fc.requested_mode = e1000_fc_none; 1299 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 1300 NVM_WORD0F_ASM_DIR) 1301 hw->fc.requested_mode = e1000_fc_tx_pause; 1302 else 1303 hw->fc.requested_mode = e1000_fc_full; 1304 1305 out: 1306 return ret_val; 1307 } 1308 1309 /** 1310 * e1000_force_mac_fc_generic - Force the MAC's flow control settings 1311 * @hw: pointer to the HW structure 1312 * 1313 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 1314 * device control register to reflect the adapter settings. TFCE and RFCE 1315 * need to be explicitly set by software when a copper PHY is used because 1316 * autonegotiation is managed by the PHY rather than the MAC. Software must 1317 * also configure these bits when link is forced on a fiber connection. 1318 **/ 1319 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw) 1320 { 1321 u32 ctrl; 1322 s32 ret_val = E1000_SUCCESS; 1323 1324 DEBUGFUNC("e1000_force_mac_fc_generic"); 1325 1326 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1327 1328 /* 1329 * Because we didn't get link via the internal auto-negotiation 1330 * mechanism (we either forced link or we got link via PHY 1331 * auto-neg), we have to manually enable/disable transmit an 1332 * receive flow control. 1333 * 1334 * The "Case" statement below enables/disable flow control 1335 * according to the "hw->fc.current_mode" parameter. 1336 * 1337 * The possible values of the "fc" parameter are: 1338 * 0: Flow control is completely disabled 1339 * 1: Rx flow control is enabled (we can receive pause 1340 * frames but not send pause frames). 1341 * 2: Tx flow control is enabled (we can send pause frames 1342 * frames but we do not receive pause frames). 1343 * 3: Both Rx and Tx flow control (symmetric) is enabled. 1344 * other: No other values should be possible at this point. 1345 */ 1346 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); 1347 1348 switch (hw->fc.current_mode) { 1349 case e1000_fc_none: 1350 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1351 break; 1352 case e1000_fc_rx_pause: 1353 ctrl &= (~E1000_CTRL_TFCE); 1354 ctrl |= E1000_CTRL_RFCE; 1355 break; 1356 case e1000_fc_tx_pause: 1357 ctrl &= (~E1000_CTRL_RFCE); 1358 ctrl |= E1000_CTRL_TFCE; 1359 break; 1360 case e1000_fc_full: 1361 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1362 break; 1363 default: 1364 DEBUGOUT("Flow control param set incorrectly\n"); 1365 ret_val = -E1000_ERR_CONFIG; 1366 goto out; 1367 } 1368 1369 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1370 1371 out: 1372 return ret_val; 1373 } 1374 1375 /** 1376 * e1000_config_fc_after_link_up_generic - Configures flow control after link 1377 * @hw: pointer to the HW structure 1378 * 1379 * Checks the status of auto-negotiation after link up to ensure that the 1380 * speed and duplex were not forced. If the link needed to be forced, then 1381 * flow control needs to be forced also. If auto-negotiation is enabled 1382 * and did not fail, then we configure flow control based on our link 1383 * partner. 1384 **/ 1385 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 1386 { 1387 struct e1000_mac_info *mac = &hw->mac; 1388 s32 ret_val = E1000_SUCCESS; 1389 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1390 u16 speed, duplex; 1391 1392 DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 1393 1394 /* 1395 * Check for the case where we have fiber media and auto-neg failed 1396 * so we had to force link. In this case, we need to force the 1397 * configuration of the MAC to match the "fc" parameter. 1398 */ 1399 if (mac->autoneg_failed) { 1400 if (hw->phy.media_type == e1000_media_type_fiber || 1401 hw->phy.media_type == e1000_media_type_internal_serdes) 1402 ret_val = e1000_force_mac_fc_generic(hw); 1403 } else { 1404 if (hw->phy.media_type == e1000_media_type_copper) 1405 ret_val = e1000_force_mac_fc_generic(hw); 1406 } 1407 1408 if (ret_val) { 1409 DEBUGOUT("Error forcing flow control settings\n"); 1410 goto out; 1411 } 1412 1413 /* 1414 * Check for the case where we have copper media and auto-neg is 1415 * enabled. In this case, we need to check and see if Auto-Neg 1416 * has completed, and if so, how the PHY and link partner has 1417 * flow control configured. 1418 */ 1419 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1420 /* 1421 * Read the MII Status Register and check to see if AutoNeg 1422 * has completed. We read this twice because this reg has 1423 * some "sticky" (latched) bits. 1424 */ 1425 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1426 if (ret_val) 1427 goto out; 1428 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1429 if (ret_val) 1430 goto out; 1431 1432 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1433 DEBUGOUT("Copper PHY and Auto Neg " 1434 "has not completed.\n"); 1435 goto out; 1436 } 1437 1438 /* 1439 * The AutoNeg process has completed, so we now need to 1440 * read both the Auto Negotiation Advertisement 1441 * Register (Address 4) and the Auto_Negotiation Base 1442 * Page Ability Register (Address 5) to determine how 1443 * flow control was negotiated. 1444 */ 1445 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 1446 &mii_nway_adv_reg); 1447 if (ret_val) 1448 goto out; 1449 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 1450 &mii_nway_lp_ability_reg); 1451 if (ret_val) 1452 goto out; 1453 1454 /* 1455 * Two bits in the Auto Negotiation Advertisement Register 1456 * (Address 4) and two bits in the Auto Negotiation Base 1457 * Page Ability Register (Address 5) determine flow control 1458 * for both the PHY and the link partner. The following 1459 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1460 * 1999, describes these PAUSE resolution bits and how flow 1461 * control is determined based upon these settings. 1462 * NOTE: DC = Don't Care 1463 * 1464 * LOCAL DEVICE | LINK PARTNER 1465 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1466 *-------|---------|-------|---------|-------------------- 1467 * 0 | 0 | DC | DC | e1000_fc_none 1468 * 0 | 1 | 0 | DC | e1000_fc_none 1469 * 0 | 1 | 1 | 0 | e1000_fc_none 1470 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1471 * 1 | 0 | 0 | DC | e1000_fc_none 1472 * 1 | DC | 1 | DC | e1000_fc_full 1473 * 1 | 1 | 0 | 0 | e1000_fc_none 1474 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1475 * 1476 * Are both PAUSE bits set to 1? If so, this implies 1477 * Symmetric Flow Control is enabled at both ends. The 1478 * ASM_DIR bits are irrelevant per the spec. 1479 * 1480 * For Symmetric Flow Control: 1481 * 1482 * LOCAL DEVICE | LINK PARTNER 1483 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1484 *-------|---------|-------|---------|-------------------- 1485 * 1 | DC | 1 | DC | E1000_fc_full 1486 * 1487 */ 1488 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1489 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1490 /* 1491 * Now we need to check if the user selected Rx ONLY 1492 * of pause frames. In this case, we had to advertise 1493 * FULL flow control because we could not advertise Rx 1494 * ONLY. Hence, we must now check to see if we need to 1495 * turn OFF the TRANSMISSION of PAUSE frames. 1496 */ 1497 if (hw->fc.requested_mode == e1000_fc_full) { 1498 hw->fc.current_mode = e1000_fc_full; 1499 DEBUGOUT("Flow Control = FULL.\r\n"); 1500 } else { 1501 hw->fc.current_mode = e1000_fc_rx_pause; 1502 DEBUGOUT("Flow Control = " 1503 "Rx PAUSE frames only.\r\n"); 1504 } 1505 } 1506 /* 1507 * For receiving PAUSE frames ONLY. 1508 * 1509 * LOCAL DEVICE | LINK PARTNER 1510 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1511 *-------|---------|-------|---------|-------------------- 1512 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1513 */ 1514 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1515 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1516 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1517 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1518 hw->fc.current_mode = e1000_fc_tx_pause; 1519 DEBUGOUT("Flow Control = Tx PAUSE frames only.\r\n"); 1520 } 1521 /* 1522 * For transmitting PAUSE frames ONLY. 1523 * 1524 * LOCAL DEVICE | LINK PARTNER 1525 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1526 *-------|---------|-------|---------|-------------------- 1527 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1528 */ 1529 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1530 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1531 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1532 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1533 hw->fc.current_mode = e1000_fc_rx_pause; 1534 DEBUGOUT("Flow Control = Rx PAUSE frames only.\r\n"); 1535 } else { 1536 /* 1537 * Per the IEEE spec, at this point flow control 1538 * should be disabled. 1539 */ 1540 hw->fc.current_mode = e1000_fc_none; 1541 DEBUGOUT("Flow Control = NONE.\r\n"); 1542 } 1543 1544 /* 1545 * Now we need to do one last check... If we auto- 1546 * negotiated to HALF DUPLEX, flow control should not be 1547 * enabled per IEEE 802.3 spec. 1548 */ 1549 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1550 if (ret_val) { 1551 DEBUGOUT("Error getting link speed and duplex\n"); 1552 goto out; 1553 } 1554 1555 if (duplex == HALF_DUPLEX) 1556 hw->fc.current_mode = e1000_fc_none; 1557 1558 /* 1559 * Now we call a subroutine to actually force the MAC 1560 * controller to use the correct flow control settings. 1561 */ 1562 ret_val = e1000_force_mac_fc_generic(hw); 1563 if (ret_val) { 1564 DEBUGOUT("Error forcing flow control settings\n"); 1565 goto out; 1566 } 1567 } 1568 1569 out: 1570 return ret_val; 1571 } 1572 1573 /** 1574 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 1575 * @hw: pointer to the HW structure 1576 * @speed: stores the current speed 1577 * @duplex: stores the current duplex 1578 * 1579 * Read the status register for the current speed/duplex and store the current 1580 * speed and duplex for copper connections. 1581 **/ 1582 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 1583 u16 *duplex) 1584 { 1585 u32 status; 1586 1587 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 1588 1589 status = E1000_READ_REG(hw, E1000_STATUS); 1590 if (status & E1000_STATUS_SPEED_1000) { 1591 *speed = SPEED_1000; 1592 DEBUGOUT("1000 Mbs, "); 1593 } else if (status & E1000_STATUS_SPEED_100) { 1594 *speed = SPEED_100; 1595 DEBUGOUT("100 Mbs, "); 1596 } else { 1597 *speed = SPEED_10; 1598 DEBUGOUT("10 Mbs, "); 1599 } 1600 1601 if (status & E1000_STATUS_FD) { 1602 *duplex = FULL_DUPLEX; 1603 DEBUGOUT("Full Duplex\n"); 1604 } else { 1605 *duplex = HALF_DUPLEX; 1606 DEBUGOUT("Half Duplex\n"); 1607 } 1608 1609 return E1000_SUCCESS; 1610 } 1611 1612 /** 1613 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex 1614 * @hw: pointer to the HW structure 1615 * @speed: stores the current speed 1616 * @duplex: stores the current duplex 1617 * 1618 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1619 * for fiber/serdes links. 1620 **/ 1621 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw, 1622 u16 *speed, u16 *duplex) 1623 { 1624 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 1625 1626 *speed = SPEED_1000; 1627 *duplex = FULL_DUPLEX; 1628 1629 return E1000_SUCCESS; 1630 } 1631 1632 /** 1633 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 1634 * @hw: pointer to the HW structure 1635 * 1636 * Acquire the HW semaphore to access the PHY or NVM 1637 **/ 1638 s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 1639 { 1640 u32 swsm; 1641 s32 ret_val = E1000_SUCCESS; 1642 s32 timeout = hw->nvm.word_size + 1; 1643 s32 i = 0; 1644 1645 DEBUGFUNC("e1000_get_hw_semaphore_generic"); 1646 1647 /* Get the SW semaphore */ 1648 while (i < timeout) { 1649 swsm = E1000_READ_REG(hw, E1000_SWSM); 1650 if (!(swsm & E1000_SWSM_SMBI)) 1651 break; 1652 1653 usec_delay(50); 1654 i++; 1655 } 1656 1657 if (i == timeout) { 1658 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1659 ret_val = -E1000_ERR_NVM; 1660 goto out; 1661 } 1662 1663 /* Get the FW semaphore. */ 1664 for (i = 0; i < timeout; i++) { 1665 swsm = E1000_READ_REG(hw, E1000_SWSM); 1666 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 1667 1668 /* Semaphore acquired if bit latched */ 1669 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 1670 break; 1671 1672 usec_delay(50); 1673 } 1674 1675 if (i == timeout) { 1676 /* Release semaphores */ 1677 e1000_put_hw_semaphore_generic(hw); 1678 DEBUGOUT("Driver can't access the NVM\n"); 1679 ret_val = -E1000_ERR_NVM; 1680 goto out; 1681 } 1682 1683 out: 1684 return ret_val; 1685 } 1686 1687 /** 1688 * e1000_put_hw_semaphore_generic - Release hardware semaphore 1689 * @hw: pointer to the HW structure 1690 * 1691 * Release hardware semaphore used to access the PHY or NVM 1692 **/ 1693 void e1000_put_hw_semaphore_generic(struct e1000_hw *hw) 1694 { 1695 u32 swsm; 1696 1697 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 1698 1699 swsm = E1000_READ_REG(hw, E1000_SWSM); 1700 1701 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1702 1703 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 1704 } 1705 1706 /** 1707 * e1000_get_auto_rd_done_generic - Check for auto read completion 1708 * @hw: pointer to the HW structure 1709 * 1710 * Check EEPROM for Auto Read done bit. 1711 **/ 1712 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 1713 { 1714 s32 i = 0; 1715 s32 ret_val = E1000_SUCCESS; 1716 1717 DEBUGFUNC("e1000_get_auto_rd_done_generic"); 1718 1719 while (i < AUTO_READ_DONE_TIMEOUT) { 1720 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 1721 break; 1722 msec_delay(1); 1723 i++; 1724 } 1725 1726 if (i == AUTO_READ_DONE_TIMEOUT) { 1727 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1728 ret_val = -E1000_ERR_RESET; 1729 goto out; 1730 } 1731 1732 out: 1733 return ret_val; 1734 } 1735 1736 /** 1737 * e1000_valid_led_default_generic - Verify a valid default LED config 1738 * @hw: pointer to the HW structure 1739 * @data: pointer to the NVM (EEPROM) 1740 * 1741 * Read the EEPROM for the current default LED configuration. If the 1742 * LED configuration is not valid, set to a valid LED configuration. 1743 **/ 1744 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 1745 { 1746 s32 ret_val; 1747 1748 DEBUGFUNC("e1000_valid_led_default_generic"); 1749 1750 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1751 if (ret_val) { 1752 DEBUGOUT("NVM Read Error\n"); 1753 goto out; 1754 } 1755 1756 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1757 *data = ID_LED_DEFAULT; 1758 1759 out: 1760 return ret_val; 1761 } 1762 1763 /** 1764 * e1000_id_led_init_generic - 1765 * @hw: pointer to the HW structure 1766 * 1767 **/ 1768 s32 e1000_id_led_init_generic(struct e1000_hw *hw) 1769 { 1770 struct e1000_mac_info *mac = &hw->mac; 1771 s32 ret_val; 1772 const u32 ledctl_mask = 0x000000FF; 1773 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1774 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1775 u16 data, i, temp; 1776 const u16 led_mask = 0x0F; 1777 1778 DEBUGFUNC("e1000_id_led_init_generic"); 1779 1780 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 1781 if (ret_val) 1782 goto out; 1783 1784 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 1785 mac->ledctl_mode1 = mac->ledctl_default; 1786 mac->ledctl_mode2 = mac->ledctl_default; 1787 1788 for (i = 0; i < 4; i++) { 1789 temp = (data >> (i << 2)) & led_mask; 1790 switch (temp) { 1791 case ID_LED_ON1_DEF2: 1792 case ID_LED_ON1_ON2: 1793 case ID_LED_ON1_OFF2: 1794 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1795 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1796 break; 1797 case ID_LED_OFF1_DEF2: 1798 case ID_LED_OFF1_ON2: 1799 case ID_LED_OFF1_OFF2: 1800 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1801 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1802 break; 1803 default: 1804 /* Do nothing */ 1805 break; 1806 } 1807 switch (temp) { 1808 case ID_LED_DEF1_ON2: 1809 case ID_LED_ON1_ON2: 1810 case ID_LED_OFF1_ON2: 1811 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1812 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1813 break; 1814 case ID_LED_DEF1_OFF2: 1815 case ID_LED_ON1_OFF2: 1816 case ID_LED_OFF1_OFF2: 1817 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1818 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1819 break; 1820 default: 1821 /* Do nothing */ 1822 break; 1823 } 1824 } 1825 1826 out: 1827 return ret_val; 1828 } 1829 1830 /** 1831 * e1000_setup_led_generic - Configures SW controllable LED 1832 * @hw: pointer to the HW structure 1833 * 1834 * This prepares the SW controllable LED for use and saves the current state 1835 * of the LED so it can be later restored. 1836 **/ 1837 s32 e1000_setup_led_generic(struct e1000_hw *hw) 1838 { 1839 u32 ledctl; 1840 s32 ret_val = E1000_SUCCESS; 1841 1842 DEBUGFUNC("e1000_setup_led_generic"); 1843 1844 if (hw->mac.ops.setup_led != e1000_setup_led_generic) { 1845 ret_val = -E1000_ERR_CONFIG; 1846 goto out; 1847 } 1848 1849 if (hw->phy.media_type == e1000_media_type_fiber) { 1850 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 1851 hw->mac.ledctl_default = ledctl; 1852 /* Turn off LED0 */ 1853 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | 1854 E1000_LEDCTL_LED0_BLINK | 1855 E1000_LEDCTL_LED0_MODE_MASK); 1856 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1857 E1000_LEDCTL_LED0_MODE_SHIFT); 1858 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 1859 } else if (hw->phy.media_type == e1000_media_type_copper) { 1860 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1861 } 1862 1863 out: 1864 return ret_val; 1865 } 1866 1867 /** 1868 * e1000_cleanup_led_generic - Set LED config to default operation 1869 * @hw: pointer to the HW structure 1870 * 1871 * Remove the current LED configuration and set the LED configuration 1872 * to the default value, saved from the EEPROM. 1873 **/ 1874 s32 e1000_cleanup_led_generic(struct e1000_hw *hw) 1875 { 1876 DEBUGFUNC("e1000_cleanup_led_generic"); 1877 1878 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1879 return E1000_SUCCESS; 1880 } 1881 1882 /** 1883 * e1000_blink_led_generic - Blink LED 1884 * @hw: pointer to the HW structure 1885 * 1886 * Blink the LEDs which are set to be on. 1887 **/ 1888 s32 e1000_blink_led_generic(struct e1000_hw *hw) 1889 { 1890 u32 ledctl_blink = 0; 1891 u32 i; 1892 1893 DEBUGFUNC("e1000_blink_led_generic"); 1894 1895 if (hw->phy.media_type == e1000_media_type_fiber) { 1896 /* always blink LED0 for PCI-E fiber */ 1897 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1898 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1899 } else { 1900 /* 1901 * set the blink bit for each LED that's "on" (0x0E) 1902 * in ledctl_mode2 1903 */ 1904 ledctl_blink = hw->mac.ledctl_mode2; 1905 for (i = 0; i < 4; i++) 1906 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1907 E1000_LEDCTL_MODE_LED_ON) 1908 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << 1909 (i * 8)); 1910 } 1911 1912 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 1913 1914 return E1000_SUCCESS; 1915 } 1916 1917 /** 1918 * e1000_led_on_generic - Turn LED on 1919 * @hw: pointer to the HW structure 1920 * 1921 * Turn LED on. 1922 **/ 1923 s32 e1000_led_on_generic(struct e1000_hw *hw) 1924 { 1925 u32 ctrl; 1926 1927 DEBUGFUNC("e1000_led_on_generic"); 1928 1929 switch (hw->phy.media_type) { 1930 case e1000_media_type_fiber: 1931 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1932 ctrl &= ~E1000_CTRL_SWDPIN0; 1933 ctrl |= E1000_CTRL_SWDPIO0; 1934 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1935 break; 1936 case e1000_media_type_copper: 1937 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 1938 break; 1939 default: 1940 break; 1941 } 1942 1943 return E1000_SUCCESS; 1944 } 1945 1946 /** 1947 * e1000_led_off_generic - Turn LED off 1948 * @hw: pointer to the HW structure 1949 * 1950 * Turn LED off. 1951 **/ 1952 s32 e1000_led_off_generic(struct e1000_hw *hw) 1953 { 1954 u32 ctrl; 1955 1956 DEBUGFUNC("e1000_led_off_generic"); 1957 1958 switch (hw->phy.media_type) { 1959 case e1000_media_type_fiber: 1960 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1961 ctrl |= E1000_CTRL_SWDPIN0; 1962 ctrl |= E1000_CTRL_SWDPIO0; 1963 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1964 break; 1965 case e1000_media_type_copper: 1966 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1967 break; 1968 default: 1969 break; 1970 } 1971 1972 return E1000_SUCCESS; 1973 } 1974 1975 /** 1976 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 1977 * @hw: pointer to the HW structure 1978 * @no_snoop: bitmap of snoop events 1979 * 1980 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 1981 **/ 1982 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 1983 { 1984 u32 gcr; 1985 1986 DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 1987 1988 if (hw->bus.type != e1000_bus_type_pci_express) 1989 goto out; 1990 1991 if (no_snoop) { 1992 gcr = E1000_READ_REG(hw, E1000_GCR); 1993 gcr &= ~(PCIE_NO_SNOOP_ALL); 1994 gcr |= no_snoop; 1995 E1000_WRITE_REG(hw, E1000_GCR, gcr); 1996 } 1997 out: 1998 return; 1999 } 2000 2001 /** 2002 * e1000_disable_pcie_master_generic - Disables PCI-express master access 2003 * @hw: pointer to the HW structure 2004 * 2005 * Returns E1000_SUCCESS if successful, else returns -10 2006 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 2007 * the master requests to be disabled. 2008 * 2009 * Disables PCI-Express master access and verifies there are no pending 2010 * requests. 2011 **/ 2012 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw) 2013 { 2014 u32 ctrl; 2015 s32 timeout = MASTER_DISABLE_TIMEOUT; 2016 s32 ret_val = E1000_SUCCESS; 2017 2018 DEBUGFUNC("e1000_disable_pcie_master_generic"); 2019 2020 if (hw->bus.type != e1000_bus_type_pci_express) 2021 goto out; 2022 2023 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2024 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 2025 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2026 2027 while (timeout) { 2028 if (!(E1000_READ_REG(hw, E1000_STATUS) & 2029 E1000_STATUS_GIO_MASTER_ENABLE)) 2030 break; 2031 usec_delay(100); 2032 timeout--; 2033 } 2034 2035 if (!timeout) { 2036 DEBUGOUT("Master requests are pending.\n"); 2037 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; 2038 } 2039 2040 out: 2041 return ret_val; 2042 } 2043 2044 /** 2045 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 2046 * @hw: pointer to the HW structure 2047 * 2048 * Reset the Adaptive Interframe Spacing throttle to default values. 2049 **/ 2050 void e1000_reset_adaptive_generic(struct e1000_hw *hw) 2051 { 2052 struct e1000_mac_info *mac = &hw->mac; 2053 2054 DEBUGFUNC("e1000_reset_adaptive_generic"); 2055 2056 if (!mac->adaptive_ifs) { 2057 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2058 goto out; 2059 } 2060 2061 mac->current_ifs_val = 0; 2062 mac->ifs_min_val = IFS_MIN; 2063 mac->ifs_max_val = IFS_MAX; 2064 mac->ifs_step_size = IFS_STEP; 2065 mac->ifs_ratio = IFS_RATIO; 2066 2067 mac->in_ifs_mode = FALSE; 2068 E1000_WRITE_REG(hw, E1000_AIT, 0); 2069 out: 2070 return; 2071 } 2072 2073 /** 2074 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 2075 * @hw: pointer to the HW structure 2076 * 2077 * Update the Adaptive Interframe Spacing Throttle value based on the 2078 * time between transmitted packets and time between collisions. 2079 **/ 2080 void e1000_update_adaptive_generic(struct e1000_hw *hw) 2081 { 2082 struct e1000_mac_info *mac = &hw->mac; 2083 2084 DEBUGFUNC("e1000_update_adaptive_generic"); 2085 2086 if (!mac->adaptive_ifs) { 2087 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2088 goto out; 2089 } 2090 2091 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 2092 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 2093 mac->in_ifs_mode = TRUE; 2094 if (mac->current_ifs_val < mac->ifs_max_val) { 2095 if (!mac->current_ifs_val) 2096 mac->current_ifs_val = mac->ifs_min_val; 2097 else 2098 mac->current_ifs_val += 2099 mac->ifs_step_size; 2100 E1000_WRITE_REG(hw, E1000_AIT, mac->current_ifs_val); 2101 } 2102 } 2103 } else { 2104 if (mac->in_ifs_mode && 2105 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 2106 mac->current_ifs_val = 0; 2107 mac->in_ifs_mode = FALSE; 2108 E1000_WRITE_REG(hw, E1000_AIT, 0); 2109 } 2110 } 2111 out: 2112 return; 2113 } 2114 2115 /** 2116 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 2117 * @hw: pointer to the HW structure 2118 * 2119 * Verify that when not using auto-negotiation that MDI/MDIx is correctly 2120 * set, which is forced to MDI mode only. 2121 **/ 2122 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 2123 { 2124 s32 ret_val = E1000_SUCCESS; 2125 2126 DEBUGFUNC("e1000_validate_mdi_setting_generic"); 2127 2128 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 2129 DEBUGOUT("Invalid MDI setting detected\n"); 2130 hw->phy.mdix = 1; 2131 ret_val = -E1000_ERR_CONFIG; 2132 goto out; 2133 } 2134 2135 out: 2136 return ret_val; 2137 } 2138 2139 /** 2140 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register 2141 * @hw: pointer to the HW structure 2142 * @reg: 32bit register offset such as E1000_SCTL 2143 * @offset: register offset to write to 2144 * @data: data to write at register offset 2145 * 2146 * Writes an address/data control type register. There are several of these 2147 * and they all have the format address << 8 | data and bit 31 is polled for 2148 * completion. 2149 **/ 2150 s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, 2151 u32 offset, u8 data) 2152 { 2153 u32 i, regvalue = 0; 2154 s32 ret_val = E1000_SUCCESS; 2155 2156 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); 2157 2158 /* Set up the address and data */ 2159 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 2160 E1000_WRITE_REG(hw, reg, regvalue); 2161 2162 /* Poll the ready bit to see if the MDI read completed */ 2163 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 2164 usec_delay(5); 2165 regvalue = E1000_READ_REG(hw, reg); 2166 if (regvalue & E1000_GEN_CTL_READY) 2167 break; 2168 } 2169 if (!(regvalue & E1000_GEN_CTL_READY)) { 2170 DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 2171 ret_val = -E1000_ERR_PHY; 2172 goto out; 2173 } 2174 2175 out: 2176 return ret_val; 2177 } 2178