1 /****************************************************************************** 2 3 Copyright (c) 2001-2016, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "e1000_api.h" 36 37 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw); 38 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); 39 static void e1000_config_collision_dist_generic(struct e1000_hw *hw); 40 static int e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index); 41 42 /** 43 * e1000_init_mac_ops_generic - Initialize MAC function pointers 44 * @hw: pointer to the HW structure 45 * 46 * Setups up the function pointers to no-op functions 47 **/ 48 void e1000_init_mac_ops_generic(struct e1000_hw *hw) 49 { 50 struct e1000_mac_info *mac = &hw->mac; 51 DEBUGFUNC("e1000_init_mac_ops_generic"); 52 53 /* General Setup */ 54 mac->ops.init_params = e1000_null_ops_generic; 55 mac->ops.init_hw = e1000_null_ops_generic; 56 mac->ops.reset_hw = e1000_null_ops_generic; 57 mac->ops.setup_physical_interface = e1000_null_ops_generic; 58 mac->ops.get_bus_info = e1000_null_ops_generic; 59 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie; 60 mac->ops.read_mac_addr = e1000_read_mac_addr_generic; 61 mac->ops.config_collision_dist = e1000_config_collision_dist_generic; 62 mac->ops.clear_hw_cntrs = e1000_null_mac_generic; 63 /* LED */ 64 mac->ops.cleanup_led = e1000_null_ops_generic; 65 mac->ops.setup_led = e1000_null_ops_generic; 66 mac->ops.blink_led = e1000_null_ops_generic; 67 mac->ops.led_on = e1000_null_ops_generic; 68 mac->ops.led_off = e1000_null_ops_generic; 69 /* LINK */ 70 mac->ops.setup_link = e1000_null_ops_generic; 71 mac->ops.get_link_up_info = e1000_null_link_info; 72 mac->ops.check_for_link = e1000_null_ops_generic; 73 mac->ops.set_obff_timer = e1000_null_set_obff_timer; 74 /* Management */ 75 mac->ops.check_mng_mode = e1000_null_mng_mode; 76 /* VLAN, MC, etc. */ 77 mac->ops.update_mc_addr_list = e1000_null_update_mc; 78 mac->ops.clear_vfta = e1000_null_mac_generic; 79 mac->ops.write_vfta = e1000_null_write_vfta; 80 mac->ops.rar_set = e1000_rar_set_generic; 81 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; 82 } 83 84 /** 85 * e1000_null_ops_generic - No-op function, returns 0 86 * @hw: pointer to the HW structure 87 **/ 88 s32 e1000_null_ops_generic(struct e1000_hw E1000_UNUSEDARG *hw) 89 { 90 DEBUGFUNC("e1000_null_ops_generic"); 91 return E1000_SUCCESS; 92 } 93 94 /** 95 * e1000_null_mac_generic - No-op function, return void 96 * @hw: pointer to the HW structure 97 **/ 98 void e1000_null_mac_generic(struct e1000_hw E1000_UNUSEDARG *hw) 99 { 100 DEBUGFUNC("e1000_null_mac_generic"); 101 return; 102 } 103 104 /** 105 * e1000_null_link_info - No-op function, return 0 106 * @hw: pointer to the HW structure 107 **/ 108 s32 e1000_null_link_info(struct e1000_hw E1000_UNUSEDARG *hw, 109 u16 E1000_UNUSEDARG *s, u16 E1000_UNUSEDARG *d) 110 { 111 DEBUGFUNC("e1000_null_link_info"); 112 return E1000_SUCCESS; 113 } 114 115 /** 116 * e1000_null_mng_mode - No-op function, return FALSE 117 * @hw: pointer to the HW structure 118 **/ 119 bool e1000_null_mng_mode(struct e1000_hw E1000_UNUSEDARG *hw) 120 { 121 DEBUGFUNC("e1000_null_mng_mode"); 122 return FALSE; 123 } 124 125 /** 126 * e1000_null_update_mc - No-op function, return void 127 * @hw: pointer to the HW structure 128 **/ 129 void e1000_null_update_mc(struct e1000_hw E1000_UNUSEDARG *hw, 130 u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a) 131 { 132 DEBUGFUNC("e1000_null_update_mc"); 133 return; 134 } 135 136 /** 137 * e1000_null_write_vfta - No-op function, return void 138 * @hw: pointer to the HW structure 139 **/ 140 void e1000_null_write_vfta(struct e1000_hw E1000_UNUSEDARG *hw, 141 u32 E1000_UNUSEDARG a, u32 E1000_UNUSEDARG b) 142 { 143 DEBUGFUNC("e1000_null_write_vfta"); 144 return; 145 } 146 147 /** 148 * e1000_null_rar_set - No-op function, return 0 149 * @hw: pointer to the HW structure 150 **/ 151 int e1000_null_rar_set(struct e1000_hw E1000_UNUSEDARG *hw, 152 u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a) 153 { 154 DEBUGFUNC("e1000_null_rar_set"); 155 return E1000_SUCCESS; 156 } 157 158 /** 159 * e1000_null_set_obff_timer - No-op function, return 0 160 * @hw: pointer to the HW structure 161 **/ 162 s32 e1000_null_set_obff_timer(struct e1000_hw E1000_UNUSEDARG *hw, 163 u32 E1000_UNUSEDARG a) 164 { 165 DEBUGFUNC("e1000_null_set_obff_timer"); 166 return E1000_SUCCESS; 167 } 168 169 /** 170 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information 171 * @hw: pointer to the HW structure 172 * 173 * Determines and stores the system bus information for a particular 174 * network interface. The following bus information is determined and stored: 175 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function. 176 **/ 177 s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw) 178 { 179 struct e1000_mac_info *mac = &hw->mac; 180 struct e1000_bus_info *bus = &hw->bus; 181 u32 status = E1000_READ_REG(hw, E1000_STATUS); 182 s32 ret_val = E1000_SUCCESS; 183 184 DEBUGFUNC("e1000_get_bus_info_pci_generic"); 185 186 /* PCI or PCI-X? */ 187 bus->type = (status & E1000_STATUS_PCIX_MODE) 188 ? e1000_bus_type_pcix 189 : e1000_bus_type_pci; 190 191 /* Bus speed */ 192 if (bus->type == e1000_bus_type_pci) { 193 bus->speed = (status & E1000_STATUS_PCI66) 194 ? e1000_bus_speed_66 195 : e1000_bus_speed_33; 196 } else { 197 switch (status & E1000_STATUS_PCIX_SPEED) { 198 case E1000_STATUS_PCIX_SPEED_66: 199 bus->speed = e1000_bus_speed_66; 200 break; 201 case E1000_STATUS_PCIX_SPEED_100: 202 bus->speed = e1000_bus_speed_100; 203 break; 204 case E1000_STATUS_PCIX_SPEED_133: 205 bus->speed = e1000_bus_speed_133; 206 break; 207 default: 208 bus->speed = e1000_bus_speed_reserved; 209 break; 210 } 211 } 212 213 /* Bus width */ 214 bus->width = (status & E1000_STATUS_BUS64) 215 ? e1000_bus_width_64 216 : e1000_bus_width_32; 217 218 /* Which PCI(-X) function? */ 219 mac->ops.set_lan_id(hw); 220 221 return ret_val; 222 } 223 224 /** 225 * e1000_get_bus_info_pcie_generic - Get PCIe bus information 226 * @hw: pointer to the HW structure 227 * 228 * Determines and stores the system bus information for a particular 229 * network interface. The following bus information is determined and stored: 230 * bus speed, bus width, type (PCIe), and PCIe function. 231 **/ 232 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 233 { 234 struct e1000_mac_info *mac = &hw->mac; 235 struct e1000_bus_info *bus = &hw->bus; 236 s32 ret_val; 237 u16 pcie_link_status; 238 239 DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 240 241 bus->type = e1000_bus_type_pci_express; 242 243 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS, 244 &pcie_link_status); 245 if (ret_val) { 246 bus->width = e1000_bus_width_unknown; 247 bus->speed = e1000_bus_speed_unknown; 248 } else { 249 switch (pcie_link_status & PCIE_LINK_SPEED_MASK) { 250 case PCIE_LINK_SPEED_2500: 251 bus->speed = e1000_bus_speed_2500; 252 break; 253 case PCIE_LINK_SPEED_5000: 254 bus->speed = e1000_bus_speed_5000; 255 break; 256 default: 257 bus->speed = e1000_bus_speed_unknown; 258 break; 259 } 260 261 bus->width = (enum e1000_bus_width)((pcie_link_status & 262 PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT); 263 } 264 265 mac->ops.set_lan_id(hw); 266 267 return E1000_SUCCESS; 268 } 269 270 /** 271 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 272 * 273 * @hw: pointer to the HW structure 274 * 275 * Determines the LAN function id by reading memory-mapped registers 276 * and swaps the port value if requested. 277 **/ 278 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) 279 { 280 struct e1000_bus_info *bus = &hw->bus; 281 u32 reg; 282 283 /* The status register reports the correct function number 284 * for the device regardless of function swap state. 285 */ 286 reg = E1000_READ_REG(hw, E1000_STATUS); 287 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 288 } 289 290 /** 291 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices 292 * @hw: pointer to the HW structure 293 * 294 * Determines the LAN function id by reading PCI config space. 295 **/ 296 void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw) 297 { 298 struct e1000_bus_info *bus = &hw->bus; 299 u16 pci_header_type; 300 u32 status; 301 302 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 303 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { 304 status = E1000_READ_REG(hw, E1000_STATUS); 305 bus->func = (status & E1000_STATUS_FUNC_MASK) 306 >> E1000_STATUS_FUNC_SHIFT; 307 } else { 308 bus->func = 0; 309 } 310 } 311 312 /** 313 * e1000_set_lan_id_single_port - Set LAN id for a single port device 314 * @hw: pointer to the HW structure 315 * 316 * Sets the LAN function id to zero for a single port device. 317 **/ 318 void e1000_set_lan_id_single_port(struct e1000_hw *hw) 319 { 320 struct e1000_bus_info *bus = &hw->bus; 321 322 bus->func = 0; 323 } 324 325 /** 326 * e1000_clear_vfta_generic - Clear VLAN filter table 327 * @hw: pointer to the HW structure 328 * 329 * Clears the register array which contains the VLAN filter table by 330 * setting all the values to 0. 331 **/ 332 void e1000_clear_vfta_generic(struct e1000_hw *hw) 333 { 334 u32 offset; 335 336 DEBUGFUNC("e1000_clear_vfta_generic"); 337 338 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 339 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 340 E1000_WRITE_FLUSH(hw); 341 } 342 } 343 344 /** 345 * e1000_write_vfta_generic - Write value to VLAN filter table 346 * @hw: pointer to the HW structure 347 * @offset: register offset in VLAN filter table 348 * @value: register value written to VLAN filter table 349 * 350 * Writes value at the given offset in the register array which stores 351 * the VLAN filter table. 352 **/ 353 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 354 { 355 DEBUGFUNC("e1000_write_vfta_generic"); 356 357 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 358 E1000_WRITE_FLUSH(hw); 359 } 360 361 /** 362 * e1000_init_rx_addrs_generic - Initialize receive address's 363 * @hw: pointer to the HW structure 364 * @rar_count: receive address registers 365 * 366 * Setup the receive address registers by setting the base receive address 367 * register to the devices MAC address and clearing all the other receive 368 * address registers to 0. 369 **/ 370 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 371 { 372 u32 i; 373 u8 mac_addr[ETH_ADDR_LEN] = {0}; 374 375 DEBUGFUNC("e1000_init_rx_addrs_generic"); 376 377 /* Setup the receive address */ 378 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 379 380 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 381 382 /* Zero out the other (rar_entry_count - 1) receive addresses */ 383 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 384 for (i = 1; i < rar_count; i++) 385 hw->mac.ops.rar_set(hw, mac_addr, i); 386 } 387 388 /** 389 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 390 * @hw: pointer to the HW structure 391 * 392 * Checks the nvm for an alternate MAC address. An alternate MAC address 393 * can be setup by pre-boot software and must be treated like a permanent 394 * address and must override the actual permanent MAC address. If an 395 * alternate MAC address is found it is programmed into RAR0, replacing 396 * the permanent address that was installed into RAR0 by the Si on reset. 397 * This function will return SUCCESS unless it encounters an error while 398 * reading the EEPROM. 399 **/ 400 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 401 { 402 u32 i; 403 s32 ret_val; 404 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 405 u8 alt_mac_addr[ETH_ADDR_LEN]; 406 407 DEBUGFUNC("e1000_check_alt_mac_addr_generic"); 408 409 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data); 410 if (ret_val) 411 return ret_val; 412 413 /* not supported on older hardware or 82573. 414 * 415 * Alternate MAC address is handled by the option ROM for 82580 416 * and newer. SW support not required. 417 */ 418 if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573) || 419 hw->mac.type >= e1000_82580) 420 return E1000_SUCCESS; 421 422 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 423 &nvm_alt_mac_addr_offset); 424 if (ret_val) { 425 DEBUGOUT("NVM Read Error\n"); 426 return ret_val; 427 } 428 429 if ((nvm_alt_mac_addr_offset == 0xFFFF) || 430 (nvm_alt_mac_addr_offset == 0x0000)) 431 /* There is no Alternate MAC Address */ 432 return E1000_SUCCESS; 433 434 if (hw->bus.func == E1000_FUNC_1) 435 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 436 if (hw->bus.func == E1000_FUNC_2) 437 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2; 438 439 if (hw->bus.func == E1000_FUNC_3) 440 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3; 441 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 442 offset = nvm_alt_mac_addr_offset + (i >> 1); 443 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 444 if (ret_val) { 445 DEBUGOUT("NVM Read Error\n"); 446 return ret_val; 447 } 448 449 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 450 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 451 } 452 453 /* if multicast bit is set, the alternate address will not be used */ 454 if (alt_mac_addr[0] & 0x01) { 455 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); 456 return E1000_SUCCESS; 457 } 458 459 /* We have a valid alternate MAC address, and we want to treat it the 460 * same as the normal permanent MAC address stored by the HW into the 461 * RAR. Do this by mapping this address into RAR0. 462 */ 463 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 464 465 return E1000_SUCCESS; 466 } 467 468 /** 469 * e1000_rar_set_generic - Set receive address register 470 * @hw: pointer to the HW structure 471 * @addr: pointer to the receive address 472 * @index: receive address array register 473 * 474 * Sets the receive address array register at index to the address passed 475 * in by addr. 476 **/ 477 static int e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 478 { 479 u32 rar_low, rar_high; 480 481 DEBUGFUNC("e1000_rar_set_generic"); 482 483 /* HW expects these in little endian so we reverse the byte order 484 * from network order (big endian) to little endian 485 */ 486 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 487 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 488 489 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 490 491 /* If MAC address zero, no need to set the AV bit */ 492 if (rar_low || rar_high) 493 rar_high |= E1000_RAH_AV; 494 495 /* Some bridges will combine consecutive 32-bit writes into 496 * a single burst write, which will malfunction on some parts. 497 * The flushes avoid this. 498 */ 499 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 500 E1000_WRITE_FLUSH(hw); 501 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 502 E1000_WRITE_FLUSH(hw); 503 504 return E1000_SUCCESS; 505 } 506 507 /** 508 * e1000_hash_mc_addr_generic - Generate a multicast hash value 509 * @hw: pointer to the HW structure 510 * @mc_addr: pointer to a multicast address 511 * 512 * Generates a multicast address hash value which is used to determine 513 * the multicast filter table array address and new table value. 514 **/ 515 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 516 { 517 u32 hash_value, hash_mask; 518 u8 bit_shift = 0; 519 520 DEBUGFUNC("e1000_hash_mc_addr_generic"); 521 522 /* Register count multiplied by bits per register */ 523 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 524 525 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts 526 * where 0xFF would still fall within the hash mask. 527 */ 528 while (hash_mask >> bit_shift != 0xFF) 529 bit_shift++; 530 531 /* The portion of the address that is used for the hash table 532 * is determined by the mc_filter_type setting. 533 * The algorithm is such that there is a total of 8 bits of shifting. 534 * The bit_shift for a mc_filter_type of 0 represents the number of 535 * left-shifts where the MSB of mc_addr[5] would still fall within 536 * the hash_mask. Case 0 does this exactly. Since there are a total 537 * of 8 bits of shifting, then mc_addr[4] will shift right the 538 * remaining number of bits. Thus 8 - bit_shift. The rest of the 539 * cases are a variation of this algorithm...essentially raising the 540 * number of bits to shift mc_addr[5] left, while still keeping the 541 * 8-bit shifting total. 542 * 543 * For example, given the following Destination MAC Address and an 544 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 545 * we can see that the bit_shift for case 0 is 4. These are the hash 546 * values resulting from each mc_filter_type... 547 * [0] [1] [2] [3] [4] [5] 548 * 01 AA 00 12 34 56 549 * LSB MSB 550 * 551 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 552 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 553 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 554 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 555 */ 556 switch (hw->mac.mc_filter_type) { 557 default: 558 case 0: 559 break; 560 case 1: 561 bit_shift += 1; 562 break; 563 case 2: 564 bit_shift += 2; 565 break; 566 case 3: 567 bit_shift += 4; 568 break; 569 } 570 571 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 572 (((u16) mc_addr[5]) << bit_shift))); 573 574 return hash_value; 575 } 576 577 /** 578 * e1000_update_mc_addr_list_generic - Update Multicast addresses 579 * @hw: pointer to the HW structure 580 * @mc_addr_list: array of multicast addresses to program 581 * @mc_addr_count: number of multicast addresses to program 582 * 583 * Updates entire Multicast Table Array. 584 * The caller must have a packed mc_addr_list of multicast addresses. 585 **/ 586 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw, 587 u8 *mc_addr_list, u32 mc_addr_count) 588 { 589 u32 hash_value, hash_bit, hash_reg; 590 int i; 591 592 DEBUGFUNC("e1000_update_mc_addr_list_generic"); 593 594 /* clear mta_shadow */ 595 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 596 597 /* update mta_shadow from mc_addr_list */ 598 for (i = 0; (u32) i < mc_addr_count; i++) { 599 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list); 600 601 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 602 hash_bit = hash_value & 0x1F; 603 604 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 605 mc_addr_list += (ETH_ADDR_LEN); 606 } 607 608 /* replace the entire MTA table */ 609 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 610 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 611 E1000_WRITE_FLUSH(hw); 612 } 613 614 /** 615 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value 616 * @hw: pointer to the HW structure 617 * 618 * In certain situations, a system BIOS may report that the PCIx maximum 619 * memory read byte count (MMRBC) value is higher than than the actual 620 * value. We check the PCIx command register with the current PCIx status 621 * register. 622 **/ 623 void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw) 624 { 625 u16 cmd_mmrbc; 626 u16 pcix_cmd; 627 u16 pcix_stat_hi_word; 628 u16 stat_mmrbc; 629 630 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); 631 632 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ 633 if (hw->bus.type != e1000_bus_type_pcix) 634 return; 635 636 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 637 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 638 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> 639 PCIX_COMMAND_MMRBC_SHIFT; 640 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 641 PCIX_STATUS_HI_MMRBC_SHIFT; 642 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 643 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 644 if (cmd_mmrbc > stat_mmrbc) { 645 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; 646 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 647 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 648 } 649 } 650 651 /** 652 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 653 * @hw: pointer to the HW structure 654 * 655 * Clears the base hardware counters by reading the counter registers. 656 **/ 657 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 658 { 659 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 660 661 E1000_READ_REG(hw, E1000_CRCERRS); 662 E1000_READ_REG(hw, E1000_SYMERRS); 663 E1000_READ_REG(hw, E1000_MPC); 664 E1000_READ_REG(hw, E1000_SCC); 665 E1000_READ_REG(hw, E1000_ECOL); 666 E1000_READ_REG(hw, E1000_MCC); 667 E1000_READ_REG(hw, E1000_LATECOL); 668 E1000_READ_REG(hw, E1000_COLC); 669 E1000_READ_REG(hw, E1000_DC); 670 E1000_READ_REG(hw, E1000_SEC); 671 E1000_READ_REG(hw, E1000_RLEC); 672 E1000_READ_REG(hw, E1000_XONRXC); 673 E1000_READ_REG(hw, E1000_XONTXC); 674 E1000_READ_REG(hw, E1000_XOFFRXC); 675 E1000_READ_REG(hw, E1000_XOFFTXC); 676 E1000_READ_REG(hw, E1000_FCRUC); 677 E1000_READ_REG(hw, E1000_GPRC); 678 E1000_READ_REG(hw, E1000_BPRC); 679 E1000_READ_REG(hw, E1000_MPRC); 680 E1000_READ_REG(hw, E1000_GPTC); 681 E1000_READ_REG(hw, E1000_GORCL); 682 E1000_READ_REG(hw, E1000_GORCH); 683 E1000_READ_REG(hw, E1000_GOTCL); 684 E1000_READ_REG(hw, E1000_GOTCH); 685 E1000_READ_REG(hw, E1000_RNBC); 686 E1000_READ_REG(hw, E1000_RUC); 687 E1000_READ_REG(hw, E1000_RFC); 688 E1000_READ_REG(hw, E1000_ROC); 689 E1000_READ_REG(hw, E1000_RJC); 690 E1000_READ_REG(hw, E1000_TORL); 691 E1000_READ_REG(hw, E1000_TORH); 692 E1000_READ_REG(hw, E1000_TOTL); 693 E1000_READ_REG(hw, E1000_TOTH); 694 E1000_READ_REG(hw, E1000_TPR); 695 E1000_READ_REG(hw, E1000_TPT); 696 E1000_READ_REG(hw, E1000_MPTC); 697 E1000_READ_REG(hw, E1000_BPTC); 698 } 699 700 /** 701 * e1000_check_for_copper_link_generic - Check for link (Copper) 702 * @hw: pointer to the HW structure 703 * 704 * Checks to see of the link status of the hardware has changed. If a 705 * change in link status has been detected, then we read the PHY registers 706 * to get the current speed/duplex if link exists. 707 **/ 708 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) 709 { 710 struct e1000_mac_info *mac = &hw->mac; 711 s32 ret_val; 712 bool link; 713 714 DEBUGFUNC("e1000_check_for_copper_link"); 715 716 /* We only want to go out to the PHY registers to see if Auto-Neg 717 * has completed and/or if our link status has changed. The 718 * get_link_status flag is set upon receiving a Link Status 719 * Change or Rx Sequence Error interrupt. 720 */ 721 if (!mac->get_link_status) 722 return E1000_SUCCESS; 723 724 /* First we want to see if the MII Status Register reports 725 * link. If so, then we want to get the current speed/duplex 726 * of the PHY. 727 */ 728 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 729 if (ret_val) 730 return ret_val; 731 732 if (!link) 733 return E1000_SUCCESS; /* No link detected */ 734 735 mac->get_link_status = FALSE; 736 737 /* Check if there was DownShift, must be checked 738 * immediately after link-up 739 */ 740 e1000_check_downshift_generic(hw); 741 742 /* If we are forcing speed/duplex, then we simply return since 743 * we have already determined whether we have link or not. 744 */ 745 if (!mac->autoneg) 746 return -E1000_ERR_CONFIG; 747 748 /* Auto-Neg is enabled. Auto Speed Detection takes care 749 * of MAC speed/duplex configuration. So we only need to 750 * configure Collision Distance in the MAC. 751 */ 752 mac->ops.config_collision_dist(hw); 753 754 /* Configure Flow Control now that Auto-Neg has completed. 755 * First, we need to restore the desired flow control 756 * settings because we may have had to re-autoneg with a 757 * different link partner. 758 */ 759 ret_val = e1000_config_fc_after_link_up_generic(hw); 760 if (ret_val) 761 DEBUGOUT("Error configuring flow control\n"); 762 763 return ret_val; 764 } 765 766 /** 767 * e1000_check_for_fiber_link_generic - Check for link (Fiber) 768 * @hw: pointer to the HW structure 769 * 770 * Checks for link up on the hardware. If link is not up and we have 771 * a signal, then we need to force link up. 772 **/ 773 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 774 { 775 struct e1000_mac_info *mac = &hw->mac; 776 u32 rxcw; 777 u32 ctrl; 778 u32 status; 779 s32 ret_val; 780 781 DEBUGFUNC("e1000_check_for_fiber_link_generic"); 782 783 ctrl = E1000_READ_REG(hw, E1000_CTRL); 784 status = E1000_READ_REG(hw, E1000_STATUS); 785 rxcw = E1000_READ_REG(hw, E1000_RXCW); 786 787 /* If we don't have link (auto-negotiation failed or link partner 788 * cannot auto-negotiate), the cable is plugged in (we have signal), 789 * and our link partner is not trying to auto-negotiate with us (we 790 * are receiving idles or data), we need to force link up. We also 791 * need to give auto-negotiation time to complete, in case the cable 792 * was just plugged in. The autoneg_failed flag does this. 793 */ 794 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 795 if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) && 796 !(rxcw & E1000_RXCW_C)) { 797 if (!mac->autoneg_failed) { 798 mac->autoneg_failed = TRUE; 799 return E1000_SUCCESS; 800 } 801 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 802 803 /* Disable auto-negotiation in the TXCW register */ 804 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 805 806 /* Force link-up and also force full-duplex. */ 807 ctrl = E1000_READ_REG(hw, E1000_CTRL); 808 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 809 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 810 811 /* Configure Flow Control after forcing link up. */ 812 ret_val = e1000_config_fc_after_link_up_generic(hw); 813 if (ret_val) { 814 DEBUGOUT("Error configuring flow control\n"); 815 return ret_val; 816 } 817 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 818 /* If we are forcing link and we are receiving /C/ ordered 819 * sets, re-enable auto-negotiation in the TXCW register 820 * and disable forced link in the Device Control register 821 * in an attempt to auto-negotiate with our link partner. 822 */ 823 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 824 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 825 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 826 827 mac->serdes_has_link = TRUE; 828 } 829 830 return E1000_SUCCESS; 831 } 832 833 /** 834 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 835 * @hw: pointer to the HW structure 836 * 837 * Checks for link up on the hardware. If link is not up and we have 838 * a signal, then we need to force link up. 839 **/ 840 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 841 { 842 struct e1000_mac_info *mac = &hw->mac; 843 u32 rxcw; 844 u32 ctrl; 845 u32 status; 846 s32 ret_val; 847 848 DEBUGFUNC("e1000_check_for_serdes_link_generic"); 849 850 ctrl = E1000_READ_REG(hw, E1000_CTRL); 851 status = E1000_READ_REG(hw, E1000_STATUS); 852 rxcw = E1000_READ_REG(hw, E1000_RXCW); 853 854 /* If we don't have link (auto-negotiation failed or link partner 855 * cannot auto-negotiate), and our link partner is not trying to 856 * auto-negotiate with us (we are receiving idles or data), 857 * we need to force link up. We also need to give auto-negotiation 858 * time to complete. 859 */ 860 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 861 if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) { 862 if (!mac->autoneg_failed) { 863 mac->autoneg_failed = TRUE; 864 return E1000_SUCCESS; 865 } 866 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 867 868 /* Disable auto-negotiation in the TXCW register */ 869 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 870 871 /* Force link-up and also force full-duplex. */ 872 ctrl = E1000_READ_REG(hw, E1000_CTRL); 873 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 874 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 875 876 /* Configure Flow Control after forcing link up. */ 877 ret_val = e1000_config_fc_after_link_up_generic(hw); 878 if (ret_val) { 879 DEBUGOUT("Error configuring flow control\n"); 880 return ret_val; 881 } 882 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 883 /* If we are forcing link and we are receiving /C/ ordered 884 * sets, re-enable auto-negotiation in the TXCW register 885 * and disable forced link in the Device Control register 886 * in an attempt to auto-negotiate with our link partner. 887 */ 888 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 889 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 890 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 891 892 mac->serdes_has_link = TRUE; 893 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 894 /* If we force link for non-auto-negotiation switch, check 895 * link status based on MAC synchronization for internal 896 * serdes media type. 897 */ 898 /* SYNCH bit and IV bit are sticky. */ 899 usec_delay(10); 900 rxcw = E1000_READ_REG(hw, E1000_RXCW); 901 if (rxcw & E1000_RXCW_SYNCH) { 902 if (!(rxcw & E1000_RXCW_IV)) { 903 mac->serdes_has_link = TRUE; 904 DEBUGOUT("SERDES: Link up - forced.\n"); 905 } 906 } else { 907 mac->serdes_has_link = FALSE; 908 DEBUGOUT("SERDES: Link down - force failed.\n"); 909 } 910 } 911 912 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 913 status = E1000_READ_REG(hw, E1000_STATUS); 914 if (status & E1000_STATUS_LU) { 915 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 916 usec_delay(10); 917 rxcw = E1000_READ_REG(hw, E1000_RXCW); 918 if (rxcw & E1000_RXCW_SYNCH) { 919 if (!(rxcw & E1000_RXCW_IV)) { 920 mac->serdes_has_link = TRUE; 921 DEBUGOUT("SERDES: Link up - autoneg completed successfully.\n"); 922 } else { 923 mac->serdes_has_link = FALSE; 924 DEBUGOUT("SERDES: Link down - invalid codewords detected in autoneg.\n"); 925 } 926 } else { 927 mac->serdes_has_link = FALSE; 928 DEBUGOUT("SERDES: Link down - no sync.\n"); 929 } 930 } else { 931 mac->serdes_has_link = FALSE; 932 DEBUGOUT("SERDES: Link down - autoneg failed\n"); 933 } 934 } 935 936 return E1000_SUCCESS; 937 } 938 939 /** 940 * e1000_set_default_fc_generic - Set flow control default values 941 * @hw: pointer to the HW structure 942 * 943 * Read the EEPROM for the default values for flow control and store the 944 * values. 945 **/ 946 s32 e1000_set_default_fc_generic(struct e1000_hw *hw) 947 { 948 s32 ret_val; 949 u16 nvm_data; 950 u16 nvm_offset = 0; 951 952 DEBUGFUNC("e1000_set_default_fc_generic"); 953 954 /* Read and store word 0x0F of the EEPROM. This word contains bits 955 * that determine the hardware's default PAUSE (flow control) mode, 956 * a bit that determines whether the HW defaults to enabling or 957 * disabling auto-negotiation, and the direction of the 958 * SW defined pins. If there is no SW over-ride of the flow 959 * control setting, then the variable hw->fc will 960 * be initialized based on a value in the EEPROM. 961 */ 962 if (hw->mac.type == e1000_i350) { 963 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(hw->bus.func); 964 ret_val = hw->nvm.ops.read(hw, 965 NVM_INIT_CONTROL2_REG + 966 nvm_offset, 967 1, &nvm_data); 968 } else { 969 ret_val = hw->nvm.ops.read(hw, 970 NVM_INIT_CONTROL2_REG, 971 1, &nvm_data); 972 } 973 974 975 if (ret_val) { 976 DEBUGOUT("NVM Read Error\n"); 977 return ret_val; 978 } 979 980 if (!(nvm_data & NVM_WORD0F_PAUSE_MASK)) 981 hw->fc.requested_mode = e1000_fc_none; 982 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 983 NVM_WORD0F_ASM_DIR) 984 hw->fc.requested_mode = e1000_fc_tx_pause; 985 else 986 hw->fc.requested_mode = e1000_fc_full; 987 988 return E1000_SUCCESS; 989 } 990 991 /** 992 * e1000_setup_link_generic - Setup flow control and link settings 993 * @hw: pointer to the HW structure 994 * 995 * Determines which flow control settings to use, then configures flow 996 * control. Calls the appropriate media-specific link configuration 997 * function. Assuming the adapter has a valid link partner, a valid link 998 * should be established. Assumes the hardware has previously been reset 999 * and the transmitter and receiver are not enabled. 1000 **/ 1001 s32 e1000_setup_link_generic(struct e1000_hw *hw) 1002 { 1003 s32 ret_val; 1004 1005 DEBUGFUNC("e1000_setup_link_generic"); 1006 1007 /* In the case of the phy reset being blocked, we already have a link. 1008 * We do not need to set it up again. 1009 */ 1010 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 1011 return E1000_SUCCESS; 1012 1013 /* If requested flow control is set to default, set flow control 1014 * based on the EEPROM flow control settings. 1015 */ 1016 if (hw->fc.requested_mode == e1000_fc_default) { 1017 ret_val = e1000_set_default_fc_generic(hw); 1018 if (ret_val) 1019 return ret_val; 1020 } 1021 1022 /* Save off the requested flow control mode for use later. Depending 1023 * on the link partner's capabilities, we may or may not use this mode. 1024 */ 1025 hw->fc.current_mode = hw->fc.requested_mode; 1026 1027 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 1028 hw->fc.current_mode); 1029 1030 /* Call the necessary media_type subroutine to configure the link. */ 1031 ret_val = hw->mac.ops.setup_physical_interface(hw); 1032 if (ret_val) 1033 return ret_val; 1034 1035 /* Initialize the flow control address, type, and PAUSE timer 1036 * registers to their default values. This is done even if flow 1037 * control is disabled, because it does not hurt anything to 1038 * initialize these registers. 1039 */ 1040 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 1041 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 1042 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1043 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 1044 1045 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 1046 1047 return e1000_set_fc_watermarks_generic(hw); 1048 } 1049 1050 /** 1051 * e1000_commit_fc_settings_generic - Configure flow control 1052 * @hw: pointer to the HW structure 1053 * 1054 * Write the flow control settings to the Transmit Config Word Register (TXCW) 1055 * base on the flow control settings in e1000_mac_info. 1056 **/ 1057 s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 1058 { 1059 struct e1000_mac_info *mac = &hw->mac; 1060 u32 txcw; 1061 1062 DEBUGFUNC("e1000_commit_fc_settings_generic"); 1063 1064 /* Check for a software override of the flow control settings, and 1065 * setup the device accordingly. If auto-negotiation is enabled, then 1066 * software will have to set the "PAUSE" bits to the correct value in 1067 * the Transmit Config Word Register (TXCW) and re-start auto- 1068 * negotiation. However, if auto-negotiation is disabled, then 1069 * software will have to manually configure the two flow control enable 1070 * bits in the CTRL register. 1071 * 1072 * The possible values of the "fc" parameter are: 1073 * 0: Flow control is completely disabled 1074 * 1: Rx flow control is enabled (we can receive pause frames, 1075 * but not send pause frames). 1076 * 2: Tx flow control is enabled (we can send pause frames but we 1077 * do not support receiving pause frames). 1078 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1079 */ 1080 switch (hw->fc.current_mode) { 1081 case e1000_fc_none: 1082 /* Flow control completely disabled by a software over-ride. */ 1083 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1084 break; 1085 case e1000_fc_rx_pause: 1086 /* Rx Flow control is enabled and Tx Flow control is disabled 1087 * by a software over-ride. Since there really isn't a way to 1088 * advertise that we are capable of Rx Pause ONLY, we will 1089 * advertise that we support both symmetric and asymmetric Rx 1090 * PAUSE. Later, we will disable the adapter's ability to send 1091 * PAUSE frames. 1092 */ 1093 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1094 break; 1095 case e1000_fc_tx_pause: 1096 /* Tx Flow control is enabled, and Rx Flow control is disabled, 1097 * by a software over-ride. 1098 */ 1099 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1100 break; 1101 case e1000_fc_full: 1102 /* Flow control (both Rx and Tx) is enabled by a software 1103 * over-ride. 1104 */ 1105 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1106 break; 1107 default: 1108 DEBUGOUT("Flow control param set incorrectly\n"); 1109 return -E1000_ERR_CONFIG; 1110 break; 1111 } 1112 1113 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1114 mac->txcw = txcw; 1115 1116 return E1000_SUCCESS; 1117 } 1118 1119 /** 1120 * e1000_poll_fiber_serdes_link_generic - Poll for link up 1121 * @hw: pointer to the HW structure 1122 * 1123 * Polls for link up by reading the status register, if link fails to come 1124 * up with auto-negotiation, then the link is forced if a signal is detected. 1125 **/ 1126 s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 1127 { 1128 struct e1000_mac_info *mac = &hw->mac; 1129 u32 i, status; 1130 s32 ret_val; 1131 1132 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 1133 1134 /* If we have a signal (the cable is plugged in, or assumed TRUE for 1135 * serdes media) then poll for a "Link-Up" indication in the Device 1136 * Status Register. Time-out if a link isn't seen in 500 milliseconds 1137 * seconds (Auto-negotiation should complete in less than 500 1138 * milliseconds even if the other end is doing it in SW). 1139 */ 1140 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 1141 msec_delay(10); 1142 status = E1000_READ_REG(hw, E1000_STATUS); 1143 if (status & E1000_STATUS_LU) 1144 break; 1145 } 1146 if (i == FIBER_LINK_UP_LIMIT) { 1147 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1148 mac->autoneg_failed = TRUE; 1149 /* AutoNeg failed to achieve a link, so we'll call 1150 * mac->check_for_link. This routine will force the 1151 * link up if we detect a signal. This will allow us to 1152 * communicate with non-autonegotiating link partners. 1153 */ 1154 ret_val = mac->ops.check_for_link(hw); 1155 if (ret_val) { 1156 DEBUGOUT("Error while checking for link\n"); 1157 return ret_val; 1158 } 1159 mac->autoneg_failed = FALSE; 1160 } else { 1161 mac->autoneg_failed = FALSE; 1162 DEBUGOUT("Valid Link Found\n"); 1163 } 1164 1165 return E1000_SUCCESS; 1166 } 1167 1168 /** 1169 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 1170 * @hw: pointer to the HW structure 1171 * 1172 * Configures collision distance and flow control for fiber and serdes 1173 * links. Upon successful setup, poll for link. 1174 **/ 1175 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 1176 { 1177 u32 ctrl; 1178 s32 ret_val; 1179 1180 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 1181 1182 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1183 1184 /* Take the link out of reset */ 1185 ctrl &= ~E1000_CTRL_LRST; 1186 1187 hw->mac.ops.config_collision_dist(hw); 1188 1189 ret_val = e1000_commit_fc_settings_generic(hw); 1190 if (ret_val) 1191 return ret_val; 1192 1193 /* Since auto-negotiation is enabled, take the link out of reset (the 1194 * link will be in reset, because we previously reset the chip). This 1195 * will restart auto-negotiation. If auto-negotiation is successful 1196 * then the link-up status bit will be set and the flow control enable 1197 * bits (RFCE and TFCE) will be set according to their negotiated value. 1198 */ 1199 DEBUGOUT("Auto-negotiation enabled\n"); 1200 1201 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1202 E1000_WRITE_FLUSH(hw); 1203 msec_delay(1); 1204 1205 /* For these adapters, the SW definable pin 1 is set when the optics 1206 * detect a signal. If we have a signal, then poll for a "Link-Up" 1207 * indication. 1208 */ 1209 if (hw->phy.media_type == e1000_media_type_internal_serdes || 1210 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1211 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1212 } else { 1213 DEBUGOUT("No signal detected\n"); 1214 } 1215 1216 return ret_val; 1217 } 1218 1219 /** 1220 * e1000_config_collision_dist_generic - Configure collision distance 1221 * @hw: pointer to the HW structure 1222 * 1223 * Configures the collision distance to the default value and is used 1224 * during link setup. 1225 **/ 1226 static void e1000_config_collision_dist_generic(struct e1000_hw *hw) 1227 { 1228 u32 tctl; 1229 1230 DEBUGFUNC("e1000_config_collision_dist_generic"); 1231 1232 tctl = E1000_READ_REG(hw, E1000_TCTL); 1233 1234 tctl &= ~E1000_TCTL_COLD; 1235 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1236 1237 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 1238 E1000_WRITE_FLUSH(hw); 1239 } 1240 1241 /** 1242 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 1243 * @hw: pointer to the HW structure 1244 * 1245 * Sets the flow control high/low threshold (watermark) registers. If 1246 * flow control XON frame transmission is enabled, then set XON frame 1247 * transmission as well. 1248 **/ 1249 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 1250 { 1251 u32 fcrtl = 0, fcrth = 0; 1252 1253 DEBUGFUNC("e1000_set_fc_watermarks_generic"); 1254 1255 /* Set the flow control receive threshold registers. Normally, 1256 * these registers will be set to a default threshold that may be 1257 * adjusted later by the driver's runtime code. However, if the 1258 * ability to transmit pause frames is not enabled, then these 1259 * registers will be set to 0. 1260 */ 1261 if (hw->fc.current_mode & e1000_fc_tx_pause) { 1262 /* We need to set up the Receive Threshold high and low water 1263 * marks as well as (optionally) enabling the transmission of 1264 * XON frames. 1265 */ 1266 fcrtl = hw->fc.low_water; 1267 if (hw->fc.send_xon) 1268 fcrtl |= E1000_FCRTL_XONE; 1269 1270 fcrth = hw->fc.high_water; 1271 } 1272 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 1273 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 1274 1275 return E1000_SUCCESS; 1276 } 1277 1278 /** 1279 * e1000_force_mac_fc_generic - Force the MAC's flow control settings 1280 * @hw: pointer to the HW structure 1281 * 1282 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 1283 * device control register to reflect the adapter settings. TFCE and RFCE 1284 * need to be explicitly set by software when a copper PHY is used because 1285 * autonegotiation is managed by the PHY rather than the MAC. Software must 1286 * also configure these bits when link is forced on a fiber connection. 1287 **/ 1288 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw) 1289 { 1290 u32 ctrl; 1291 1292 DEBUGFUNC("e1000_force_mac_fc_generic"); 1293 1294 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1295 1296 /* Because we didn't get link via the internal auto-negotiation 1297 * mechanism (we either forced link or we got link via PHY 1298 * auto-neg), we have to manually enable/disable transmit an 1299 * receive flow control. 1300 * 1301 * The "Case" statement below enables/disable flow control 1302 * according to the "hw->fc.current_mode" parameter. 1303 * 1304 * The possible values of the "fc" parameter are: 1305 * 0: Flow control is completely disabled 1306 * 1: Rx flow control is enabled (we can receive pause 1307 * frames but not send pause frames). 1308 * 2: Tx flow control is enabled (we can send pause frames 1309 * frames but we do not receive pause frames). 1310 * 3: Both Rx and Tx flow control (symmetric) is enabled. 1311 * other: No other values should be possible at this point. 1312 */ 1313 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); 1314 1315 switch (hw->fc.current_mode) { 1316 case e1000_fc_none: 1317 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1318 break; 1319 case e1000_fc_rx_pause: 1320 ctrl &= (~E1000_CTRL_TFCE); 1321 ctrl |= E1000_CTRL_RFCE; 1322 break; 1323 case e1000_fc_tx_pause: 1324 ctrl &= (~E1000_CTRL_RFCE); 1325 ctrl |= E1000_CTRL_TFCE; 1326 break; 1327 case e1000_fc_full: 1328 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1329 break; 1330 default: 1331 DEBUGOUT("Flow control param set incorrectly\n"); 1332 return -E1000_ERR_CONFIG; 1333 } 1334 1335 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1336 1337 return E1000_SUCCESS; 1338 } 1339 1340 /** 1341 * e1000_config_fc_after_link_up_generic - Configures flow control after link 1342 * @hw: pointer to the HW structure 1343 * 1344 * Checks the status of auto-negotiation after link up to ensure that the 1345 * speed and duplex were not forced. If the link needed to be forced, then 1346 * flow control needs to be forced also. If auto-negotiation is enabled 1347 * and did not fail, then we configure flow control based on our link 1348 * partner. 1349 **/ 1350 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 1351 { 1352 struct e1000_mac_info *mac = &hw->mac; 1353 s32 ret_val = E1000_SUCCESS; 1354 u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg; 1355 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1356 u16 speed, duplex; 1357 1358 DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 1359 1360 /* Check for the case where we have fiber media and auto-neg failed 1361 * so we had to force link. In this case, we need to force the 1362 * configuration of the MAC to match the "fc" parameter. 1363 */ 1364 if (mac->autoneg_failed) { 1365 if (hw->phy.media_type == e1000_media_type_fiber || 1366 hw->phy.media_type == e1000_media_type_internal_serdes) 1367 ret_val = e1000_force_mac_fc_generic(hw); 1368 } else { 1369 if (hw->phy.media_type == e1000_media_type_copper) 1370 ret_val = e1000_force_mac_fc_generic(hw); 1371 } 1372 1373 if (ret_val) { 1374 DEBUGOUT("Error forcing flow control settings\n"); 1375 return ret_val; 1376 } 1377 1378 /* Check for the case where we have copper media and auto-neg is 1379 * enabled. In this case, we need to check and see if Auto-Neg 1380 * has completed, and if so, how the PHY and link partner has 1381 * flow control configured. 1382 */ 1383 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1384 /* Read the MII Status Register and check to see if AutoNeg 1385 * has completed. We read this twice because this reg has 1386 * some "sticky" (latched) bits. 1387 */ 1388 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1389 if (ret_val) 1390 return ret_val; 1391 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1392 if (ret_val) 1393 return ret_val; 1394 1395 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1396 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n"); 1397 return ret_val; 1398 } 1399 1400 /* The AutoNeg process has completed, so we now need to 1401 * read both the Auto Negotiation Advertisement 1402 * Register (Address 4) and the Auto_Negotiation Base 1403 * Page Ability Register (Address 5) to determine how 1404 * flow control was negotiated. 1405 */ 1406 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 1407 &mii_nway_adv_reg); 1408 if (ret_val) 1409 return ret_val; 1410 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 1411 &mii_nway_lp_ability_reg); 1412 if (ret_val) 1413 return ret_val; 1414 1415 /* Two bits in the Auto Negotiation Advertisement Register 1416 * (Address 4) and two bits in the Auto Negotiation Base 1417 * Page Ability Register (Address 5) determine flow control 1418 * for both the PHY and the link partner. The following 1419 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1420 * 1999, describes these PAUSE resolution bits and how flow 1421 * control is determined based upon these settings. 1422 * NOTE: DC = Don't Care 1423 * 1424 * LOCAL DEVICE | LINK PARTNER 1425 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1426 *-------|---------|-------|---------|-------------------- 1427 * 0 | 0 | DC | DC | e1000_fc_none 1428 * 0 | 1 | 0 | DC | e1000_fc_none 1429 * 0 | 1 | 1 | 0 | e1000_fc_none 1430 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1431 * 1 | 0 | 0 | DC | e1000_fc_none 1432 * 1 | DC | 1 | DC | e1000_fc_full 1433 * 1 | 1 | 0 | 0 | e1000_fc_none 1434 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1435 * 1436 * Are both PAUSE bits set to 1? If so, this implies 1437 * Symmetric Flow Control is enabled at both ends. The 1438 * ASM_DIR bits are irrelevant per the spec. 1439 * 1440 * For Symmetric Flow Control: 1441 * 1442 * LOCAL DEVICE | LINK PARTNER 1443 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1444 *-------|---------|-------|---------|-------------------- 1445 * 1 | DC | 1 | DC | E1000_fc_full 1446 * 1447 */ 1448 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1449 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1450 /* Now we need to check if the user selected Rx ONLY 1451 * of pause frames. In this case, we had to advertise 1452 * FULL flow control because we could not advertise Rx 1453 * ONLY. Hence, we must now check to see if we need to 1454 * turn OFF the TRANSMISSION of PAUSE frames. 1455 */ 1456 if (hw->fc.requested_mode == e1000_fc_full) { 1457 hw->fc.current_mode = e1000_fc_full; 1458 DEBUGOUT("Flow Control = FULL.\n"); 1459 } else { 1460 hw->fc.current_mode = e1000_fc_rx_pause; 1461 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1462 } 1463 } 1464 /* For receiving PAUSE frames ONLY. 1465 * 1466 * LOCAL DEVICE | LINK PARTNER 1467 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1468 *-------|---------|-------|---------|-------------------- 1469 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1470 */ 1471 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1472 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1473 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1474 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1475 hw->fc.current_mode = e1000_fc_tx_pause; 1476 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); 1477 } 1478 /* For transmitting PAUSE frames ONLY. 1479 * 1480 * LOCAL DEVICE | LINK PARTNER 1481 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1482 *-------|---------|-------|---------|-------------------- 1483 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1484 */ 1485 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1486 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1487 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1488 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1489 hw->fc.current_mode = e1000_fc_rx_pause; 1490 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1491 } else { 1492 /* Per the IEEE spec, at this point flow control 1493 * should be disabled. 1494 */ 1495 hw->fc.current_mode = e1000_fc_none; 1496 DEBUGOUT("Flow Control = NONE.\n"); 1497 } 1498 1499 /* Now we need to do one last check... If we auto- 1500 * negotiated to HALF DUPLEX, flow control should not be 1501 * enabled per IEEE 802.3 spec. 1502 */ 1503 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1504 if (ret_val) { 1505 DEBUGOUT("Error getting link speed and duplex\n"); 1506 return ret_val; 1507 } 1508 1509 if (duplex == HALF_DUPLEX) 1510 hw->fc.current_mode = e1000_fc_none; 1511 1512 /* Now we call a subroutine to actually force the MAC 1513 * controller to use the correct flow control settings. 1514 */ 1515 ret_val = e1000_force_mac_fc_generic(hw); 1516 if (ret_val) { 1517 DEBUGOUT("Error forcing flow control settings\n"); 1518 return ret_val; 1519 } 1520 } 1521 1522 /* Check for the case where we have SerDes media and auto-neg is 1523 * enabled. In this case, we need to check and see if Auto-Neg 1524 * has completed, and if so, how the PHY and link partner has 1525 * flow control configured. 1526 */ 1527 if ((hw->phy.media_type == e1000_media_type_internal_serdes) && 1528 mac->autoneg) { 1529 /* Read the PCS_LSTS and check to see if AutoNeg 1530 * has completed. 1531 */ 1532 pcs_status_reg = E1000_READ_REG(hw, E1000_PCS_LSTAT); 1533 1534 if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) { 1535 DEBUGOUT("PCS Auto Neg has not completed.\n"); 1536 return ret_val; 1537 } 1538 1539 /* The AutoNeg process has completed, so we now need to 1540 * read both the Auto Negotiation Advertisement 1541 * Register (PCS_ANADV) and the Auto_Negotiation Base 1542 * Page Ability Register (PCS_LPAB) to determine how 1543 * flow control was negotiated. 1544 */ 1545 pcs_adv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV); 1546 pcs_lp_ability_reg = E1000_READ_REG(hw, E1000_PCS_LPAB); 1547 1548 /* Two bits in the Auto Negotiation Advertisement Register 1549 * (PCS_ANADV) and two bits in the Auto Negotiation Base 1550 * Page Ability Register (PCS_LPAB) determine flow control 1551 * for both the PHY and the link partner. The following 1552 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1553 * 1999, describes these PAUSE resolution bits and how flow 1554 * control is determined based upon these settings. 1555 * NOTE: DC = Don't Care 1556 * 1557 * LOCAL DEVICE | LINK PARTNER 1558 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1559 *-------|---------|-------|---------|-------------------- 1560 * 0 | 0 | DC | DC | e1000_fc_none 1561 * 0 | 1 | 0 | DC | e1000_fc_none 1562 * 0 | 1 | 1 | 0 | e1000_fc_none 1563 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1564 * 1 | 0 | 0 | DC | e1000_fc_none 1565 * 1 | DC | 1 | DC | e1000_fc_full 1566 * 1 | 1 | 0 | 0 | e1000_fc_none 1567 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1568 * 1569 * Are both PAUSE bits set to 1? If so, this implies 1570 * Symmetric Flow Control is enabled at both ends. The 1571 * ASM_DIR bits are irrelevant per the spec. 1572 * 1573 * For Symmetric Flow Control: 1574 * 1575 * LOCAL DEVICE | LINK PARTNER 1576 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1577 *-------|---------|-------|---------|-------------------- 1578 * 1 | DC | 1 | DC | e1000_fc_full 1579 * 1580 */ 1581 if ((pcs_adv_reg & E1000_TXCW_PAUSE) && 1582 (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) { 1583 /* Now we need to check if the user selected Rx ONLY 1584 * of pause frames. In this case, we had to advertise 1585 * FULL flow control because we could not advertise Rx 1586 * ONLY. Hence, we must now check to see if we need to 1587 * turn OFF the TRANSMISSION of PAUSE frames. 1588 */ 1589 if (hw->fc.requested_mode == e1000_fc_full) { 1590 hw->fc.current_mode = e1000_fc_full; 1591 DEBUGOUT("Flow Control = FULL.\n"); 1592 } else { 1593 hw->fc.current_mode = e1000_fc_rx_pause; 1594 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1595 } 1596 } 1597 /* For receiving PAUSE frames ONLY. 1598 * 1599 * LOCAL DEVICE | LINK PARTNER 1600 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1601 *-------|---------|-------|---------|-------------------- 1602 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1603 */ 1604 else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) && 1605 (pcs_adv_reg & E1000_TXCW_ASM_DIR) && 1606 (pcs_lp_ability_reg & E1000_TXCW_PAUSE) && 1607 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { 1608 hw->fc.current_mode = e1000_fc_tx_pause; 1609 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); 1610 } 1611 /* For transmitting PAUSE frames ONLY. 1612 * 1613 * LOCAL DEVICE | LINK PARTNER 1614 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1615 *-------|---------|-------|---------|-------------------- 1616 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1617 */ 1618 else if ((pcs_adv_reg & E1000_TXCW_PAUSE) && 1619 (pcs_adv_reg & E1000_TXCW_ASM_DIR) && 1620 !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) && 1621 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { 1622 hw->fc.current_mode = e1000_fc_rx_pause; 1623 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1624 } else { 1625 /* Per the IEEE spec, at this point flow control 1626 * should be disabled. 1627 */ 1628 hw->fc.current_mode = e1000_fc_none; 1629 DEBUGOUT("Flow Control = NONE.\n"); 1630 } 1631 1632 /* Now we call a subroutine to actually force the MAC 1633 * controller to use the correct flow control settings. 1634 */ 1635 pcs_ctrl_reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 1636 pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1637 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_ctrl_reg); 1638 1639 ret_val = e1000_force_mac_fc_generic(hw); 1640 if (ret_val) { 1641 DEBUGOUT("Error forcing flow control settings\n"); 1642 return ret_val; 1643 } 1644 } 1645 1646 return E1000_SUCCESS; 1647 } 1648 1649 /** 1650 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 1651 * @hw: pointer to the HW structure 1652 * @speed: stores the current speed 1653 * @duplex: stores the current duplex 1654 * 1655 * Read the status register for the current speed/duplex and store the current 1656 * speed and duplex for copper connections. 1657 **/ 1658 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 1659 u16 *duplex) 1660 { 1661 u32 status; 1662 1663 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 1664 1665 status = E1000_READ_REG(hw, E1000_STATUS); 1666 if (status & E1000_STATUS_SPEED_1000) { 1667 *speed = SPEED_1000; 1668 DEBUGOUT("1000 Mbs, "); 1669 } else if (status & E1000_STATUS_SPEED_100) { 1670 *speed = SPEED_100; 1671 DEBUGOUT("100 Mbs, "); 1672 } else { 1673 *speed = SPEED_10; 1674 DEBUGOUT("10 Mbs, "); 1675 } 1676 1677 if (status & E1000_STATUS_FD) { 1678 *duplex = FULL_DUPLEX; 1679 DEBUGOUT("Full Duplex\n"); 1680 } else { 1681 *duplex = HALF_DUPLEX; 1682 DEBUGOUT("Half Duplex\n"); 1683 } 1684 1685 return E1000_SUCCESS; 1686 } 1687 1688 /** 1689 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex 1690 * @hw: pointer to the HW structure 1691 * @speed: stores the current speed 1692 * @duplex: stores the current duplex 1693 * 1694 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1695 * for fiber/serdes links. 1696 **/ 1697 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw E1000_UNUSEDARG *hw, 1698 u16 *speed, u16 *duplex) 1699 { 1700 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 1701 1702 *speed = SPEED_1000; 1703 *duplex = FULL_DUPLEX; 1704 1705 return E1000_SUCCESS; 1706 } 1707 1708 /** 1709 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 1710 * @hw: pointer to the HW structure 1711 * 1712 * Acquire the HW semaphore to access the PHY or NVM 1713 **/ 1714 s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 1715 { 1716 u32 swsm; 1717 s32 timeout = hw->nvm.word_size + 1; 1718 s32 i = 0; 1719 1720 DEBUGFUNC("e1000_get_hw_semaphore_generic"); 1721 1722 /* Get the SW semaphore */ 1723 while (i < timeout) { 1724 swsm = E1000_READ_REG(hw, E1000_SWSM); 1725 if (!(swsm & E1000_SWSM_SMBI)) 1726 break; 1727 1728 usec_delay(50); 1729 i++; 1730 } 1731 1732 if (i == timeout) { 1733 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1734 return -E1000_ERR_NVM; 1735 } 1736 1737 /* Get the FW semaphore. */ 1738 for (i = 0; i < timeout; i++) { 1739 swsm = E1000_READ_REG(hw, E1000_SWSM); 1740 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 1741 1742 /* Semaphore acquired if bit latched */ 1743 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 1744 break; 1745 1746 usec_delay(50); 1747 } 1748 1749 if (i == timeout) { 1750 /* Release semaphores */ 1751 e1000_put_hw_semaphore_generic(hw); 1752 DEBUGOUT("Driver can't access the NVM\n"); 1753 return -E1000_ERR_NVM; 1754 } 1755 1756 return E1000_SUCCESS; 1757 } 1758 1759 /** 1760 * e1000_put_hw_semaphore_generic - Release hardware semaphore 1761 * @hw: pointer to the HW structure 1762 * 1763 * Release hardware semaphore used to access the PHY or NVM 1764 **/ 1765 void e1000_put_hw_semaphore_generic(struct e1000_hw *hw) 1766 { 1767 u32 swsm; 1768 1769 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 1770 1771 swsm = E1000_READ_REG(hw, E1000_SWSM); 1772 1773 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1774 1775 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 1776 } 1777 1778 /** 1779 * e1000_get_auto_rd_done_generic - Check for auto read completion 1780 * @hw: pointer to the HW structure 1781 * 1782 * Check EEPROM for Auto Read done bit. 1783 **/ 1784 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 1785 { 1786 s32 i = 0; 1787 1788 DEBUGFUNC("e1000_get_auto_rd_done_generic"); 1789 1790 while (i < AUTO_READ_DONE_TIMEOUT) { 1791 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 1792 break; 1793 msec_delay(1); 1794 i++; 1795 } 1796 1797 if (i == AUTO_READ_DONE_TIMEOUT) { 1798 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1799 return -E1000_ERR_RESET; 1800 } 1801 1802 return E1000_SUCCESS; 1803 } 1804 1805 /** 1806 * e1000_valid_led_default_generic - Verify a valid default LED config 1807 * @hw: pointer to the HW structure 1808 * @data: pointer to the NVM (EEPROM) 1809 * 1810 * Read the EEPROM for the current default LED configuration. If the 1811 * LED configuration is not valid, set to a valid LED configuration. 1812 **/ 1813 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 1814 { 1815 s32 ret_val; 1816 1817 DEBUGFUNC("e1000_valid_led_default_generic"); 1818 1819 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1820 if (ret_val) { 1821 DEBUGOUT("NVM Read Error\n"); 1822 return ret_val; 1823 } 1824 1825 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1826 *data = ID_LED_DEFAULT; 1827 1828 return E1000_SUCCESS; 1829 } 1830 1831 /** 1832 * e1000_id_led_init_generic - 1833 * @hw: pointer to the HW structure 1834 * 1835 **/ 1836 s32 e1000_id_led_init_generic(struct e1000_hw *hw) 1837 { 1838 struct e1000_mac_info *mac = &hw->mac; 1839 s32 ret_val; 1840 const u32 ledctl_mask = 0x000000FF; 1841 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1842 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1843 u16 data, i, temp; 1844 const u16 led_mask = 0x0F; 1845 1846 DEBUGFUNC("e1000_id_led_init_generic"); 1847 1848 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 1849 if (ret_val) 1850 return ret_val; 1851 1852 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 1853 mac->ledctl_mode1 = mac->ledctl_default; 1854 mac->ledctl_mode2 = mac->ledctl_default; 1855 1856 for (i = 0; i < 4; i++) { 1857 temp = (data >> (i << 2)) & led_mask; 1858 switch (temp) { 1859 case ID_LED_ON1_DEF2: 1860 case ID_LED_ON1_ON2: 1861 case ID_LED_ON1_OFF2: 1862 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1863 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1864 break; 1865 case ID_LED_OFF1_DEF2: 1866 case ID_LED_OFF1_ON2: 1867 case ID_LED_OFF1_OFF2: 1868 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1869 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1870 break; 1871 default: 1872 /* Do nothing */ 1873 break; 1874 } 1875 switch (temp) { 1876 case ID_LED_DEF1_ON2: 1877 case ID_LED_ON1_ON2: 1878 case ID_LED_OFF1_ON2: 1879 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1880 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1881 break; 1882 case ID_LED_DEF1_OFF2: 1883 case ID_LED_ON1_OFF2: 1884 case ID_LED_OFF1_OFF2: 1885 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1886 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1887 break; 1888 default: 1889 /* Do nothing */ 1890 break; 1891 } 1892 } 1893 1894 return E1000_SUCCESS; 1895 } 1896 1897 /** 1898 * e1000_setup_led_generic - Configures SW controllable LED 1899 * @hw: pointer to the HW structure 1900 * 1901 * This prepares the SW controllable LED for use and saves the current state 1902 * of the LED so it can be later restored. 1903 **/ 1904 s32 e1000_setup_led_generic(struct e1000_hw *hw) 1905 { 1906 u32 ledctl; 1907 1908 DEBUGFUNC("e1000_setup_led_generic"); 1909 1910 if (hw->mac.ops.setup_led != e1000_setup_led_generic) 1911 return -E1000_ERR_CONFIG; 1912 1913 if (hw->phy.media_type == e1000_media_type_fiber) { 1914 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 1915 hw->mac.ledctl_default = ledctl; 1916 /* Turn off LED0 */ 1917 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK | 1918 E1000_LEDCTL_LED0_MODE_MASK); 1919 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1920 E1000_LEDCTL_LED0_MODE_SHIFT); 1921 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 1922 } else if (hw->phy.media_type == e1000_media_type_copper) { 1923 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1924 } 1925 1926 return E1000_SUCCESS; 1927 } 1928 1929 /** 1930 * e1000_cleanup_led_generic - Set LED config to default operation 1931 * @hw: pointer to the HW structure 1932 * 1933 * Remove the current LED configuration and set the LED configuration 1934 * to the default value, saved from the EEPROM. 1935 **/ 1936 s32 e1000_cleanup_led_generic(struct e1000_hw *hw) 1937 { 1938 DEBUGFUNC("e1000_cleanup_led_generic"); 1939 1940 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1941 return E1000_SUCCESS; 1942 } 1943 1944 /** 1945 * e1000_blink_led_generic - Blink LED 1946 * @hw: pointer to the HW structure 1947 * 1948 * Blink the LEDs which are set to be on. 1949 **/ 1950 s32 e1000_blink_led_generic(struct e1000_hw *hw) 1951 { 1952 u32 ledctl_blink = 0; 1953 u32 i; 1954 1955 DEBUGFUNC("e1000_blink_led_generic"); 1956 1957 if (hw->phy.media_type == e1000_media_type_fiber) { 1958 /* always blink LED0 for PCI-E fiber */ 1959 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1960 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1961 } else { 1962 /* Set the blink bit for each LED that's "on" (0x0E) 1963 * (or "off" if inverted) in ledctl_mode2. The blink 1964 * logic in hardware only works when mode is set to "on" 1965 * so it must be changed accordingly when the mode is 1966 * "off" and inverted. 1967 */ 1968 ledctl_blink = hw->mac.ledctl_mode2; 1969 for (i = 0; i < 32; i += 8) { 1970 u32 mode = (hw->mac.ledctl_mode2 >> i) & 1971 E1000_LEDCTL_LED0_MODE_MASK; 1972 u32 led_default = hw->mac.ledctl_default >> i; 1973 1974 if ((!(led_default & E1000_LEDCTL_LED0_IVRT) && 1975 (mode == E1000_LEDCTL_MODE_LED_ON)) || 1976 ((led_default & E1000_LEDCTL_LED0_IVRT) && 1977 (mode == E1000_LEDCTL_MODE_LED_OFF))) { 1978 ledctl_blink &= 1979 ~(E1000_LEDCTL_LED0_MODE_MASK << i); 1980 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK | 1981 E1000_LEDCTL_MODE_LED_ON) << i; 1982 } 1983 } 1984 } 1985 1986 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 1987 1988 return E1000_SUCCESS; 1989 } 1990 1991 /** 1992 * e1000_led_on_generic - Turn LED on 1993 * @hw: pointer to the HW structure 1994 * 1995 * Turn LED on. 1996 **/ 1997 s32 e1000_led_on_generic(struct e1000_hw *hw) 1998 { 1999 u32 ctrl; 2000 2001 DEBUGFUNC("e1000_led_on_generic"); 2002 2003 switch (hw->phy.media_type) { 2004 case e1000_media_type_fiber: 2005 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2006 ctrl &= ~E1000_CTRL_SWDPIN0; 2007 ctrl |= E1000_CTRL_SWDPIO0; 2008 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2009 break; 2010 case e1000_media_type_copper: 2011 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 2012 break; 2013 default: 2014 break; 2015 } 2016 2017 return E1000_SUCCESS; 2018 } 2019 2020 /** 2021 * e1000_led_off_generic - Turn LED off 2022 * @hw: pointer to the HW structure 2023 * 2024 * Turn LED off. 2025 **/ 2026 s32 e1000_led_off_generic(struct e1000_hw *hw) 2027 { 2028 u32 ctrl; 2029 2030 DEBUGFUNC("e1000_led_off_generic"); 2031 2032 switch (hw->phy.media_type) { 2033 case e1000_media_type_fiber: 2034 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2035 ctrl |= E1000_CTRL_SWDPIN0; 2036 ctrl |= E1000_CTRL_SWDPIO0; 2037 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2038 break; 2039 case e1000_media_type_copper: 2040 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 2041 break; 2042 default: 2043 break; 2044 } 2045 2046 return E1000_SUCCESS; 2047 } 2048 2049 /** 2050 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 2051 * @hw: pointer to the HW structure 2052 * @no_snoop: bitmap of snoop events 2053 * 2054 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 2055 **/ 2056 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 2057 { 2058 u32 gcr; 2059 2060 DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 2061 2062 if (hw->bus.type != e1000_bus_type_pci_express) 2063 return; 2064 2065 if (no_snoop) { 2066 gcr = E1000_READ_REG(hw, E1000_GCR); 2067 gcr &= ~(PCIE_NO_SNOOP_ALL); 2068 gcr |= no_snoop; 2069 E1000_WRITE_REG(hw, E1000_GCR, gcr); 2070 } 2071 } 2072 2073 /** 2074 * e1000_disable_pcie_master_generic - Disables PCI-express master access 2075 * @hw: pointer to the HW structure 2076 * 2077 * Returns E1000_SUCCESS if successful, else returns -10 2078 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 2079 * the master requests to be disabled. 2080 * 2081 * Disables PCI-Express master access and verifies there are no pending 2082 * requests. 2083 **/ 2084 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw) 2085 { 2086 u32 ctrl; 2087 s32 timeout = MASTER_DISABLE_TIMEOUT; 2088 2089 DEBUGFUNC("e1000_disable_pcie_master_generic"); 2090 2091 if (hw->bus.type != e1000_bus_type_pci_express) 2092 return E1000_SUCCESS; 2093 2094 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2095 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 2096 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2097 2098 while (timeout) { 2099 if (!(E1000_READ_REG(hw, E1000_STATUS) & 2100 E1000_STATUS_GIO_MASTER_ENABLE) || 2101 E1000_REMOVED(hw->hw_addr)) 2102 break; 2103 usec_delay(100); 2104 timeout--; 2105 } 2106 2107 if (!timeout) { 2108 DEBUGOUT("Master requests are pending.\n"); 2109 return -E1000_ERR_MASTER_REQUESTS_PENDING; 2110 } 2111 2112 return E1000_SUCCESS; 2113 } 2114 2115 /** 2116 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 2117 * @hw: pointer to the HW structure 2118 * 2119 * Reset the Adaptive Interframe Spacing throttle to default values. 2120 **/ 2121 void e1000_reset_adaptive_generic(struct e1000_hw *hw) 2122 { 2123 struct e1000_mac_info *mac = &hw->mac; 2124 2125 DEBUGFUNC("e1000_reset_adaptive_generic"); 2126 2127 if (!mac->adaptive_ifs) { 2128 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2129 return; 2130 } 2131 2132 mac->current_ifs_val = 0; 2133 mac->ifs_min_val = IFS_MIN; 2134 mac->ifs_max_val = IFS_MAX; 2135 mac->ifs_step_size = IFS_STEP; 2136 mac->ifs_ratio = IFS_RATIO; 2137 2138 mac->in_ifs_mode = FALSE; 2139 E1000_WRITE_REG(hw, E1000_AIT, 0); 2140 } 2141 2142 /** 2143 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 2144 * @hw: pointer to the HW structure 2145 * 2146 * Update the Adaptive Interframe Spacing Throttle value based on the 2147 * time between transmitted packets and time between collisions. 2148 **/ 2149 void e1000_update_adaptive_generic(struct e1000_hw *hw) 2150 { 2151 struct e1000_mac_info *mac = &hw->mac; 2152 2153 DEBUGFUNC("e1000_update_adaptive_generic"); 2154 2155 if (!mac->adaptive_ifs) { 2156 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2157 return; 2158 } 2159 2160 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 2161 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 2162 mac->in_ifs_mode = TRUE; 2163 if (mac->current_ifs_val < mac->ifs_max_val) { 2164 if (!mac->current_ifs_val) 2165 mac->current_ifs_val = mac->ifs_min_val; 2166 else 2167 mac->current_ifs_val += 2168 mac->ifs_step_size; 2169 E1000_WRITE_REG(hw, E1000_AIT, 2170 mac->current_ifs_val); 2171 } 2172 } 2173 } else { 2174 if (mac->in_ifs_mode && 2175 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 2176 mac->current_ifs_val = 0; 2177 mac->in_ifs_mode = FALSE; 2178 E1000_WRITE_REG(hw, E1000_AIT, 0); 2179 } 2180 } 2181 } 2182 2183 /** 2184 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 2185 * @hw: pointer to the HW structure 2186 * 2187 * Verify that when not using auto-negotiation that MDI/MDIx is correctly 2188 * set, which is forced to MDI mode only. 2189 **/ 2190 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 2191 { 2192 DEBUGFUNC("e1000_validate_mdi_setting_generic"); 2193 2194 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 2195 DEBUGOUT("Invalid MDI setting detected\n"); 2196 hw->phy.mdix = 1; 2197 return -E1000_ERR_CONFIG; 2198 } 2199 2200 return E1000_SUCCESS; 2201 } 2202 2203 /** 2204 * e1000_validate_mdi_setting_crossover_generic - Verify MDI/MDIx settings 2205 * @hw: pointer to the HW structure 2206 * 2207 * Validate the MDI/MDIx setting, allowing for auto-crossover during forced 2208 * operation. 2209 **/ 2210 s32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw E1000_UNUSEDARG *hw) 2211 { 2212 DEBUGFUNC("e1000_validate_mdi_setting_crossover_generic"); 2213 2214 return E1000_SUCCESS; 2215 } 2216 2217 /** 2218 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register 2219 * @hw: pointer to the HW structure 2220 * @reg: 32bit register offset such as E1000_SCTL 2221 * @offset: register offset to write to 2222 * @data: data to write at register offset 2223 * 2224 * Writes an address/data control type register. There are several of these 2225 * and they all have the format address << 8 | data and bit 31 is polled for 2226 * completion. 2227 **/ 2228 s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, 2229 u32 offset, u8 data) 2230 { 2231 u32 i, regvalue = 0; 2232 2233 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); 2234 2235 /* Set up the address and data */ 2236 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 2237 E1000_WRITE_REG(hw, reg, regvalue); 2238 2239 /* Poll the ready bit to see if the MDI read completed */ 2240 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 2241 usec_delay(5); 2242 regvalue = E1000_READ_REG(hw, reg); 2243 if (regvalue & E1000_GEN_CTL_READY) 2244 break; 2245 } 2246 if (!(regvalue & E1000_GEN_CTL_READY)) { 2247 DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 2248 return -E1000_ERR_PHY; 2249 } 2250 2251 return E1000_SUCCESS; 2252 } 2253