1 /****************************************************************************** 2 3 Copyright (c) 2001-2011, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "e1000_api.h" 36 37 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw); 38 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); 39 static void e1000_config_collision_dist_generic(struct e1000_hw *hw); 40 41 /** 42 * e1000_init_mac_ops_generic - Initialize MAC function pointers 43 * @hw: pointer to the HW structure 44 * 45 * Setups up the function pointers to no-op functions 46 **/ 47 void e1000_init_mac_ops_generic(struct e1000_hw *hw) 48 { 49 struct e1000_mac_info *mac = &hw->mac; 50 DEBUGFUNC("e1000_init_mac_ops_generic"); 51 52 /* General Setup */ 53 mac->ops.init_params = e1000_null_ops_generic; 54 mac->ops.init_hw = e1000_null_ops_generic; 55 mac->ops.reset_hw = e1000_null_ops_generic; 56 mac->ops.setup_physical_interface = e1000_null_ops_generic; 57 mac->ops.get_bus_info = e1000_null_ops_generic; 58 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie; 59 mac->ops.read_mac_addr = e1000_read_mac_addr_generic; 60 mac->ops.config_collision_dist = e1000_config_collision_dist_generic; 61 mac->ops.clear_hw_cntrs = e1000_null_mac_generic; 62 /* LED */ 63 mac->ops.cleanup_led = e1000_null_ops_generic; 64 mac->ops.setup_led = e1000_null_ops_generic; 65 mac->ops.blink_led = e1000_null_ops_generic; 66 mac->ops.led_on = e1000_null_ops_generic; 67 mac->ops.led_off = e1000_null_ops_generic; 68 /* LINK */ 69 mac->ops.setup_link = e1000_null_ops_generic; 70 mac->ops.get_link_up_info = e1000_null_link_info; 71 mac->ops.check_for_link = e1000_null_ops_generic; 72 mac->ops.wait_autoneg = e1000_wait_autoneg_generic; 73 /* Management */ 74 mac->ops.check_mng_mode = e1000_null_mng_mode; 75 mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic; 76 mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic; 77 mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic; 78 /* VLAN, MC, etc. */ 79 mac->ops.update_mc_addr_list = e1000_null_update_mc; 80 mac->ops.clear_vfta = e1000_null_mac_generic; 81 mac->ops.write_vfta = e1000_null_write_vfta; 82 mac->ops.rar_set = e1000_rar_set_generic; 83 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; 84 } 85 86 /** 87 * e1000_null_ops_generic - No-op function, returns 0 88 * @hw: pointer to the HW structure 89 **/ 90 s32 e1000_null_ops_generic(struct e1000_hw *hw) 91 { 92 DEBUGFUNC("e1000_null_ops_generic"); 93 return E1000_SUCCESS; 94 } 95 96 /** 97 * e1000_null_mac_generic - No-op function, return void 98 * @hw: pointer to the HW structure 99 **/ 100 void e1000_null_mac_generic(struct e1000_hw *hw) 101 { 102 DEBUGFUNC("e1000_null_mac_generic"); 103 return; 104 } 105 106 /** 107 * e1000_null_link_info - No-op function, return 0 108 * @hw: pointer to the HW structure 109 **/ 110 s32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d) 111 { 112 DEBUGFUNC("e1000_null_link_info"); 113 return E1000_SUCCESS; 114 } 115 116 /** 117 * e1000_null_mng_mode - No-op function, return FALSE 118 * @hw: pointer to the HW structure 119 **/ 120 bool e1000_null_mng_mode(struct e1000_hw *hw) 121 { 122 DEBUGFUNC("e1000_null_mng_mode"); 123 return FALSE; 124 } 125 126 /** 127 * e1000_null_update_mc - No-op function, return void 128 * @hw: pointer to the HW structure 129 **/ 130 void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a) 131 { 132 DEBUGFUNC("e1000_null_update_mc"); 133 return; 134 } 135 136 /** 137 * e1000_null_write_vfta - No-op function, return void 138 * @hw: pointer to the HW structure 139 **/ 140 void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b) 141 { 142 DEBUGFUNC("e1000_null_write_vfta"); 143 return; 144 } 145 146 /** 147 * e1000_null_rar_set - No-op function, return void 148 * @hw: pointer to the HW structure 149 **/ 150 void e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a) 151 { 152 DEBUGFUNC("e1000_null_rar_set"); 153 return; 154 } 155 156 /** 157 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information 158 * @hw: pointer to the HW structure 159 * 160 * Determines and stores the system bus information for a particular 161 * network interface. The following bus information is determined and stored: 162 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function. 163 **/ 164 s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw) 165 { 166 struct e1000_mac_info *mac = &hw->mac; 167 struct e1000_bus_info *bus = &hw->bus; 168 u32 status = E1000_READ_REG(hw, E1000_STATUS); 169 s32 ret_val = E1000_SUCCESS; 170 171 DEBUGFUNC("e1000_get_bus_info_pci_generic"); 172 173 /* PCI or PCI-X? */ 174 bus->type = (status & E1000_STATUS_PCIX_MODE) 175 ? e1000_bus_type_pcix 176 : e1000_bus_type_pci; 177 178 /* Bus speed */ 179 if (bus->type == e1000_bus_type_pci) { 180 bus->speed = (status & E1000_STATUS_PCI66) 181 ? e1000_bus_speed_66 182 : e1000_bus_speed_33; 183 } else { 184 switch (status & E1000_STATUS_PCIX_SPEED) { 185 case E1000_STATUS_PCIX_SPEED_66: 186 bus->speed = e1000_bus_speed_66; 187 break; 188 case E1000_STATUS_PCIX_SPEED_100: 189 bus->speed = e1000_bus_speed_100; 190 break; 191 case E1000_STATUS_PCIX_SPEED_133: 192 bus->speed = e1000_bus_speed_133; 193 break; 194 default: 195 bus->speed = e1000_bus_speed_reserved; 196 break; 197 } 198 } 199 200 /* Bus width */ 201 bus->width = (status & E1000_STATUS_BUS64) 202 ? e1000_bus_width_64 203 : e1000_bus_width_32; 204 205 /* Which PCI(-X) function? */ 206 mac->ops.set_lan_id(hw); 207 208 return ret_val; 209 } 210 211 /** 212 * e1000_get_bus_info_pcie_generic - Get PCIe bus information 213 * @hw: pointer to the HW structure 214 * 215 * Determines and stores the system bus information for a particular 216 * network interface. The following bus information is determined and stored: 217 * bus speed, bus width, type (PCIe), and PCIe function. 218 **/ 219 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 220 { 221 struct e1000_mac_info *mac = &hw->mac; 222 struct e1000_bus_info *bus = &hw->bus; 223 s32 ret_val; 224 u16 pcie_link_status; 225 226 DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 227 228 bus->type = e1000_bus_type_pci_express; 229 230 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS, 231 &pcie_link_status); 232 if (ret_val) { 233 bus->width = e1000_bus_width_unknown; 234 bus->speed = e1000_bus_speed_unknown; 235 } else { 236 switch (pcie_link_status & PCIE_LINK_SPEED_MASK) { 237 case PCIE_LINK_SPEED_2500: 238 bus->speed = e1000_bus_speed_2500; 239 break; 240 case PCIE_LINK_SPEED_5000: 241 bus->speed = e1000_bus_speed_5000; 242 break; 243 default: 244 bus->speed = e1000_bus_speed_unknown; 245 break; 246 } 247 248 bus->width = (enum e1000_bus_width)((pcie_link_status & 249 PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT); 250 } 251 252 mac->ops.set_lan_id(hw); 253 254 return E1000_SUCCESS; 255 } 256 257 /** 258 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 259 * 260 * @hw: pointer to the HW structure 261 * 262 * Determines the LAN function id by reading memory-mapped registers 263 * and swaps the port value if requested. 264 **/ 265 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) 266 { 267 struct e1000_bus_info *bus = &hw->bus; 268 u32 reg; 269 270 /* 271 * The status register reports the correct function number 272 * for the device regardless of function swap state. 273 */ 274 reg = E1000_READ_REG(hw, E1000_STATUS); 275 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 276 } 277 278 /** 279 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices 280 * @hw: pointer to the HW structure 281 * 282 * Determines the LAN function id by reading PCI config space. 283 **/ 284 void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw) 285 { 286 struct e1000_bus_info *bus = &hw->bus; 287 u16 pci_header_type; 288 u32 status; 289 290 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 291 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { 292 status = E1000_READ_REG(hw, E1000_STATUS); 293 bus->func = (status & E1000_STATUS_FUNC_MASK) 294 >> E1000_STATUS_FUNC_SHIFT; 295 } else { 296 bus->func = 0; 297 } 298 } 299 300 /** 301 * e1000_set_lan_id_single_port - Set LAN id for a single port device 302 * @hw: pointer to the HW structure 303 * 304 * Sets the LAN function id to zero for a single port device. 305 **/ 306 void e1000_set_lan_id_single_port(struct e1000_hw *hw) 307 { 308 struct e1000_bus_info *bus = &hw->bus; 309 310 bus->func = 0; 311 } 312 313 /** 314 * e1000_clear_vfta_generic - Clear VLAN filter table 315 * @hw: pointer to the HW structure 316 * 317 * Clears the register array which contains the VLAN filter table by 318 * setting all the values to 0. 319 **/ 320 void e1000_clear_vfta_generic(struct e1000_hw *hw) 321 { 322 u32 offset; 323 324 DEBUGFUNC("e1000_clear_vfta_generic"); 325 326 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 327 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 328 E1000_WRITE_FLUSH(hw); 329 } 330 } 331 332 /** 333 * e1000_write_vfta_generic - Write value to VLAN filter table 334 * @hw: pointer to the HW structure 335 * @offset: register offset in VLAN filter table 336 * @value: register value written to VLAN filter table 337 * 338 * Writes value at the given offset in the register array which stores 339 * the VLAN filter table. 340 **/ 341 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 342 { 343 DEBUGFUNC("e1000_write_vfta_generic"); 344 345 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 346 E1000_WRITE_FLUSH(hw); 347 } 348 349 /** 350 * e1000_init_rx_addrs_generic - Initialize receive address's 351 * @hw: pointer to the HW structure 352 * @rar_count: receive address registers 353 * 354 * Setup the receive address registers by setting the base receive address 355 * register to the devices MAC address and clearing all the other receive 356 * address registers to 0. 357 **/ 358 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 359 { 360 u32 i; 361 u8 mac_addr[ETH_ADDR_LEN] = {0}; 362 363 DEBUGFUNC("e1000_init_rx_addrs_generic"); 364 365 /* Setup the receive address */ 366 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 367 368 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 369 370 /* Zero out the other (rar_entry_count - 1) receive addresses */ 371 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 372 for (i = 1; i < rar_count; i++) 373 hw->mac.ops.rar_set(hw, mac_addr, i); 374 } 375 376 /** 377 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 378 * @hw: pointer to the HW structure 379 * 380 * Checks the nvm for an alternate MAC address. An alternate MAC address 381 * can be setup by pre-boot software and must be treated like a permanent 382 * address and must override the actual permanent MAC address. If an 383 * alternate MAC address is found it is programmed into RAR0, replacing 384 * the permanent address that was installed into RAR0 by the Si on reset. 385 * This function will return SUCCESS unless it encounters an error while 386 * reading the EEPROM. 387 **/ 388 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 389 { 390 u32 i; 391 s32 ret_val = E1000_SUCCESS; 392 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 393 u8 alt_mac_addr[ETH_ADDR_LEN]; 394 395 DEBUGFUNC("e1000_check_alt_mac_addr_generic"); 396 397 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data); 398 if (ret_val) 399 return ret_val; 400 401 #if !defined(NO_82542_SUPPORT) || !defined(NO_82543_SUPPORT) || !defined(NO_82540_SUPPORT) || !defined(NO_82541_SUPPORT) 402 /* not supported on older hardware or 82573 */ 403 if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573)) 404 #else 405 /* not supported on 82573 */ 406 if (hw->mac.type == e1000_82573) 407 #endif 408 return E1000_SUCCESS; 409 410 /* 411 * Alternate MAC address is handled by the option ROM for 82580 412 * and newer. SW support not required. 413 */ 414 if (hw->mac.type >= e1000_82580) 415 return E1000_SUCCESS; 416 417 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 418 &nvm_alt_mac_addr_offset); 419 if (ret_val) { 420 DEBUGOUT("NVM Read Error\n"); 421 return ret_val; 422 } 423 424 if ((nvm_alt_mac_addr_offset == 0xFFFF) || 425 (nvm_alt_mac_addr_offset == 0x0000)) 426 /* There is no Alternate MAC Address */ 427 return E1000_SUCCESS; 428 429 if (hw->bus.func == E1000_FUNC_1) 430 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 431 if (hw->bus.func == E1000_FUNC_2) 432 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2; 433 434 if (hw->bus.func == E1000_FUNC_3) 435 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3; 436 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 437 offset = nvm_alt_mac_addr_offset + (i >> 1); 438 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 439 if (ret_val) { 440 DEBUGOUT("NVM Read Error\n"); 441 return ret_val; 442 } 443 444 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 445 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 446 } 447 448 /* if multicast bit is set, the alternate address will not be used */ 449 if (alt_mac_addr[0] & 0x01) { 450 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); 451 return E1000_SUCCESS; 452 } 453 454 /* 455 * We have a valid alternate MAC address, and we want to treat it the 456 * same as the normal permanent MAC address stored by the HW into the 457 * RAR. Do this by mapping this address into RAR0. 458 */ 459 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 460 461 return E1000_SUCCESS; 462 } 463 464 /** 465 * e1000_rar_set_generic - Set receive address register 466 * @hw: pointer to the HW structure 467 * @addr: pointer to the receive address 468 * @index: receive address array register 469 * 470 * Sets the receive address array register at index to the address passed 471 * in by addr. 472 **/ 473 void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 474 { 475 u32 rar_low, rar_high; 476 477 DEBUGFUNC("e1000_rar_set_generic"); 478 479 /* 480 * HW expects these in little endian so we reverse the byte order 481 * from network order (big endian) to little endian 482 */ 483 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 484 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 485 486 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 487 488 /* If MAC address zero, no need to set the AV bit */ 489 if (rar_low || rar_high) 490 rar_high |= E1000_RAH_AV; 491 492 /* 493 * Some bridges will combine consecutive 32-bit writes into 494 * a single burst write, which will malfunction on some parts. 495 * The flushes avoid this. 496 */ 497 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 498 E1000_WRITE_FLUSH(hw); 499 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 500 E1000_WRITE_FLUSH(hw); 501 } 502 503 /** 504 * e1000_hash_mc_addr_generic - Generate a multicast hash value 505 * @hw: pointer to the HW structure 506 * @mc_addr: pointer to a multicast address 507 * 508 * Generates a multicast address hash value which is used to determine 509 * the multicast filter table array address and new table value. 510 **/ 511 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 512 { 513 u32 hash_value, hash_mask; 514 u8 bit_shift = 0; 515 516 DEBUGFUNC("e1000_hash_mc_addr_generic"); 517 518 /* Register count multiplied by bits per register */ 519 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 520 521 /* 522 * For a mc_filter_type of 0, bit_shift is the number of left-shifts 523 * where 0xFF would still fall within the hash mask. 524 */ 525 while (hash_mask >> bit_shift != 0xFF) 526 bit_shift++; 527 528 /* 529 * The portion of the address that is used for the hash table 530 * is determined by the mc_filter_type setting. 531 * The algorithm is such that there is a total of 8 bits of shifting. 532 * The bit_shift for a mc_filter_type of 0 represents the number of 533 * left-shifts where the MSB of mc_addr[5] would still fall within 534 * the hash_mask. Case 0 does this exactly. Since there are a total 535 * of 8 bits of shifting, then mc_addr[4] will shift right the 536 * remaining number of bits. Thus 8 - bit_shift. The rest of the 537 * cases are a variation of this algorithm...essentially raising the 538 * number of bits to shift mc_addr[5] left, while still keeping the 539 * 8-bit shifting total. 540 * 541 * For example, given the following Destination MAC Address and an 542 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 543 * we can see that the bit_shift for case 0 is 4. These are the hash 544 * values resulting from each mc_filter_type... 545 * [0] [1] [2] [3] [4] [5] 546 * 01 AA 00 12 34 56 547 * LSB MSB 548 * 549 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 550 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 551 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 552 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 553 */ 554 switch (hw->mac.mc_filter_type) { 555 default: 556 case 0: 557 break; 558 case 1: 559 bit_shift += 1; 560 break; 561 case 2: 562 bit_shift += 2; 563 break; 564 case 3: 565 bit_shift += 4; 566 break; 567 } 568 569 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 570 (((u16) mc_addr[5]) << bit_shift))); 571 572 return hash_value; 573 } 574 575 /** 576 * e1000_update_mc_addr_list_generic - Update Multicast addresses 577 * @hw: pointer to the HW structure 578 * @mc_addr_list: array of multicast addresses to program 579 * @mc_addr_count: number of multicast addresses to program 580 * 581 * Updates entire Multicast Table Array. 582 * The caller must have a packed mc_addr_list of multicast addresses. 583 **/ 584 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw, 585 u8 *mc_addr_list, u32 mc_addr_count) 586 { 587 u32 hash_value, hash_bit, hash_reg; 588 int i; 589 590 DEBUGFUNC("e1000_update_mc_addr_list_generic"); 591 592 /* clear mta_shadow */ 593 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 594 595 /* update mta_shadow from mc_addr_list */ 596 for (i = 0; (u32) i < mc_addr_count; i++) { 597 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list); 598 599 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 600 hash_bit = hash_value & 0x1F; 601 602 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 603 mc_addr_list += (ETH_ADDR_LEN); 604 } 605 606 /* replace the entire MTA table */ 607 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 608 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 609 E1000_WRITE_FLUSH(hw); 610 } 611 612 /** 613 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value 614 * @hw: pointer to the HW structure 615 * 616 * In certain situations, a system BIOS may report that the PCIx maximum 617 * memory read byte count (MMRBC) value is higher than than the actual 618 * value. We check the PCIx command register with the current PCIx status 619 * register. 620 **/ 621 void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw) 622 { 623 u16 cmd_mmrbc; 624 u16 pcix_cmd; 625 u16 pcix_stat_hi_word; 626 u16 stat_mmrbc; 627 628 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); 629 630 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ 631 if (hw->bus.type != e1000_bus_type_pcix) 632 return; 633 634 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 635 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 636 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> 637 PCIX_COMMAND_MMRBC_SHIFT; 638 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 639 PCIX_STATUS_HI_MMRBC_SHIFT; 640 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 641 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 642 if (cmd_mmrbc > stat_mmrbc) { 643 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; 644 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 645 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 646 } 647 } 648 649 /** 650 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 651 * @hw: pointer to the HW structure 652 * 653 * Clears the base hardware counters by reading the counter registers. 654 **/ 655 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 656 { 657 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 658 659 E1000_READ_REG(hw, E1000_CRCERRS); 660 E1000_READ_REG(hw, E1000_SYMERRS); 661 E1000_READ_REG(hw, E1000_MPC); 662 E1000_READ_REG(hw, E1000_SCC); 663 E1000_READ_REG(hw, E1000_ECOL); 664 E1000_READ_REG(hw, E1000_MCC); 665 E1000_READ_REG(hw, E1000_LATECOL); 666 E1000_READ_REG(hw, E1000_COLC); 667 E1000_READ_REG(hw, E1000_DC); 668 E1000_READ_REG(hw, E1000_SEC); 669 E1000_READ_REG(hw, E1000_RLEC); 670 E1000_READ_REG(hw, E1000_XONRXC); 671 E1000_READ_REG(hw, E1000_XONTXC); 672 E1000_READ_REG(hw, E1000_XOFFRXC); 673 E1000_READ_REG(hw, E1000_XOFFTXC); 674 E1000_READ_REG(hw, E1000_FCRUC); 675 E1000_READ_REG(hw, E1000_GPRC); 676 E1000_READ_REG(hw, E1000_BPRC); 677 E1000_READ_REG(hw, E1000_MPRC); 678 E1000_READ_REG(hw, E1000_GPTC); 679 E1000_READ_REG(hw, E1000_GORCL); 680 E1000_READ_REG(hw, E1000_GORCH); 681 E1000_READ_REG(hw, E1000_GOTCL); 682 E1000_READ_REG(hw, E1000_GOTCH); 683 E1000_READ_REG(hw, E1000_RNBC); 684 E1000_READ_REG(hw, E1000_RUC); 685 E1000_READ_REG(hw, E1000_RFC); 686 E1000_READ_REG(hw, E1000_ROC); 687 E1000_READ_REG(hw, E1000_RJC); 688 E1000_READ_REG(hw, E1000_TORL); 689 E1000_READ_REG(hw, E1000_TORH); 690 E1000_READ_REG(hw, E1000_TOTL); 691 E1000_READ_REG(hw, E1000_TOTH); 692 E1000_READ_REG(hw, E1000_TPR); 693 E1000_READ_REG(hw, E1000_TPT); 694 E1000_READ_REG(hw, E1000_MPTC); 695 E1000_READ_REG(hw, E1000_BPTC); 696 } 697 698 /** 699 * e1000_check_for_copper_link_generic - Check for link (Copper) 700 * @hw: pointer to the HW structure 701 * 702 * Checks to see of the link status of the hardware has changed. If a 703 * change in link status has been detected, then we read the PHY registers 704 * to get the current speed/duplex if link exists. 705 **/ 706 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) 707 { 708 struct e1000_mac_info *mac = &hw->mac; 709 s32 ret_val; 710 bool link; 711 712 DEBUGFUNC("e1000_check_for_copper_link"); 713 714 /* 715 * We only want to go out to the PHY registers to see if Auto-Neg 716 * has completed and/or if our link status has changed. The 717 * get_link_status flag is set upon receiving a Link Status 718 * Change or Rx Sequence Error interrupt. 719 */ 720 if (!mac->get_link_status) 721 return E1000_SUCCESS; 722 723 /* 724 * First we want to see if the MII Status Register reports 725 * link. If so, then we want to get the current speed/duplex 726 * of the PHY. 727 */ 728 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 729 if (ret_val) 730 return ret_val; 731 732 if (!link) 733 return E1000_SUCCESS; /* No link detected */ 734 735 mac->get_link_status = FALSE; 736 737 /* 738 * Check if there was DownShift, must be checked 739 * immediately after link-up 740 */ 741 e1000_check_downshift_generic(hw); 742 743 /* 744 * If we are forcing speed/duplex, then we simply return since 745 * we have already determined whether we have link or not. 746 */ 747 if (!mac->autoneg) 748 return -E1000_ERR_CONFIG; 749 750 /* 751 * Auto-Neg is enabled. Auto Speed Detection takes care 752 * of MAC speed/duplex configuration. So we only need to 753 * configure Collision Distance in the MAC. 754 */ 755 mac->ops.config_collision_dist(hw); 756 757 /* 758 * Configure Flow Control now that Auto-Neg has completed. 759 * First, we need to restore the desired flow control 760 * settings because we may have had to re-autoneg with a 761 * different link partner. 762 */ 763 ret_val = e1000_config_fc_after_link_up_generic(hw); 764 if (ret_val) 765 DEBUGOUT("Error configuring flow control\n"); 766 767 return ret_val; 768 } 769 770 /** 771 * e1000_check_for_fiber_link_generic - Check for link (Fiber) 772 * @hw: pointer to the HW structure 773 * 774 * Checks for link up on the hardware. If link is not up and we have 775 * a signal, then we need to force link up. 776 **/ 777 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 778 { 779 struct e1000_mac_info *mac = &hw->mac; 780 u32 rxcw; 781 u32 ctrl; 782 u32 status; 783 s32 ret_val; 784 785 DEBUGFUNC("e1000_check_for_fiber_link_generic"); 786 787 ctrl = E1000_READ_REG(hw, E1000_CTRL); 788 status = E1000_READ_REG(hw, E1000_STATUS); 789 rxcw = E1000_READ_REG(hw, E1000_RXCW); 790 791 /* 792 * If we don't have link (auto-negotiation failed or link partner 793 * cannot auto-negotiate), the cable is plugged in (we have signal), 794 * and our link partner is not trying to auto-negotiate with us (we 795 * are receiving idles or data), we need to force link up. We also 796 * need to give auto-negotiation time to complete, in case the cable 797 * was just plugged in. The autoneg_failed flag does this. 798 */ 799 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 800 if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) && 801 !(rxcw & E1000_RXCW_C)) { 802 if (!mac->autoneg_failed) { 803 mac->autoneg_failed = TRUE; 804 return E1000_SUCCESS; 805 } 806 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 807 808 /* Disable auto-negotiation in the TXCW register */ 809 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 810 811 /* Force link-up and also force full-duplex. */ 812 ctrl = E1000_READ_REG(hw, E1000_CTRL); 813 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 814 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 815 816 /* Configure Flow Control after forcing link up. */ 817 ret_val = e1000_config_fc_after_link_up_generic(hw); 818 if (ret_val) { 819 DEBUGOUT("Error configuring flow control\n"); 820 return ret_val; 821 } 822 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 823 /* 824 * If we are forcing link and we are receiving /C/ ordered 825 * sets, re-enable auto-negotiation in the TXCW register 826 * and disable forced link in the Device Control register 827 * in an attempt to auto-negotiate with our link partner. 828 */ 829 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 830 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 831 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 832 833 mac->serdes_has_link = TRUE; 834 } 835 836 return E1000_SUCCESS; 837 } 838 839 /** 840 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 841 * @hw: pointer to the HW structure 842 * 843 * Checks for link up on the hardware. If link is not up and we have 844 * a signal, then we need to force link up. 845 **/ 846 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 847 { 848 struct e1000_mac_info *mac = &hw->mac; 849 u32 rxcw; 850 u32 ctrl; 851 u32 status; 852 s32 ret_val; 853 854 DEBUGFUNC("e1000_check_for_serdes_link_generic"); 855 856 ctrl = E1000_READ_REG(hw, E1000_CTRL); 857 status = E1000_READ_REG(hw, E1000_STATUS); 858 rxcw = E1000_READ_REG(hw, E1000_RXCW); 859 860 /* 861 * If we don't have link (auto-negotiation failed or link partner 862 * cannot auto-negotiate), and our link partner is not trying to 863 * auto-negotiate with us (we are receiving idles or data), 864 * we need to force link up. We also need to give auto-negotiation 865 * time to complete. 866 */ 867 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 868 if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) { 869 if (!mac->autoneg_failed) { 870 mac->autoneg_failed = TRUE; 871 return E1000_SUCCESS; 872 } 873 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 874 875 /* Disable auto-negotiation in the TXCW register */ 876 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 877 878 /* Force link-up and also force full-duplex. */ 879 ctrl = E1000_READ_REG(hw, E1000_CTRL); 880 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 881 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 882 883 /* Configure Flow Control after forcing link up. */ 884 ret_val = e1000_config_fc_after_link_up_generic(hw); 885 if (ret_val) { 886 DEBUGOUT("Error configuring flow control\n"); 887 return ret_val; 888 } 889 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 890 /* 891 * If we are forcing link and we are receiving /C/ ordered 892 * sets, re-enable auto-negotiation in the TXCW register 893 * and disable forced link in the Device Control register 894 * in an attempt to auto-negotiate with our link partner. 895 */ 896 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 897 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 898 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 899 900 mac->serdes_has_link = TRUE; 901 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 902 /* 903 * If we force link for non-auto-negotiation switch, check 904 * link status based on MAC synchronization for internal 905 * serdes media type. 906 */ 907 /* SYNCH bit and IV bit are sticky. */ 908 usec_delay(10); 909 rxcw = E1000_READ_REG(hw, E1000_RXCW); 910 if (rxcw & E1000_RXCW_SYNCH) { 911 if (!(rxcw & E1000_RXCW_IV)) { 912 mac->serdes_has_link = TRUE; 913 DEBUGOUT("SERDES: Link up - forced.\n"); 914 } 915 } else { 916 mac->serdes_has_link = FALSE; 917 DEBUGOUT("SERDES: Link down - force failed.\n"); 918 } 919 } 920 921 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 922 status = E1000_READ_REG(hw, E1000_STATUS); 923 if (status & E1000_STATUS_LU) { 924 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 925 usec_delay(10); 926 rxcw = E1000_READ_REG(hw, E1000_RXCW); 927 if (rxcw & E1000_RXCW_SYNCH) { 928 if (!(rxcw & E1000_RXCW_IV)) { 929 mac->serdes_has_link = TRUE; 930 DEBUGOUT("SERDES: Link up - autoneg completed successfully.\n"); 931 } else { 932 mac->serdes_has_link = FALSE; 933 DEBUGOUT("SERDES: Link down - invalid codewords detected in autoneg.\n"); 934 } 935 } else { 936 mac->serdes_has_link = FALSE; 937 DEBUGOUT("SERDES: Link down - no sync.\n"); 938 } 939 } else { 940 mac->serdes_has_link = FALSE; 941 DEBUGOUT("SERDES: Link down - autoneg failed\n"); 942 } 943 } 944 945 return E1000_SUCCESS; 946 } 947 948 /** 949 * e1000_set_default_fc_generic - Set flow control default values 950 * @hw: pointer to the HW structure 951 * 952 * Read the EEPROM for the default values for flow control and store the 953 * values. 954 **/ 955 #ifdef NO_82542_SUPPORT 956 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw) 957 #else 958 s32 e1000_set_default_fc_generic(struct e1000_hw *hw) 959 #endif 960 { 961 s32 ret_val; 962 u16 nvm_data; 963 964 DEBUGFUNC("e1000_set_default_fc_generic"); 965 966 /* 967 * Read and store word 0x0F of the EEPROM. This word contains bits 968 * that determine the hardware's default PAUSE (flow control) mode, 969 * a bit that determines whether the HW defaults to enabling or 970 * disabling auto-negotiation, and the direction of the 971 * SW defined pins. If there is no SW over-ride of the flow 972 * control setting, then the variable hw->fc will 973 * be initialized based on a value in the EEPROM. 974 */ 975 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); 976 977 if (ret_val) { 978 DEBUGOUT("NVM Read Error\n"); 979 return ret_val; 980 } 981 982 if (!(nvm_data & NVM_WORD0F_PAUSE_MASK)) 983 hw->fc.requested_mode = e1000_fc_none; 984 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 985 NVM_WORD0F_ASM_DIR) 986 hw->fc.requested_mode = e1000_fc_tx_pause; 987 else 988 hw->fc.requested_mode = e1000_fc_full; 989 990 return E1000_SUCCESS; 991 } 992 993 /** 994 * e1000_setup_link_generic - Setup flow control and link settings 995 * @hw: pointer to the HW structure 996 * 997 * Determines which flow control settings to use, then configures flow 998 * control. Calls the appropriate media-specific link configuration 999 * function. Assuming the adapter has a valid link partner, a valid link 1000 * should be established. Assumes the hardware has previously been reset 1001 * and the transmitter and receiver are not enabled. 1002 **/ 1003 s32 e1000_setup_link_generic(struct e1000_hw *hw) 1004 { 1005 s32 ret_val; 1006 1007 DEBUGFUNC("e1000_setup_link_generic"); 1008 1009 /* 1010 * In the case of the phy reset being blocked, we already have a link. 1011 * We do not need to set it up again. 1012 */ 1013 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 1014 return E1000_SUCCESS; 1015 1016 /* 1017 * If requested flow control is set to default, set flow control 1018 * based on the EEPROM flow control settings. 1019 */ 1020 if (hw->fc.requested_mode == e1000_fc_default) { 1021 ret_val = e1000_set_default_fc_generic(hw); 1022 if (ret_val) 1023 return ret_val; 1024 } 1025 1026 /* 1027 * Save off the requested flow control mode for use later. Depending 1028 * on the link partner's capabilities, we may or may not use this mode. 1029 */ 1030 hw->fc.current_mode = hw->fc.requested_mode; 1031 1032 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 1033 hw->fc.current_mode); 1034 1035 /* Call the necessary media_type subroutine to configure the link. */ 1036 ret_val = hw->mac.ops.setup_physical_interface(hw); 1037 if (ret_val) 1038 return ret_val; 1039 1040 /* 1041 * Initialize the flow control address, type, and PAUSE timer 1042 * registers to their default values. This is done even if flow 1043 * control is disabled, because it does not hurt anything to 1044 * initialize these registers. 1045 */ 1046 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 1047 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 1048 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1049 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 1050 1051 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 1052 1053 return e1000_set_fc_watermarks_generic(hw); 1054 } 1055 1056 /** 1057 * e1000_commit_fc_settings_generic - Configure flow control 1058 * @hw: pointer to the HW structure 1059 * 1060 * Write the flow control settings to the Transmit Config Word Register (TXCW) 1061 * base on the flow control settings in e1000_mac_info. 1062 **/ 1063 s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 1064 { 1065 struct e1000_mac_info *mac = &hw->mac; 1066 u32 txcw; 1067 1068 DEBUGFUNC("e1000_commit_fc_settings_generic"); 1069 1070 /* 1071 * Check for a software override of the flow control settings, and 1072 * setup the device accordingly. If auto-negotiation is enabled, then 1073 * software will have to set the "PAUSE" bits to the correct value in 1074 * the Transmit Config Word Register (TXCW) and re-start auto- 1075 * negotiation. However, if auto-negotiation is disabled, then 1076 * software will have to manually configure the two flow control enable 1077 * bits in the CTRL register. 1078 * 1079 * The possible values of the "fc" parameter are: 1080 * 0: Flow control is completely disabled 1081 * 1: Rx flow control is enabled (we can receive pause frames, 1082 * but not send pause frames). 1083 * 2: Tx flow control is enabled (we can send pause frames but we 1084 * do not support receiving pause frames). 1085 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1086 */ 1087 switch (hw->fc.current_mode) { 1088 case e1000_fc_none: 1089 /* Flow control completely disabled by a software over-ride. */ 1090 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1091 break; 1092 case e1000_fc_rx_pause: 1093 /* 1094 * Rx Flow control is enabled and Tx Flow control is disabled 1095 * by a software over-ride. Since there really isn't a way to 1096 * advertise that we are capable of Rx Pause ONLY, we will 1097 * advertise that we support both symmetric and asymmetric Rx 1098 * PAUSE. Later, we will disable the adapter's ability to send 1099 * PAUSE frames. 1100 */ 1101 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1102 break; 1103 case e1000_fc_tx_pause: 1104 /* 1105 * Tx Flow control is enabled, and Rx Flow control is disabled, 1106 * by a software over-ride. 1107 */ 1108 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1109 break; 1110 case e1000_fc_full: 1111 /* 1112 * Flow control (both Rx and Tx) is enabled by a software 1113 * over-ride. 1114 */ 1115 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1116 break; 1117 default: 1118 DEBUGOUT("Flow control param set incorrectly\n"); 1119 return -E1000_ERR_CONFIG; 1120 break; 1121 } 1122 1123 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1124 mac->txcw = txcw; 1125 1126 return E1000_SUCCESS; 1127 } 1128 1129 /** 1130 * e1000_poll_fiber_serdes_link_generic - Poll for link up 1131 * @hw: pointer to the HW structure 1132 * 1133 * Polls for link up by reading the status register, if link fails to come 1134 * up with auto-negotiation, then the link is forced if a signal is detected. 1135 **/ 1136 s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 1137 { 1138 struct e1000_mac_info *mac = &hw->mac; 1139 u32 i, status; 1140 s32 ret_val; 1141 1142 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 1143 1144 /* 1145 * If we have a signal (the cable is plugged in, or assumed TRUE for 1146 * serdes media) then poll for a "Link-Up" indication in the Device 1147 * Status Register. Time-out if a link isn't seen in 500 milliseconds 1148 * seconds (Auto-negotiation should complete in less than 500 1149 * milliseconds even if the other end is doing it in SW). 1150 */ 1151 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 1152 msec_delay(10); 1153 status = E1000_READ_REG(hw, E1000_STATUS); 1154 if (status & E1000_STATUS_LU) 1155 break; 1156 } 1157 if (i == FIBER_LINK_UP_LIMIT) { 1158 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1159 mac->autoneg_failed = TRUE; 1160 /* 1161 * AutoNeg failed to achieve a link, so we'll call 1162 * mac->check_for_link. This routine will force the 1163 * link up if we detect a signal. This will allow us to 1164 * communicate with non-autonegotiating link partners. 1165 */ 1166 ret_val = mac->ops.check_for_link(hw); 1167 if (ret_val) { 1168 DEBUGOUT("Error while checking for link\n"); 1169 return ret_val; 1170 } 1171 mac->autoneg_failed = FALSE; 1172 } else { 1173 mac->autoneg_failed = FALSE; 1174 DEBUGOUT("Valid Link Found\n"); 1175 } 1176 1177 return E1000_SUCCESS; 1178 } 1179 1180 /** 1181 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 1182 * @hw: pointer to the HW structure 1183 * 1184 * Configures collision distance and flow control for fiber and serdes 1185 * links. Upon successful setup, poll for link. 1186 **/ 1187 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 1188 { 1189 u32 ctrl; 1190 s32 ret_val; 1191 1192 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 1193 1194 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1195 1196 /* Take the link out of reset */ 1197 ctrl &= ~E1000_CTRL_LRST; 1198 1199 hw->mac.ops.config_collision_dist(hw); 1200 1201 ret_val = e1000_commit_fc_settings_generic(hw); 1202 if (ret_val) 1203 return ret_val; 1204 1205 /* 1206 * Since auto-negotiation is enabled, take the link out of reset (the 1207 * link will be in reset, because we previously reset the chip). This 1208 * will restart auto-negotiation. If auto-negotiation is successful 1209 * then the link-up status bit will be set and the flow control enable 1210 * bits (RFCE and TFCE) will be set according to their negotiated value. 1211 */ 1212 DEBUGOUT("Auto-negotiation enabled\n"); 1213 1214 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1215 E1000_WRITE_FLUSH(hw); 1216 msec_delay(1); 1217 1218 /* 1219 * For these adapters, the SW definable pin 1 is set when the optics 1220 * detect a signal. If we have a signal, then poll for a "Link-Up" 1221 * indication. 1222 */ 1223 if (hw->phy.media_type == e1000_media_type_internal_serdes || 1224 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1225 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1226 } else { 1227 DEBUGOUT("No signal detected\n"); 1228 } 1229 1230 return ret_val; 1231 } 1232 1233 /** 1234 * e1000_config_collision_dist_generic - Configure collision distance 1235 * @hw: pointer to the HW structure 1236 * 1237 * Configures the collision distance to the default value and is used 1238 * during link setup. 1239 **/ 1240 static void e1000_config_collision_dist_generic(struct e1000_hw *hw) 1241 { 1242 u32 tctl; 1243 1244 DEBUGFUNC("e1000_config_collision_dist_generic"); 1245 1246 tctl = E1000_READ_REG(hw, E1000_TCTL); 1247 1248 tctl &= ~E1000_TCTL_COLD; 1249 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1250 1251 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 1252 E1000_WRITE_FLUSH(hw); 1253 } 1254 1255 /** 1256 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 1257 * @hw: pointer to the HW structure 1258 * 1259 * Sets the flow control high/low threshold (watermark) registers. If 1260 * flow control XON frame transmission is enabled, then set XON frame 1261 * transmission as well. 1262 **/ 1263 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 1264 { 1265 u32 fcrtl = 0, fcrth = 0; 1266 1267 DEBUGFUNC("e1000_set_fc_watermarks_generic"); 1268 1269 /* 1270 * Set the flow control receive threshold registers. Normally, 1271 * these registers will be set to a default threshold that may be 1272 * adjusted later by the driver's runtime code. However, if the 1273 * ability to transmit pause frames is not enabled, then these 1274 * registers will be set to 0. 1275 */ 1276 if (hw->fc.current_mode & e1000_fc_tx_pause) { 1277 /* 1278 * We need to set up the Receive Threshold high and low water 1279 * marks as well as (optionally) enabling the transmission of 1280 * XON frames. 1281 */ 1282 fcrtl = hw->fc.low_water; 1283 if (hw->fc.send_xon) 1284 fcrtl |= E1000_FCRTL_XONE; 1285 1286 fcrth = hw->fc.high_water; 1287 } 1288 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 1289 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 1290 1291 return E1000_SUCCESS; 1292 } 1293 1294 /** 1295 * e1000_force_mac_fc_generic - Force the MAC's flow control settings 1296 * @hw: pointer to the HW structure 1297 * 1298 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 1299 * device control register to reflect the adapter settings. TFCE and RFCE 1300 * need to be explicitly set by software when a copper PHY is used because 1301 * autonegotiation is managed by the PHY rather than the MAC. Software must 1302 * also configure these bits when link is forced on a fiber connection. 1303 **/ 1304 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw) 1305 { 1306 u32 ctrl; 1307 1308 DEBUGFUNC("e1000_force_mac_fc_generic"); 1309 1310 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1311 1312 /* 1313 * Because we didn't get link via the internal auto-negotiation 1314 * mechanism (we either forced link or we got link via PHY 1315 * auto-neg), we have to manually enable/disable transmit an 1316 * receive flow control. 1317 * 1318 * The "Case" statement below enables/disable flow control 1319 * according to the "hw->fc.current_mode" parameter. 1320 * 1321 * The possible values of the "fc" parameter are: 1322 * 0: Flow control is completely disabled 1323 * 1: Rx flow control is enabled (we can receive pause 1324 * frames but not send pause frames). 1325 * 2: Tx flow control is enabled (we can send pause frames 1326 * frames but we do not receive pause frames). 1327 * 3: Both Rx and Tx flow control (symmetric) is enabled. 1328 * other: No other values should be possible at this point. 1329 */ 1330 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); 1331 1332 switch (hw->fc.current_mode) { 1333 case e1000_fc_none: 1334 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1335 break; 1336 case e1000_fc_rx_pause: 1337 ctrl &= (~E1000_CTRL_TFCE); 1338 ctrl |= E1000_CTRL_RFCE; 1339 break; 1340 case e1000_fc_tx_pause: 1341 ctrl &= (~E1000_CTRL_RFCE); 1342 ctrl |= E1000_CTRL_TFCE; 1343 break; 1344 case e1000_fc_full: 1345 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1346 break; 1347 default: 1348 DEBUGOUT("Flow control param set incorrectly\n"); 1349 return -E1000_ERR_CONFIG; 1350 } 1351 1352 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1353 1354 return E1000_SUCCESS; 1355 } 1356 1357 /** 1358 * e1000_config_fc_after_link_up_generic - Configures flow control after link 1359 * @hw: pointer to the HW structure 1360 * 1361 * Checks the status of auto-negotiation after link up to ensure that the 1362 * speed and duplex were not forced. If the link needed to be forced, then 1363 * flow control needs to be forced also. If auto-negotiation is enabled 1364 * and did not fail, then we configure flow control based on our link 1365 * partner. 1366 **/ 1367 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 1368 { 1369 struct e1000_mac_info *mac = &hw->mac; 1370 s32 ret_val = E1000_SUCCESS; 1371 u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg; 1372 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1373 u16 speed, duplex; 1374 1375 DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 1376 1377 /* 1378 * Check for the case where we have fiber media and auto-neg failed 1379 * so we had to force link. In this case, we need to force the 1380 * configuration of the MAC to match the "fc" parameter. 1381 */ 1382 if (mac->autoneg_failed) { 1383 if (hw->phy.media_type == e1000_media_type_fiber || 1384 hw->phy.media_type == e1000_media_type_internal_serdes) 1385 ret_val = e1000_force_mac_fc_generic(hw); 1386 } else { 1387 if (hw->phy.media_type == e1000_media_type_copper) 1388 ret_val = e1000_force_mac_fc_generic(hw); 1389 } 1390 1391 if (ret_val) { 1392 DEBUGOUT("Error forcing flow control settings\n"); 1393 return ret_val; 1394 } 1395 1396 /* 1397 * Check for the case where we have copper media and auto-neg is 1398 * enabled. In this case, we need to check and see if Auto-Neg 1399 * has completed, and if so, how the PHY and link partner has 1400 * flow control configured. 1401 */ 1402 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1403 /* 1404 * Read the MII Status Register and check to see if AutoNeg 1405 * has completed. We read this twice because this reg has 1406 * some "sticky" (latched) bits. 1407 */ 1408 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1409 if (ret_val) 1410 return ret_val; 1411 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1412 if (ret_val) 1413 return ret_val; 1414 1415 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1416 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n"); 1417 return ret_val; 1418 } 1419 1420 /* 1421 * The AutoNeg process has completed, so we now need to 1422 * read both the Auto Negotiation Advertisement 1423 * Register (Address 4) and the Auto_Negotiation Base 1424 * Page Ability Register (Address 5) to determine how 1425 * flow control was negotiated. 1426 */ 1427 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 1428 &mii_nway_adv_reg); 1429 if (ret_val) 1430 return ret_val; 1431 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 1432 &mii_nway_lp_ability_reg); 1433 if (ret_val) 1434 return ret_val; 1435 1436 /* 1437 * Two bits in the Auto Negotiation Advertisement Register 1438 * (Address 4) and two bits in the Auto Negotiation Base 1439 * Page Ability Register (Address 5) determine flow control 1440 * for both the PHY and the link partner. The following 1441 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1442 * 1999, describes these PAUSE resolution bits and how flow 1443 * control is determined based upon these settings. 1444 * NOTE: DC = Don't Care 1445 * 1446 * LOCAL DEVICE | LINK PARTNER 1447 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1448 *-------|---------|-------|---------|-------------------- 1449 * 0 | 0 | DC | DC | e1000_fc_none 1450 * 0 | 1 | 0 | DC | e1000_fc_none 1451 * 0 | 1 | 1 | 0 | e1000_fc_none 1452 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1453 * 1 | 0 | 0 | DC | e1000_fc_none 1454 * 1 | DC | 1 | DC | e1000_fc_full 1455 * 1 | 1 | 0 | 0 | e1000_fc_none 1456 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1457 * 1458 * Are both PAUSE bits set to 1? If so, this implies 1459 * Symmetric Flow Control is enabled at both ends. The 1460 * ASM_DIR bits are irrelevant per the spec. 1461 * 1462 * For Symmetric Flow Control: 1463 * 1464 * LOCAL DEVICE | LINK PARTNER 1465 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1466 *-------|---------|-------|---------|-------------------- 1467 * 1 | DC | 1 | DC | E1000_fc_full 1468 * 1469 */ 1470 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1471 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1472 /* 1473 * Now we need to check if the user selected Rx ONLY 1474 * of pause frames. In this case, we had to advertise 1475 * FULL flow control because we could not advertise Rx 1476 * ONLY. Hence, we must now check to see if we need to 1477 * turn OFF the TRANSMISSION of PAUSE frames. 1478 */ 1479 if (hw->fc.requested_mode == e1000_fc_full) { 1480 hw->fc.current_mode = e1000_fc_full; 1481 DEBUGOUT("Flow Control = FULL.\n"); 1482 } else { 1483 hw->fc.current_mode = e1000_fc_rx_pause; 1484 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1485 } 1486 } 1487 /* 1488 * For receiving PAUSE frames ONLY. 1489 * 1490 * LOCAL DEVICE | LINK PARTNER 1491 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1492 *-------|---------|-------|---------|-------------------- 1493 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1494 */ 1495 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1496 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1497 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1498 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1499 hw->fc.current_mode = e1000_fc_tx_pause; 1500 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); 1501 } 1502 /* 1503 * For transmitting PAUSE frames ONLY. 1504 * 1505 * LOCAL DEVICE | LINK PARTNER 1506 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1507 *-------|---------|-------|---------|-------------------- 1508 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1509 */ 1510 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1511 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1512 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1513 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1514 hw->fc.current_mode = e1000_fc_rx_pause; 1515 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1516 } else { 1517 /* 1518 * Per the IEEE spec, at this point flow control 1519 * should be disabled. 1520 */ 1521 hw->fc.current_mode = e1000_fc_none; 1522 DEBUGOUT("Flow Control = NONE.\n"); 1523 } 1524 1525 /* 1526 * Now we need to do one last check... If we auto- 1527 * negotiated to HALF DUPLEX, flow control should not be 1528 * enabled per IEEE 802.3 spec. 1529 */ 1530 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1531 if (ret_val) { 1532 DEBUGOUT("Error getting link speed and duplex\n"); 1533 return ret_val; 1534 } 1535 1536 if (duplex == HALF_DUPLEX) 1537 hw->fc.current_mode = e1000_fc_none; 1538 1539 /* 1540 * Now we call a subroutine to actually force the MAC 1541 * controller to use the correct flow control settings. 1542 */ 1543 ret_val = e1000_force_mac_fc_generic(hw); 1544 if (ret_val) { 1545 DEBUGOUT("Error forcing flow control settings\n"); 1546 return ret_val; 1547 } 1548 } 1549 1550 /* 1551 * Check for the case where we have SerDes media and auto-neg is 1552 * enabled. In this case, we need to check and see if Auto-Neg 1553 * has completed, and if so, how the PHY and link partner has 1554 * flow control configured. 1555 */ 1556 if ((hw->phy.media_type == e1000_media_type_internal_serdes) 1557 && mac->autoneg) { 1558 /* 1559 * Read the PCS_LSTS and check to see if AutoNeg 1560 * has completed. 1561 */ 1562 pcs_status_reg = E1000_READ_REG(hw, E1000_PCS_LSTAT); 1563 1564 if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) { 1565 DEBUGOUT("PCS Auto Neg has not completed.\n"); 1566 return ret_val; 1567 } 1568 1569 /* 1570 * The AutoNeg process has completed, so we now need to 1571 * read both the Auto Negotiation Advertisement 1572 * Register (PCS_ANADV) and the Auto_Negotiation Base 1573 * Page Ability Register (PCS_LPAB) to determine how 1574 * flow control was negotiated. 1575 */ 1576 pcs_adv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV); 1577 pcs_lp_ability_reg = E1000_READ_REG(hw, E1000_PCS_LPAB); 1578 1579 /* 1580 * Two bits in the Auto Negotiation Advertisement Register 1581 * (PCS_ANADV) and two bits in the Auto Negotiation Base 1582 * Page Ability Register (PCS_LPAB) determine flow control 1583 * for both the PHY and the link partner. The following 1584 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1585 * 1999, describes these PAUSE resolution bits and how flow 1586 * control is determined based upon these settings. 1587 * NOTE: DC = Don't Care 1588 * 1589 * LOCAL DEVICE | LINK PARTNER 1590 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1591 *-------|---------|-------|---------|-------------------- 1592 * 0 | 0 | DC | DC | e1000_fc_none 1593 * 0 | 1 | 0 | DC | e1000_fc_none 1594 * 0 | 1 | 1 | 0 | e1000_fc_none 1595 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1596 * 1 | 0 | 0 | DC | e1000_fc_none 1597 * 1 | DC | 1 | DC | e1000_fc_full 1598 * 1 | 1 | 0 | 0 | e1000_fc_none 1599 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1600 * 1601 * Are both PAUSE bits set to 1? If so, this implies 1602 * Symmetric Flow Control is enabled at both ends. The 1603 * ASM_DIR bits are irrelevant per the spec. 1604 * 1605 * For Symmetric Flow Control: 1606 * 1607 * LOCAL DEVICE | LINK PARTNER 1608 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1609 *-------|---------|-------|---------|-------------------- 1610 * 1 | DC | 1 | DC | e1000_fc_full 1611 * 1612 */ 1613 if ((pcs_adv_reg & E1000_TXCW_PAUSE) && 1614 (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) { 1615 /* 1616 * Now we need to check if the user selected Rx ONLY 1617 * of pause frames. In this case, we had to advertise 1618 * FULL flow control because we could not advertise Rx 1619 * ONLY. Hence, we must now check to see if we need to 1620 * turn OFF the TRANSMISSION of PAUSE frames. 1621 */ 1622 if (hw->fc.requested_mode == e1000_fc_full) { 1623 hw->fc.current_mode = e1000_fc_full; 1624 DEBUGOUT("Flow Control = FULL.\n"); 1625 } else { 1626 hw->fc.current_mode = e1000_fc_rx_pause; 1627 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1628 } 1629 } 1630 /* 1631 * For receiving PAUSE frames ONLY. 1632 * 1633 * LOCAL DEVICE | LINK PARTNER 1634 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1635 *-------|---------|-------|---------|-------------------- 1636 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1637 */ 1638 else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) && 1639 (pcs_adv_reg & E1000_TXCW_ASM_DIR) && 1640 (pcs_lp_ability_reg & E1000_TXCW_PAUSE) && 1641 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { 1642 hw->fc.current_mode = e1000_fc_tx_pause; 1643 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); 1644 } 1645 /* 1646 * For transmitting PAUSE frames ONLY. 1647 * 1648 * LOCAL DEVICE | LINK PARTNER 1649 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1650 *-------|---------|-------|---------|-------------------- 1651 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1652 */ 1653 else if ((pcs_adv_reg & E1000_TXCW_PAUSE) && 1654 (pcs_adv_reg & E1000_TXCW_ASM_DIR) && 1655 !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) && 1656 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { 1657 hw->fc.current_mode = e1000_fc_rx_pause; 1658 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1659 } else { 1660 /* 1661 * Per the IEEE spec, at this point flow control 1662 * should be disabled. 1663 */ 1664 hw->fc.current_mode = e1000_fc_none; 1665 DEBUGOUT("Flow Control = NONE.\n"); 1666 } 1667 1668 /* 1669 * Now we call a subroutine to actually force the MAC 1670 * controller to use the correct flow control settings. 1671 */ 1672 pcs_ctrl_reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 1673 pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1674 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_ctrl_reg); 1675 1676 ret_val = e1000_force_mac_fc_generic(hw); 1677 if (ret_val) { 1678 DEBUGOUT("Error forcing flow control settings\n"); 1679 return ret_val; 1680 } 1681 } 1682 1683 return E1000_SUCCESS; 1684 } 1685 1686 /** 1687 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 1688 * @hw: pointer to the HW structure 1689 * @speed: stores the current speed 1690 * @duplex: stores the current duplex 1691 * 1692 * Read the status register for the current speed/duplex and store the current 1693 * speed and duplex for copper connections. 1694 **/ 1695 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 1696 u16 *duplex) 1697 { 1698 u32 status; 1699 1700 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 1701 1702 status = E1000_READ_REG(hw, E1000_STATUS); 1703 if (status & E1000_STATUS_SPEED_1000) { 1704 *speed = SPEED_1000; 1705 DEBUGOUT("1000 Mbs, "); 1706 } else if (status & E1000_STATUS_SPEED_100) { 1707 *speed = SPEED_100; 1708 DEBUGOUT("100 Mbs, "); 1709 } else { 1710 *speed = SPEED_10; 1711 DEBUGOUT("10 Mbs, "); 1712 } 1713 1714 if (status & E1000_STATUS_FD) { 1715 *duplex = FULL_DUPLEX; 1716 DEBUGOUT("Full Duplex\n"); 1717 } else { 1718 *duplex = HALF_DUPLEX; 1719 DEBUGOUT("Half Duplex\n"); 1720 } 1721 1722 return E1000_SUCCESS; 1723 } 1724 1725 /** 1726 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex 1727 * @hw: pointer to the HW structure 1728 * @speed: stores the current speed 1729 * @duplex: stores the current duplex 1730 * 1731 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1732 * for fiber/serdes links. 1733 **/ 1734 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw, 1735 u16 *speed, u16 *duplex) 1736 { 1737 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 1738 1739 *speed = SPEED_1000; 1740 *duplex = FULL_DUPLEX; 1741 1742 return E1000_SUCCESS; 1743 } 1744 1745 /** 1746 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 1747 * @hw: pointer to the HW structure 1748 * 1749 * Acquire the HW semaphore to access the PHY or NVM 1750 **/ 1751 s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 1752 { 1753 u32 swsm; 1754 s32 timeout = hw->nvm.word_size + 1; 1755 s32 i = 0; 1756 1757 DEBUGFUNC("e1000_get_hw_semaphore_generic"); 1758 1759 /* Get the SW semaphore */ 1760 while (i < timeout) { 1761 swsm = E1000_READ_REG(hw, E1000_SWSM); 1762 if (!(swsm & E1000_SWSM_SMBI)) 1763 break; 1764 1765 usec_delay(50); 1766 i++; 1767 } 1768 1769 if (i == timeout) { 1770 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1771 return -E1000_ERR_NVM; 1772 } 1773 1774 /* Get the FW semaphore. */ 1775 for (i = 0; i < timeout; i++) { 1776 swsm = E1000_READ_REG(hw, E1000_SWSM); 1777 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 1778 1779 /* Semaphore acquired if bit latched */ 1780 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 1781 break; 1782 1783 usec_delay(50); 1784 } 1785 1786 if (i == timeout) { 1787 /* Release semaphores */ 1788 e1000_put_hw_semaphore_generic(hw); 1789 DEBUGOUT("Driver can't access the NVM\n"); 1790 return -E1000_ERR_NVM; 1791 } 1792 1793 return E1000_SUCCESS; 1794 } 1795 1796 /** 1797 * e1000_put_hw_semaphore_generic - Release hardware semaphore 1798 * @hw: pointer to the HW structure 1799 * 1800 * Release hardware semaphore used to access the PHY or NVM 1801 **/ 1802 void e1000_put_hw_semaphore_generic(struct e1000_hw *hw) 1803 { 1804 u32 swsm; 1805 1806 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 1807 1808 swsm = E1000_READ_REG(hw, E1000_SWSM); 1809 1810 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1811 1812 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 1813 } 1814 1815 /** 1816 * e1000_get_auto_rd_done_generic - Check for auto read completion 1817 * @hw: pointer to the HW structure 1818 * 1819 * Check EEPROM for Auto Read done bit. 1820 **/ 1821 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 1822 { 1823 s32 i = 0; 1824 1825 DEBUGFUNC("e1000_get_auto_rd_done_generic"); 1826 1827 while (i < AUTO_READ_DONE_TIMEOUT) { 1828 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 1829 break; 1830 msec_delay(1); 1831 i++; 1832 } 1833 1834 if (i == AUTO_READ_DONE_TIMEOUT) { 1835 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1836 return -E1000_ERR_RESET; 1837 } 1838 1839 return E1000_SUCCESS; 1840 } 1841 1842 /** 1843 * e1000_valid_led_default_generic - Verify a valid default LED config 1844 * @hw: pointer to the HW structure 1845 * @data: pointer to the NVM (EEPROM) 1846 * 1847 * Read the EEPROM for the current default LED configuration. If the 1848 * LED configuration is not valid, set to a valid LED configuration. 1849 **/ 1850 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 1851 { 1852 s32 ret_val; 1853 1854 DEBUGFUNC("e1000_valid_led_default_generic"); 1855 1856 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1857 if (ret_val) { 1858 DEBUGOUT("NVM Read Error\n"); 1859 return ret_val; 1860 } 1861 1862 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1863 *data = ID_LED_DEFAULT; 1864 1865 return E1000_SUCCESS; 1866 } 1867 1868 /** 1869 * e1000_id_led_init_generic - 1870 * @hw: pointer to the HW structure 1871 * 1872 **/ 1873 s32 e1000_id_led_init_generic(struct e1000_hw *hw) 1874 { 1875 struct e1000_mac_info *mac = &hw->mac; 1876 s32 ret_val; 1877 const u32 ledctl_mask = 0x000000FF; 1878 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1879 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1880 u16 data, i, temp; 1881 const u16 led_mask = 0x0F; 1882 1883 DEBUGFUNC("e1000_id_led_init_generic"); 1884 1885 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 1886 if (ret_val) 1887 return ret_val; 1888 1889 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 1890 mac->ledctl_mode1 = mac->ledctl_default; 1891 mac->ledctl_mode2 = mac->ledctl_default; 1892 1893 for (i = 0; i < 4; i++) { 1894 temp = (data >> (i << 2)) & led_mask; 1895 switch (temp) { 1896 case ID_LED_ON1_DEF2: 1897 case ID_LED_ON1_ON2: 1898 case ID_LED_ON1_OFF2: 1899 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1900 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1901 break; 1902 case ID_LED_OFF1_DEF2: 1903 case ID_LED_OFF1_ON2: 1904 case ID_LED_OFF1_OFF2: 1905 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1906 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1907 break; 1908 default: 1909 /* Do nothing */ 1910 break; 1911 } 1912 switch (temp) { 1913 case ID_LED_DEF1_ON2: 1914 case ID_LED_ON1_ON2: 1915 case ID_LED_OFF1_ON2: 1916 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1917 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1918 break; 1919 case ID_LED_DEF1_OFF2: 1920 case ID_LED_ON1_OFF2: 1921 case ID_LED_OFF1_OFF2: 1922 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1923 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1924 break; 1925 default: 1926 /* Do nothing */ 1927 break; 1928 } 1929 } 1930 1931 return E1000_SUCCESS; 1932 } 1933 1934 /** 1935 * e1000_setup_led_generic - Configures SW controllable LED 1936 * @hw: pointer to the HW structure 1937 * 1938 * This prepares the SW controllable LED for use and saves the current state 1939 * of the LED so it can be later restored. 1940 **/ 1941 s32 e1000_setup_led_generic(struct e1000_hw *hw) 1942 { 1943 u32 ledctl; 1944 1945 DEBUGFUNC("e1000_setup_led_generic"); 1946 1947 if (hw->mac.ops.setup_led != e1000_setup_led_generic) 1948 return -E1000_ERR_CONFIG; 1949 1950 if (hw->phy.media_type == e1000_media_type_fiber) { 1951 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 1952 hw->mac.ledctl_default = ledctl; 1953 /* Turn off LED0 */ 1954 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK | 1955 E1000_LEDCTL_LED0_MODE_MASK); 1956 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1957 E1000_LEDCTL_LED0_MODE_SHIFT); 1958 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 1959 } else if (hw->phy.media_type == e1000_media_type_copper) { 1960 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1961 } 1962 1963 return E1000_SUCCESS; 1964 } 1965 1966 /** 1967 * e1000_cleanup_led_generic - Set LED config to default operation 1968 * @hw: pointer to the HW structure 1969 * 1970 * Remove the current LED configuration and set the LED configuration 1971 * to the default value, saved from the EEPROM. 1972 **/ 1973 s32 e1000_cleanup_led_generic(struct e1000_hw *hw) 1974 { 1975 DEBUGFUNC("e1000_cleanup_led_generic"); 1976 1977 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1978 return E1000_SUCCESS; 1979 } 1980 1981 /** 1982 * e1000_blink_led_generic - Blink LED 1983 * @hw: pointer to the HW structure 1984 * 1985 * Blink the LEDs which are set to be on. 1986 **/ 1987 s32 e1000_blink_led_generic(struct e1000_hw *hw) 1988 { 1989 u32 ledctl_blink = 0; 1990 u32 i; 1991 1992 DEBUGFUNC("e1000_blink_led_generic"); 1993 1994 if (hw->phy.media_type == e1000_media_type_fiber) { 1995 /* always blink LED0 for PCI-E fiber */ 1996 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1997 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1998 } else { 1999 /* 2000 * set the blink bit for each LED that's "on" (0x0E) 2001 * in ledctl_mode2 2002 */ 2003 ledctl_blink = hw->mac.ledctl_mode2; 2004 for (i = 0; i < 4; i++) 2005 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 2006 E1000_LEDCTL_MODE_LED_ON) 2007 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << 2008 (i * 8)); 2009 } 2010 2011 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 2012 2013 return E1000_SUCCESS; 2014 } 2015 2016 /** 2017 * e1000_led_on_generic - Turn LED on 2018 * @hw: pointer to the HW structure 2019 * 2020 * Turn LED on. 2021 **/ 2022 s32 e1000_led_on_generic(struct e1000_hw *hw) 2023 { 2024 u32 ctrl; 2025 2026 DEBUGFUNC("e1000_led_on_generic"); 2027 2028 switch (hw->phy.media_type) { 2029 case e1000_media_type_fiber: 2030 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2031 ctrl &= ~E1000_CTRL_SWDPIN0; 2032 ctrl |= E1000_CTRL_SWDPIO0; 2033 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2034 break; 2035 case e1000_media_type_copper: 2036 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 2037 break; 2038 default: 2039 break; 2040 } 2041 2042 return E1000_SUCCESS; 2043 } 2044 2045 /** 2046 * e1000_led_off_generic - Turn LED off 2047 * @hw: pointer to the HW structure 2048 * 2049 * Turn LED off. 2050 **/ 2051 s32 e1000_led_off_generic(struct e1000_hw *hw) 2052 { 2053 u32 ctrl; 2054 2055 DEBUGFUNC("e1000_led_off_generic"); 2056 2057 switch (hw->phy.media_type) { 2058 case e1000_media_type_fiber: 2059 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2060 ctrl |= E1000_CTRL_SWDPIN0; 2061 ctrl |= E1000_CTRL_SWDPIO0; 2062 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2063 break; 2064 case e1000_media_type_copper: 2065 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 2066 break; 2067 default: 2068 break; 2069 } 2070 2071 return E1000_SUCCESS; 2072 } 2073 2074 /** 2075 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 2076 * @hw: pointer to the HW structure 2077 * @no_snoop: bitmap of snoop events 2078 * 2079 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 2080 **/ 2081 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 2082 { 2083 u32 gcr; 2084 2085 DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 2086 2087 if (hw->bus.type != e1000_bus_type_pci_express) 2088 return; 2089 2090 if (no_snoop) { 2091 gcr = E1000_READ_REG(hw, E1000_GCR); 2092 gcr &= ~(PCIE_NO_SNOOP_ALL); 2093 gcr |= no_snoop; 2094 E1000_WRITE_REG(hw, E1000_GCR, gcr); 2095 } 2096 } 2097 2098 /** 2099 * e1000_disable_pcie_master_generic - Disables PCI-express master access 2100 * @hw: pointer to the HW structure 2101 * 2102 * Returns E1000_SUCCESS if successful, else returns -10 2103 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 2104 * the master requests to be disabled. 2105 * 2106 * Disables PCI-Express master access and verifies there are no pending 2107 * requests. 2108 **/ 2109 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw) 2110 { 2111 u32 ctrl; 2112 s32 timeout = MASTER_DISABLE_TIMEOUT; 2113 2114 DEBUGFUNC("e1000_disable_pcie_master_generic"); 2115 2116 if (hw->bus.type != e1000_bus_type_pci_express) 2117 return E1000_SUCCESS; 2118 2119 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2120 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 2121 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2122 2123 while (timeout) { 2124 if (!(E1000_READ_REG(hw, E1000_STATUS) & 2125 E1000_STATUS_GIO_MASTER_ENABLE)) 2126 break; 2127 usec_delay(100); 2128 timeout--; 2129 } 2130 2131 if (!timeout) { 2132 DEBUGOUT("Master requests are pending.\n"); 2133 return -E1000_ERR_MASTER_REQUESTS_PENDING; 2134 } 2135 2136 return E1000_SUCCESS; 2137 } 2138 2139 /** 2140 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 2141 * @hw: pointer to the HW structure 2142 * 2143 * Reset the Adaptive Interframe Spacing throttle to default values. 2144 **/ 2145 void e1000_reset_adaptive_generic(struct e1000_hw *hw) 2146 { 2147 struct e1000_mac_info *mac = &hw->mac; 2148 2149 DEBUGFUNC("e1000_reset_adaptive_generic"); 2150 2151 if (!mac->adaptive_ifs) { 2152 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2153 return; 2154 } 2155 2156 mac->current_ifs_val = 0; 2157 mac->ifs_min_val = IFS_MIN; 2158 mac->ifs_max_val = IFS_MAX; 2159 mac->ifs_step_size = IFS_STEP; 2160 mac->ifs_ratio = IFS_RATIO; 2161 2162 mac->in_ifs_mode = FALSE; 2163 E1000_WRITE_REG(hw, E1000_AIT, 0); 2164 } 2165 2166 /** 2167 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 2168 * @hw: pointer to the HW structure 2169 * 2170 * Update the Adaptive Interframe Spacing Throttle value based on the 2171 * time between transmitted packets and time between collisions. 2172 **/ 2173 void e1000_update_adaptive_generic(struct e1000_hw *hw) 2174 { 2175 struct e1000_mac_info *mac = &hw->mac; 2176 2177 DEBUGFUNC("e1000_update_adaptive_generic"); 2178 2179 if (!mac->adaptive_ifs) { 2180 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2181 return; 2182 } 2183 2184 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 2185 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 2186 mac->in_ifs_mode = TRUE; 2187 if (mac->current_ifs_val < mac->ifs_max_val) { 2188 if (!mac->current_ifs_val) 2189 mac->current_ifs_val = mac->ifs_min_val; 2190 else 2191 mac->current_ifs_val += 2192 mac->ifs_step_size; 2193 E1000_WRITE_REG(hw, E1000_AIT, 2194 mac->current_ifs_val); 2195 } 2196 } 2197 } else { 2198 if (mac->in_ifs_mode && 2199 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 2200 mac->current_ifs_val = 0; 2201 mac->in_ifs_mode = FALSE; 2202 E1000_WRITE_REG(hw, E1000_AIT, 0); 2203 } 2204 } 2205 } 2206 2207 /** 2208 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 2209 * @hw: pointer to the HW structure 2210 * 2211 * Verify that when not using auto-negotiation that MDI/MDIx is correctly 2212 * set, which is forced to MDI mode only. 2213 **/ 2214 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 2215 { 2216 DEBUGFUNC("e1000_validate_mdi_setting_generic"); 2217 2218 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 2219 DEBUGOUT("Invalid MDI setting detected\n"); 2220 hw->phy.mdix = 1; 2221 return -E1000_ERR_CONFIG; 2222 } 2223 2224 return E1000_SUCCESS; 2225 } 2226 2227 /** 2228 * e1000_validate_mdi_setting_crossover_generic - Verify MDI/MDIx settings 2229 * @hw: pointer to the HW structure 2230 * 2231 * Validate the MDI/MDIx setting, allowing for auto-crossover during forced 2232 * operation. 2233 **/ 2234 s32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw *hw) 2235 { 2236 DEBUGFUNC("e1000_validate_mdi_setting_crossover_generic"); 2237 2238 return E1000_SUCCESS; 2239 } 2240 2241 /** 2242 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register 2243 * @hw: pointer to the HW structure 2244 * @reg: 32bit register offset such as E1000_SCTL 2245 * @offset: register offset to write to 2246 * @data: data to write at register offset 2247 * 2248 * Writes an address/data control type register. There are several of these 2249 * and they all have the format address << 8 | data and bit 31 is polled for 2250 * completion. 2251 **/ 2252 s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, 2253 u32 offset, u8 data) 2254 { 2255 u32 i, regvalue = 0; 2256 2257 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); 2258 2259 /* Set up the address and data */ 2260 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 2261 E1000_WRITE_REG(hw, reg, regvalue); 2262 2263 /* Poll the ready bit to see if the MDI read completed */ 2264 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 2265 usec_delay(5); 2266 regvalue = E1000_READ_REG(hw, reg); 2267 if (regvalue & E1000_GEN_CTL_READY) 2268 break; 2269 } 2270 if (!(regvalue & E1000_GEN_CTL_READY)) { 2271 DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 2272 return -E1000_ERR_PHY; 2273 } 2274 2275 return E1000_SUCCESS; 2276 } 2277