1 /****************************************************************************** 2 3 Copyright (c) 2001-2014, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD:$*/ 34 35 #include "e1000_api.h" 36 37 static void e1000_reload_nvm_generic(struct e1000_hw *hw); 38 39 /** 40 * e1000_init_nvm_ops_generic - Initialize NVM function pointers 41 * @hw: pointer to the HW structure 42 * 43 * Setups up the function pointers to no-op functions 44 **/ 45 void e1000_init_nvm_ops_generic(struct e1000_hw *hw) 46 { 47 struct e1000_nvm_info *nvm = &hw->nvm; 48 DEBUGFUNC("e1000_init_nvm_ops_generic"); 49 50 /* Initialize function pointers */ 51 nvm->ops.init_params = e1000_null_ops_generic; 52 nvm->ops.acquire = e1000_null_ops_generic; 53 nvm->ops.read = e1000_null_read_nvm; 54 nvm->ops.release = e1000_null_nvm_generic; 55 nvm->ops.reload = e1000_reload_nvm_generic; 56 nvm->ops.update = e1000_null_ops_generic; 57 nvm->ops.valid_led_default = e1000_null_led_default; 58 nvm->ops.validate = e1000_null_ops_generic; 59 nvm->ops.write = e1000_null_write_nvm; 60 } 61 62 /** 63 * e1000_null_nvm_read - No-op function, return 0 64 * @hw: pointer to the HW structure 65 **/ 66 s32 e1000_null_read_nvm(struct e1000_hw E1000_UNUSEDARG *hw, 67 u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b, 68 u16 E1000_UNUSEDARG *c) 69 { 70 DEBUGFUNC("e1000_null_read_nvm"); 71 return E1000_SUCCESS; 72 } 73 74 /** 75 * e1000_null_nvm_generic - No-op function, return void 76 * @hw: pointer to the HW structure 77 **/ 78 void e1000_null_nvm_generic(struct e1000_hw E1000_UNUSEDARG *hw) 79 { 80 DEBUGFUNC("e1000_null_nvm_generic"); 81 return; 82 } 83 84 /** 85 * e1000_null_led_default - No-op function, return 0 86 * @hw: pointer to the HW structure 87 **/ 88 s32 e1000_null_led_default(struct e1000_hw E1000_UNUSEDARG *hw, 89 u16 E1000_UNUSEDARG *data) 90 { 91 DEBUGFUNC("e1000_null_led_default"); 92 return E1000_SUCCESS; 93 } 94 95 /** 96 * e1000_null_write_nvm - No-op function, return 0 97 * @hw: pointer to the HW structure 98 **/ 99 s32 e1000_null_write_nvm(struct e1000_hw E1000_UNUSEDARG *hw, 100 u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b, 101 u16 E1000_UNUSEDARG *c) 102 { 103 DEBUGFUNC("e1000_null_write_nvm"); 104 return E1000_SUCCESS; 105 } 106 107 /** 108 * e1000_raise_eec_clk - Raise EEPROM clock 109 * @hw: pointer to the HW structure 110 * @eecd: pointer to the EEPROM 111 * 112 * Enable/Raise the EEPROM clock bit. 113 **/ 114 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd) 115 { 116 *eecd = *eecd | E1000_EECD_SK; 117 E1000_WRITE_REG(hw, E1000_EECD, *eecd); 118 E1000_WRITE_FLUSH(hw); 119 usec_delay(hw->nvm.delay_usec); 120 } 121 122 /** 123 * e1000_lower_eec_clk - Lower EEPROM clock 124 * @hw: pointer to the HW structure 125 * @eecd: pointer to the EEPROM 126 * 127 * Clear/Lower the EEPROM clock bit. 128 **/ 129 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd) 130 { 131 *eecd = *eecd & ~E1000_EECD_SK; 132 E1000_WRITE_REG(hw, E1000_EECD, *eecd); 133 E1000_WRITE_FLUSH(hw); 134 usec_delay(hw->nvm.delay_usec); 135 } 136 137 /** 138 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM 139 * @hw: pointer to the HW structure 140 * @data: data to send to the EEPROM 141 * @count: number of bits to shift out 142 * 143 * We need to shift 'count' bits out to the EEPROM. So, the value in the 144 * "data" parameter will be shifted out to the EEPROM one bit at a time. 145 * In order to do this, "data" must be broken down into bits. 146 **/ 147 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count) 148 { 149 struct e1000_nvm_info *nvm = &hw->nvm; 150 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 151 u32 mask; 152 153 DEBUGFUNC("e1000_shift_out_eec_bits"); 154 155 mask = 0x01 << (count - 1); 156 if (nvm->type == e1000_nvm_eeprom_microwire) 157 eecd &= ~E1000_EECD_DO; 158 else 159 if (nvm->type == e1000_nvm_eeprom_spi) 160 eecd |= E1000_EECD_DO; 161 162 do { 163 eecd &= ~E1000_EECD_DI; 164 165 if (data & mask) 166 eecd |= E1000_EECD_DI; 167 168 E1000_WRITE_REG(hw, E1000_EECD, eecd); 169 E1000_WRITE_FLUSH(hw); 170 171 usec_delay(nvm->delay_usec); 172 173 e1000_raise_eec_clk(hw, &eecd); 174 e1000_lower_eec_clk(hw, &eecd); 175 176 mask >>= 1; 177 } while (mask); 178 179 eecd &= ~E1000_EECD_DI; 180 E1000_WRITE_REG(hw, E1000_EECD, eecd); 181 } 182 183 /** 184 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM 185 * @hw: pointer to the HW structure 186 * @count: number of bits to shift in 187 * 188 * In order to read a register from the EEPROM, we need to shift 'count' bits 189 * in from the EEPROM. Bits are "shifted in" by raising the clock input to 190 * the EEPROM (setting the SK bit), and then reading the value of the data out 191 * "DO" bit. During this "shifting in" process the data in "DI" bit should 192 * always be clear. 193 **/ 194 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count) 195 { 196 u32 eecd; 197 u32 i; 198 u16 data; 199 200 DEBUGFUNC("e1000_shift_in_eec_bits"); 201 202 eecd = E1000_READ_REG(hw, E1000_EECD); 203 204 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 205 data = 0; 206 207 for (i = 0; i < count; i++) { 208 data <<= 1; 209 e1000_raise_eec_clk(hw, &eecd); 210 211 eecd = E1000_READ_REG(hw, E1000_EECD); 212 213 eecd &= ~E1000_EECD_DI; 214 if (eecd & E1000_EECD_DO) 215 data |= 1; 216 217 e1000_lower_eec_clk(hw, &eecd); 218 } 219 220 return data; 221 } 222 223 /** 224 * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion 225 * @hw: pointer to the HW structure 226 * @ee_reg: EEPROM flag for polling 227 * 228 * Polls the EEPROM status bit for either read or write completion based 229 * upon the value of 'ee_reg'. 230 **/ 231 s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) 232 { 233 u32 attempts = 100000; 234 u32 i, reg = 0; 235 236 DEBUGFUNC("e1000_poll_eerd_eewr_done"); 237 238 for (i = 0; i < attempts; i++) { 239 if (ee_reg == E1000_NVM_POLL_READ) 240 reg = E1000_READ_REG(hw, E1000_EERD); 241 else 242 reg = E1000_READ_REG(hw, E1000_EEWR); 243 244 if (reg & E1000_NVM_RW_REG_DONE) 245 return E1000_SUCCESS; 246 247 usec_delay(5); 248 } 249 250 return -E1000_ERR_NVM; 251 } 252 253 /** 254 * e1000_acquire_nvm_generic - Generic request for access to EEPROM 255 * @hw: pointer to the HW structure 256 * 257 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 258 * Return successful if access grant bit set, else clear the request for 259 * EEPROM access and return -E1000_ERR_NVM (-1). 260 **/ 261 s32 e1000_acquire_nvm_generic(struct e1000_hw *hw) 262 { 263 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 264 s32 timeout = E1000_NVM_GRANT_ATTEMPTS; 265 266 DEBUGFUNC("e1000_acquire_nvm_generic"); 267 268 E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ); 269 eecd = E1000_READ_REG(hw, E1000_EECD); 270 271 while (timeout) { 272 if (eecd & E1000_EECD_GNT) 273 break; 274 usec_delay(5); 275 eecd = E1000_READ_REG(hw, E1000_EECD); 276 timeout--; 277 } 278 279 if (!timeout) { 280 eecd &= ~E1000_EECD_REQ; 281 E1000_WRITE_REG(hw, E1000_EECD, eecd); 282 DEBUGOUT("Could not acquire NVM grant\n"); 283 return -E1000_ERR_NVM; 284 } 285 286 return E1000_SUCCESS; 287 } 288 289 /** 290 * e1000_standby_nvm - Return EEPROM to standby state 291 * @hw: pointer to the HW structure 292 * 293 * Return the EEPROM to a standby state. 294 **/ 295 static void e1000_standby_nvm(struct e1000_hw *hw) 296 { 297 struct e1000_nvm_info *nvm = &hw->nvm; 298 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 299 300 DEBUGFUNC("e1000_standby_nvm"); 301 302 if (nvm->type == e1000_nvm_eeprom_microwire) { 303 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 304 E1000_WRITE_REG(hw, E1000_EECD, eecd); 305 E1000_WRITE_FLUSH(hw); 306 usec_delay(nvm->delay_usec); 307 308 e1000_raise_eec_clk(hw, &eecd); 309 310 /* Select EEPROM */ 311 eecd |= E1000_EECD_CS; 312 E1000_WRITE_REG(hw, E1000_EECD, eecd); 313 E1000_WRITE_FLUSH(hw); 314 usec_delay(nvm->delay_usec); 315 316 e1000_lower_eec_clk(hw, &eecd); 317 } else if (nvm->type == e1000_nvm_eeprom_spi) { 318 /* Toggle CS to flush commands */ 319 eecd |= E1000_EECD_CS; 320 E1000_WRITE_REG(hw, E1000_EECD, eecd); 321 E1000_WRITE_FLUSH(hw); 322 usec_delay(nvm->delay_usec); 323 eecd &= ~E1000_EECD_CS; 324 E1000_WRITE_REG(hw, E1000_EECD, eecd); 325 E1000_WRITE_FLUSH(hw); 326 usec_delay(nvm->delay_usec); 327 } 328 } 329 330 /** 331 * e1000_stop_nvm - Terminate EEPROM command 332 * @hw: pointer to the HW structure 333 * 334 * Terminates the current command by inverting the EEPROM's chip select pin. 335 **/ 336 #ifdef NO_82542_SUPPORT 337 static void e1000_stop_nvm(struct e1000_hw *hw) 338 #else 339 void e1000_stop_nvm(struct e1000_hw *hw) 340 #endif 341 { 342 u32 eecd; 343 344 DEBUGFUNC("e1000_stop_nvm"); 345 346 eecd = E1000_READ_REG(hw, E1000_EECD); 347 if (hw->nvm.type == e1000_nvm_eeprom_spi) { 348 /* Pull CS high */ 349 eecd |= E1000_EECD_CS; 350 e1000_lower_eec_clk(hw, &eecd); 351 } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) { 352 /* CS on Microwire is active-high */ 353 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 354 E1000_WRITE_REG(hw, E1000_EECD, eecd); 355 e1000_raise_eec_clk(hw, &eecd); 356 e1000_lower_eec_clk(hw, &eecd); 357 } 358 } 359 360 /** 361 * e1000_release_nvm_generic - Release exclusive access to EEPROM 362 * @hw: pointer to the HW structure 363 * 364 * Stop any current commands to the EEPROM and clear the EEPROM request bit. 365 **/ 366 void e1000_release_nvm_generic(struct e1000_hw *hw) 367 { 368 u32 eecd; 369 370 DEBUGFUNC("e1000_release_nvm_generic"); 371 372 e1000_stop_nvm(hw); 373 374 eecd = E1000_READ_REG(hw, E1000_EECD); 375 eecd &= ~E1000_EECD_REQ; 376 E1000_WRITE_REG(hw, E1000_EECD, eecd); 377 } 378 379 /** 380 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write 381 * @hw: pointer to the HW structure 382 * 383 * Setups the EEPROM for reading and writing. 384 **/ 385 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw) 386 { 387 struct e1000_nvm_info *nvm = &hw->nvm; 388 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 389 u8 spi_stat_reg; 390 391 DEBUGFUNC("e1000_ready_nvm_eeprom"); 392 393 if (nvm->type == e1000_nvm_eeprom_microwire) { 394 /* Clear SK and DI */ 395 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 396 E1000_WRITE_REG(hw, E1000_EECD, eecd); 397 /* Set CS */ 398 eecd |= E1000_EECD_CS; 399 E1000_WRITE_REG(hw, E1000_EECD, eecd); 400 } else if (nvm->type == e1000_nvm_eeprom_spi) { 401 u16 timeout = NVM_MAX_RETRY_SPI; 402 403 /* Clear SK and CS */ 404 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 405 E1000_WRITE_REG(hw, E1000_EECD, eecd); 406 E1000_WRITE_FLUSH(hw); 407 usec_delay(1); 408 409 /* Read "Status Register" repeatedly until the LSB is cleared. 410 * The EEPROM will signal that the command has been completed 411 * by clearing bit 0 of the internal status register. If it's 412 * not cleared within 'timeout', then error out. 413 */ 414 while (timeout) { 415 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI, 416 hw->nvm.opcode_bits); 417 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8); 418 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI)) 419 break; 420 421 usec_delay(5); 422 e1000_standby_nvm(hw); 423 timeout--; 424 } 425 426 if (!timeout) { 427 DEBUGOUT("SPI NVM Status error\n"); 428 return -E1000_ERR_NVM; 429 } 430 } 431 432 return E1000_SUCCESS; 433 } 434 435 /** 436 * e1000_read_nvm_spi - Read EEPROM's using SPI 437 * @hw: pointer to the HW structure 438 * @offset: offset of word in the EEPROM to read 439 * @words: number of words to read 440 * @data: word read from the EEPROM 441 * 442 * Reads a 16 bit word from the EEPROM. 443 **/ 444 s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 445 { 446 struct e1000_nvm_info *nvm = &hw->nvm; 447 u32 i = 0; 448 s32 ret_val; 449 u16 word_in; 450 u8 read_opcode = NVM_READ_OPCODE_SPI; 451 452 DEBUGFUNC("e1000_read_nvm_spi"); 453 454 /* A check for invalid values: offset too large, too many words, 455 * and not enough words. 456 */ 457 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 458 (words == 0)) { 459 DEBUGOUT("nvm parameter(s) out of bounds\n"); 460 return -E1000_ERR_NVM; 461 } 462 463 ret_val = nvm->ops.acquire(hw); 464 if (ret_val) 465 return ret_val; 466 467 ret_val = e1000_ready_nvm_eeprom(hw); 468 if (ret_val) 469 goto release; 470 471 e1000_standby_nvm(hw); 472 473 if ((nvm->address_bits == 8) && (offset >= 128)) 474 read_opcode |= NVM_A8_OPCODE_SPI; 475 476 /* Send the READ command (opcode + addr) */ 477 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits); 478 e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits); 479 480 /* Read the data. SPI NVMs increment the address with each byte 481 * read and will roll over if reading beyond the end. This allows 482 * us to read the whole NVM from any offset 483 */ 484 for (i = 0; i < words; i++) { 485 word_in = e1000_shift_in_eec_bits(hw, 16); 486 data[i] = (word_in >> 8) | (word_in << 8); 487 } 488 489 release: 490 nvm->ops.release(hw); 491 492 return ret_val; 493 } 494 495 /** 496 * e1000_read_nvm_microwire - Reads EEPROM's using microwire 497 * @hw: pointer to the HW structure 498 * @offset: offset of word in the EEPROM to read 499 * @words: number of words to read 500 * @data: word read from the EEPROM 501 * 502 * Reads a 16 bit word from the EEPROM. 503 **/ 504 s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, 505 u16 *data) 506 { 507 struct e1000_nvm_info *nvm = &hw->nvm; 508 u32 i = 0; 509 s32 ret_val; 510 u8 read_opcode = NVM_READ_OPCODE_MICROWIRE; 511 512 DEBUGFUNC("e1000_read_nvm_microwire"); 513 514 /* A check for invalid values: offset too large, too many words, 515 * and not enough words. 516 */ 517 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 518 (words == 0)) { 519 DEBUGOUT("nvm parameter(s) out of bounds\n"); 520 return -E1000_ERR_NVM; 521 } 522 523 ret_val = nvm->ops.acquire(hw); 524 if (ret_val) 525 return ret_val; 526 527 ret_val = e1000_ready_nvm_eeprom(hw); 528 if (ret_val) 529 goto release; 530 531 for (i = 0; i < words; i++) { 532 /* Send the READ command (opcode + addr) */ 533 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits); 534 e1000_shift_out_eec_bits(hw, (u16)(offset + i), 535 nvm->address_bits); 536 537 /* Read the data. For microwire, each word requires the 538 * overhead of setup and tear-down. 539 */ 540 data[i] = e1000_shift_in_eec_bits(hw, 16); 541 e1000_standby_nvm(hw); 542 } 543 544 release: 545 nvm->ops.release(hw); 546 547 return ret_val; 548 } 549 550 /** 551 * e1000_read_nvm_eerd - Reads EEPROM using EERD register 552 * @hw: pointer to the HW structure 553 * @offset: offset of word in the EEPROM to read 554 * @words: number of words to read 555 * @data: word read from the EEPROM 556 * 557 * Reads a 16 bit word from the EEPROM using the EERD register. 558 **/ 559 s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 560 { 561 struct e1000_nvm_info *nvm = &hw->nvm; 562 u32 i, eerd = 0; 563 s32 ret_val = E1000_SUCCESS; 564 565 DEBUGFUNC("e1000_read_nvm_eerd"); 566 567 /* A check for invalid values: offset too large, too many words, 568 * too many words for the offset, and not enough words. 569 */ 570 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 571 (words == 0)) { 572 DEBUGOUT("nvm parameter(s) out of bounds\n"); 573 return -E1000_ERR_NVM; 574 } 575 576 for (i = 0; i < words; i++) { 577 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) + 578 E1000_NVM_RW_REG_START; 579 580 E1000_WRITE_REG(hw, E1000_EERD, eerd); 581 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ); 582 if (ret_val) 583 break; 584 585 data[i] = (E1000_READ_REG(hw, E1000_EERD) >> 586 E1000_NVM_RW_REG_DATA); 587 } 588 589 if (ret_val) 590 DEBUGOUT1("NVM read error: %d\n", ret_val); 591 592 return ret_val; 593 } 594 595 /** 596 * e1000_write_nvm_spi - Write to EEPROM using SPI 597 * @hw: pointer to the HW structure 598 * @offset: offset within the EEPROM to be written to 599 * @words: number of words to write 600 * @data: 16 bit word(s) to be written to the EEPROM 601 * 602 * Writes data to EEPROM at offset using SPI interface. 603 * 604 * If e1000_update_nvm_checksum is not called after this function , the 605 * EEPROM will most likely contain an invalid checksum. 606 **/ 607 s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 608 { 609 struct e1000_nvm_info *nvm = &hw->nvm; 610 s32 ret_val = -E1000_ERR_NVM; 611 u16 widx = 0; 612 613 DEBUGFUNC("e1000_write_nvm_spi"); 614 615 /* A check for invalid values: offset too large, too many words, 616 * and not enough words. 617 */ 618 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 619 (words == 0)) { 620 DEBUGOUT("nvm parameter(s) out of bounds\n"); 621 return -E1000_ERR_NVM; 622 } 623 624 while (widx < words) { 625 u8 write_opcode = NVM_WRITE_OPCODE_SPI; 626 627 ret_val = nvm->ops.acquire(hw); 628 if (ret_val) 629 return ret_val; 630 631 ret_val = e1000_ready_nvm_eeprom(hw); 632 if (ret_val) { 633 nvm->ops.release(hw); 634 return ret_val; 635 } 636 637 e1000_standby_nvm(hw); 638 639 /* Send the WRITE ENABLE command (8 bit opcode) */ 640 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI, 641 nvm->opcode_bits); 642 643 e1000_standby_nvm(hw); 644 645 /* Some SPI eeproms use the 8th address bit embedded in the 646 * opcode 647 */ 648 if ((nvm->address_bits == 8) && (offset >= 128)) 649 write_opcode |= NVM_A8_OPCODE_SPI; 650 651 /* Send the Write command (8-bit opcode + addr) */ 652 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits); 653 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2), 654 nvm->address_bits); 655 656 /* Loop to allow for up to whole page write of eeprom */ 657 while (widx < words) { 658 u16 word_out = data[widx]; 659 word_out = (word_out >> 8) | (word_out << 8); 660 e1000_shift_out_eec_bits(hw, word_out, 16); 661 widx++; 662 663 if ((((offset + widx) * 2) % nvm->page_size) == 0) { 664 e1000_standby_nvm(hw); 665 break; 666 } 667 } 668 msec_delay(10); 669 nvm->ops.release(hw); 670 } 671 672 return ret_val; 673 } 674 675 /** 676 * e1000_write_nvm_microwire - Writes EEPROM using microwire 677 * @hw: pointer to the HW structure 678 * @offset: offset within the EEPROM to be written to 679 * @words: number of words to write 680 * @data: 16 bit word(s) to be written to the EEPROM 681 * 682 * Writes data to EEPROM at offset using microwire interface. 683 * 684 * If e1000_update_nvm_checksum is not called after this function , the 685 * EEPROM will most likely contain an invalid checksum. 686 **/ 687 s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, 688 u16 *data) 689 { 690 struct e1000_nvm_info *nvm = &hw->nvm; 691 s32 ret_val; 692 u32 eecd; 693 u16 words_written = 0; 694 u16 widx = 0; 695 696 DEBUGFUNC("e1000_write_nvm_microwire"); 697 698 /* A check for invalid values: offset too large, too many words, 699 * and not enough words. 700 */ 701 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 702 (words == 0)) { 703 DEBUGOUT("nvm parameter(s) out of bounds\n"); 704 return -E1000_ERR_NVM; 705 } 706 707 ret_val = nvm->ops.acquire(hw); 708 if (ret_val) 709 return ret_val; 710 711 ret_val = e1000_ready_nvm_eeprom(hw); 712 if (ret_val) 713 goto release; 714 715 e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE, 716 (u16)(nvm->opcode_bits + 2)); 717 718 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2)); 719 720 e1000_standby_nvm(hw); 721 722 while (words_written < words) { 723 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE, 724 nvm->opcode_bits); 725 726 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written), 727 nvm->address_bits); 728 729 e1000_shift_out_eec_bits(hw, data[words_written], 16); 730 731 e1000_standby_nvm(hw); 732 733 for (widx = 0; widx < 200; widx++) { 734 eecd = E1000_READ_REG(hw, E1000_EECD); 735 if (eecd & E1000_EECD_DO) 736 break; 737 usec_delay(50); 738 } 739 740 if (widx == 200) { 741 DEBUGOUT("NVM Write did not complete\n"); 742 ret_val = -E1000_ERR_NVM; 743 goto release; 744 } 745 746 e1000_standby_nvm(hw); 747 748 words_written++; 749 } 750 751 e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE, 752 (u16)(nvm->opcode_bits + 2)); 753 754 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2)); 755 756 release: 757 nvm->ops.release(hw); 758 759 return ret_val; 760 } 761 762 /** 763 * e1000_read_pba_string_generic - Read device part number 764 * @hw: pointer to the HW structure 765 * @pba_num: pointer to device part number 766 * @pba_num_size: size of part number buffer 767 * 768 * Reads the product board assembly (PBA) number from the EEPROM and stores 769 * the value in pba_num. 770 **/ 771 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num, 772 u32 pba_num_size) 773 { 774 s32 ret_val; 775 u16 nvm_data; 776 u16 pba_ptr; 777 u16 offset; 778 u16 length; 779 780 DEBUGFUNC("e1000_read_pba_string_generic"); 781 782 if (pba_num == NULL) { 783 DEBUGOUT("PBA string buffer was null\n"); 784 return -E1000_ERR_INVALID_ARGUMENT; 785 } 786 787 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); 788 if (ret_val) { 789 DEBUGOUT("NVM Read Error\n"); 790 return ret_val; 791 } 792 793 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr); 794 if (ret_val) { 795 DEBUGOUT("NVM Read Error\n"); 796 return ret_val; 797 } 798 799 /* if nvm_data is not ptr guard the PBA must be in legacy format which 800 * means pba_ptr is actually our second data word for the PBA number 801 * and we can decode it into an ascii string 802 */ 803 if (nvm_data != NVM_PBA_PTR_GUARD) { 804 DEBUGOUT("NVM PBA number is not stored as string\n"); 805 806 /* make sure callers buffer is big enough to store the PBA */ 807 if (pba_num_size < E1000_PBANUM_LENGTH) { 808 DEBUGOUT("PBA string buffer too small\n"); 809 return E1000_ERR_NO_SPACE; 810 } 811 812 /* extract hex string from data and pba_ptr */ 813 pba_num[0] = (nvm_data >> 12) & 0xF; 814 pba_num[1] = (nvm_data >> 8) & 0xF; 815 pba_num[2] = (nvm_data >> 4) & 0xF; 816 pba_num[3] = nvm_data & 0xF; 817 pba_num[4] = (pba_ptr >> 12) & 0xF; 818 pba_num[5] = (pba_ptr >> 8) & 0xF; 819 pba_num[6] = '-'; 820 pba_num[7] = 0; 821 pba_num[8] = (pba_ptr >> 4) & 0xF; 822 pba_num[9] = pba_ptr & 0xF; 823 824 /* put a null character on the end of our string */ 825 pba_num[10] = '\0'; 826 827 /* switch all the data but the '-' to hex char */ 828 for (offset = 0; offset < 10; offset++) { 829 if (pba_num[offset] < 0xA) 830 pba_num[offset] += '0'; 831 else if (pba_num[offset] < 0x10) 832 pba_num[offset] += 'A' - 0xA; 833 } 834 835 return E1000_SUCCESS; 836 } 837 838 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length); 839 if (ret_val) { 840 DEBUGOUT("NVM Read Error\n"); 841 return ret_val; 842 } 843 844 if (length == 0xFFFF || length == 0) { 845 DEBUGOUT("NVM PBA number section invalid length\n"); 846 return -E1000_ERR_NVM_PBA_SECTION; 847 } 848 /* check if pba_num buffer is big enough */ 849 if (pba_num_size < (((u32)length * 2) - 1)) { 850 DEBUGOUT("PBA string buffer too small\n"); 851 return -E1000_ERR_NO_SPACE; 852 } 853 854 /* trim pba length from start of string */ 855 pba_ptr++; 856 length--; 857 858 for (offset = 0; offset < length; offset++) { 859 ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data); 860 if (ret_val) { 861 DEBUGOUT("NVM Read Error\n"); 862 return ret_val; 863 } 864 pba_num[offset * 2] = (u8)(nvm_data >> 8); 865 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF); 866 } 867 pba_num[offset * 2] = '\0'; 868 869 return E1000_SUCCESS; 870 } 871 872 /** 873 * e1000_read_pba_length_generic - Read device part number length 874 * @hw: pointer to the HW structure 875 * @pba_num_size: size of part number buffer 876 * 877 * Reads the product board assembly (PBA) number length from the EEPROM and 878 * stores the value in pba_num_size. 879 **/ 880 s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size) 881 { 882 s32 ret_val; 883 u16 nvm_data; 884 u16 pba_ptr; 885 u16 length; 886 887 DEBUGFUNC("e1000_read_pba_length_generic"); 888 889 if (pba_num_size == NULL) { 890 DEBUGOUT("PBA buffer size was null\n"); 891 return -E1000_ERR_INVALID_ARGUMENT; 892 } 893 894 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); 895 if (ret_val) { 896 DEBUGOUT("NVM Read Error\n"); 897 return ret_val; 898 } 899 900 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr); 901 if (ret_val) { 902 DEBUGOUT("NVM Read Error\n"); 903 return ret_val; 904 } 905 906 /* if data is not ptr guard the PBA must be in legacy format */ 907 if (nvm_data != NVM_PBA_PTR_GUARD) { 908 *pba_num_size = E1000_PBANUM_LENGTH; 909 return E1000_SUCCESS; 910 } 911 912 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length); 913 if (ret_val) { 914 DEBUGOUT("NVM Read Error\n"); 915 return ret_val; 916 } 917 918 if (length == 0xFFFF || length == 0) { 919 DEBUGOUT("NVM PBA number section invalid length\n"); 920 return -E1000_ERR_NVM_PBA_SECTION; 921 } 922 923 /* Convert from length in u16 values to u8 chars, add 1 for NULL, 924 * and subtract 2 because length field is included in length. 925 */ 926 *pba_num_size = ((u32)length * 2) - 1; 927 928 return E1000_SUCCESS; 929 } 930 931 /** 932 * e1000_read_pba_num_generic - Read device part number 933 * @hw: pointer to the HW structure 934 * @pba_num: pointer to device part number 935 * 936 * Reads the product board assembly (PBA) number from the EEPROM and stores 937 * the value in pba_num. 938 **/ 939 s32 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num) 940 { 941 s32 ret_val; 942 u16 nvm_data; 943 944 DEBUGFUNC("e1000_read_pba_num_generic"); 945 946 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); 947 if (ret_val) { 948 DEBUGOUT("NVM Read Error\n"); 949 return ret_val; 950 } else if (nvm_data == NVM_PBA_PTR_GUARD) { 951 DEBUGOUT("NVM Not Supported\n"); 952 return -E1000_NOT_IMPLEMENTED; 953 } 954 *pba_num = (u32)(nvm_data << 16); 955 956 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data); 957 if (ret_val) { 958 DEBUGOUT("NVM Read Error\n"); 959 return ret_val; 960 } 961 *pba_num |= nvm_data; 962 963 return E1000_SUCCESS; 964 } 965 966 /** 967 * e1000_read_pba_raw 968 * @hw: pointer to the HW structure 969 * @eeprom_buf: optional pointer to EEPROM image 970 * @eeprom_buf_size: size of EEPROM image in words 971 * @max_pba_block_size: PBA block size limit 972 * @pba: pointer to output PBA structure 973 * 974 * Reads PBA from EEPROM image when eeprom_buf is not NULL. 975 * Reads PBA from physical EEPROM device when eeprom_buf is NULL. 976 * 977 **/ 978 s32 e1000_read_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf, 979 u32 eeprom_buf_size, u16 max_pba_block_size, 980 struct e1000_pba *pba) 981 { 982 s32 ret_val; 983 u16 pba_block_size; 984 985 if (pba == NULL) 986 return -E1000_ERR_PARAM; 987 988 if (eeprom_buf == NULL) { 989 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2, 990 &pba->word[0]); 991 if (ret_val) 992 return ret_val; 993 } else { 994 if (eeprom_buf_size > NVM_PBA_OFFSET_1) { 995 pba->word[0] = eeprom_buf[NVM_PBA_OFFSET_0]; 996 pba->word[1] = eeprom_buf[NVM_PBA_OFFSET_1]; 997 } else { 998 return -E1000_ERR_PARAM; 999 } 1000 } 1001 1002 if (pba->word[0] == NVM_PBA_PTR_GUARD) { 1003 if (pba->pba_block == NULL) 1004 return -E1000_ERR_PARAM; 1005 1006 ret_val = e1000_get_pba_block_size(hw, eeprom_buf, 1007 eeprom_buf_size, 1008 &pba_block_size); 1009 if (ret_val) 1010 return ret_val; 1011 1012 if (pba_block_size > max_pba_block_size) 1013 return -E1000_ERR_PARAM; 1014 1015 if (eeprom_buf == NULL) { 1016 ret_val = e1000_read_nvm(hw, pba->word[1], 1017 pba_block_size, 1018 pba->pba_block); 1019 if (ret_val) 1020 return ret_val; 1021 } else { 1022 if (eeprom_buf_size > (u32)(pba->word[1] + 1023 pba_block_size)) { 1024 memcpy(pba->pba_block, 1025 &eeprom_buf[pba->word[1]], 1026 pba_block_size * sizeof(u16)); 1027 } else { 1028 return -E1000_ERR_PARAM; 1029 } 1030 } 1031 } 1032 1033 return E1000_SUCCESS; 1034 } 1035 1036 /** 1037 * e1000_write_pba_raw 1038 * @hw: pointer to the HW structure 1039 * @eeprom_buf: optional pointer to EEPROM image 1040 * @eeprom_buf_size: size of EEPROM image in words 1041 * @pba: pointer to PBA structure 1042 * 1043 * Writes PBA to EEPROM image when eeprom_buf is not NULL. 1044 * Writes PBA to physical EEPROM device when eeprom_buf is NULL. 1045 * 1046 **/ 1047 s32 e1000_write_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf, 1048 u32 eeprom_buf_size, struct e1000_pba *pba) 1049 { 1050 s32 ret_val; 1051 1052 if (pba == NULL) 1053 return -E1000_ERR_PARAM; 1054 1055 if (eeprom_buf == NULL) { 1056 ret_val = e1000_write_nvm(hw, NVM_PBA_OFFSET_0, 2, 1057 &pba->word[0]); 1058 if (ret_val) 1059 return ret_val; 1060 } else { 1061 if (eeprom_buf_size > NVM_PBA_OFFSET_1) { 1062 eeprom_buf[NVM_PBA_OFFSET_0] = pba->word[0]; 1063 eeprom_buf[NVM_PBA_OFFSET_1] = pba->word[1]; 1064 } else { 1065 return -E1000_ERR_PARAM; 1066 } 1067 } 1068 1069 if (pba->word[0] == NVM_PBA_PTR_GUARD) { 1070 if (pba->pba_block == NULL) 1071 return -E1000_ERR_PARAM; 1072 1073 if (eeprom_buf == NULL) { 1074 ret_val = e1000_write_nvm(hw, pba->word[1], 1075 pba->pba_block[0], 1076 pba->pba_block); 1077 if (ret_val) 1078 return ret_val; 1079 } else { 1080 if (eeprom_buf_size > (u32)(pba->word[1] + 1081 pba->pba_block[0])) { 1082 memcpy(&eeprom_buf[pba->word[1]], 1083 pba->pba_block, 1084 pba->pba_block[0] * sizeof(u16)); 1085 } else { 1086 return -E1000_ERR_PARAM; 1087 } 1088 } 1089 } 1090 1091 return E1000_SUCCESS; 1092 } 1093 1094 /** 1095 * e1000_get_pba_block_size 1096 * @hw: pointer to the HW structure 1097 * @eeprom_buf: optional pointer to EEPROM image 1098 * @eeprom_buf_size: size of EEPROM image in words 1099 * @pba_data_size: pointer to output variable 1100 * 1101 * Returns the size of the PBA block in words. Function operates on EEPROM 1102 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical 1103 * EEPROM device. 1104 * 1105 **/ 1106 s32 e1000_get_pba_block_size(struct e1000_hw *hw, u16 *eeprom_buf, 1107 u32 eeprom_buf_size, u16 *pba_block_size) 1108 { 1109 s32 ret_val; 1110 u16 pba_word[2]; 1111 u16 length; 1112 1113 DEBUGFUNC("e1000_get_pba_block_size"); 1114 1115 if (eeprom_buf == NULL) { 1116 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2, &pba_word[0]); 1117 if (ret_val) 1118 return ret_val; 1119 } else { 1120 if (eeprom_buf_size > NVM_PBA_OFFSET_1) { 1121 pba_word[0] = eeprom_buf[NVM_PBA_OFFSET_0]; 1122 pba_word[1] = eeprom_buf[NVM_PBA_OFFSET_1]; 1123 } else { 1124 return -E1000_ERR_PARAM; 1125 } 1126 } 1127 1128 if (pba_word[0] == NVM_PBA_PTR_GUARD) { 1129 if (eeprom_buf == NULL) { 1130 ret_val = e1000_read_nvm(hw, pba_word[1] + 0, 1, 1131 &length); 1132 if (ret_val) 1133 return ret_val; 1134 } else { 1135 if (eeprom_buf_size > pba_word[1]) 1136 length = eeprom_buf[pba_word[1] + 0]; 1137 else 1138 return -E1000_ERR_PARAM; 1139 } 1140 1141 if (length == 0xFFFF || length == 0) 1142 return -E1000_ERR_NVM_PBA_SECTION; 1143 } else { 1144 /* PBA number in legacy format, there is no PBA Block. */ 1145 length = 0; 1146 } 1147 1148 if (pba_block_size != NULL) 1149 *pba_block_size = length; 1150 1151 return E1000_SUCCESS; 1152 } 1153 1154 /** 1155 * e1000_read_mac_addr_generic - Read device MAC address 1156 * @hw: pointer to the HW structure 1157 * 1158 * Reads the device MAC address from the EEPROM and stores the value. 1159 * Since devices with two ports use the same EEPROM, we increment the 1160 * last bit in the MAC address for the second port. 1161 **/ 1162 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw) 1163 { 1164 u32 rar_high; 1165 u32 rar_low; 1166 u16 i; 1167 1168 rar_high = E1000_READ_REG(hw, E1000_RAH(0)); 1169 rar_low = E1000_READ_REG(hw, E1000_RAL(0)); 1170 1171 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++) 1172 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8)); 1173 1174 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++) 1175 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8)); 1176 1177 for (i = 0; i < ETH_ADDR_LEN; i++) 1178 hw->mac.addr[i] = hw->mac.perm_addr[i]; 1179 1180 return E1000_SUCCESS; 1181 } 1182 1183 /** 1184 * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum 1185 * @hw: pointer to the HW structure 1186 * 1187 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 1188 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 1189 **/ 1190 s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw) 1191 { 1192 s32 ret_val; 1193 u16 checksum = 0; 1194 u16 i, nvm_data; 1195 1196 DEBUGFUNC("e1000_validate_nvm_checksum_generic"); 1197 1198 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { 1199 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 1200 if (ret_val) { 1201 DEBUGOUT("NVM Read Error\n"); 1202 return ret_val; 1203 } 1204 checksum += nvm_data; 1205 } 1206 1207 if (checksum != (u16) NVM_SUM) { 1208 DEBUGOUT("NVM Checksum Invalid\n"); 1209 return -E1000_ERR_NVM; 1210 } 1211 1212 return E1000_SUCCESS; 1213 } 1214 1215 /** 1216 * e1000_update_nvm_checksum_generic - Update EEPROM checksum 1217 * @hw: pointer to the HW structure 1218 * 1219 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 1220 * up to the checksum. Then calculates the EEPROM checksum and writes the 1221 * value to the EEPROM. 1222 **/ 1223 s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw) 1224 { 1225 s32 ret_val; 1226 u16 checksum = 0; 1227 u16 i, nvm_data; 1228 1229 DEBUGFUNC("e1000_update_nvm_checksum"); 1230 1231 for (i = 0; i < NVM_CHECKSUM_REG; i++) { 1232 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 1233 if (ret_val) { 1234 DEBUGOUT("NVM Read Error while updating checksum.\n"); 1235 return ret_val; 1236 } 1237 checksum += nvm_data; 1238 } 1239 checksum = (u16) NVM_SUM - checksum; 1240 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum); 1241 if (ret_val) 1242 DEBUGOUT("NVM Write Error while updating checksum.\n"); 1243 1244 return ret_val; 1245 } 1246 1247 /** 1248 * e1000_reload_nvm_generic - Reloads EEPROM 1249 * @hw: pointer to the HW structure 1250 * 1251 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the 1252 * extended control register. 1253 **/ 1254 static void e1000_reload_nvm_generic(struct e1000_hw *hw) 1255 { 1256 u32 ctrl_ext; 1257 1258 DEBUGFUNC("e1000_reload_nvm_generic"); 1259 1260 usec_delay(10); 1261 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1262 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1263 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1264 E1000_WRITE_FLUSH(hw); 1265 } 1266 1267 /** 1268 * e1000_get_fw_version - Get firmware version information 1269 * @hw: pointer to the HW structure 1270 * @fw_vers: pointer to output version structure 1271 * 1272 * unsupported/not present features return 0 in version structure 1273 **/ 1274 void e1000_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers) 1275 { 1276 u16 eeprom_verh, eeprom_verl, etrack_test, fw_version; 1277 u8 q, hval, rem, result; 1278 u16 comb_verh, comb_verl, comb_offset; 1279 1280 memset(fw_vers, 0, sizeof(struct e1000_fw_version)); 1281 1282 /* basic eeprom version numbers, bits used vary by part and by tool 1283 * used to create the nvm images */ 1284 /* Check which data format we have */ 1285 hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test); 1286 switch (hw->mac.type) { 1287 case e1000_i211: 1288 e1000_read_invm_version(hw, fw_vers); 1289 return; 1290 case e1000_82575: 1291 case e1000_82576: 1292 case e1000_82580: 1293 /* Use this format, unless EETRACK ID exists, 1294 * then use alternate format 1295 */ 1296 if ((etrack_test & NVM_MAJOR_MASK) != NVM_ETRACK_VALID) { 1297 hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version); 1298 fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK) 1299 >> NVM_MAJOR_SHIFT; 1300 fw_vers->eep_minor = (fw_version & NVM_MINOR_MASK) 1301 >> NVM_MINOR_SHIFT; 1302 fw_vers->eep_build = (fw_version & NVM_IMAGE_ID_MASK); 1303 goto etrack_id; 1304 } 1305 break; 1306 case e1000_i210: 1307 case e1000_i350: 1308 /* find combo image version */ 1309 hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset); 1310 if ((comb_offset != 0x0) && 1311 (comb_offset != NVM_VER_INVALID)) { 1312 1313 hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset 1314 + 1), 1, &comb_verh); 1315 hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset), 1316 1, &comb_verl); 1317 1318 /* get Option Rom version if it exists and is valid */ 1319 if ((comb_verh && comb_verl) && 1320 ((comb_verh != NVM_VER_INVALID) && 1321 (comb_verl != NVM_VER_INVALID))) { 1322 1323 fw_vers->or_valid = TRUE; 1324 fw_vers->or_major = 1325 comb_verl >> NVM_COMB_VER_SHFT; 1326 fw_vers->or_build = 1327 (comb_verl << NVM_COMB_VER_SHFT) 1328 | (comb_verh >> NVM_COMB_VER_SHFT); 1329 fw_vers->or_patch = 1330 comb_verh & NVM_COMB_VER_MASK; 1331 } 1332 } 1333 break; 1334 default: 1335 return; 1336 } 1337 hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version); 1338 fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK) 1339 >> NVM_MAJOR_SHIFT; 1340 1341 /* check for old style version format in newer images*/ 1342 if ((fw_version & NVM_NEW_DEC_MASK) == 0x0) { 1343 eeprom_verl = (fw_version & NVM_COMB_VER_MASK); 1344 } else { 1345 eeprom_verl = (fw_version & NVM_MINOR_MASK) 1346 >> NVM_MINOR_SHIFT; 1347 } 1348 /* Convert minor value to hex before assigning to output struct 1349 * Val to be converted will not be higher than 99, per tool output 1350 */ 1351 q = eeprom_verl / NVM_HEX_CONV; 1352 hval = q * NVM_HEX_TENS; 1353 rem = eeprom_verl % NVM_HEX_CONV; 1354 result = hval + rem; 1355 fw_vers->eep_minor = result; 1356 1357 etrack_id: 1358 if ((etrack_test & NVM_MAJOR_MASK) == NVM_ETRACK_VALID) { 1359 hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verl); 1360 hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verh); 1361 fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT) 1362 | eeprom_verl; 1363 } 1364 return; 1365 } 1366 1367 1368