1 /****************************************************************************** 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "e1000_api.h" 36 37 /** 38 * e1000_init_nvm_ops_generic - Initialize NVM function pointers 39 * @hw: pointer to the HW structure 40 * 41 * Setups up the function pointers to no-op functions 42 **/ 43 void e1000_init_nvm_ops_generic(struct e1000_hw *hw) 44 { 45 struct e1000_nvm_info *nvm = &hw->nvm; 46 DEBUGFUNC("e1000_init_nvm_ops_generic"); 47 48 /* Initialize function pointers */ 49 nvm->ops.init_params = e1000_null_ops_generic; 50 nvm->ops.acquire = e1000_null_ops_generic; 51 nvm->ops.read = e1000_null_read_nvm; 52 nvm->ops.release = e1000_null_nvm_generic; 53 nvm->ops.reload = e1000_reload_nvm_generic; 54 nvm->ops.update = e1000_null_ops_generic; 55 nvm->ops.valid_led_default = e1000_null_led_default; 56 nvm->ops.validate = e1000_null_ops_generic; 57 nvm->ops.write = e1000_null_write_nvm; 58 } 59 60 /** 61 * e1000_null_nvm_read - No-op function, return 0 62 * @hw: pointer to the HW structure 63 **/ 64 s32 e1000_null_read_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c) 65 { 66 DEBUGFUNC("e1000_null_read_nvm"); 67 return E1000_SUCCESS; 68 } 69 70 /** 71 * e1000_null_nvm_generic - No-op function, return void 72 * @hw: pointer to the HW structure 73 **/ 74 void e1000_null_nvm_generic(struct e1000_hw *hw) 75 { 76 DEBUGFUNC("e1000_null_nvm_generic"); 77 return; 78 } 79 80 /** 81 * e1000_null_led_default - No-op function, return 0 82 * @hw: pointer to the HW structure 83 **/ 84 s32 e1000_null_led_default(struct e1000_hw *hw, u16 *data) 85 { 86 DEBUGFUNC("e1000_null_led_default"); 87 return E1000_SUCCESS; 88 } 89 90 /** 91 * e1000_null_write_nvm - No-op function, return 0 92 * @hw: pointer to the HW structure 93 **/ 94 s32 e1000_null_write_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c) 95 { 96 DEBUGFUNC("e1000_null_write_nvm"); 97 return E1000_SUCCESS; 98 } 99 100 /** 101 * e1000_raise_eec_clk - Raise EEPROM clock 102 * @hw: pointer to the HW structure 103 * @eecd: pointer to the EEPROM 104 * 105 * Enable/Raise the EEPROM clock bit. 106 **/ 107 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd) 108 { 109 *eecd = *eecd | E1000_EECD_SK; 110 E1000_WRITE_REG(hw, E1000_EECD, *eecd); 111 E1000_WRITE_FLUSH(hw); 112 usec_delay(hw->nvm.delay_usec); 113 } 114 115 /** 116 * e1000_lower_eec_clk - Lower EEPROM clock 117 * @hw: pointer to the HW structure 118 * @eecd: pointer to the EEPROM 119 * 120 * Clear/Lower the EEPROM clock bit. 121 **/ 122 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd) 123 { 124 *eecd = *eecd & ~E1000_EECD_SK; 125 E1000_WRITE_REG(hw, E1000_EECD, *eecd); 126 E1000_WRITE_FLUSH(hw); 127 usec_delay(hw->nvm.delay_usec); 128 } 129 130 /** 131 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM 132 * @hw: pointer to the HW structure 133 * @data: data to send to the EEPROM 134 * @count: number of bits to shift out 135 * 136 * We need to shift 'count' bits out to the EEPROM. So, the value in the 137 * "data" parameter will be shifted out to the EEPROM one bit at a time. 138 * In order to do this, "data" must be broken down into bits. 139 **/ 140 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count) 141 { 142 struct e1000_nvm_info *nvm = &hw->nvm; 143 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 144 u32 mask; 145 146 DEBUGFUNC("e1000_shift_out_eec_bits"); 147 148 mask = 0x01 << (count - 1); 149 if (nvm->type == e1000_nvm_eeprom_microwire) 150 eecd &= ~E1000_EECD_DO; 151 else 152 if (nvm->type == e1000_nvm_eeprom_spi) 153 eecd |= E1000_EECD_DO; 154 155 do { 156 eecd &= ~E1000_EECD_DI; 157 158 if (data & mask) 159 eecd |= E1000_EECD_DI; 160 161 E1000_WRITE_REG(hw, E1000_EECD, eecd); 162 E1000_WRITE_FLUSH(hw); 163 164 usec_delay(nvm->delay_usec); 165 166 e1000_raise_eec_clk(hw, &eecd); 167 e1000_lower_eec_clk(hw, &eecd); 168 169 mask >>= 1; 170 } while (mask); 171 172 eecd &= ~E1000_EECD_DI; 173 E1000_WRITE_REG(hw, E1000_EECD, eecd); 174 } 175 176 /** 177 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM 178 * @hw: pointer to the HW structure 179 * @count: number of bits to shift in 180 * 181 * In order to read a register from the EEPROM, we need to shift 'count' bits 182 * in from the EEPROM. Bits are "shifted in" by raising the clock input to 183 * the EEPROM (setting the SK bit), and then reading the value of the data out 184 * "DO" bit. During this "shifting in" process the data in "DI" bit should 185 * always be clear. 186 **/ 187 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count) 188 { 189 u32 eecd; 190 u32 i; 191 u16 data; 192 193 DEBUGFUNC("e1000_shift_in_eec_bits"); 194 195 eecd = E1000_READ_REG(hw, E1000_EECD); 196 197 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 198 data = 0; 199 200 for (i = 0; i < count; i++) { 201 data <<= 1; 202 e1000_raise_eec_clk(hw, &eecd); 203 204 eecd = E1000_READ_REG(hw, E1000_EECD); 205 206 eecd &= ~E1000_EECD_DI; 207 if (eecd & E1000_EECD_DO) 208 data |= 1; 209 210 e1000_lower_eec_clk(hw, &eecd); 211 } 212 213 return data; 214 } 215 216 /** 217 * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion 218 * @hw: pointer to the HW structure 219 * @ee_reg: EEPROM flag for polling 220 * 221 * Polls the EEPROM status bit for either read or write completion based 222 * upon the value of 'ee_reg'. 223 **/ 224 s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) 225 { 226 u32 attempts = 100000; 227 u32 i, reg = 0; 228 s32 ret_val = -E1000_ERR_NVM; 229 230 DEBUGFUNC("e1000_poll_eerd_eewr_done"); 231 232 for (i = 0; i < attempts; i++) { 233 if (ee_reg == E1000_NVM_POLL_READ) 234 reg = E1000_READ_REG(hw, E1000_EERD); 235 else 236 reg = E1000_READ_REG(hw, E1000_EEWR); 237 238 if (reg & E1000_NVM_RW_REG_DONE) { 239 ret_val = E1000_SUCCESS; 240 break; 241 } 242 243 usec_delay(5); 244 } 245 246 return ret_val; 247 } 248 249 /** 250 * e1000_acquire_nvm_generic - Generic request for access to EEPROM 251 * @hw: pointer to the HW structure 252 * 253 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 254 * Return successful if access grant bit set, else clear the request for 255 * EEPROM access and return -E1000_ERR_NVM (-1). 256 **/ 257 s32 e1000_acquire_nvm_generic(struct e1000_hw *hw) 258 { 259 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 260 s32 timeout = E1000_NVM_GRANT_ATTEMPTS; 261 s32 ret_val = E1000_SUCCESS; 262 263 DEBUGFUNC("e1000_acquire_nvm_generic"); 264 265 E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ); 266 eecd = E1000_READ_REG(hw, E1000_EECD); 267 268 while (timeout) { 269 if (eecd & E1000_EECD_GNT) 270 break; 271 usec_delay(5); 272 eecd = E1000_READ_REG(hw, E1000_EECD); 273 timeout--; 274 } 275 276 if (!timeout) { 277 eecd &= ~E1000_EECD_REQ; 278 E1000_WRITE_REG(hw, E1000_EECD, eecd); 279 DEBUGOUT("Could not acquire NVM grant\n"); 280 ret_val = -E1000_ERR_NVM; 281 } 282 283 return ret_val; 284 } 285 286 /** 287 * e1000_standby_nvm - Return EEPROM to standby state 288 * @hw: pointer to the HW structure 289 * 290 * Return the EEPROM to a standby state. 291 **/ 292 static void e1000_standby_nvm(struct e1000_hw *hw) 293 { 294 struct e1000_nvm_info *nvm = &hw->nvm; 295 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 296 297 DEBUGFUNC("e1000_standby_nvm"); 298 299 if (nvm->type == e1000_nvm_eeprom_microwire) { 300 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 301 E1000_WRITE_REG(hw, E1000_EECD, eecd); 302 E1000_WRITE_FLUSH(hw); 303 usec_delay(nvm->delay_usec); 304 305 e1000_raise_eec_clk(hw, &eecd); 306 307 /* Select EEPROM */ 308 eecd |= E1000_EECD_CS; 309 E1000_WRITE_REG(hw, E1000_EECD, eecd); 310 E1000_WRITE_FLUSH(hw); 311 usec_delay(nvm->delay_usec); 312 313 e1000_lower_eec_clk(hw, &eecd); 314 } else 315 if (nvm->type == e1000_nvm_eeprom_spi) { 316 /* Toggle CS to flush commands */ 317 eecd |= E1000_EECD_CS; 318 E1000_WRITE_REG(hw, E1000_EECD, eecd); 319 E1000_WRITE_FLUSH(hw); 320 usec_delay(nvm->delay_usec); 321 eecd &= ~E1000_EECD_CS; 322 E1000_WRITE_REG(hw, E1000_EECD, eecd); 323 E1000_WRITE_FLUSH(hw); 324 usec_delay(nvm->delay_usec); 325 } 326 } 327 328 /** 329 * e1000_stop_nvm - Terminate EEPROM command 330 * @hw: pointer to the HW structure 331 * 332 * Terminates the current command by inverting the EEPROM's chip select pin. 333 **/ 334 void e1000_stop_nvm(struct e1000_hw *hw) 335 { 336 u32 eecd; 337 338 DEBUGFUNC("e1000_stop_nvm"); 339 340 eecd = E1000_READ_REG(hw, E1000_EECD); 341 if (hw->nvm.type == e1000_nvm_eeprom_spi) { 342 /* Pull CS high */ 343 eecd |= E1000_EECD_CS; 344 e1000_lower_eec_clk(hw, &eecd); 345 } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) { 346 /* CS on Microwire is active-high */ 347 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 348 E1000_WRITE_REG(hw, E1000_EECD, eecd); 349 e1000_raise_eec_clk(hw, &eecd); 350 e1000_lower_eec_clk(hw, &eecd); 351 } 352 } 353 354 /** 355 * e1000_release_nvm_generic - Release exclusive access to EEPROM 356 * @hw: pointer to the HW structure 357 * 358 * Stop any current commands to the EEPROM and clear the EEPROM request bit. 359 **/ 360 void e1000_release_nvm_generic(struct e1000_hw *hw) 361 { 362 u32 eecd; 363 364 DEBUGFUNC("e1000_release_nvm_generic"); 365 366 e1000_stop_nvm(hw); 367 368 eecd = E1000_READ_REG(hw, E1000_EECD); 369 eecd &= ~E1000_EECD_REQ; 370 E1000_WRITE_REG(hw, E1000_EECD, eecd); 371 } 372 373 /** 374 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write 375 * @hw: pointer to the HW structure 376 * 377 * Setups the EEPROM for reading and writing. 378 **/ 379 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw) 380 { 381 struct e1000_nvm_info *nvm = &hw->nvm; 382 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 383 s32 ret_val = E1000_SUCCESS; 384 u16 timeout = 0; 385 u8 spi_stat_reg; 386 387 DEBUGFUNC("e1000_ready_nvm_eeprom"); 388 389 if (nvm->type == e1000_nvm_eeprom_microwire) { 390 /* Clear SK and DI */ 391 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 392 E1000_WRITE_REG(hw, E1000_EECD, eecd); 393 /* Set CS */ 394 eecd |= E1000_EECD_CS; 395 E1000_WRITE_REG(hw, E1000_EECD, eecd); 396 } else 397 if (nvm->type == e1000_nvm_eeprom_spi) { 398 /* Clear SK and CS */ 399 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 400 E1000_WRITE_REG(hw, E1000_EECD, eecd); 401 usec_delay(1); 402 timeout = NVM_MAX_RETRY_SPI; 403 404 /* 405 * Read "Status Register" repeatedly until the LSB is cleared. 406 * The EEPROM will signal that the command has been completed 407 * by clearing bit 0 of the internal status register. If it's 408 * not cleared within 'timeout', then error out. 409 */ 410 while (timeout) { 411 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI, 412 hw->nvm.opcode_bits); 413 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8); 414 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI)) 415 break; 416 417 usec_delay(5); 418 e1000_standby_nvm(hw); 419 timeout--; 420 } 421 422 if (!timeout) { 423 DEBUGOUT("SPI NVM Status error\n"); 424 ret_val = -E1000_ERR_NVM; 425 goto out; 426 } 427 } 428 429 out: 430 return ret_val; 431 } 432 433 /** 434 * e1000_read_nvm_spi - Read EEPROM's using SPI 435 * @hw: pointer to the HW structure 436 * @offset: offset of word in the EEPROM to read 437 * @words: number of words to read 438 * @data: word read from the EEPROM 439 * 440 * Reads a 16 bit word from the EEPROM. 441 **/ 442 s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 443 { 444 struct e1000_nvm_info *nvm = &hw->nvm; 445 u32 i = 0; 446 s32 ret_val; 447 u16 word_in; 448 u8 read_opcode = NVM_READ_OPCODE_SPI; 449 450 DEBUGFUNC("e1000_read_nvm_spi"); 451 452 /* 453 * A check for invalid values: offset too large, too many words, 454 * and not enough words. 455 */ 456 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 457 (words == 0)) { 458 DEBUGOUT("nvm parameter(s) out of bounds\n"); 459 ret_val = -E1000_ERR_NVM; 460 goto out; 461 } 462 463 ret_val = nvm->ops.acquire(hw); 464 if (ret_val) 465 goto out; 466 467 ret_val = e1000_ready_nvm_eeprom(hw); 468 if (ret_val) 469 goto release; 470 471 e1000_standby_nvm(hw); 472 473 if ((nvm->address_bits == 8) && (offset >= 128)) 474 read_opcode |= NVM_A8_OPCODE_SPI; 475 476 /* Send the READ command (opcode + addr) */ 477 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits); 478 e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits); 479 480 /* 481 * Read the data. SPI NVMs increment the address with each byte 482 * read and will roll over if reading beyond the end. This allows 483 * us to read the whole NVM from any offset 484 */ 485 for (i = 0; i < words; i++) { 486 word_in = e1000_shift_in_eec_bits(hw, 16); 487 data[i] = (word_in >> 8) | (word_in << 8); 488 } 489 490 release: 491 nvm->ops.release(hw); 492 493 out: 494 return ret_val; 495 } 496 497 /** 498 * e1000_read_nvm_microwire - Reads EEPROM's using microwire 499 * @hw: pointer to the HW structure 500 * @offset: offset of word in the EEPROM to read 501 * @words: number of words to read 502 * @data: word read from the EEPROM 503 * 504 * Reads a 16 bit word from the EEPROM. 505 **/ 506 s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, 507 u16 *data) 508 { 509 struct e1000_nvm_info *nvm = &hw->nvm; 510 u32 i = 0; 511 s32 ret_val; 512 u8 read_opcode = NVM_READ_OPCODE_MICROWIRE; 513 514 DEBUGFUNC("e1000_read_nvm_microwire"); 515 516 /* 517 * A check for invalid values: offset too large, too many words, 518 * and not enough words. 519 */ 520 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 521 (words == 0)) { 522 DEBUGOUT("nvm parameter(s) out of bounds\n"); 523 ret_val = -E1000_ERR_NVM; 524 goto out; 525 } 526 527 ret_val = nvm->ops.acquire(hw); 528 if (ret_val) 529 goto out; 530 531 ret_val = e1000_ready_nvm_eeprom(hw); 532 if (ret_val) 533 goto release; 534 535 for (i = 0; i < words; i++) { 536 /* Send the READ command (opcode + addr) */ 537 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits); 538 e1000_shift_out_eec_bits(hw, (u16)(offset + i), 539 nvm->address_bits); 540 541 /* 542 * Read the data. For microwire, each word requires the 543 * overhead of setup and tear-down. 544 */ 545 data[i] = e1000_shift_in_eec_bits(hw, 16); 546 e1000_standby_nvm(hw); 547 } 548 549 release: 550 nvm->ops.release(hw); 551 552 out: 553 return ret_val; 554 } 555 556 /** 557 * e1000_read_nvm_eerd - Reads EEPROM using EERD register 558 * @hw: pointer to the HW structure 559 * @offset: offset of word in the EEPROM to read 560 * @words: number of words to read 561 * @data: word read from the EEPROM 562 * 563 * Reads a 16 bit word from the EEPROM using the EERD register. 564 **/ 565 s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 566 { 567 struct e1000_nvm_info *nvm = &hw->nvm; 568 u32 i, eerd = 0; 569 s32 ret_val = E1000_SUCCESS; 570 571 DEBUGFUNC("e1000_read_nvm_eerd"); 572 573 /* 574 * A check for invalid values: offset too large, too many words, 575 * too many words for the offset, and not enough words. 576 */ 577 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 578 (words == 0)) { 579 DEBUGOUT("nvm parameter(s) out of bounds\n"); 580 ret_val = -E1000_ERR_NVM; 581 goto out; 582 } 583 584 for (i = 0; i < words; i++) { 585 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) + 586 E1000_NVM_RW_REG_START; 587 588 E1000_WRITE_REG(hw, E1000_EERD, eerd); 589 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ); 590 if (ret_val) 591 break; 592 593 data[i] = (E1000_READ_REG(hw, E1000_EERD) >> 594 E1000_NVM_RW_REG_DATA); 595 } 596 597 out: 598 return ret_val; 599 } 600 601 /** 602 * e1000_write_nvm_spi - Write to EEPROM using SPI 603 * @hw: pointer to the HW structure 604 * @offset: offset within the EEPROM to be written to 605 * @words: number of words to write 606 * @data: 16 bit word(s) to be written to the EEPROM 607 * 608 * Writes data to EEPROM at offset using SPI interface. 609 * 610 * If e1000_update_nvm_checksum is not called after this function , the 611 * EEPROM will most likely contain an invalid checksum. 612 **/ 613 s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 614 { 615 struct e1000_nvm_info *nvm = &hw->nvm; 616 s32 ret_val; 617 u16 widx = 0; 618 619 DEBUGFUNC("e1000_write_nvm_spi"); 620 621 /* 622 * A check for invalid values: offset too large, too many words, 623 * and not enough words. 624 */ 625 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 626 (words == 0)) { 627 DEBUGOUT("nvm parameter(s) out of bounds\n"); 628 ret_val = -E1000_ERR_NVM; 629 goto out; 630 } 631 632 ret_val = nvm->ops.acquire(hw); 633 if (ret_val) 634 goto out; 635 636 while (widx < words) { 637 u8 write_opcode = NVM_WRITE_OPCODE_SPI; 638 639 ret_val = e1000_ready_nvm_eeprom(hw); 640 if (ret_val) 641 goto release; 642 643 e1000_standby_nvm(hw); 644 645 /* Send the WRITE ENABLE command (8 bit opcode) */ 646 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI, 647 nvm->opcode_bits); 648 649 e1000_standby_nvm(hw); 650 651 /* 652 * Some SPI eeproms use the 8th address bit embedded in the 653 * opcode 654 */ 655 if ((nvm->address_bits == 8) && (offset >= 128)) 656 write_opcode |= NVM_A8_OPCODE_SPI; 657 658 /* Send the Write command (8-bit opcode + addr) */ 659 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits); 660 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2), 661 nvm->address_bits); 662 663 /* Loop to allow for up to whole page write of eeprom */ 664 while (widx < words) { 665 u16 word_out = data[widx]; 666 word_out = (word_out >> 8) | (word_out << 8); 667 e1000_shift_out_eec_bits(hw, word_out, 16); 668 widx++; 669 670 if ((((offset + widx) * 2) % nvm->page_size) == 0) { 671 e1000_standby_nvm(hw); 672 break; 673 } 674 } 675 } 676 677 msec_delay(10); 678 release: 679 nvm->ops.release(hw); 680 681 out: 682 return ret_val; 683 } 684 685 /** 686 * e1000_write_nvm_microwire - Writes EEPROM using microwire 687 * @hw: pointer to the HW structure 688 * @offset: offset within the EEPROM to be written to 689 * @words: number of words to write 690 * @data: 16 bit word(s) to be written to the EEPROM 691 * 692 * Writes data to EEPROM at offset using microwire interface. 693 * 694 * If e1000_update_nvm_checksum is not called after this function , the 695 * EEPROM will most likely contain an invalid checksum. 696 **/ 697 s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, 698 u16 *data) 699 { 700 struct e1000_nvm_info *nvm = &hw->nvm; 701 s32 ret_val; 702 u32 eecd; 703 u16 words_written = 0; 704 u16 widx = 0; 705 706 DEBUGFUNC("e1000_write_nvm_microwire"); 707 708 /* 709 * A check for invalid values: offset too large, too many words, 710 * and not enough words. 711 */ 712 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 713 (words == 0)) { 714 DEBUGOUT("nvm parameter(s) out of bounds\n"); 715 ret_val = -E1000_ERR_NVM; 716 goto out; 717 } 718 719 ret_val = nvm->ops.acquire(hw); 720 if (ret_val) 721 goto out; 722 723 ret_val = e1000_ready_nvm_eeprom(hw); 724 if (ret_val) 725 goto release; 726 727 e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE, 728 (u16)(nvm->opcode_bits + 2)); 729 730 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2)); 731 732 e1000_standby_nvm(hw); 733 734 while (words_written < words) { 735 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE, 736 nvm->opcode_bits); 737 738 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written), 739 nvm->address_bits); 740 741 e1000_shift_out_eec_bits(hw, data[words_written], 16); 742 743 e1000_standby_nvm(hw); 744 745 for (widx = 0; widx < 200; widx++) { 746 eecd = E1000_READ_REG(hw, E1000_EECD); 747 if (eecd & E1000_EECD_DO) 748 break; 749 usec_delay(50); 750 } 751 752 if (widx == 200) { 753 DEBUGOUT("NVM Write did not complete\n"); 754 ret_val = -E1000_ERR_NVM; 755 goto release; 756 } 757 758 e1000_standby_nvm(hw); 759 760 words_written++; 761 } 762 763 e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE, 764 (u16)(nvm->opcode_bits + 2)); 765 766 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2)); 767 768 release: 769 nvm->ops.release(hw); 770 771 out: 772 return ret_val; 773 } 774 775 /** 776 * e1000_read_pba_num_generic - Read device part number 777 * @hw: pointer to the HW structure 778 * @pba_num: pointer to device part number 779 * 780 * Reads the product board assembly (PBA) number from the EEPROM and stores 781 * the value in pba_num. 782 **/ 783 s32 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num) 784 { 785 s32 ret_val; 786 u16 nvm_data; 787 788 DEBUGFUNC("e1000_read_pba_num_generic"); 789 790 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); 791 if (ret_val) { 792 DEBUGOUT("NVM Read Error\n"); 793 goto out; 794 } 795 *pba_num = (u32)(nvm_data << 16); 796 797 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data); 798 if (ret_val) { 799 DEBUGOUT("NVM Read Error\n"); 800 goto out; 801 } 802 *pba_num |= nvm_data; 803 804 out: 805 return ret_val; 806 } 807 808 /** 809 * e1000_read_mac_addr_generic - Read device MAC address 810 * @hw: pointer to the HW structure 811 * 812 * Reads the device MAC address from the EEPROM and stores the value. 813 * Since devices with two ports use the same EEPROM, we increment the 814 * last bit in the MAC address for the second port. 815 **/ 816 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw) 817 { 818 s32 ret_val = E1000_SUCCESS; 819 u16 offset, nvm_data, i; 820 821 DEBUGFUNC("e1000_read_mac_addr"); 822 823 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 824 offset = i >> 1; 825 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 826 if (ret_val) { 827 DEBUGOUT("NVM Read Error\n"); 828 goto out; 829 } 830 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF); 831 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8); 832 } 833 834 /* Flip last bit of mac address if we're on second port */ 835 if (hw->bus.func == E1000_FUNC_1) 836 hw->mac.perm_addr[5] ^= 1; 837 838 for (i = 0; i < ETH_ADDR_LEN; i++) 839 hw->mac.addr[i] = hw->mac.perm_addr[i]; 840 841 out: 842 return ret_val; 843 } 844 845 /** 846 * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum 847 * @hw: pointer to the HW structure 848 * 849 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 850 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 851 **/ 852 s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw) 853 { 854 s32 ret_val = E1000_SUCCESS; 855 u16 checksum = 0; 856 u16 i, nvm_data; 857 858 DEBUGFUNC("e1000_validate_nvm_checksum_generic"); 859 860 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { 861 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 862 if (ret_val) { 863 DEBUGOUT("NVM Read Error\n"); 864 goto out; 865 } 866 checksum += nvm_data; 867 } 868 869 if (checksum != (u16) NVM_SUM) { 870 DEBUGOUT("NVM Checksum Invalid\n"); 871 ret_val = -E1000_ERR_NVM; 872 goto out; 873 } 874 875 out: 876 return ret_val; 877 } 878 879 /** 880 * e1000_update_nvm_checksum_generic - Update EEPROM checksum 881 * @hw: pointer to the HW structure 882 * 883 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 884 * up to the checksum. Then calculates the EEPROM checksum and writes the 885 * value to the EEPROM. 886 **/ 887 s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw) 888 { 889 s32 ret_val; 890 u16 checksum = 0; 891 u16 i, nvm_data; 892 893 DEBUGFUNC("e1000_update_nvm_checksum"); 894 895 for (i = 0; i < NVM_CHECKSUM_REG; i++) { 896 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 897 if (ret_val) { 898 DEBUGOUT("NVM Read Error while updating checksum.\n"); 899 goto out; 900 } 901 checksum += nvm_data; 902 } 903 checksum = (u16) NVM_SUM - checksum; 904 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum); 905 if (ret_val) 906 DEBUGOUT("NVM Write Error while updating checksum.\n"); 907 908 out: 909 return ret_val; 910 } 911 912 /** 913 * e1000_reload_nvm_generic - Reloads EEPROM 914 * @hw: pointer to the HW structure 915 * 916 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the 917 * extended control register. 918 **/ 919 void e1000_reload_nvm_generic(struct e1000_hw *hw) 920 { 921 u32 ctrl_ext; 922 923 DEBUGFUNC("e1000_reload_nvm_generic"); 924 925 usec_delay(10); 926 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 927 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 928 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 929 E1000_WRITE_FLUSH(hw); 930 } 931 932