1 /****************************************************************************** 2 3 Copyright (c) 2001-2019, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "e1000_api.h" 36 37 static void e1000_reload_nvm_generic(struct e1000_hw *hw); 38 39 /** 40 * e1000_init_nvm_ops_generic - Initialize NVM function pointers 41 * @hw: pointer to the HW structure 42 * 43 * Setups up the function pointers to no-op functions 44 **/ 45 void e1000_init_nvm_ops_generic(struct e1000_hw *hw) 46 { 47 struct e1000_nvm_info *nvm = &hw->nvm; 48 DEBUGFUNC("e1000_init_nvm_ops_generic"); 49 50 /* Initialize function pointers */ 51 nvm->ops.init_params = e1000_null_ops_generic; 52 nvm->ops.acquire = e1000_null_ops_generic; 53 nvm->ops.read = e1000_null_read_nvm; 54 nvm->ops.release = e1000_null_nvm_generic; 55 nvm->ops.reload = e1000_reload_nvm_generic; 56 nvm->ops.update = e1000_null_ops_generic; 57 nvm->ops.valid_led_default = e1000_null_led_default; 58 nvm->ops.validate = e1000_null_ops_generic; 59 nvm->ops.write = e1000_null_write_nvm; 60 } 61 62 /** 63 * e1000_null_nvm_read - No-op function, return 0 64 * @hw: pointer to the HW structure 65 * @a: dummy variable 66 * @b: dummy variable 67 * @c: dummy variable 68 **/ 69 s32 e1000_null_read_nvm(struct e1000_hw E1000_UNUSEDARG *hw, 70 u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b, 71 u16 E1000_UNUSEDARG *c) 72 { 73 DEBUGFUNC("e1000_null_read_nvm"); 74 return E1000_SUCCESS; 75 } 76 77 /** 78 * e1000_null_nvm_generic - No-op function, return void 79 * @hw: pointer to the HW structure 80 **/ 81 void e1000_null_nvm_generic(struct e1000_hw E1000_UNUSEDARG *hw) 82 { 83 DEBUGFUNC("e1000_null_nvm_generic"); 84 return; 85 } 86 87 /** 88 * e1000_null_led_default - No-op function, return 0 89 * @hw: pointer to the HW structure 90 * @data: dummy variable 91 **/ 92 s32 e1000_null_led_default(struct e1000_hw E1000_UNUSEDARG *hw, 93 u16 E1000_UNUSEDARG *data) 94 { 95 DEBUGFUNC("e1000_null_led_default"); 96 return E1000_SUCCESS; 97 } 98 99 /** 100 * e1000_null_write_nvm - No-op function, return 0 101 * @hw: pointer to the HW structure 102 * @a: dummy variable 103 * @b: dummy variable 104 * @c: dummy variable 105 **/ 106 s32 e1000_null_write_nvm(struct e1000_hw E1000_UNUSEDARG *hw, 107 u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b, 108 u16 E1000_UNUSEDARG *c) 109 { 110 DEBUGFUNC("e1000_null_write_nvm"); 111 return E1000_SUCCESS; 112 } 113 114 /** 115 * e1000_raise_eec_clk - Raise EEPROM clock 116 * @hw: pointer to the HW structure 117 * @eecd: pointer to the EEPROM 118 * 119 * Enable/Raise the EEPROM clock bit. 120 **/ 121 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd) 122 { 123 *eecd = *eecd | E1000_EECD_SK; 124 E1000_WRITE_REG(hw, E1000_EECD, *eecd); 125 E1000_WRITE_FLUSH(hw); 126 usec_delay(hw->nvm.delay_usec); 127 } 128 129 /** 130 * e1000_lower_eec_clk - Lower EEPROM clock 131 * @hw: pointer to the HW structure 132 * @eecd: pointer to the EEPROM 133 * 134 * Clear/Lower the EEPROM clock bit. 135 **/ 136 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd) 137 { 138 *eecd = *eecd & ~E1000_EECD_SK; 139 E1000_WRITE_REG(hw, E1000_EECD, *eecd); 140 E1000_WRITE_FLUSH(hw); 141 usec_delay(hw->nvm.delay_usec); 142 } 143 144 /** 145 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM 146 * @hw: pointer to the HW structure 147 * @data: data to send to the EEPROM 148 * @count: number of bits to shift out 149 * 150 * We need to shift 'count' bits out to the EEPROM. So, the value in the 151 * "data" parameter will be shifted out to the EEPROM one bit at a time. 152 * In order to do this, "data" must be broken down into bits. 153 **/ 154 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count) 155 { 156 struct e1000_nvm_info *nvm = &hw->nvm; 157 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 158 u32 mask; 159 160 DEBUGFUNC("e1000_shift_out_eec_bits"); 161 162 mask = 0x01 << (count - 1); 163 if (nvm->type == e1000_nvm_eeprom_microwire) 164 eecd &= ~E1000_EECD_DO; 165 else 166 if (nvm->type == e1000_nvm_eeprom_spi) 167 eecd |= E1000_EECD_DO; 168 169 do { 170 eecd &= ~E1000_EECD_DI; 171 172 if (data & mask) 173 eecd |= E1000_EECD_DI; 174 175 E1000_WRITE_REG(hw, E1000_EECD, eecd); 176 E1000_WRITE_FLUSH(hw); 177 178 usec_delay(nvm->delay_usec); 179 180 e1000_raise_eec_clk(hw, &eecd); 181 e1000_lower_eec_clk(hw, &eecd); 182 183 mask >>= 1; 184 } while (mask); 185 186 eecd &= ~E1000_EECD_DI; 187 E1000_WRITE_REG(hw, E1000_EECD, eecd); 188 } 189 190 /** 191 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM 192 * @hw: pointer to the HW structure 193 * @count: number of bits to shift in 194 * 195 * In order to read a register from the EEPROM, we need to shift 'count' bits 196 * in from the EEPROM. Bits are "shifted in" by raising the clock input to 197 * the EEPROM (setting the SK bit), and then reading the value of the data out 198 * "DO" bit. During this "shifting in" process the data in "DI" bit should 199 * always be clear. 200 **/ 201 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count) 202 { 203 u32 eecd; 204 u32 i; 205 u16 data; 206 207 DEBUGFUNC("e1000_shift_in_eec_bits"); 208 209 eecd = E1000_READ_REG(hw, E1000_EECD); 210 211 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 212 data = 0; 213 214 for (i = 0; i < count; i++) { 215 data <<= 1; 216 e1000_raise_eec_clk(hw, &eecd); 217 218 eecd = E1000_READ_REG(hw, E1000_EECD); 219 220 eecd &= ~E1000_EECD_DI; 221 if (eecd & E1000_EECD_DO) 222 data |= 1; 223 224 e1000_lower_eec_clk(hw, &eecd); 225 } 226 227 return data; 228 } 229 230 /** 231 * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion 232 * @hw: pointer to the HW structure 233 * @ee_reg: EEPROM flag for polling 234 * 235 * Polls the EEPROM status bit for either read or write completion based 236 * upon the value of 'ee_reg'. 237 **/ 238 s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) 239 { 240 u32 attempts = 100000; 241 u32 i, reg = 0; 242 243 DEBUGFUNC("e1000_poll_eerd_eewr_done"); 244 245 for (i = 0; i < attempts; i++) { 246 if (ee_reg == E1000_NVM_POLL_READ) 247 reg = E1000_READ_REG(hw, E1000_EERD); 248 else 249 reg = E1000_READ_REG(hw, E1000_EEWR); 250 251 if (reg & E1000_NVM_RW_REG_DONE) 252 return E1000_SUCCESS; 253 254 usec_delay(5); 255 } 256 257 return -E1000_ERR_NVM; 258 } 259 260 /** 261 * e1000_acquire_nvm_generic - Generic request for access to EEPROM 262 * @hw: pointer to the HW structure 263 * 264 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 265 * Return successful if access grant bit set, else clear the request for 266 * EEPROM access and return -E1000_ERR_NVM (-1). 267 **/ 268 s32 e1000_acquire_nvm_generic(struct e1000_hw *hw) 269 { 270 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 271 s32 timeout = E1000_NVM_GRANT_ATTEMPTS; 272 273 DEBUGFUNC("e1000_acquire_nvm_generic"); 274 275 E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ); 276 eecd = E1000_READ_REG(hw, E1000_EECD); 277 278 while (timeout) { 279 if (eecd & E1000_EECD_GNT) 280 break; 281 usec_delay(5); 282 eecd = E1000_READ_REG(hw, E1000_EECD); 283 timeout--; 284 } 285 286 if (!timeout) { 287 eecd &= ~E1000_EECD_REQ; 288 E1000_WRITE_REG(hw, E1000_EECD, eecd); 289 DEBUGOUT("Could not acquire NVM grant\n"); 290 return -E1000_ERR_NVM; 291 } 292 293 return E1000_SUCCESS; 294 } 295 296 /** 297 * e1000_standby_nvm - Return EEPROM to standby state 298 * @hw: pointer to the HW structure 299 * 300 * Return the EEPROM to a standby state. 301 **/ 302 static void e1000_standby_nvm(struct e1000_hw *hw) 303 { 304 struct e1000_nvm_info *nvm = &hw->nvm; 305 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 306 307 DEBUGFUNC("e1000_standby_nvm"); 308 309 if (nvm->type == e1000_nvm_eeprom_microwire) { 310 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 311 E1000_WRITE_REG(hw, E1000_EECD, eecd); 312 E1000_WRITE_FLUSH(hw); 313 usec_delay(nvm->delay_usec); 314 315 e1000_raise_eec_clk(hw, &eecd); 316 317 /* Select EEPROM */ 318 eecd |= E1000_EECD_CS; 319 E1000_WRITE_REG(hw, E1000_EECD, eecd); 320 E1000_WRITE_FLUSH(hw); 321 usec_delay(nvm->delay_usec); 322 323 e1000_lower_eec_clk(hw, &eecd); 324 } else if (nvm->type == e1000_nvm_eeprom_spi) { 325 /* Toggle CS to flush commands */ 326 eecd |= E1000_EECD_CS; 327 E1000_WRITE_REG(hw, E1000_EECD, eecd); 328 E1000_WRITE_FLUSH(hw); 329 usec_delay(nvm->delay_usec); 330 eecd &= ~E1000_EECD_CS; 331 E1000_WRITE_REG(hw, E1000_EECD, eecd); 332 E1000_WRITE_FLUSH(hw); 333 usec_delay(nvm->delay_usec); 334 } 335 } 336 337 /** 338 * e1000_stop_nvm - Terminate EEPROM command 339 * @hw: pointer to the HW structure 340 * 341 * Terminates the current command by inverting the EEPROM's chip select pin. 342 **/ 343 void e1000_stop_nvm(struct e1000_hw *hw) 344 { 345 u32 eecd; 346 347 DEBUGFUNC("e1000_stop_nvm"); 348 349 eecd = E1000_READ_REG(hw, E1000_EECD); 350 if (hw->nvm.type == e1000_nvm_eeprom_spi) { 351 /* Pull CS high */ 352 eecd |= E1000_EECD_CS; 353 e1000_lower_eec_clk(hw, &eecd); 354 } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) { 355 /* CS on Microwire is active-high */ 356 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 357 E1000_WRITE_REG(hw, E1000_EECD, eecd); 358 e1000_raise_eec_clk(hw, &eecd); 359 e1000_lower_eec_clk(hw, &eecd); 360 } 361 } 362 363 /** 364 * e1000_release_nvm_generic - Release exclusive access to EEPROM 365 * @hw: pointer to the HW structure 366 * 367 * Stop any current commands to the EEPROM and clear the EEPROM request bit. 368 **/ 369 void e1000_release_nvm_generic(struct e1000_hw *hw) 370 { 371 u32 eecd; 372 373 DEBUGFUNC("e1000_release_nvm_generic"); 374 375 e1000_stop_nvm(hw); 376 377 eecd = E1000_READ_REG(hw, E1000_EECD); 378 eecd &= ~E1000_EECD_REQ; 379 E1000_WRITE_REG(hw, E1000_EECD, eecd); 380 } 381 382 /** 383 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write 384 * @hw: pointer to the HW structure 385 * 386 * Setups the EEPROM for reading and writing. 387 **/ 388 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw) 389 { 390 struct e1000_nvm_info *nvm = &hw->nvm; 391 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 392 u8 spi_stat_reg; 393 394 DEBUGFUNC("e1000_ready_nvm_eeprom"); 395 396 if (nvm->type == e1000_nvm_eeprom_microwire) { 397 /* Clear SK and DI */ 398 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 399 E1000_WRITE_REG(hw, E1000_EECD, eecd); 400 /* Set CS */ 401 eecd |= E1000_EECD_CS; 402 E1000_WRITE_REG(hw, E1000_EECD, eecd); 403 } else if (nvm->type == e1000_nvm_eeprom_spi) { 404 u16 timeout = NVM_MAX_RETRY_SPI; 405 406 /* Clear SK and CS */ 407 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 408 E1000_WRITE_REG(hw, E1000_EECD, eecd); 409 E1000_WRITE_FLUSH(hw); 410 usec_delay(1); 411 412 /* Read "Status Register" repeatedly until the LSB is cleared. 413 * The EEPROM will signal that the command has been completed 414 * by clearing bit 0 of the internal status register. If it's 415 * not cleared within 'timeout', then error out. 416 */ 417 while (timeout) { 418 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI, 419 hw->nvm.opcode_bits); 420 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8); 421 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI)) 422 break; 423 424 usec_delay(5); 425 e1000_standby_nvm(hw); 426 timeout--; 427 } 428 429 if (!timeout) { 430 DEBUGOUT("SPI NVM Status error\n"); 431 return -E1000_ERR_NVM; 432 } 433 } 434 435 return E1000_SUCCESS; 436 } 437 438 /** 439 * e1000_read_nvm_spi - Read EEPROM's using SPI 440 * @hw: pointer to the HW structure 441 * @offset: offset of word in the EEPROM to read 442 * @words: number of words to read 443 * @data: word read from the EEPROM 444 * 445 * Reads a 16 bit word from the EEPROM. 446 **/ 447 s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 448 { 449 struct e1000_nvm_info *nvm = &hw->nvm; 450 u32 i = 0; 451 s32 ret_val; 452 u16 word_in; 453 u8 read_opcode = NVM_READ_OPCODE_SPI; 454 455 DEBUGFUNC("e1000_read_nvm_spi"); 456 457 /* A check for invalid values: offset too large, too many words, 458 * and not enough words. 459 */ 460 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 461 (words == 0)) { 462 DEBUGOUT("nvm parameter(s) out of bounds\n"); 463 return -E1000_ERR_NVM; 464 } 465 466 ret_val = nvm->ops.acquire(hw); 467 if (ret_val) 468 return ret_val; 469 470 ret_val = e1000_ready_nvm_eeprom(hw); 471 if (ret_val) 472 goto release; 473 474 e1000_standby_nvm(hw); 475 476 if ((nvm->address_bits == 8) && (offset >= 128)) 477 read_opcode |= NVM_A8_OPCODE_SPI; 478 479 /* Send the READ command (opcode + addr) */ 480 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits); 481 e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits); 482 483 /* Read the data. SPI NVMs increment the address with each byte 484 * read and will roll over if reading beyond the end. This allows 485 * us to read the whole NVM from any offset 486 */ 487 for (i = 0; i < words; i++) { 488 word_in = e1000_shift_in_eec_bits(hw, 16); 489 data[i] = (word_in >> 8) | (word_in << 8); 490 } 491 492 release: 493 nvm->ops.release(hw); 494 495 return ret_val; 496 } 497 498 /** 499 * e1000_read_nvm_microwire - Reads EEPROM's using microwire 500 * @hw: pointer to the HW structure 501 * @offset: offset of word in the EEPROM to read 502 * @words: number of words to read 503 * @data: word read from the EEPROM 504 * 505 * Reads a 16 bit word from the EEPROM. 506 **/ 507 s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, 508 u16 *data) 509 { 510 struct e1000_nvm_info *nvm = &hw->nvm; 511 u32 i = 0; 512 s32 ret_val; 513 u8 read_opcode = NVM_READ_OPCODE_MICROWIRE; 514 515 DEBUGFUNC("e1000_read_nvm_microwire"); 516 517 /* A check for invalid values: offset too large, too many words, 518 * and not enough words. 519 */ 520 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 521 (words == 0)) { 522 DEBUGOUT("nvm parameter(s) out of bounds\n"); 523 return -E1000_ERR_NVM; 524 } 525 526 ret_val = nvm->ops.acquire(hw); 527 if (ret_val) 528 return ret_val; 529 530 ret_val = e1000_ready_nvm_eeprom(hw); 531 if (ret_val) 532 goto release; 533 534 for (i = 0; i < words; i++) { 535 /* Send the READ command (opcode + addr) */ 536 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits); 537 e1000_shift_out_eec_bits(hw, (u16)(offset + i), 538 nvm->address_bits); 539 540 /* Read the data. For microwire, each word requires the 541 * overhead of setup and tear-down. 542 */ 543 data[i] = e1000_shift_in_eec_bits(hw, 16); 544 e1000_standby_nvm(hw); 545 } 546 547 release: 548 nvm->ops.release(hw); 549 550 return ret_val; 551 } 552 553 /** 554 * e1000_read_nvm_eerd - Reads EEPROM using EERD register 555 * @hw: pointer to the HW structure 556 * @offset: offset of word in the EEPROM to read 557 * @words: number of words to read 558 * @data: word read from the EEPROM 559 * 560 * Reads a 16 bit word from the EEPROM using the EERD register. 561 **/ 562 s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 563 { 564 struct e1000_nvm_info *nvm = &hw->nvm; 565 u32 i, eerd = 0; 566 s32 ret_val = E1000_SUCCESS; 567 568 DEBUGFUNC("e1000_read_nvm_eerd"); 569 570 /* A check for invalid values: offset too large, too many words, 571 * too many words for the offset, and not enough words. 572 */ 573 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 574 (words == 0)) { 575 DEBUGOUT("nvm parameter(s) out of bounds\n"); 576 return -E1000_ERR_NVM; 577 } 578 579 for (i = 0; i < words; i++) { 580 eerd = ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) + 581 E1000_NVM_RW_REG_START; 582 583 E1000_WRITE_REG(hw, E1000_EERD, eerd); 584 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ); 585 if (ret_val) 586 break; 587 588 data[i] = (E1000_READ_REG(hw, E1000_EERD) >> 589 E1000_NVM_RW_REG_DATA); 590 } 591 592 if (ret_val) 593 DEBUGOUT1("NVM read error: %d\n", ret_val); 594 595 return ret_val; 596 } 597 598 /** 599 * e1000_write_nvm_spi - Write to EEPROM using SPI 600 * @hw: pointer to the HW structure 601 * @offset: offset within the EEPROM to be written to 602 * @words: number of words to write 603 * @data: 16 bit word(s) to be written to the EEPROM 604 * 605 * Writes data to EEPROM at offset using SPI interface. 606 * 607 * If e1000_update_nvm_checksum is not called after this function , the 608 * EEPROM will most likely contain an invalid checksum. 609 **/ 610 s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 611 { 612 struct e1000_nvm_info *nvm = &hw->nvm; 613 s32 ret_val = -E1000_ERR_NVM; 614 u16 widx = 0; 615 616 DEBUGFUNC("e1000_write_nvm_spi"); 617 618 /* A check for invalid values: offset too large, too many words, 619 * and not enough words. 620 */ 621 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 622 (words == 0)) { 623 DEBUGOUT("nvm parameter(s) out of bounds\n"); 624 return -E1000_ERR_NVM; 625 } 626 627 while (widx < words) { 628 u8 write_opcode = NVM_WRITE_OPCODE_SPI; 629 630 ret_val = nvm->ops.acquire(hw); 631 if (ret_val) 632 return ret_val; 633 634 ret_val = e1000_ready_nvm_eeprom(hw); 635 if (ret_val) { 636 nvm->ops.release(hw); 637 return ret_val; 638 } 639 640 e1000_standby_nvm(hw); 641 642 /* Send the WRITE ENABLE command (8 bit opcode) */ 643 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI, 644 nvm->opcode_bits); 645 646 e1000_standby_nvm(hw); 647 648 /* Some SPI eeproms use the 8th address bit embedded in the 649 * opcode 650 */ 651 if ((nvm->address_bits == 8) && (offset >= 128)) 652 write_opcode |= NVM_A8_OPCODE_SPI; 653 654 /* Send the Write command (8-bit opcode + addr) */ 655 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits); 656 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2), 657 nvm->address_bits); 658 659 /* Loop to allow for up to whole page write of eeprom */ 660 while (widx < words) { 661 u16 word_out = data[widx]; 662 word_out = (word_out >> 8) | (word_out << 8); 663 e1000_shift_out_eec_bits(hw, word_out, 16); 664 widx++; 665 666 if ((((offset + widx) * 2) % nvm->page_size) == 0) { 667 e1000_standby_nvm(hw); 668 break; 669 } 670 } 671 msec_delay(10); 672 nvm->ops.release(hw); 673 } 674 675 return ret_val; 676 } 677 678 /** 679 * e1000_write_nvm_microwire - Writes EEPROM using microwire 680 * @hw: pointer to the HW structure 681 * @offset: offset within the EEPROM to be written to 682 * @words: number of words to write 683 * @data: 16 bit word(s) to be written to the EEPROM 684 * 685 * Writes data to EEPROM at offset using microwire interface. 686 * 687 * If e1000_update_nvm_checksum is not called after this function , the 688 * EEPROM will most likely contain an invalid checksum. 689 **/ 690 s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, 691 u16 *data) 692 { 693 struct e1000_nvm_info *nvm = &hw->nvm; 694 s32 ret_val; 695 u32 eecd; 696 u16 words_written = 0; 697 u16 widx = 0; 698 699 DEBUGFUNC("e1000_write_nvm_microwire"); 700 701 /* A check for invalid values: offset too large, too many words, 702 * and not enough words. 703 */ 704 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 705 (words == 0)) { 706 DEBUGOUT("nvm parameter(s) out of bounds\n"); 707 return -E1000_ERR_NVM; 708 } 709 710 ret_val = nvm->ops.acquire(hw); 711 if (ret_val) 712 return ret_val; 713 714 ret_val = e1000_ready_nvm_eeprom(hw); 715 if (ret_val) 716 goto release; 717 718 e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE, 719 (u16)(nvm->opcode_bits + 2)); 720 721 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2)); 722 723 e1000_standby_nvm(hw); 724 725 while (words_written < words) { 726 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE, 727 nvm->opcode_bits); 728 729 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written), 730 nvm->address_bits); 731 732 e1000_shift_out_eec_bits(hw, data[words_written], 16); 733 734 e1000_standby_nvm(hw); 735 736 for (widx = 0; widx < 200; widx++) { 737 eecd = E1000_READ_REG(hw, E1000_EECD); 738 if (eecd & E1000_EECD_DO) 739 break; 740 usec_delay(50); 741 } 742 743 if (widx == 200) { 744 DEBUGOUT("NVM Write did not complete\n"); 745 ret_val = -E1000_ERR_NVM; 746 goto release; 747 } 748 749 e1000_standby_nvm(hw); 750 751 words_written++; 752 } 753 754 e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE, 755 (u16)(nvm->opcode_bits + 2)); 756 757 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2)); 758 759 release: 760 nvm->ops.release(hw); 761 762 return ret_val; 763 } 764 765 /** 766 * e1000_read_pba_string_generic - Read device part number 767 * @hw: pointer to the HW structure 768 * @pba_num: pointer to device part number 769 * @pba_num_size: size of part number buffer 770 * 771 * Reads the product board assembly (PBA) number from the EEPROM and stores 772 * the value in pba_num. 773 **/ 774 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num, 775 u32 pba_num_size) 776 { 777 s32 ret_val; 778 u16 nvm_data; 779 u16 pba_ptr; 780 u16 offset; 781 u16 length; 782 783 DEBUGFUNC("e1000_read_pba_string_generic"); 784 785 if ((hw->mac.type >= e1000_i210) && 786 !e1000_get_flash_presence_i210(hw)) { 787 DEBUGOUT("Flashless no PBA string\n"); 788 return -E1000_ERR_NVM_PBA_SECTION; 789 } 790 791 if (pba_num == NULL) { 792 DEBUGOUT("PBA string buffer was null\n"); 793 return -E1000_ERR_INVALID_ARGUMENT; 794 } 795 796 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); 797 if (ret_val) { 798 DEBUGOUT("NVM Read Error\n"); 799 return ret_val; 800 } 801 802 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr); 803 if (ret_val) { 804 DEBUGOUT("NVM Read Error\n"); 805 return ret_val; 806 } 807 808 /* if nvm_data is not ptr guard the PBA must be in legacy format which 809 * means pba_ptr is actually our second data word for the PBA number 810 * and we can decode it into an ascii string 811 */ 812 if (nvm_data != NVM_PBA_PTR_GUARD) { 813 DEBUGOUT("NVM PBA number is not stored as string\n"); 814 815 /* make sure callers buffer is big enough to store the PBA */ 816 if (pba_num_size < E1000_PBANUM_LENGTH) { 817 DEBUGOUT("PBA string buffer too small\n"); 818 return E1000_ERR_NO_SPACE; 819 } 820 821 /* extract hex string from data and pba_ptr */ 822 pba_num[0] = (nvm_data >> 12) & 0xF; 823 pba_num[1] = (nvm_data >> 8) & 0xF; 824 pba_num[2] = (nvm_data >> 4) & 0xF; 825 pba_num[3] = nvm_data & 0xF; 826 pba_num[4] = (pba_ptr >> 12) & 0xF; 827 pba_num[5] = (pba_ptr >> 8) & 0xF; 828 pba_num[6] = '-'; 829 pba_num[7] = 0; 830 pba_num[8] = (pba_ptr >> 4) & 0xF; 831 pba_num[9] = pba_ptr & 0xF; 832 833 /* put a null character on the end of our string */ 834 pba_num[10] = '\0'; 835 836 /* switch all the data but the '-' to hex char */ 837 for (offset = 0; offset < 10; offset++) { 838 if (pba_num[offset] < 0xA) 839 pba_num[offset] += '0'; 840 else if (pba_num[offset] < 0x10) 841 pba_num[offset] += 'A' - 0xA; 842 } 843 844 return E1000_SUCCESS; 845 } 846 847 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length); 848 if (ret_val) { 849 DEBUGOUT("NVM Read Error\n"); 850 return ret_val; 851 } 852 853 if (length == 0xFFFF || length == 0) { 854 DEBUGOUT("NVM PBA number section invalid length\n"); 855 return -E1000_ERR_NVM_PBA_SECTION; 856 } 857 /* check if pba_num buffer is big enough */ 858 if (pba_num_size < (((u32)length * 2) - 1)) { 859 DEBUGOUT("PBA string buffer too small\n"); 860 return -E1000_ERR_NO_SPACE; 861 } 862 863 /* trim pba length from start of string */ 864 pba_ptr++; 865 length--; 866 867 for (offset = 0; offset < length; offset++) { 868 ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data); 869 if (ret_val) { 870 DEBUGOUT("NVM Read Error\n"); 871 return ret_val; 872 } 873 pba_num[offset * 2] = (u8)(nvm_data >> 8); 874 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF); 875 } 876 pba_num[offset * 2] = '\0'; 877 878 return E1000_SUCCESS; 879 } 880 881 /** 882 * e1000_read_pba_length_generic - Read device part number length 883 * @hw: pointer to the HW structure 884 * @pba_num_size: size of part number buffer 885 * 886 * Reads the product board assembly (PBA) number length from the EEPROM and 887 * stores the value in pba_num_size. 888 **/ 889 s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size) 890 { 891 s32 ret_val; 892 u16 nvm_data; 893 u16 pba_ptr; 894 u16 length; 895 896 DEBUGFUNC("e1000_read_pba_length_generic"); 897 898 if (pba_num_size == NULL) { 899 DEBUGOUT("PBA buffer size was null\n"); 900 return -E1000_ERR_INVALID_ARGUMENT; 901 } 902 903 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); 904 if (ret_val) { 905 DEBUGOUT("NVM Read Error\n"); 906 return ret_val; 907 } 908 909 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr); 910 if (ret_val) { 911 DEBUGOUT("NVM Read Error\n"); 912 return ret_val; 913 } 914 915 /* if data is not ptr guard the PBA must be in legacy format */ 916 if (nvm_data != NVM_PBA_PTR_GUARD) { 917 *pba_num_size = E1000_PBANUM_LENGTH; 918 return E1000_SUCCESS; 919 } 920 921 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length); 922 if (ret_val) { 923 DEBUGOUT("NVM Read Error\n"); 924 return ret_val; 925 } 926 927 if (length == 0xFFFF || length == 0) { 928 DEBUGOUT("NVM PBA number section invalid length\n"); 929 return -E1000_ERR_NVM_PBA_SECTION; 930 } 931 932 /* Convert from length in u16 values to u8 chars, add 1 for NULL, 933 * and subtract 2 because length field is included in length. 934 */ 935 *pba_num_size = ((u32)length * 2) - 1; 936 937 return E1000_SUCCESS; 938 } 939 940 941 /** 942 * e1000_read_pba_raw 943 * @hw: pointer to the HW structure 944 * @eeprom_buf: optional pointer to EEPROM image 945 * @eeprom_buf_size: size of EEPROM image in words 946 * @max_pba_block_size: PBA block size limit 947 * @pba: pointer to output PBA structure 948 * 949 * Reads PBA from EEPROM image when eeprom_buf is not NULL. 950 * Reads PBA from physical EEPROM device when eeprom_buf is NULL. 951 * 952 **/ 953 s32 e1000_read_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf, 954 u32 eeprom_buf_size, u16 max_pba_block_size, 955 struct e1000_pba *pba) 956 { 957 s32 ret_val; 958 u16 pba_block_size; 959 960 if (pba == NULL) 961 return -E1000_ERR_PARAM; 962 963 if (eeprom_buf == NULL) { 964 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2, 965 &pba->word[0]); 966 if (ret_val) 967 return ret_val; 968 } else { 969 if (eeprom_buf_size > NVM_PBA_OFFSET_1) { 970 pba->word[0] = eeprom_buf[NVM_PBA_OFFSET_0]; 971 pba->word[1] = eeprom_buf[NVM_PBA_OFFSET_1]; 972 } else { 973 return -E1000_ERR_PARAM; 974 } 975 } 976 977 if (pba->word[0] == NVM_PBA_PTR_GUARD) { 978 if (pba->pba_block == NULL) 979 return -E1000_ERR_PARAM; 980 981 ret_val = e1000_get_pba_block_size(hw, eeprom_buf, 982 eeprom_buf_size, 983 &pba_block_size); 984 if (ret_val) 985 return ret_val; 986 987 if (pba_block_size > max_pba_block_size) 988 return -E1000_ERR_PARAM; 989 990 if (eeprom_buf == NULL) { 991 ret_val = e1000_read_nvm(hw, pba->word[1], 992 pba_block_size, 993 pba->pba_block); 994 if (ret_val) 995 return ret_val; 996 } else { 997 if (eeprom_buf_size > (u32)(pba->word[1] + 998 pba_block_size)) { 999 memcpy(pba->pba_block, 1000 &eeprom_buf[pba->word[1]], 1001 pba_block_size * sizeof(u16)); 1002 } else { 1003 return -E1000_ERR_PARAM; 1004 } 1005 } 1006 } 1007 1008 return E1000_SUCCESS; 1009 } 1010 1011 /** 1012 * e1000_write_pba_raw 1013 * @hw: pointer to the HW structure 1014 * @eeprom_buf: optional pointer to EEPROM image 1015 * @eeprom_buf_size: size of EEPROM image in words 1016 * @pba: pointer to PBA structure 1017 * 1018 * Writes PBA to EEPROM image when eeprom_buf is not NULL. 1019 * Writes PBA to physical EEPROM device when eeprom_buf is NULL. 1020 * 1021 **/ 1022 s32 e1000_write_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf, 1023 u32 eeprom_buf_size, struct e1000_pba *pba) 1024 { 1025 s32 ret_val; 1026 1027 if (pba == NULL) 1028 return -E1000_ERR_PARAM; 1029 1030 if (eeprom_buf == NULL) { 1031 ret_val = e1000_write_nvm(hw, NVM_PBA_OFFSET_0, 2, 1032 &pba->word[0]); 1033 if (ret_val) 1034 return ret_val; 1035 } else { 1036 if (eeprom_buf_size > NVM_PBA_OFFSET_1) { 1037 eeprom_buf[NVM_PBA_OFFSET_0] = pba->word[0]; 1038 eeprom_buf[NVM_PBA_OFFSET_1] = pba->word[1]; 1039 } else { 1040 return -E1000_ERR_PARAM; 1041 } 1042 } 1043 1044 if (pba->word[0] == NVM_PBA_PTR_GUARD) { 1045 if (pba->pba_block == NULL) 1046 return -E1000_ERR_PARAM; 1047 1048 if (eeprom_buf == NULL) { 1049 ret_val = e1000_write_nvm(hw, pba->word[1], 1050 pba->pba_block[0], 1051 pba->pba_block); 1052 if (ret_val) 1053 return ret_val; 1054 } else { 1055 if (eeprom_buf_size > (u32)(pba->word[1] + 1056 pba->pba_block[0])) { 1057 memcpy(&eeprom_buf[pba->word[1]], 1058 pba->pba_block, 1059 pba->pba_block[0] * sizeof(u16)); 1060 } else { 1061 return -E1000_ERR_PARAM; 1062 } 1063 } 1064 } 1065 1066 return E1000_SUCCESS; 1067 } 1068 1069 /** 1070 * e1000_get_pba_block_size 1071 * @hw: pointer to the HW structure 1072 * @eeprom_buf: optional pointer to EEPROM image 1073 * @eeprom_buf_size: size of EEPROM image in words 1074 * @pba_data_size: pointer to output variable 1075 * 1076 * Returns the size of the PBA block in words. Function operates on EEPROM 1077 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical 1078 * EEPROM device. 1079 * 1080 **/ 1081 s32 e1000_get_pba_block_size(struct e1000_hw *hw, u16 *eeprom_buf, 1082 u32 eeprom_buf_size, u16 *pba_block_size) 1083 { 1084 s32 ret_val; 1085 u16 pba_word[2]; 1086 u16 length; 1087 1088 DEBUGFUNC("e1000_get_pba_block_size"); 1089 1090 if (eeprom_buf == NULL) { 1091 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2, &pba_word[0]); 1092 if (ret_val) 1093 return ret_val; 1094 } else { 1095 if (eeprom_buf_size > NVM_PBA_OFFSET_1) { 1096 pba_word[0] = eeprom_buf[NVM_PBA_OFFSET_0]; 1097 pba_word[1] = eeprom_buf[NVM_PBA_OFFSET_1]; 1098 } else { 1099 return -E1000_ERR_PARAM; 1100 } 1101 } 1102 1103 if (pba_word[0] == NVM_PBA_PTR_GUARD) { 1104 if (eeprom_buf == NULL) { 1105 ret_val = e1000_read_nvm(hw, pba_word[1] + 0, 1, 1106 &length); 1107 if (ret_val) 1108 return ret_val; 1109 } else { 1110 if (eeprom_buf_size > pba_word[1]) 1111 length = eeprom_buf[pba_word[1] + 0]; 1112 else 1113 return -E1000_ERR_PARAM; 1114 } 1115 1116 if (length == 0xFFFF || length == 0) 1117 return -E1000_ERR_NVM_PBA_SECTION; 1118 } else { 1119 /* PBA number in legacy format, there is no PBA Block. */ 1120 length = 0; 1121 } 1122 1123 if (pba_block_size != NULL) 1124 *pba_block_size = length; 1125 1126 return E1000_SUCCESS; 1127 } 1128 1129 /** 1130 * e1000_read_mac_addr_generic - Read device MAC address 1131 * @hw: pointer to the HW structure 1132 * 1133 * Reads the device MAC address from the EEPROM and stores the value. 1134 * Since devices with two ports use the same EEPROM, we increment the 1135 * last bit in the MAC address for the second port. 1136 **/ 1137 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw) 1138 { 1139 u32 rar_high; 1140 u32 rar_low; 1141 u16 i; 1142 1143 rar_high = E1000_READ_REG(hw, E1000_RAH(0)); 1144 rar_low = E1000_READ_REG(hw, E1000_RAL(0)); 1145 1146 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++) 1147 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8)); 1148 1149 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++) 1150 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8)); 1151 1152 for (i = 0; i < ETH_ADDR_LEN; i++) 1153 hw->mac.addr[i] = hw->mac.perm_addr[i]; 1154 1155 return E1000_SUCCESS; 1156 } 1157 1158 /** 1159 * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum 1160 * @hw: pointer to the HW structure 1161 * 1162 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 1163 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 1164 **/ 1165 s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw) 1166 { 1167 s32 ret_val; 1168 u16 checksum = 0; 1169 u16 i, nvm_data; 1170 1171 DEBUGFUNC("e1000_validate_nvm_checksum_generic"); 1172 1173 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { 1174 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 1175 if (ret_val) { 1176 DEBUGOUT("NVM Read Error\n"); 1177 return ret_val; 1178 } 1179 checksum += nvm_data; 1180 } 1181 1182 if (checksum != (u16) NVM_SUM) { 1183 DEBUGOUT("NVM Checksum Invalid\n"); 1184 return -E1000_ERR_NVM; 1185 } 1186 1187 return E1000_SUCCESS; 1188 } 1189 1190 /** 1191 * e1000_update_nvm_checksum_generic - Update EEPROM checksum 1192 * @hw: pointer to the HW structure 1193 * 1194 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 1195 * up to the checksum. Then calculates the EEPROM checksum and writes the 1196 * value to the EEPROM. 1197 **/ 1198 s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw) 1199 { 1200 s32 ret_val; 1201 u16 checksum = 0; 1202 u16 i, nvm_data; 1203 1204 DEBUGFUNC("e1000_update_nvm_checksum"); 1205 1206 for (i = 0; i < NVM_CHECKSUM_REG; i++) { 1207 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 1208 if (ret_val) { 1209 DEBUGOUT("NVM Read Error while updating checksum.\n"); 1210 return ret_val; 1211 } 1212 checksum += nvm_data; 1213 } 1214 checksum = (u16) NVM_SUM - checksum; 1215 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum); 1216 if (ret_val) 1217 DEBUGOUT("NVM Write Error while updating checksum.\n"); 1218 1219 return ret_val; 1220 } 1221 1222 /** 1223 * e1000_reload_nvm_generic - Reloads EEPROM 1224 * @hw: pointer to the HW structure 1225 * 1226 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the 1227 * extended control register. 1228 **/ 1229 static void e1000_reload_nvm_generic(struct e1000_hw *hw) 1230 { 1231 u32 ctrl_ext; 1232 1233 DEBUGFUNC("e1000_reload_nvm_generic"); 1234 1235 usec_delay(10); 1236 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1237 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1238 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1239 E1000_WRITE_FLUSH(hw); 1240 } 1241 1242 /** 1243 * e1000_get_fw_version - Get firmware version information 1244 * @hw: pointer to the HW structure 1245 * @fw_vers: pointer to output version structure 1246 * 1247 * unsupported/not present features return 0 in version structure 1248 **/ 1249 void e1000_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers) 1250 { 1251 u16 eeprom_verh, eeprom_verl, etrack_test, fw_version; 1252 u8 q, hval, rem, result; 1253 u16 comb_verh, comb_verl, comb_offset; 1254 1255 memset(fw_vers, 0, sizeof(struct e1000_fw_version)); 1256 1257 /* basic eeprom version numbers, bits used vary by part and by tool 1258 * used to create the nvm images */ 1259 /* Check which data format we have */ 1260 switch (hw->mac.type) { 1261 case e1000_i211: 1262 e1000_read_invm_version(hw, fw_vers); 1263 return; 1264 case e1000_82575: 1265 case e1000_82576: 1266 case e1000_82580: 1267 case e1000_i354: 1268 hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test); 1269 /* Use this format, unless EETRACK ID exists, 1270 * then use alternate format 1271 */ 1272 if ((etrack_test & NVM_MAJOR_MASK) != NVM_ETRACK_VALID) { 1273 hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version); 1274 fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK) 1275 >> NVM_MAJOR_SHIFT; 1276 fw_vers->eep_minor = (fw_version & NVM_MINOR_MASK) 1277 >> NVM_MINOR_SHIFT; 1278 fw_vers->eep_build = (fw_version & NVM_IMAGE_ID_MASK); 1279 goto etrack_id; 1280 } 1281 break; 1282 case e1000_i210: 1283 if (!(e1000_get_flash_presence_i210(hw))) { 1284 e1000_read_invm_version(hw, fw_vers); 1285 return; 1286 } 1287 /* fall through */ 1288 case e1000_i350: 1289 hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test); 1290 /* find combo image version */ 1291 hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset); 1292 if ((comb_offset != 0x0) && 1293 (comb_offset != NVM_VER_INVALID)) { 1294 1295 hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset 1296 + 1), 1, &comb_verh); 1297 hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset), 1298 1, &comb_verl); 1299 1300 /* get Option Rom version if it exists and is valid */ 1301 if ((comb_verh && comb_verl) && 1302 ((comb_verh != NVM_VER_INVALID) && 1303 (comb_verl != NVM_VER_INVALID))) { 1304 1305 fw_vers->or_valid = TRUE; 1306 fw_vers->or_major = 1307 comb_verl >> NVM_COMB_VER_SHFT; 1308 fw_vers->or_build = 1309 (comb_verl << NVM_COMB_VER_SHFT) 1310 | (comb_verh >> NVM_COMB_VER_SHFT); 1311 fw_vers->or_patch = 1312 comb_verh & NVM_COMB_VER_MASK; 1313 } 1314 } 1315 break; 1316 default: 1317 hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test); 1318 return; 1319 } 1320 hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version); 1321 fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK) 1322 >> NVM_MAJOR_SHIFT; 1323 1324 /* check for old style version format in newer images*/ 1325 if ((fw_version & NVM_NEW_DEC_MASK) == 0x0) { 1326 eeprom_verl = (fw_version & NVM_COMB_VER_MASK); 1327 } else { 1328 eeprom_verl = (fw_version & NVM_MINOR_MASK) 1329 >> NVM_MINOR_SHIFT; 1330 } 1331 /* Convert minor value to hex before assigning to output struct 1332 * Val to be converted will not be higher than 99, per tool output 1333 */ 1334 q = eeprom_verl / NVM_HEX_CONV; 1335 hval = q * NVM_HEX_TENS; 1336 rem = eeprom_verl % NVM_HEX_CONV; 1337 result = hval + rem; 1338 fw_vers->eep_minor = result; 1339 1340 etrack_id: 1341 if ((etrack_test & NVM_MAJOR_MASK) == NVM_ETRACK_VALID) { 1342 hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verl); 1343 hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verh); 1344 fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT) 1345 | eeprom_verl; 1346 } else if ((etrack_test & NVM_ETRACK_VALID) == 0) { 1347 hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verh); 1348 hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verl); 1349 fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT) | 1350 eeprom_verl; 1351 } 1352 } 1353 1354