1 /****************************************************************************** 2 3 Copyright (c) 2001-2014, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 34 #include <sys/param.h> 35 #include <sys/sysctl.h> 36 #include <net/if_var.h> 37 #include <net/if_media.h> 38 39 #include "e1000_api.h" 40 #include "e1000_dragonfly.h" 41 42 /* 43 * NOTE: the following routines using the e1000 44 * naming style are provided to the shared 45 * code but are OS specific 46 */ 47 48 void 49 e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) 50 { 51 pci_write_config(((struct e1000_osdep *)hw->back)->dev, reg, *value, 2); 52 } 53 54 void 55 e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) 56 { 57 *value = pci_read_config(((struct e1000_osdep *)hw->back)->dev, reg, 2); 58 } 59 60 void 61 e1000_pci_set_mwi(struct e1000_hw *hw) 62 { 63 pci_write_config(((struct e1000_osdep *)hw->back)->dev, PCIR_COMMAND, 64 (hw->bus.pci_cmd_word | CMD_MEM_WRT_INVALIDATE), 2); 65 } 66 67 void 68 e1000_pci_clear_mwi(struct e1000_hw *hw) 69 { 70 pci_write_config(((struct e1000_osdep *)hw->back)->dev, PCIR_COMMAND, 71 (hw->bus.pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE), 2); 72 } 73 74 /* 75 * Read the PCI Express capabilities 76 */ 77 int32_t 78 e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) 79 { 80 device_t dev = ((struct e1000_osdep *)hw->back)->dev; 81 uint8_t pcie_ptr; 82 83 pcie_ptr = pci_get_pciecap_ptr(dev); 84 if (pcie_ptr == 0) 85 return E1000_NOT_IMPLEMENTED; 86 87 *value = pci_read_config(dev, pcie_ptr + reg, 2); 88 return E1000_SUCCESS; 89 } 90 91 int32_t 92 e1000_write_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) 93 { 94 device_t dev = ((struct e1000_osdep *)hw->back)->dev; 95 uint8_t pcie_ptr; 96 97 pcie_ptr = pci_get_pciecap_ptr(dev); 98 if (pcie_ptr == 0) 99 return E1000_NOT_IMPLEMENTED; 100 101 pci_write_config(dev, pcie_ptr + reg, *value, 2); 102 return E1000_SUCCESS; 103 } 104 105 void 106 e1000_fc2str(enum e1000_fc_mode fc, char *str, int len) 107 { 108 const char *fc_str = IFM_ETH_FC_NONE; 109 110 switch (fc) { 111 case e1000_fc_full: 112 fc_str = IFM_ETH_FC_FULL; 113 break; 114 115 case e1000_fc_rx_pause: 116 fc_str = IFM_ETH_FC_RXPAUSE; 117 break; 118 119 case e1000_fc_tx_pause: 120 fc_str = IFM_ETH_FC_TXPAUSE; 121 break; 122 123 default: 124 break; 125 } 126 strlcpy(str, fc_str, len); 127 } 128 129 enum e1000_fc_mode 130 e1000_ifmedia2fc(int ifm) 131 { 132 int fc_opt = ifm & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE); 133 134 switch (fc_opt) { 135 case (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE): 136 return e1000_fc_full; 137 138 case IFM_ETH_RXPAUSE: 139 return e1000_fc_rx_pause; 140 141 case IFM_ETH_TXPAUSE: 142 return e1000_fc_tx_pause; 143 144 default: 145 return e1000_fc_none; 146 } 147 } 148 149 int 150 e1000_fc2ifmedia(enum e1000_fc_mode fc) 151 { 152 switch (fc) { 153 case e1000_fc_full: 154 return (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE); 155 156 case e1000_fc_rx_pause: 157 return IFM_ETH_RXPAUSE; 158 159 case e1000_fc_tx_pause: 160 return IFM_ETH_TXPAUSE; 161 162 default: 163 return 0; 164 } 165 } 166 167 void 168 e1000_force_flowctrl(struct e1000_hw *hw, int ifm) 169 { 170 enum e1000_fc_mode fc; 171 172 fc = e1000_ifmedia2fc(ifm); 173 if (hw->fc.current_mode != fc) { 174 hw->fc.requested_mode = fc; 175 hw->fc.current_mode = fc; 176 e1000_force_mac_fc(hw); 177 } 178 } 179 180 /* Module glue */ 181 static moduledata_t ig_hal_mod = { "ig_hal" }; 182 DECLARE_MODULE(ig_hal, ig_hal_mod, SI_SUB_DRIVERS, SI_ORDER_MIDDLE); 183 MODULE_VERSION(ig_hal, 1); 184