1 /****************************************************************************** 2 3 Copyright (c) 2001-2014, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 34 #ifndef _DRAGONFLY_OS_H_ 35 #define _DRAGONFLY_OS_H_ 36 37 #include <sys/param.h> 38 #include <sys/bus.h> 39 #include <sys/kernel.h> 40 #include <sys/systm.h> 41 42 #include <bus/pci/pcivar.h> 43 #include <bus/pci/pcireg.h> 44 45 #define usec_delay(x) DELAY(x) 46 #define usec_delay_irq usec_delay 47 #define msec_delay(x) DELAY(1000*(x)) 48 /* TODO: Should we be paranoid about delaying in interrupt context? */ 49 #define msec_delay_irq(x) DELAY(1000*(x)) 50 51 extern int e1000_debug; 52 53 #define DEBUGPRINT(S, args...) \ 54 do { \ 55 if (e1000_debug) \ 56 kprintf(S, ##args); \ 57 } while (0) 58 #define DEBUGFUNC(F) DEBUGOUT(F) 59 #define DEBUGOUT(S) DEBUGPRINT(S) 60 #define DEBUGOUT1(S,A) DEBUGPRINT(S, A) 61 #define DEBUGOUT2(S,A,B) DEBUGPRINT(S, A, B) 62 #define DEBUGOUT3(S,A,B,C) DEBUGPRINT(S, A, B, C) 63 #define DEBUGOUT7(S,A,B,C,D,E,F,G) DEBUGPRINT(S, A, B, C, D, E, F, G) 64 65 #define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */ 66 #define PCI_COMMAND_REGISTER PCIR_COMMAND 67 68 /* 69 * These typedefs are necessary due to the new 70 * shared code, they are native to Linux. 71 */ 72 typedef uint64_t u64; 73 typedef uint32_t u32; 74 typedef uint16_t u16; 75 typedef uint8_t u8; 76 typedef int64_t s64; 77 typedef int32_t s32; 78 typedef int16_t s16; 79 typedef int8_t s8; 80 typedef boolean_t bool; 81 82 #define __le16 u16 83 #define __le32 u32 84 #define __le64 u64 85 86 struct e1000_osdep { 87 bus_space_tag_t mem_bus_space_tag; 88 bus_space_handle_t mem_bus_space_handle; 89 bus_space_tag_t io_bus_space_tag; 90 bus_space_handle_t io_bus_space_handle; 91 bus_space_tag_t flash_bus_space_tag; 92 bus_space_handle_t flash_bus_space_handle; 93 device_t dev; 94 }; 95 96 #define E1000_REGISTER(hw, reg) (((hw)->mac.type >= e1000_82543) \ 97 ? reg : e1000_translate_register_82542(reg)) 98 99 #define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, E1000_STATUS) 100 101 /* Read from an absolute offset in the adapter's memory space */ 102 #define E1000_READ_OFFSET(hw, offset) \ 103 bus_space_read_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ 104 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, offset) 105 106 /* Write to an absolute offset in the adapter's memory space */ 107 #define E1000_WRITE_OFFSET(hw, offset, value) \ 108 bus_space_write_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ 109 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, offset, value) 110 111 /* Register READ/WRITE macros */ 112 113 #define E1000_READ_REG(hw, reg) \ 114 bus_space_read_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ 115 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \ 116 E1000_REGISTER(hw, reg)) 117 118 #define E1000_READ_REG16(hw, reg) \ 119 bus_space_read_2(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ 120 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \ 121 E1000_REGISTER(hw, reg)) 122 123 #define E1000_WRITE_REG(hw, reg, value) \ 124 bus_space_write_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ 125 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \ 126 E1000_REGISTER(hw, reg), value) 127 128 #define E1000_WRITE_REG16(hw, reg, value) \ 129 bus_space_write_2(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ 130 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \ 131 E1000_REGISTER(hw, reg), value) 132 133 #define E1000_READ_REG_ARRAY(hw, reg, index) \ 134 bus_space_read_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ 135 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \ 136 E1000_REGISTER(hw, reg) + ((index)<< 2)) 137 138 #define E1000_WRITE_REG_ARRAY(hw, reg, index, value) \ 139 bus_space_write_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ 140 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \ 141 E1000_REGISTER(hw, reg) + ((index)<< 2), value) 142 143 #define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY 144 #define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY 145 146 #define E1000_READ_REG_ARRAY_BYTE(hw, reg, index) \ 147 bus_space_read_1(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ 148 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \ 149 E1000_REGISTER(hw, reg) + index) 150 151 #define E1000_WRITE_REG_ARRAY_BYTE(hw, reg, index, value) \ 152 bus_space_write_1(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ 153 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \ 154 E1000_REGISTER(hw, reg) + index, value) 155 156 #define E1000_WRITE_REG_ARRAY_WORD(hw, reg, index, value) \ 157 bus_space_write_2(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ 158 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \ 159 E1000_REGISTER(hw, reg) + (index << 1), value) 160 161 #define E1000_WRITE_REG_IO(hw, reg, value) do {\ 162 bus_space_write_4(((struct e1000_osdep *)(hw)->back)->io_bus_space_tag, \ 163 ((struct e1000_osdep *)(hw)->back)->io_bus_space_handle, \ 164 (hw)->io_base, reg); \ 165 bus_space_write_4(((struct e1000_osdep *)(hw)->back)->io_bus_space_tag, \ 166 ((struct e1000_osdep *)(hw)->back)->io_bus_space_handle, \ 167 (hw)->io_base + 4, value); } while (0) 168 169 #define E1000_READ_FLASH_REG(hw, reg) \ 170 (((hw)->mac.type == e1000_pch_spt) ? E1000_READ_REG(hw, (reg) + 0xE000): \ 171 bus_space_read_4(((struct e1000_osdep *)(hw)->back)->flash_bus_space_tag, \ 172 ((struct e1000_osdep *)(hw)->back)->flash_bus_space_handle, reg)) 173 174 #define E1000_READ_FLASH_REG16(hw, reg) \ 175 (((hw)->mac.type == e1000_pch_spt) ? E1000_READ_REG16(hw, (reg) + 0xE000): \ 176 bus_space_read_2(((struct e1000_osdep *)(hw)->back)->flash_bus_space_tag, \ 177 ((struct e1000_osdep *)(hw)->back)->flash_bus_space_handle, reg)) 178 179 #define E1000_WRITE_FLASH_REG(hw, reg, value) \ 180 (((hw)->mac.type == e1000_pch_spt) ? E1000_WRITE_REG(hw, (reg) + 0xE000, value): \ 181 bus_space_write_4(((struct e1000_osdep *)(hw)->back)->flash_bus_space_tag, \ 182 ((struct e1000_osdep *)(hw)->back)->flash_bus_space_handle, reg, value)) 183 184 #define E1000_WRITE_FLASH_REG16(hw, reg, value) \ 185 (((hw)->mac.type == e1000_pch_spt) ? E1000_WRITE_REG16(hw, (reg) + 0xE000, value): \ 186 bus_space_write_2(((struct e1000_osdep *)(hw)->back)->flash_bus_space_tag, \ 187 ((struct e1000_osdep *)(hw)->back)->flash_bus_space_handle, reg, value)) 188 189 #endif /* _DRAGONFLY_OS_H_ */ 190