1 /****************************************************************************** 2 3 Copyright (c) 2001-2014, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 34 #ifndef _DRAGONFLY_OS_H_ 35 #define _DRAGONFLY_OS_H_ 36 37 #include <sys/param.h> 38 #include <sys/bus.h> 39 #include <sys/kernel.h> 40 #include <sys/systm.h> 41 42 #include <bus/pci/pcivar.h> 43 #include <bus/pci/pcireg.h> 44 45 #define usec_delay(x) DELAY(x) 46 #define usec_delay_irq usec_delay 47 #define msec_delay(x) DELAY(1000*(x)) 48 /* TODO: Should we be paranoid about delaying in interrupt context? */ 49 #define msec_delay_irq(x) DELAY(1000*(x)) 50 51 #define DEBUGFUNC(F) DEBUGOUT(F) 52 #define DEBUGOUT(S) 53 #define DEBUGOUT1(S,A) 54 #define DEBUGOUT2(S,A,B) 55 #define DEBUGOUT3(S,A,B,C) 56 #define DEBUGOUT7(S,A,B,C,D,E,F,G) 57 58 #define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */ 59 #define PCI_COMMAND_REGISTER PCIR_COMMAND 60 61 /* 62 * These typedefs are necessary due to the new 63 * shared code, they are native to Linux. 64 */ 65 typedef uint64_t u64; 66 typedef uint32_t u32; 67 typedef uint16_t u16; 68 typedef uint8_t u8; 69 typedef int64_t s64; 70 typedef int32_t s32; 71 typedef int16_t s16; 72 typedef int8_t s8; 73 typedef boolean_t bool; 74 75 #define __le16 u16 76 #define __le32 u32 77 #define __le64 u64 78 79 struct e1000_osdep { 80 bus_space_tag_t mem_bus_space_tag; 81 bus_space_handle_t mem_bus_space_handle; 82 bus_space_tag_t io_bus_space_tag; 83 bus_space_handle_t io_bus_space_handle; 84 bus_space_tag_t flash_bus_space_tag; 85 bus_space_handle_t flash_bus_space_handle; 86 device_t dev; 87 }; 88 89 #define E1000_REGISTER(hw, reg) (((hw)->mac.type >= e1000_82543) \ 90 ? reg : e1000_translate_register_82542(reg)) 91 92 #define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, E1000_STATUS) 93 94 /* Read from an absolute offset in the adapter's memory space */ 95 #define E1000_READ_OFFSET(hw, offset) \ 96 bus_space_read_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ 97 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, offset) 98 99 /* Write to an absolute offset in the adapter's memory space */ 100 #define E1000_WRITE_OFFSET(hw, offset, value) \ 101 bus_space_write_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ 102 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, offset, value) 103 104 /* Register READ/WRITE macros */ 105 106 #define E1000_READ_REG(hw, reg) \ 107 bus_space_read_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ 108 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \ 109 E1000_REGISTER(hw, reg)) 110 111 #define E1000_WRITE_REG(hw, reg, value) \ 112 bus_space_write_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ 113 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \ 114 E1000_REGISTER(hw, reg), value) 115 116 #define E1000_READ_REG_ARRAY(hw, reg, index) \ 117 bus_space_read_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ 118 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \ 119 E1000_REGISTER(hw, reg) + ((index)<< 2)) 120 121 #define E1000_WRITE_REG_ARRAY(hw, reg, index, value) \ 122 bus_space_write_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ 123 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \ 124 E1000_REGISTER(hw, reg) + ((index)<< 2), value) 125 126 #define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY 127 #define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY 128 129 #define E1000_READ_REG_ARRAY_BYTE(hw, reg, index) \ 130 bus_space_read_1(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ 131 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \ 132 E1000_REGISTER(hw, reg) + index) 133 134 #define E1000_WRITE_REG_ARRAY_BYTE(hw, reg, index, value) \ 135 bus_space_write_1(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ 136 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \ 137 E1000_REGISTER(hw, reg) + index, value) 138 139 #define E1000_WRITE_REG_ARRAY_WORD(hw, reg, index, value) \ 140 bus_space_write_2(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ 141 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \ 142 E1000_REGISTER(hw, reg) + (index << 1), value) 143 144 #define E1000_WRITE_REG_IO(hw, reg, value) do {\ 145 bus_space_write_4(((struct e1000_osdep *)(hw)->back)->io_bus_space_tag, \ 146 ((struct e1000_osdep *)(hw)->back)->io_bus_space_handle, \ 147 (hw)->io_base, reg); \ 148 bus_space_write_4(((struct e1000_osdep *)(hw)->back)->io_bus_space_tag, \ 149 ((struct e1000_osdep *)(hw)->back)->io_bus_space_handle, \ 150 (hw)->io_base + 4, value); } while (0) 151 152 #define E1000_READ_FLASH_REG(hw, reg) \ 153 bus_space_read_4(((struct e1000_osdep *)(hw)->back)->flash_bus_space_tag, \ 154 ((struct e1000_osdep *)(hw)->back)->flash_bus_space_handle, reg) 155 156 #define E1000_READ_FLASH_REG16(hw, reg) \ 157 bus_space_read_2(((struct e1000_osdep *)(hw)->back)->flash_bus_space_tag, \ 158 ((struct e1000_osdep *)(hw)->back)->flash_bus_space_handle, reg) 159 160 #define E1000_WRITE_FLASH_REG(hw, reg, value) \ 161 bus_space_write_4(((struct e1000_osdep *)(hw)->back)->flash_bus_space_tag, \ 162 ((struct e1000_osdep *)(hw)->back)->flash_bus_space_handle, reg, value) 163 164 #define E1000_WRITE_FLASH_REG16(hw, reg, value) \ 165 bus_space_write_2(((struct e1000_osdep *)(hw)->back)->flash_bus_space_tag, \ 166 ((struct e1000_osdep *)(hw)->back)->flash_bus_space_handle, reg, value) 167 168 #endif /* _DRAGONFLY_OS_H_ */ 169